[MIPS32] Emulate MSA instructions for MIPS32

[slthakur]

Summary

This patch adds MSA branch instruction emulation for MIPS32.

[tberghammer]

LGTM

source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp

608

(nit): Indentation

[jaydeep]

Looks good to me.

[slthakur]

Committed in revision 248277

source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.h

protected:
 
     bool
     Emulate_BC1ANY4F  (llvm::MCInst& insn);
 
     bool
     Emulate_BC1ANY4T  (llvm::MCInst& insn);
 
     bool
+    Emulate_BNZB  (llvm::MCInst& insn);
+
+    bool
+    Emulate_BNZH  (llvm::MCInst& insn);
+
+    bool
+    Emulate_BNZW  (llvm::MCInst& insn);
+
+    bool
+    Emulate_BNZD  (llvm::MCInst& insn);
+
+    bool
+    Emulate_BZB  (llvm::MCInst& insn);
+
+    bool
+    Emulate_BZH  (llvm::MCInst& insn);
+
+    bool
+    Emulate_BZW  (llvm::MCInst& insn);
+
+    bool
+    Emulate_BZD  (llvm::MCInst& insn);
+
+    bool
+    Emulate_MSA_Branch_DF (llvm::MCInst& insn, int element_byte_size, bool bnz);
+
+    bool
+    Emulate_BNZV  (llvm::MCInst& insn);
+
+    bool
+    Emulate_BZV  (llvm::MCInst& insn);
+
+    bool
+    Emulate_MSA_Branch_V (llvm::MCInst& insn, bool bnz);
+
+    bool
     nonvolatile_reg_p (uint32_t regnum);
 
     const char *
     GetRegisterName (unsigned reg_num, bool altnernate_name);
 
 private:
     std::unique_ptr<llvm::MCDisassembler>   m_disasm;
     std::unique_ptr<llvm::MCSubtargetInfo>  m_subtype_info;
     std::unique_ptr<llvm::MCRegisterInfo>   m_reg_info;
     std::unique_ptr<llvm::MCAsmInfo>        m_asm_info;
     std::unique_ptr<llvm::MCContext>        m_context;
     std::unique_ptr<llvm::MCInstrInfo>      m_insn_info;
 };
 
 #endif  // EmulateInstructionMIPS_h_

source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp

 
 const char *
 EmulateInstructionMIPS::GetRegisterName (unsigned reg_num, bool alternate_name)
 {
     if (alternate_name)
     {
         switch (reg_num)
         {
-            case gcc_dwarf_sp_mips:  return "r29"; 
-            case gcc_dwarf_r30_mips: return "r30"; 
-            case gcc_dwarf_ra_mips:  return "r31";
-            case gcc_dwarf_f0_mips:  return "f0";
-            case gcc_dwarf_f1_mips:  return "f1";
-            case gcc_dwarf_f2_mips:  return "f2";
-            case gcc_dwarf_f3_mips:  return "f3";
-            case gcc_dwarf_f4_mips:  return "f4";
-            case gcc_dwarf_f5_mips:  return "f5";
-            case gcc_dwarf_f6_mips:  return "f6";
-            case gcc_dwarf_f7_mips:  return "f7";
-            case gcc_dwarf_f8_mips:  return "f8";
-            case gcc_dwarf_f9_mips:  return "f9";
-            case gcc_dwarf_f10_mips: return "f10";
-            case gcc_dwarf_f11_mips: return "f11";
-            case gcc_dwarf_f12_mips: return "f12";
-            case gcc_dwarf_f13_mips: return "f13";
-            case gcc_dwarf_f14_mips: return "f14";
-            case gcc_dwarf_f15_mips: return "f15";
-            case gcc_dwarf_f16_mips: return "f16";
-            case gcc_dwarf_f17_mips: return "f17";
-            case gcc_dwarf_f18_mips: return "f18";
-            case gcc_dwarf_f19_mips: return "f19";
-            case gcc_dwarf_f20_mips: return "f20";
-            case gcc_dwarf_f21_mips: return "f21";
-            case gcc_dwarf_f22_mips: return "f22";
-            case gcc_dwarf_f23_mips: return "f23";
-            case gcc_dwarf_f24_mips: return "f24";
-            case gcc_dwarf_f25_mips: return "f25";
-            case gcc_dwarf_f26_mips: return "f26";
-            case gcc_dwarf_f27_mips: return "f27";
-            case gcc_dwarf_f28_mips: return "f28";
-            case gcc_dwarf_f29_mips: return "f29";
-            case gcc_dwarf_f30_mips: return "f30";
-            case gcc_dwarf_f31_mips: return "f31";
+            case gcc_dwarf_sp_mips:      return "r29";
+            case gcc_dwarf_r30_mips:     return "r30";
+            case gcc_dwarf_ra_mips:      return "r31";
+            case gcc_dwarf_f0_mips:      return "f0";
+            case gcc_dwarf_f1_mips:      return "f1";
+            case gcc_dwarf_f2_mips:      return "f2";
+            case gcc_dwarf_f3_mips:      return "f3";
+            case gcc_dwarf_f4_mips:      return "f4";
+            case gcc_dwarf_f5_mips:      return "f5";
+            case gcc_dwarf_f6_mips:      return "f6";
+            case gcc_dwarf_f7_mips:      return "f7";
+            case gcc_dwarf_f8_mips:      return "f8";
+            case gcc_dwarf_f9_mips:      return "f9";
+            case gcc_dwarf_f10_mips:     return "f10";
+            case gcc_dwarf_f11_mips:     return "f11";
+            case gcc_dwarf_f12_mips:     return "f12";
+            case gcc_dwarf_f13_mips:     return "f13";
+            case gcc_dwarf_f14_mips:     return "f14";
+            case gcc_dwarf_f15_mips:     return "f15";
+            case gcc_dwarf_f16_mips:     return "f16";
+            case gcc_dwarf_f17_mips:     return "f17";
+            case gcc_dwarf_f18_mips:     return "f18";
+            case gcc_dwarf_f19_mips:     return "f19";
+            case gcc_dwarf_f20_mips:     return "f20";
+            case gcc_dwarf_f21_mips:     return "f21";
+            case gcc_dwarf_f22_mips:     return "f22";
+            case gcc_dwarf_f23_mips:     return "f23";
+            case gcc_dwarf_f24_mips:     return "f24";
+            case gcc_dwarf_f25_mips:     return "f25";
+            case gcc_dwarf_f26_mips:     return "f26";
+            case gcc_dwarf_f27_mips:     return "f27";
+            case gcc_dwarf_f28_mips:     return "f28";
+            case gcc_dwarf_f29_mips:     return "f29";
+            case gcc_dwarf_f30_mips:     return "f30";
+            case gcc_dwarf_f31_mips:     return "f31";
+            case gcc_dwarf_w0_mips:      return "w0";
+            case gcc_dwarf_w1_mips:      return "w1";
+            case gcc_dwarf_w2_mips:      return "w2";
+            case gcc_dwarf_w3_mips:      return "w3";
+            case gcc_dwarf_w4_mips:      return "w4";
+            case gcc_dwarf_w5_mips:      return "w5";
+            case gcc_dwarf_w6_mips:      return "w6";
+            case gcc_dwarf_w7_mips:      return "w7";
+            case gcc_dwarf_w8_mips:      return "w8";
+            case gcc_dwarf_w9_mips:      return "w9";
+            case gcc_dwarf_w10_mips:     return "w10";
+            case gcc_dwarf_w11_mips:     return "w11";
+            case gcc_dwarf_w12_mips:     return "w12";
+            case gcc_dwarf_w13_mips:     return "w13";
+            case gcc_dwarf_w14_mips:     return "w14";
+            case gcc_dwarf_w15_mips:     return "w15";
+            case gcc_dwarf_w16_mips:     return "w16";
+            case gcc_dwarf_w17_mips:     return "w17";
+            case gcc_dwarf_w18_mips:     return "w18";
+            case gcc_dwarf_w19_mips:     return "w19";
+            case gcc_dwarf_w20_mips:     return "w20";
+            case gcc_dwarf_w21_mips:     return "w21";
+            case gcc_dwarf_w22_mips:     return "w22";
+            case gcc_dwarf_w23_mips:     return "w23";
+            case gcc_dwarf_w24_mips:     return "w24";
+            case gcc_dwarf_w25_mips:     return "w25";
+            case gcc_dwarf_w26_mips:     return "w26";
+            case gcc_dwarf_w27_mips:     return "w27";
+            case gcc_dwarf_w28_mips:     return "w28";
+            case gcc_dwarf_w29_mips:     return "w29";
+            case gcc_dwarf_w30_mips:     return "w30";
+            case gcc_dwarf_w31_mips:     return "w31";
+            case gcc_dwarf_mir_mips:     return "mir";
+            case gcc_dwarf_mcsr_mips:    return "mcsr";
+            case gcc_dwarf_config5_mips: return "config5";
             default:
                 break;
         }
         return nullptr;
     }
 
     switch (reg_num)
     {
switch (reg_num)
         case gcc_dwarf_f26_mips:      return "f26";
         case gcc_dwarf_f27_mips:      return "f27";
         case gcc_dwarf_f28_mips:      return "f28";
         case gcc_dwarf_f29_mips:      return "f29";
         case gcc_dwarf_f30_mips:      return "f30";
         case gcc_dwarf_f31_mips:      return "f31";
         case gcc_dwarf_fcsr_mips:     return "fcsr";
         case gcc_dwarf_fir_mips:      return "fir";
+        case gcc_dwarf_w0_mips:       return "w0";
+        case gcc_dwarf_w1_mips:       return "w1";
+        case gcc_dwarf_w2_mips:       return "w2";
+        case gcc_dwarf_w3_mips:       return "w3";
+        case gcc_dwarf_w4_mips:       return "w4";
+        case gcc_dwarf_w5_mips:       return "w5";
+        case gcc_dwarf_w6_mips:       return "w6";
+        case gcc_dwarf_w7_mips:       return "w7";
+        case gcc_dwarf_w8_mips:       return "w8";
+        case gcc_dwarf_w9_mips:       return "w9";
+        case gcc_dwarf_w10_mips:      return "w10";
+        case gcc_dwarf_w11_mips:      return "w11";
+        case gcc_dwarf_w12_mips:      return "w12";
+        case gcc_dwarf_w13_mips:      return "w13";
+        case gcc_dwarf_w14_mips:      return "w14";
+        case gcc_dwarf_w15_mips:      return "w15";
+        case gcc_dwarf_w16_mips:      return "w16";
+        case gcc_dwarf_w17_mips:      return "w17";
+        case gcc_dwarf_w18_mips:      return "w18";
+        case gcc_dwarf_w19_mips:      return "w19";
+        case gcc_dwarf_w20_mips:      return "w20";
+        case gcc_dwarf_w21_mips:      return "w21";
+        case gcc_dwarf_w22_mips:      return "w22";
+        case gcc_dwarf_w23_mips:      return "w23";
+        case gcc_dwarf_w24_mips:      return "w24";
+        case gcc_dwarf_w25_mips:      return "w25";
+        case gcc_dwarf_w26_mips:      return "w26";
+        case gcc_dwarf_w27_mips:      return "w27";
+        case gcc_dwarf_w28_mips:      return "w28";
+        case gcc_dwarf_w29_mips:      return "w29";
+        case gcc_dwarf_w30_mips:      return "w30";
+        case gcc_dwarf_w31_mips:      return "w31";
+        case gcc_dwarf_mcsr_mips:     return "mcsr";
+        case gcc_dwarf_mir_mips:      return "mir";
+        case gcc_dwarf_config5_mips:  return "config5";
     }
     return nullptr;
 }
 
 bool
 EmulateInstructionMIPS::GetRegisterInfo (RegisterKind reg_kind, uint32_t reg_num, RegisterInfo &reg_info)
 {
     if (reg_kind == eRegisterKindGeneric)
if (reg_kind == eRegisterKindGeneric)
         }
     }
 
     if (reg_kind == eRegisterKindDWARF)
     {
        ::memset (&reg_info, 0, sizeof(RegisterInfo));
        ::memset (reg_info.kinds, LLDB_INVALID_REGNUM, sizeof(reg_info.kinds));
 
-       if (reg_num == gcc_dwarf_sr_mips || reg_num == gcc_dwarf_fcsr_mips || reg_num == gcc_dwarf_fir_mips)
+       if (reg_num == gcc_dwarf_sr_mips || reg_num == gcc_dwarf_fcsr_mips || reg_num == gcc_dwarf_fir_mips  || reg_num == gcc_dwarf_mcsr_mips || reg_num == gcc_dwarf_mir_mips || reg_num == gcc_dwarf_config5_mips)
        {
            reg_info.byte_size = 4;
            reg_info.format = eFormatHex;
            reg_info.encoding = eEncodingUint;
        }
        else if ((int)reg_num >= gcc_dwarf_zero_mips && (int)reg_num <= gcc_dwarf_f31_mips)
        {
            reg_info.byte_size = 4;
            reg_info.format = eFormatHex;
            reg_info.encoding = eEncodingUint;
        }
+       else if ((int)reg_num >= gcc_dwarf_w0_mips && (int)reg_num <= gcc_dwarf_w31_mips)
+       {
+           reg_info.byte_size = 16;
+           reg_info.format = eFormatVectorOfUInt8;
+           reg_info.encoding = eEncodingVector;
+       }
        else
        {
            return false;
        }
 
        reg_info.name = GetRegisterName (reg_num, false);
        reg_info.alt_name = GetRegisterName (reg_num, true);
        reg_info.kinds[eRegisterKindDWARF] = reg_num;
g_opcodes[] =
         { "BC1FL",      &EmulateInstructionMIPS::Emulate_BC1FL,       "BC1FL cc, offset"          },
         { "BC1TL",      &EmulateInstructionMIPS::Emulate_BC1TL,       "BC1TL cc, offset"          },
         { "BC1EQZ",     &EmulateInstructionMIPS::Emulate_BC1EQZ,      "BC1EQZ ft, offset"         },
         { "BC1NEZ",     &EmulateInstructionMIPS::Emulate_BC1NEZ,      "BC1NEZ ft, offset"         },
         { "BC1ANY2F",   &EmulateInstructionMIPS::Emulate_BC1ANY2F,    "BC1ANY2F cc, offset"       },
         { "BC1ANY2T",   &EmulateInstructionMIPS::Emulate_BC1ANY2T,    "BC1ANY2T cc, offset"       },
         { "BC1ANY4F",   &EmulateInstructionMIPS::Emulate_BC1ANY4F,    "BC1ANY4F cc, offset"       },
         { "BC1ANY4T",   &EmulateInstructionMIPS::Emulate_BC1ANY4T,    "BC1ANY4T cc, offset"       },
+        { "BNZ_B",      &EmulateInstructionMIPS::Emulate_BNZB,      "BNZ.b wt,s16"              },
+        { "BNZ_H",      &EmulateInstructionMIPS::Emulate_BNZH,      "BNZ.h wt,s16"              },
+        { "BNZ_W",      &EmulateInstructionMIPS::Emulate_BNZW,      "BNZ.w wt,s16"              },
+        { "BNZ_D",      &EmulateInstructionMIPS::Emulate_BNZD,      "BNZ.d wt,s16"              },
+        { "BZ_B",       &EmulateInstructionMIPS::Emulate_BZB,       "BZ.b wt,s16"               },
+        { "BZ_H",       &EmulateInstructionMIPS::Emulate_BZH,       "BZ.h wt,s16"               },
+        { "BZ_W",       &EmulateInstructionMIPS::Emulate_BZW,       "BZ.w wt,s16"               },
+        { "BZ_D",       &EmulateInstructionMIPS::Emulate_BZD,       "BZ.d wt,s16"               },
+        { "BNZ_V",      &EmulateInstructionMIPS::Emulate_BNZV,      "BNZ.V wt,s16"              },
+        { "BZ_V",       &EmulateInstructionMIPS::Emulate_BZV,       "BZ.V wt,s16"               },
     };
 
     static const size_t k_num_mips_opcodes = llvm::array_lengthof(g_opcodes);
 
     for (size_t i = 0; i < k_num_mips_opcodes; ++i)
     {
         if (! strcasecmp (g_opcodes[i].op_name, op_name))
             return &g_opcodes[i];
EmulateInstructionMIPS::Emulate_BC1ANY4T (llvm::MCInst& insn)
 
     if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target))
         return false;
 
     return true;
 }
 
 bool
+EmulateInstructionMIPS::Emulate_BNZB (llvm::MCInst& insn)
+{
+    return Emulate_MSA_Branch_DF(insn, 1, true);
+}
+
+bool
+EmulateInstructionMIPS::Emulate_BNZH (llvm::MCInst& insn)
+{
+    return Emulate_MSA_Branch_DF(insn, 2, true);
+}
+
+bool
+EmulateInstructionMIPS::Emulate_BNZW (llvm::MCInst& insn)
+{
+    return Emulate_MSA_Branch_DF(insn, 4, true);
+}
+
+bool
+EmulateInstructionMIPS::Emulate_BNZD (llvm::MCInst& insn)
+{
+    return Emulate_MSA_Branch_DF(insn, 8, true);
+}
+
+bool
+EmulateInstructionMIPS::Emulate_BZB (llvm::MCInst& insn)
+{
+    return Emulate_MSA_Branch_DF(insn, 1, false);
+}
+
+bool
+EmulateInstructionMIPS::Emulate_BZH (llvm::MCInst& insn)
+{
+    return Emulate_MSA_Branch_DF(insn, 2, false);
+}
+
+bool
+EmulateInstructionMIPS::Emulate_BZW (llvm::MCInst& insn)
+{
+    return Emulate_MSA_Branch_DF(insn, 4, false);
+}
+
+bool
+EmulateInstructionMIPS::Emulate_BZD (llvm::MCInst& insn)
+{
+    return Emulate_MSA_Branch_DF(insn, 8, false);
+}
+
+bool
+EmulateInstructionMIPS::Emulate_MSA_Branch_DF (llvm::MCInst& insn, int element_byte_size, bool bnz)
+{
+    bool success = false, branch_hit = true;
+    int32_t target = 0;
+    RegisterValue reg_value;
+    uint8_t * ptr = NULL;
+
+    uint32_t wt = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
+    int32_t offset = insn.getOperand(1).getImm();
+
+    int32_t pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success);
+    if (!success)
+        return false;
+
+    if (ReadRegister (eRegisterKindDWARF, gcc_dwarf_w0_mips + wt, reg_value))
+        ptr = (uint8_t *)reg_value.GetBytes();
+    else
+        return false;
+
+    for(int i = 0; i < 16 / element_byte_size; i++)
+    {
+        switch(element_byte_size)
+        {
+            case 1:
+                if((*ptr == 0 && bnz) || (*ptr != 0 && !bnz) )
+                    branch_hit = false;
+                break;
+            case 2:
+                if((*(uint16_t *)ptr == 0 && bnz) || (*(uint16_t *)ptr != 0 && !bnz))
+                    branch_hit = false;
+                break;
+            case 4:
+                if((*(uint32_t *)ptr == 0 && bnz) || (*(uint32_t *)ptr != 0 && !bnz))
+                    branch_hit = false;
+                break;
+            case 8:
+                if((*(uint64_t *)ptr == 0 && bnz) || (*(uint64_t *)ptr != 0 && !bnz))
+                    branch_hit = false;
+                break;
+        }
+        if(!branch_hit)
+           break;
+        ptr = ptr + element_byte_size;
+    }
+
+    if(branch_hit)
+        target = pc + offset;
+    else
+        target = pc + 8;
+
+    Context context;
+    context.type = eContextRelativeBranchImmediate;
+
+    if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target))
+        return false;
+
+    return true;
+}
+
+bool
+EmulateInstructionMIPS::Emulate_BNZV (llvm::MCInst& insn)
+{
+    return Emulate_MSA_Branch_V (insn, true);
+}
+
+bool
+EmulateInstructionMIPS::Emulate_BZV (llvm::MCInst& insn)
+{
+    return Emulate_MSA_Branch_V (insn, false);
+}
+
+bool
+EmulateInstructionMIPS::Emulate_MSA_Branch_V (llvm::MCInst& insn, bool bnz)
+{
+    bool success = false;
+    int32_t target = 0;
+    llvm::APInt wr_val = llvm::APInt::getNullValue(128);
+    llvm::APInt fail_value = llvm::APInt::getMaxValue(128);
+    llvm::APInt zero_value = llvm::APInt::getNullValue(128);
+    RegisterValue reg_value;
+
+    uint32_t wt = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
+    int32_t offset = insn.getOperand(1).getImm();
+
+    int32_t pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips, 0, &success);
+    if (!success)
+        return false;
+
+    if (ReadRegister (eRegisterKindDWARF, gcc_dwarf_w0_mips + wt, reg_value))
+        wr_val = reg_value.GetAsUInt128(fail_value);
+    else
+        return false;
+
+    if((llvm::APInt::isSameValue(zero_value, wr_val) && !bnz) || (!llvm::APInt::isSameValue(zero_value, wr_val) && bnz))
+        target = pc + offset;
+    else
+        target = pc + 8;
+
+    Context context;
+    context.type = eContextRelativeBranchImmediate;
+
+    if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips, target))
+        return false;
+
+    return true;
+}
+
+
+bool
 EmulateInstructionMIPS::Emulate_LDST_Imm (llvm::MCInst& insn)
 {
     bool success = false;
     uint32_t base;
     int32_t imm, address;
     Context bad_vaddr_context;
 
     uint32_t num_operands = insn.getNumOperands();