llvm-reduce: run the set of passes more times, by default

[regehr]

Summary

calling llvm-reduce with -max-pass-iterations=N for some N>1 often makes a real difference in the quality of its output. I often forget to add this cumbersome option and get suboptimal results, and the other day I was talking to a heavy user of llvm-reduce who didn't even realize it could do certain transformations because they often get suppressed by the default pass ordering.

this patch sets the default max-pass-iterations to 5 instead of 1. I believe that nearly all users will benefit from this. this only drawback is increased execution time, this patch causes "ninja check" of the llvm-reduce subdir take about 1.7 seconds on my machine instead of 1.2 seconds, previously. my strong belief is that most llvm-reduce users are not bottlenecked by this sort of minor increase in execution time, and that they'll appreciate the improved outputs.

llvm/test/tools/llvm-reduce/mir/generic-vreg.mir

 # CHECK-INTERESTINGNESS: G_STORE
 
 # RESULT: %{{[0-9]+}}:vgpr(s32) = G_IMPLICIT_DEF
 # RESULT-NEXT: %{{[0-9]+}}:vgpr(<2 x s16>) = G_IMPLICIT_DEF
 # RESULT-NEXT: %{{[0-9]+}}:sgpr(p1) = G_IMPLICIT_DEF
 # RESULT-NEXT: %{{[0-9]+}}:_(s64) = G_IMPLICIT_DEF
 # RESULT-NEXT: %{{[0-9]+}}:vreg_64(s64) = IMPLICIT_DEF
 # RESULT-NEXT: %{{[0-9]+}}:_(<2 x s32>) = G_IMPLICIT_DEF
-# RESULT-NEXT: %aoeu:_(s64) = G_BITCAST %14(<2 x s32>)
+# RESULT-NEXT: %aoeu:_(s64) = G_BITCAST %{{[0-9]+}}(<2 x s32>)
 # RESULT-NEXT: %add:_(s64) = G_ADD %aoeu, %aoeu
 # RESULT-NEXT: %ptr:_(p1) = G_IMPLICIT_DEF
 # RESULT-NEXT: G_STORE %{{[0-9]+}}(s32), %ptr(p1) :: (store (s32), addrspace 1)
 # RESULT-NEXT: S_ENDPGM 0{{$}}
 
 ---
 name:            f
 tracksRegLiveness: true

llvm/test/tools/llvm-reduce/mir/reduce-instruction-unreachable-block.mir

 # REQUIRES: amdgpu-registered-target
 # RUN: llvm-reduce -abort-on-invalid-reduction -simplify-mir -mtriple=amdgcn-amd-amdhsa --delta-passes=instructions --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
 # RUN: FileCheck --check-prefix=RESULT %s < %t
 
 # Make sure there's no crash with unreachable blocks.
 
 # CHECK-INTERESTINGNESS: S_NOP
 
 # RESULT: bb.0:
 
-# RESULT: %3:vgpr_32 = IMPLICIT_DEF
-# RESULT-NEXT: %4:sreg_64 = IMPLICIT_DEF
-# RESULT-NEXT: %5:vreg_64 = IMPLICIT_DEF
+# RESULT: %{{[0-9]+}}:vgpr_32 = IMPLICIT_DEF
+# RESULT-NEXT: %{{[0-9]+}}:sreg_64 = IMPLICIT_DEF
+# RESULT-NEXT: %{{[0-9]+}}:vreg_64 = IMPLICIT_DEF
 # RESULT-NEXT: S_CBRANCH_SCC1 %bb.1, implicit undef $scc
 # RESULT-NEXT: S_BRANCH %bb.3
 
 # RESULT: bb.1:
 # RESULT-NEXT: S_BRANCH %bb.3
 
 # RESULT: bb.2:
-# RESULT-NEXT: S_NOP 0, implicit %3, implicit killed %5, implicit %4
+# RESULT-NEXT: S_NOP 0, implicit %{{[0-9]+}}, implicit killed %{{[0-9]+}}, implicit %{{[0-9]+}}
 
 ---
 name: unreachable_block
 tracksRegLiveness: true
 body:             |
   bb.0:
     %0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
     S_CBRANCH_SCC1 %bb.1, implicit undef $scc

llvm/test/tools/llvm-reduce/mir/subreg-def0.mir

 # REQUIRES: amdgpu-registered-target
 # RUN: llvm-reduce -abort-on-invalid-reduction --delta-passes=instructions -mtriple=amdgcn-amd-amdhsa --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
 # RUN: FileCheck --match-full-lines --check-prefix=RESULT %s < %t
 
 # CHECK-INTERESTINGNESS: V_ADD_U32
 
-# RESULT: undef %2.sub1:vreg_64 = IMPLICIT_DEF
-# RESULT-NEXT: %3.sub0:vreg_64 = IMPLICIT_DEF
-# RESULT-NEXT: %1:vgpr_32 = V_ADD_U32_e32 %2.sub0, %2.sub1, implicit $exec
+# RESULT: undef %{{[0-9]+}}.sub1:vreg_64 = IMPLICIT_DEF
+# RESULT-NEXT: %{{[0-9]+}}.sub0:vreg_64 = IMPLICIT_DEF
+# RESULT-NEXT: %1:vgpr_32 = V_ADD_U32_e32 %{{[0-9]+}}.sub0, %{{[0-9]+}}.sub1, implicit $exec
 # RESULT-NEXT: S_ENDPGM 0, implicit %1
 
 ---
 name:            f
 tracksRegLiveness: true
 body:             |
   bb.0:
     S_WAITCNT 0
     undef %0.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec
     %0.sub0:vreg_64 = V_MOV_B32_e32 1, implicit $exec
     %1:vgpr_32 = V_ADD_U32_e32 %0.sub0, %0.sub1, implicit $exec
     S_ENDPGM 0, implicit %1
 ...

llvm/test/tools/llvm-reduce/mir/subreg-def1.mir

 # REQUIRES: amdgpu-registered-target
 # RUN: llvm-reduce -abort-on-invalid-reduction --delta-passes=instructions -mtriple=amdgcn-amd-amdhsa --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
 # RUN: FileCheck --match-full-lines --check-prefix=RESULT %s < %t
 
 # CHECK-INTERESTINGNESS: %{{[0-9]+}}.sub0:vreg_64 = V_ADD_U32_e32 %{{[0-9]+}}.sub1, %{{[0-9]+}}.sub0, implicit $exec
 # CHECK-INTERESTINGNESS: %{{[0-9]+}}.sub0:vreg_64 = V_ADD_U32_e32 4, %{{[0-9]+}}.sub0, implicit $exec
 
-# RESULT: undef %2.sub1:vreg_64 = IMPLICIT_DEF
-# RESULT-NEXT: %0.sub0:vreg_64 = V_ADD_U32_e32 %2.sub1, %2.sub0, implicit $exec
-# RESULT-NEXT: %1.sub0:vreg_64 = V_ADD_U32_e32 4, %2.sub0, implicit $exec
-# RESULT-NEXT: S_ENDPGM 0, implicit %2, implicit %2.sub0
+# RESULT: undef %{{[0-9]+}}.sub1:vreg_64 = IMPLICIT_DEF
+# RESULT-NEXT: %0.sub0:vreg_64 = V_ADD_U32_e32 %{{[0-9]+}}.sub1, %{{[0-9]+}}.sub0, implicit $exec
+# RESULT-NEXT: %1.sub0:vreg_64 = V_ADD_U32_e32 4, %{{[0-9]+}}.sub0, implicit $exec
+# RESULT-NEXT: S_ENDPGM 0, implicit %{{[0-9]+}}, implicit %{{[0-9]+}}.sub0
 ---
 name:            f
 tracksRegLiveness: true
 body:             |
   bb.0:
     S_WAITCNT 0
     undef %0.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec
     %1.sub1:vreg_64 = V_ADD_U32_e32 2, %0.sub1, implicit $exec
     %0.sub0:vreg_64 = V_ADD_U32_e32 %1.sub1, %0.sub0, implicit $exec
     %1.sub0:vreg_64 = V_ADD_U32_e32 4, %0.sub0, implicit $exec
     S_ENDPGM 0, implicit %1, implicit %0.sub0
 ...

llvm/test/tools/llvm-reduce/remove-invoked-functions.ll

 
 ; CHECK-ALL: declare void @did_not_throw(i32)
 declare void @did_not_throw(i32)
 
 ; CHECK-ALL: declare void @thrown()
 declare void @thrown()
 
 ; CHECK-INTERESTINGNESS: define void @caller(
-; CHECK-FINAL: define void @caller(i32 %arg)
+; CHECK-FINAL: define void @caller()
 define void @caller(i32 %arg) personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
 ; CHECK-ALL: bb:
 bb:
 ; CHECK-INTERESTINGNESS: %i0 = invoke i32 {{.*}}@maybe_throwing_callee
 ; CHECK-FINAL: %i0 = invoke i32 bitcast (i32 ()* @maybe_throwing_callee to i32 (i32)*)
 ; CHECK-ALL: to label %bb3 unwind label %bb1
   %i0 = invoke i32 @maybe_throwing_callee(i32 %arg)
           to label %bb3 unwind label %bb1

llvm/test/tools/llvm-reduce/remove-operand-bundles.ll

 ; Test that llvm-reduce can remove uninteresting operand bundles from calls.
 ;
 ; RUN: llvm-reduce --test FileCheck --test-arg --check-prefixes=CHECK-ALL,CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t
 ; RUN: cat %t | FileCheck --check-prefixes=CHECK-ALL,CHECK-FINAL %s
 
 ; CHECK-ALL: declare void @f1()
 ; CHECK-ALL: declare void @f2()
 ; CHECK-ALL: declare void @f3()
 declare void @f1()
 declare void @f2()
 declare void @f3()
 
-; CHECK-FINAL-LABEL: define void @interesting(i32 %arg0, i32 %arg1, i32 %arg2) {
+; CHECK-FINAL-LABEL: define void @interesting(i32 %arg0, i32 %arg2) {
 ; CHECK-FINAL-NEXT:  entry:
 ; CHECK-FINAL-NEXT:    call void @f1() [ "bundle0"(), "align"(i32 %arg0), "whatever0"() ]
 ; CHECK-FINAL-NEXT:    call void @f2()
 ; CHECK-FINAL-NEXT:    call void @f3() [ "align"(i32 %arg2) ]
 ; CHECK-FINAL-NEXT:    ret void
 ; CHECK-FINAL-NEXT:  }
 define void @interesting(i32 %arg0, i32 %arg1, i32 %arg2) {
 entry:

llvm/tools/llvm-reduce/llvm-reduce.cpp

InputLanguage("x", cl::ValueOptional,
                   cl::init(InputLanguages::None),
                   cl::values(clEnumValN(InputLanguages::IR, "ir", ""),
                              clEnumValN(InputLanguages::MIR, "mir", "")),
                   cl::cat(LLVMReduceOptions));
 
 static cl::opt<int>
     MaxPassIterations("max-pass-iterations",
                       cl::desc("Maximum number of times to run the full set "
-                               "of delta passes (default=1)"),
-                      cl::init(1), cl::cat(LLVMReduceOptions));
+                               "of delta passes (default=5)"),
+                      cl::init(5), cl::cat(LLVMReduceOptions));
 
 static codegen::RegisterCodeGenFlags CGF;
 
 static void initializeTargetInfo() {
   InitializeAllTargets();
   InitializeAllTargetMCs();
   InitializeAllAsmPrinters();
   InitializeAllAsmParsers();