This is an archive of the discontinued LLVM Phabricator instance.

[docs] Fix typo in 'CodeGenerator' docs
ClosedPublic

Authored by JOE1994 on Apr 22 2022, 2:40 PM.

Download Raw Diff

Details

Reviewers

seaneveson
myhsu

Commits

rGe1567e771b89: [docs] Fix typos in the 'CodeGenerator' doc

Diff Detail

Repository: rG LLVM Github Monorepo

Unit TestsFailed

	Time	Test
	60,110 ms	x64 debian > AddressSanitizer-x86_64-linux-dynamic.TestCases::scariness_score_test.cpp
	60,080 ms	x64 debian > AddressSanitizer-x86_64-linux.TestCases::scariness_score_test.cpp

Event Timeline

JOE1994 created this revision.Apr 22 2022, 2:40 PM

Herald added a project: Restricted Project. · View Herald TranscriptApr 22 2022, 2:40 PM

JOE1994 requested review of this revision.Apr 22 2022, 2:40 PM

Herald added a project: Restricted Project. · View Herald TranscriptApr 22 2022, 2:40 PM

[docs] Fix typo in 'CodeGenerator' docs

Harbormaster completed remote builds in B160968: Diff 424623.Apr 22 2022, 3:37 PM

Since I do not have commit access, it would be great if the reviewer could land this commit for me.
Please use "Youngsuk Kim joseph942010@gmail.com" to commit the change.

Thank you!

JOE1994 added a reviewer: seaneveson.Apr 24 2022, 6:54 PM

LGTM
I'll commit on your behalf

This revision is now accepted and ready to land.Apr 25 2022, 11:19 AM

@myhsu Thank you !

This revision was landed with ongoing or failed builds.Apr 26 2022, 9:48 PM

Closed by commit rGe1567e771b89: [docs] Fix typos in the 'CodeGenerator' doc (authored by JOE1994, committed by myhsu). · Explain Why

This revision was automatically updated to reflect the committed changes.

myhsu added a commit: rGe1567e771b89: [docs] Fix typos in the 'CodeGenerator' doc.

Revision Contents

Path

Size

llvm/

docs/

CodeGenerator.rst

4 lines

Diff 424623

llvm/docs/CodeGenerator.rst

	Show First 20 Lines • Show All 504 Lines • ▼ Show 20 Lines
	.. _MachineFunction:			.. _MachineFunction:

	The ``MachineFunction`` class			The ``MachineFunction`` class
	-----------------------------			-----------------------------

	The ``MachineFunction`` class contains a list of machine basic blocks			The ``MachineFunction`` class contains a list of machine basic blocks
	(:raw-html:`<tt>` `MachineBasicBlock`_ :raw-html:`</tt>` instances). It			(:raw-html:`<tt>` `MachineBasicBlock`_ :raw-html:`</tt>` instances). It
	corresponds one-to-one with the LLVM function input to the instruction selector.			corresponds one-to-one with the LLVM function input to the instruction selector.
	In addition to a list of basic blocks, the ``MachineFunction`` contains a a			In addition to a list of basic blocks, the ``MachineFunction`` contains a
	``MachineConstantPool``, a ``MachineFrameInfo``, a ``MachineFunctionInfo``, and			``MachineConstantPool``, a ``MachineFrameInfo``, a ``MachineFunctionInfo``, and
	a ``MachineRegisterInfo``. See ``include/llvm/CodeGen/MachineFunction.h`` for			a ``MachineRegisterInfo``. See ``include/llvm/CodeGen/MachineFunction.h`` for
	more information.			more information.

	``MachineInstr Bundles``			``MachineInstr Bundles``
	------------------------			------------------------

	LLVM code generator can model sequences of instructions as MachineInstr			LLVM code generator can model sequences of instructions as MachineInstr
	▲ Show 20 Lines • Show All 1,756 Lines • ▼ Show 20 Lines

	Some operating systems and runtime environments use (or may in the future use)			Some operating systems and runtime environments use (or may in the future use)
	the FS/GS-segment registers for various low-level purposes, so care should be			the FS/GS-segment registers for various low-level purposes, so care should be
	taken when considering them.			taken when considering them.

	Instruction naming			Instruction naming
	^^^^^^^^^^^^^^^^^^			^^^^^^^^^^^^^^^^^^

	An instruction name consists of the base name, a default operand size, and a a			An instruction name consists of the base name, a default operand size, and a
	character per operand with an optional special size. For example:			character per operand with an optional special size. For example:

	::			::

	ADD8rr -> add, 8-bit register, 8-bit register			ADD8rr -> add, 8-bit register, 8-bit register
	IMUL16rmi -> imul, 16-bit register, 16-bit memory, 16-bit immediate			IMUL16rmi -> imul, 16-bit register, 16-bit memory, 16-bit immediate
	IMUL16rmi8 -> imul, 16-bit register, 16-bit memory, 8-bit immediate			IMUL16rmi8 -> imul, 16-bit register, 16-bit memory, 8-bit immediate
	MOVSX32rm16 -> movsx, 32-bit register, 16-bit memory			MOVSX32rm16 -> movsx, 32-bit register, 16-bit memory
	▲ Show 20 Lines • Show All 415 Lines • Show Last 20 Lines