[NVPTX] Support float <-> 2 x half bitcasts

[jchlanda]

Summary

Make sure NVPTX backend can handle bitcasting between float and <2 x half> types.

This was discovered through: https://github.com/intel/llvm/issues/5969
I'm not suggesting that such bitcasts make much sense, but it feels like the compiler should not hard crash on them.

[tra]

Thank you for the fix.

The source code which triggered this issue is full of type-puns, but I guess the user should be allowed to shoot one's foot if they really want to. I can only wish them good luck if LLVM/ptxas or hardware decides to flush fp32 value to zero if the bitpattern created by two fp16 values results in a denormal fp32. The funny thing is that their data is originally stored as an array of scalars. They didn't have to use float as an intermediate value.

[jchlanda]

@tra would you be so kind and merge it in for me please?

llvm/lib/Target/NVPTX/NVPTXInstrInfo.td

 def BITCONVERT_16_I2F : F_BITCONVERT<"16", Int16Regs, Float16Regs>;
 def BITCONVERT_16_F2I : F_BITCONVERT<"16", Float16Regs, Int16Regs>;
 def BITCONVERT_32_I2F : F_BITCONVERT<"32", Int32Regs, Float32Regs>;
 def BITCONVERT_32_F2I : F_BITCONVERT<"32", Float32Regs, Int32Regs>;
 def BITCONVERT_64_I2F : F_BITCONVERT<"64", Int64Regs, Float64Regs>;
 def BITCONVERT_64_F2I : F_BITCONVERT<"64", Float64Regs, Int64Regs>;
 def BITCONVERT_32_I2F16x2 : F_BITCONVERT<"32", Int32Regs, Float16x2Regs>;
 def BITCONVERT_32_F16x22I : F_BITCONVERT<"32", Float16x2Regs, Int32Regs>;
+def BITCONVERT_32_F2F16x2 : F_BITCONVERT<"32", Float32Regs, Float16x2Regs>;
+def BITCONVERT_32_F16x22F : F_BITCONVERT<"32", Float16x2Regs, Float32Regs>;
 
 // NOTE: pred->fp are currently sub-optimal due to an issue in TableGen where
 // we cannot specify floating-point literals in isel patterns.  Therefore, we
 // use an integer selp to select either 1 or 0 and then cvt to floating-point.
 
 // sint -> f16
 def : Pat<(f16 (sint_to_fp Int1Regs:$a)),
           (CVT_f16_s32 (SELP_u32ii 1, 0, Int1Regs:$a), CvtRN)>;

llvm/test/CodeGen/NVPTX/f16x2-instructions.ll

 ; CHECK:      mov.b32         [[R:%hh[0-9]+]], [[R1H0L]];
 ; CHECK:      st.param.b32    [func_retval0+0], [[R]];
 ; CHECK:      ret;
 define <2 x half> @test_bitcast_2xi16_to_2xhalf(<2 x i16> %a) #0 {
   %r = bitcast <2 x i16> %a to <2 x half>
   ret <2 x half> %r
 }
 
+; CHECK-LABEL: test_bitcast_float_to_2xhalf(
+; CHECK: ld.param.f32   [[AF1:%f[0-9]+]], [test_bitcast_float_to_2xhalf_param_0];
+; CHECK: mov.b32  [[R:%hh[0-9]+]], [[AF1]];
+; CHECK: st.param.b32   [func_retval0+0], [[R]];
+; CHECK: ret;
+define <2 x half> @test_bitcast_float_to_2xhalf(float %a) #0 {
+  %r = bitcast float %a to <2 x half>
+  ret <2 x half> %r
+}
+
+; CHECK-LABEL: test_bitcast_2xhalf_to_float(
+; CHECK: ld.param.u32   [[R:%r[0-9]+]], [test_bitcast_2xhalf_to_float_param_0];
+; CHECK: mov.b32  [[AF1:%f[0-9]+]], [[R]];
+; CHECK: st.param.f32   [func_retval0+0], [[AF1]];
+; CHECK: ret;
+define float @test_bitcast_2xhalf_to_float(<2 x half> %a) #0 {
+  %r = bitcast <2 x half> %a to float
+  ret float %r
+}
 
 declare <2 x half> @llvm.sqrt.f16(<2 x half> %a) #0
 declare <2 x half> @llvm.powi.f16.i32(<2 x half> %a, <2 x i32> %b) #0
 declare <2 x half> @llvm.sin.f16(<2 x half> %a) #0
 declare <2 x half> @llvm.cos.f16(<2 x half> %a) #0
 declare <2 x half> @llvm.pow.f16(<2 x half> %a, <2 x half> %b) #0
 declare <2 x half> @llvm.exp.f16(<2 x half> %a) #0
 declare <2 x half> @llvm.exp2.f16(<2 x half> %a) #0