AMDGPU: Fix assert if v_mov_b32_dpp is last instruction in the block

[arsenm]

Summary

Fixes issue 49961

[foad]

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

8073

It would be more in keeping with the original design to just exclude PHI instructions here. The assumption is that all the uses counted in NumUse will necessarily come after DefMI in the same BB, so the second loop below will always terminate before hitting the end of the BB.

[arsenm]

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

8073

That's a bit too clever for me. I'd rather just have normal looking end iterator checks

[foad]

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

8073

One argument in favour of the clever version is that you never have to run all the way to end(), which could be a long way away in a pathologically large basic block.

[arsenm]

Check if phi

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

8073

This already has a MaxInstScan to avoid pathological blocks

[foad]

Thanks.

[arsenm]

c528fbf8824b5004f9ff895de392ef731644edea

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

bool llvm::execMayBeModifiedBeforeAnyUse(const MachineRegisterInfo &MRI,
 
   const int MaxUseScan = 10;
   int NumUse = 0;
 
   for (auto &Use : MRI.use_nodbg_operands(VReg)) {
     auto &UseInst = *Use.getParent();
     // Don't bother searching between blocks, although it is possible this block
     // doesn't modify exec.
-    if (UseInst.getParent() != DefBB)
+    if (UseInst.getParent() != DefBB || UseInst.isPHI())
       return true;
 
     if (++NumUse > MaxUseScan)
       return true;
   }
 
   if (NumUse == 0)
     return false;

llvm/test/CodeGen/AMDGPU/dpp_combine.mir

bb.0:
     %0:vreg_64 = COPY $vgpr0_vgpr1
     %1:vreg_64 = COPY $vgpr2_vgpr3
     %2:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 15, 15, 1, implicit $exec
     %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 15, 15, 1, implicit $exec
     %4:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1
     %5:vgpr_32 = V_ADD_CO_U32_e32 %4.sub0, %4.sub0, implicit-def $vcc, implicit $exec
     %6:vgpr_32 = V_ADDC_U32_e32 %4.sub1, %4.sub1, implicit-def $vcc, implicit $vcc, implicit $exec
 ...
+
+# execMayBeModifiedBeforeAnyUse used to assert if the queried
+# V_MOV_B32_dpp was the last instruction in the block.
+---
+name:            mov_dpp_last_block_inst
+tracksRegLiveness: true
+body:             |
+  ; GCN-LABEL: name: mov_dpp_last_block_inst
+  ; GCN: bb.0:
+  ; GCN-NEXT:   successors: %bb.1(0x80000000)
+  ; GCN-NEXT:   liveins: $vgpr0, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8
+  ; GCN-NEXT: {{  $}}
+  ; GCN-NEXT:   [[COPY:%[0-9]+]]:sgpr_32 = COPY $sgpr8
+  ; GCN-NEXT:   [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+  ; GCN-NEXT:   [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+  ; GCN-NEXT:   [[DEF2:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
+  ; GCN-NEXT: {{  $}}
+  ; GCN-NEXT: bb.1:
+  ; GCN-NEXT:   successors: %bb.2(0x80000000)
+  ; GCN-NEXT: {{  $}}
+  ; GCN-NEXT:   [[PHI:%[0-9]+]]:vgpr_32 = PHI [[DEF]], %bb.0, %5, %bb.2
+  ; GCN-NEXT:   [[V_MOV_B32_dpp:%[0-9]+]]:vgpr_32 = V_MOV_B32_dpp [[DEF]], [[PHI]], 323, 15, 15, 0, implicit $exec
+  ; GCN-NEXT: {{  $}}
+  ; GCN-NEXT: bb.2:
+  ; GCN-NEXT:   successors: %bb.1(0x40000000), %bb.3(0x40000000)
+  ; GCN-NEXT: {{  $}}
+  ; GCN-NEXT:   [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[DEF2]], implicit $exec
+  ; GCN-NEXT:   V_CMP_NE_U32_e32 1, [[V_CNDMASK_B32_e64_]], implicit-def $vcc, implicit $exec
+  ; GCN-NEXT:   S_CBRANCH_VCCNZ %bb.1, implicit $vcc
+  ; GCN-NEXT:   S_BRANCH %bb.3
+  ; GCN-NEXT: {{  $}}
+  ; GCN-NEXT: bb.3:
+  ; GCN-NEXT:   S_ENDPGM 0
+  bb.0:
+    liveins: $vgpr0, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8
+
+    %0:sgpr_32 = COPY $sgpr8
+    %1:vgpr_32 = IMPLICIT_DEF
+    %2:sreg_32 = IMPLICIT_DEF
+    %3:sreg_64_xexec = IMPLICIT_DEF
+
+  bb.1:
+    %4:vgpr_32 = PHI %1, %bb.0, %5, %bb.2
+    %5:vgpr_32 = V_MOV_B32_dpp %1, %4, 323, 15, 15, 0, implicit $exec
+
+  bb.2:
+    %6:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %3, implicit $exec
+    V_CMP_NE_U32_e32 1, %6, implicit-def $vcc, implicit $exec
+    S_CBRANCH_VCCNZ %bb.1, implicit $vcc
+    S_BRANCH %bb.3
+
+  bb.3:
+    S_ENDPGM 0
+
+...