[AArch64] Update tests with the `update_llc_test_checks.py` script (NFC)

llvm/test/CodeGen/AArch64/adc.ll

-; RUN: llc -verify-machineinstrs < %s -mtriple=arm64-apple-ios7.0 | FileCheck --check-prefix=CHECK --check-prefix=CHECK-LE %s
-; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64_be-none-linux-gnu | FileCheck --check-prefix=CHECK --check-prefix=CHECK-BE %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs < %s -mtriple=arm64-apple-ios7.0 | FileCheck --check-prefix=CHECK-LE %s
+; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64_be-none-linux-gnu | FileCheck --check-prefix=CHECK-BE %s
 
 define i128 @test_simple(i128 %a, i128 %b, i128 %c) {
-; CHECK-LABEL: test_simple:
+; CHECK-LE-LABEL: test_simple:
+; CHECK-LE:       ; %bb.0:
+; CHECK-LE-NEXT:    adds x8, x0, x2
+; CHECK-LE-NEXT:    adcs x9, x1, x3
+; CHECK-LE-NEXT:    subs x0, x8, x4
+; CHECK-LE-NEXT:    sbcs x1, x9, x5
+; CHECK-LE-NEXT:    ret
+;
+; CHECK-BE-LABEL: test_simple:
+; CHECK-BE:       // %bb.0:
+; CHECK-BE-NEXT:    adds x8, x1, x3
+; CHECK-BE-NEXT:    adcs x9, x0, x2
+; CHECK-BE-NEXT:    subs x1, x8, x5
+; CHECK-BE-NEXT:    sbcs x0, x9, x4
+; CHECK-BE-NEXT:    ret
 
   %valadd = add i128 %a, %b
-; CHECK-LE: adds [[ADDLO:x[0-9]+]], x0, x2
-; CHECK-LE-NEXT: adcs [[ADDHI:x[0-9]+]], x1, x3
-; CHECK-BE: adds [[ADDLO:x[0-9]+]], x1, x3
-; CHECK-BE-NEXT: adcs [[ADDHI:x[0-9]+]], x0, x2
 
   %valsub = sub i128 %valadd, %c
-; CHECK-LE: subs x0, [[ADDLO]], x4
-; CHECK-LE: sbcs x1, [[ADDHI]], x5
-; CHECK-BE: subs x1, [[ADDLO]], x5
-; CHECK-BE: sbcs x0, [[ADDHI]], x4
 
   ret i128 %valsub
-; CHECK: ret
 }
 
 define i128 @test_imm(i128 %a) {
-; CHECK-LABEL: test_imm:
+; CHECK-LE-LABEL: test_imm:
+; CHECK-LE:       ; %bb.0:
+; CHECK-LE-NEXT:    adds x0, x0, #12
+; CHECK-LE-NEXT:    adcs x1, x1, xzr
+; CHECK-LE-NEXT:    ret
+;
+; CHECK-BE-LABEL: test_imm:
+; CHECK-BE:       // %bb.0:
+; CHECK-BE-NEXT:    adds x1, x1, #12
+; CHECK-BE-NEXT:    adcs x0, x0, xzr
+; CHECK-BE-NEXT:    ret
 
   %val = add i128 %a, 12
-; CHECK-LE: adds x0, x0, #12
-; CHECK-LE: adcs x1, x1, {{x[0-9]|xzr}}
-; CHECK-BE: adds x1, x1, #12
-; CHECK-BE: adcs x0, x0, {{x[0-9]|xzr}}
 
   ret i128 %val
-; CHECK: ret
 }
 
 define i128 @test_shifted(i128 %a, i128 %b) {
-; CHECK-LABEL: test_shifted:
+; CHECK-LE-LABEL: test_shifted:
+; CHECK-LE:       ; %bb.0:
+; CHECK-LE-NEXT:    extr x8, x3, x2, #19
+; CHECK-LE-NEXT:    adds x0, x0, x2, lsl #45
+; CHECK-LE-NEXT:    adcs x1, x1, x8
+; CHECK-LE-NEXT:    ret
+;
+; CHECK-BE-LABEL: test_shifted:
+; CHECK-BE:       // %bb.0:
+; CHECK-BE-NEXT:    extr x8, x2, x3, #19
+; CHECK-BE-NEXT:    adds x1, x1, x3, lsl #45
+; CHECK-BE-NEXT:    adcs x0, x0, x8
+; CHECK-BE-NEXT:    ret
 
   %rhs = shl i128 %b, 45
 
   %val = add i128 %a, %rhs
-; CHECK-LE: adds x0, x0, x2, lsl #45
-; CHECK-LE: adcs x1, x1, {{x[0-9]}}
-; CHECK-BE: adds x1, x1, x3, lsl #45
-; CHECK-BE: adcs x0, x0, {{x[0-9]}}
 
   ret i128 %val
-; CHECK: ret
 }
 
 define i128 @test_extended(i128 %a, i16 %b) {
-; CHECK-LABEL: test_extended:
+; CHECK-LE-LABEL: test_extended:
+; CHECK-LE:       ; %bb.0:
+; CHECK-LE-NEXT:    ; kill: def $w2 killed $w2 def $x2
+; CHECK-LE-NEXT:    sxth x8, w2
+; CHECK-LE-NEXT:    adds x0, x0, w2, sxth #3
+; CHECK-LE-NEXT:    asr x9, x8, #63
+; CHECK-LE-NEXT:    extr x8, x9, x8, #61
+; CHECK-LE-NEXT:    adcs x1, x1, x8
+; CHECK-LE-NEXT:    ret
+;
+; CHECK-BE-LABEL: test_extended:
+; CHECK-BE:       // %bb.0:
+; CHECK-BE-NEXT:    // kill: def $w2 killed $w2 def $x2
+; CHECK-BE-NEXT:    sxth x8, w2
+; CHECK-BE-NEXT:    adds x1, x1, w2, sxth #3
+; CHECK-BE-NEXT:    asr x9, x8, #63
+; CHECK-BE-NEXT:    extr x8, x9, x8, #61
+; CHECK-BE-NEXT:    adcs x0, x0, x8
+; CHECK-BE-NEXT:    ret
 
   %ext = sext i16 %b to i128
   %rhs = shl i128 %ext, 3
 
   %val = add i128 %a, %rhs
-; CHECK-LE: adds x0, x0, w2, sxth #3
-; CHECK-LE: adcs x1, x1, {{x[0-9]}}
-; CHECK-BE: adds x1, x1, w2, sxth #3
-; CHECK-BE: adcs x0, x0, {{x[0-9]}}
 
   ret i128 %val
-; CHECK: ret
 }

llvm/test/CodeGen/AArch64/addcarry-crash.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s | FileCheck %s
 target triple = "arm64-apple-ios7.0"
 
 define i64 @foo(i64* nocapture readonly %ptr, i64 %a, i64 %b, i64 %c) local_unnamed_addr #0 {
-; CHECK: ldr     w8, [x0, #4]
-; CHECK: lsr     x9, x1, #32
-; CHECK: cmn             x3, x2
-; CHECK: mul             x8, x8, x9
-; CHECK: cinc     x0, x8, hs
-; CHECK: ret
+; CHECK-LABEL: foo:
+; CHECK:       ; %bb.0: ; %entry
+; CHECK-NEXT:    ldr w8, [x0, #4]
+; CHECK-NEXT:    lsr x9, x1, #32
+; CHECK-NEXT:    cmn x3, x2
+; CHECK-NEXT:    mul x8, x8, x9
+; CHECK-NEXT:    cinc x0, x8, hs
+; CHECK-NEXT:    ret
 entry:
   %0 = lshr i64 %a, 32
   %1 = load i64, i64* %ptr, align 8
   %2 = lshr i64 %1, 32
   %3 = mul nuw i64 %2, %0
   %4 = add i64 %c, %b
   %5 = icmp ult i64 %4, %c
   %6 = zext i1 %5 to i64
   %7 = add i64 %3, %6
   ret i64 %7
 }
 
 attributes #0 = { norecurse nounwind readonly }

llvm/test/CodeGen/AArch64/nzcv-save.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-eabi | FileCheck %s
 
-; CHECK: mrs [[NZCV_SAVE:x[0-9]+]], NZCV
-; CHECK: msr NZCV, [[NZCV_SAVE]]
-
 ; DAG ends up with two uses for the flags from an ADCS node, which means they
 ; must be saved for later.
 define void @f(i256* nocapture %a, i256* nocapture %b, i256* nocapture %cc, i256* nocapture %dd) nounwind uwtable noinline ssp {
+; CHECK-LABEL: f:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    ldp x9, x8, [x2]
+; CHECK-NEXT:    ldp x11, x10, [x3]
+; CHECK-NEXT:    adds x9, x9, x11
+; CHECK-NEXT:    ldp x12, x11, [x2, #16]
+; CHECK-NEXT:    adcs x8, x8, x10
+; CHECK-NEXT:    ldp x13, x10, [x3, #16]
+; CHECK-NEXT:    adcs x12, x12, x13
+; CHECK-NEXT:    mrs x13, NZCV
+; CHECK-NEXT:    adcs x14, x11, x10
+; CHECK-NEXT:    orr x11, x11, #0x100
+; CHECK-NEXT:    msr NZCV, x13
+; CHECK-NEXT:    stp x9, x8, [x0]
+; CHECK-NEXT:    adcs x10, x11, x10
+; CHECK-NEXT:    stp x12, x14, [x0, #16]
+; CHECK-NEXT:    stp x9, x8, [x1]
+; CHECK-NEXT:    stp x12, x10, [x1, #16]
+; CHECK-NEXT:    ret
 entry:
   %c = load i256, i256* %cc
   %d = load i256, i256* %dd
   %add = add nsw i256 %c, %d
   store i256 %add, i256* %a, align 8
   %or = or i256 %c, 1606938044258990275541962092341162602522202993782792835301376
   %add6 = add nsw i256 %or, %d
   store i256 %add6, i256* %b, align 8
   ret void
 }