MachineVerifier: Diagnose undef set on full register defs

[arsenm]

Summary

An undef def of a full register would assert in LiveIntervalCalc.

[arsenm]

634bf829a8d289371d5b5a50b787596124228898

llvm/lib/CodeGen/MachineVerifier.cpp

case MachineOperand::MO_Register: {
     }
 
     const Register Reg = MO->getReg();
     if (!Reg)
       return;
     if (MRI->tracksLiveness() && !MI->isDebugInstr())
       checkLiveness(MO, MONum);
 
+    if (MO->isDef() && MO->isUndef() && !MO->getSubReg() &&
+        MO->getReg().isVirtual()) // TODO: Apply to physregs too
+      report("Undef virtual register def operands require a subregister", MO, MONum);
+
     // Verify the consistency of tied operands.
     if (MO->isTied()) {
       unsigned OtherIdx = MI->findTiedOperandIdx(MONum);
       const MachineOperand &OtherMO = MI->getOperand(OtherIdx);
       if (!OtherMO.isReg())
         report("Must be tied to a register", MO, MONum);
       if (!OtherMO.isTied())
         report("Missing tie flags on tied operand", MO, MONum);

llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir

bb.0:
     RET undef $lr
 ...
 ---
 # Make sure we do not pick a register marked as undef for renaming.
 #
 # CHECK-LABEL: name: test15_undef_op
 # CHECK: bb.0:
 # CHECK-NEXT: liveins: $x0, $x1, $x8
-# CHECK:       undef renamable $x10, $x11 = LDPXi renamable $x0, 0 :: (load (s64))
+# CHECK:       renamable $x10, $x11 = LDPXi renamable $x0, 0 :: (load (s64))
 # CHECK-NEXT:  renamable $x9 = LDRXui renamable $x0, 1 :: (load (s64))
 # CHECK-NEXT:  STRXui renamable $x9, renamable $x0, 100 :: (store (s64), align 4)
 # CHECK-NEXT:  renamable $x10 = ADDXrr $x10, $x10
 # CHECK-NEXT:  STPXi renamable $x10, killed $x11, renamable $x0, 10 :: (store (s64), align 4)
 # CHECK-NEXT:  RET undef $lr
 #
 name:            test15_undef_op
 alignment:       4
 tracksRegLiveness: true
 liveins:
   - { reg: '$x0' }
   - { reg: '$x1' }
   - { reg: '$x8' }
 frameInfo:
   maxAlignment:    1
   maxCallFrameSize: 0
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $x0, $x1, $x8
-    renamable undef $x10, renamable $x9 = LDPXi renamable $x0, 0 :: (load (s64))
+    renamable $x10, renamable $x9 = LDPXi renamable $x0, 0 :: (load (s64))
     STRXui renamable killed $x9, renamable $x0, 11 :: (store (s64), align 4)
     renamable $x9 = LDRXui renamable $x0, 1 :: (load (s64))
     STRXui renamable $x9, renamable $x0, 100 :: (store (s64), align 4)
     renamable $x10 = ADDXrr $x10, $x10
     STRXui renamable $x10, renamable $x0, 10 :: (store (s64), align 4)
     RET undef $lr
 
 ...

llvm/test/DebugInfo/MIR/X86/live-debug-values.mir

bb.0.entry:
     CFI_INSTRUCTION offset $rbx, -16
     DBG_VALUE $edi, _, !12, !20, debug-location !21
     DBG_VALUE $rsi, _, !13, !20, debug-location !22
     $eax = MOV32rr $edi
     DBG_VALUE $eax, _, !12, !20, debug-location !21
     $edi = MOV32ri 2
     CMP32ri8 killed $eax, 2, implicit-def $eflags, debug-location !26
     JCC_1 %bb.2.if.end, 5, implicit $eflags
-  
   bb.1.if.else:
     successors: %bb.2.if.end(0)
     liveins: $rsi
-  
     DBG_VALUE $rsi, _, !13, !20, debug-location !22
     $rdi = MOV64rm killed $rsi, 1, _, 8, _, debug-location !27 :: (load (s64) from %ir.arrayidx, !tbaa !28)
     dead $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags, implicit-def $al, debug-location !32
     CALL64pcrel32 @atoi, csr_64, implicit $rsp, implicit $rdi, implicit $al, implicit-def $rsp, implicit-def $eax, debug-location !32
     $edi = MOV32rr $eax, debug-location !32
     DBG_VALUE $edi, _, !14, !20, debug-location !33
-  
   bb.2.if.end:
     successors: %bb.3.if.then.3(16), %bb.4.if.else.5(16)
     liveins: $edi
-  
     CALL64pcrel32 @change, csr_64, implicit $rsp, implicit $edi, implicit-def $rsp, implicit-def $eax, debug-location !34
     $ebx = MOV32rr $eax, debug-location !34
     DBG_VALUE $ebx, _, !14, !20, debug-location !33
     CMP32ri8 $ebx, 11, implicit-def $eflags, debug-location !37
     JCC_1 %bb.4.if.else.5, 12, implicit killed $eflags, debug-location !37
-  
   bb.3.if.then.3:
     successors: %bb.5.if.end.7(0)
     liveins: $ebx
-  
     DBG_VALUE $ebx, _, !14, !20, debug-location !33
     $edi = MOV32rr $ebx, debug-location !38
     CALL64pcrel32 @modify, csr_64, implicit $rsp, implicit $edi, implicit-def $rsp, implicit-def $eax, debug-location !38
     $ecx = MOV32rr $eax, debug-location !38
     $ecx = ADD32rr killed $ecx, killed $ebx, implicit-def dead $eflags, debug-location !40
     JMP_1 %bb.5.if.end.7
-  
   bb.4.if.else.5:
     successors: %bb.5.if.end.7(0)
     liveins: $ebx
-  
     DBG_VALUE $ebx, _, !14, !20, debug-location !33
     $edi = MOV32rr killed $ebx, debug-location !42
     CALL64pcrel32 @inc, csr_64, implicit $rsp, implicit $edi, implicit-def $rsp, implicit-def $eax, debug-location !42
     $ecx = MOV32rr $eax, debug-location !42
-  
   bb.5.if.end.7:
     liveins: $ecx
-  
     MOV32mr $rip, 1, _, @m, _, $ecx, debug-location !43 :: (store (s32) into @m, !tbaa !44)
-    dead undef $edi = MOV32ri @.str, implicit-def $rdi, debug-location !46
+    dead $edi = MOV32ri @.str, implicit-def $rdi, debug-location !46
     dead $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags, implicit-def $al, debug-location !47
     $esi = MOV32rr killed $ecx, debug-location !46
     CALL64pcrel32 @printf, csr_64, implicit $rsp, implicit $rdi, implicit $esi, implicit $al, implicit-def $rsp, implicit-def dead $eax, debug-location !46
     $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags, debug-location !47
     $rbx = POP64r implicit-def $rsp, implicit $rsp, debug-location !47
     RET64 $eax, debug-location !47
 
 ...

llvm/test/MachineVerifier/undef-should-only-be-set-on-subreg-defs.mir

+# REQUIRES: amdgpu-registered-target
+# RUN: not --crash llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=none -o /dev/null %s 2>&1 | FileCheck %s
+
+---
+name: undef_reg_def
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    ; CHECK: *** Bad machine code: Undef def operands require a subregister ***
+    undef %0:sreg_64 = S_MOV_B64 0
+
+    ; CHECK: *** Bad machine code: Undef def operands require a subregister ***
+    S_NOP 0, implicit-def undef %1:sreg_64
+    S_ENDPGM 0, implicit %0.sub0, implicit %0.sub1
+
+...