[X86] Simplify the interface to getCondNoFromDesc.

[craig.topper]

Summary

Instead of taking a SkipDefs parameter, rename to getCondSrcNoFromDesc
and have it return the source operand number. Make getCondFromMI
responsible for adding the number of Defs for MI instructions.

While there remove some unneeded casts to unsigned and check for
negative numbers instead of explicitly -1. Less than 0 is easier
for a compiler to codegen.

[skan]

llvm/lib/Target/X86/X86InstrInfo.cpp

2593

Keep the comments here?

2606

Did you get an warning from compiler when removing this static_cast?

[craig.topper]

Add back comment.

[craig.topper]

llvm/lib/Target/X86/X86InstrInfo.cpp

2606

I didn't get any warning and this isn't the only place in tree we pass int to getOperand.

[skan]

Looks great!

llvm/lib/Target/X86/X86ISelDAGToDAG.cpp

bool X86DAGToDAGISel::isSExtAbsoluteSymbolRef(unsigned Width, SDNode *N) const {
   return CR->getSignedMin().sge(-1ull << Width) &&
          CR->getSignedMax().slt(1ull << Width);
 }
 
 X86::CondCode X86DAGToDAGISel::getCondFromNode(SDNode *N) const {
   assert(N->isMachineOpcode() && "Unexpected node");
   unsigned Opc = N->getMachineOpcode();
   const MCInstrDesc &MCID = getInstrInfo()->get(Opc);
-  int CondNo = X86::getCondNoFromDesc(MCID, /*SkipDefs=*/true);
-  if (CondNo == -1)
+  int CondNo = X86::getCondSrcNoFromDesc(MCID);
+  if (CondNo < 0)
     return X86::COND_INVALID;
 
-  return static_cast<X86::CondCode>(
-      N->getConstantOperandVal(static_cast<unsigned>(CondNo)));
+  return static_cast<X86::CondCode>(N->getConstantOperandVal(CondNo));
 }
 
 /// Test whether the given X86ISD::CMP node has any users that use a flag
 /// other than ZF.
 bool X86DAGToDAGISel::onlyUsesZeroFlag(SDValue Flags) const {
   // Examine each user of the node.
   for (SDNode::use_iterator UI = Flags->use_begin(), UE = Flags->use_end();
          UI != UE; ++UI) {

llvm/lib/Target/X86/X86InstrInfo.h

 
 /// Return a pair of condition code for the given predicate and whether
 /// the instruction operands should be swaped to match the condition code.
 std::pair<CondCode, bool> getX86ConditionCode(CmpInst::Predicate Predicate);
 
 /// Return a cmov opcode for the given register size in bytes, and operand type.
 unsigned getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand = false);
 
-/// Return the operand # for condition code by \p MCID. If
-/// the instruction doesn't have a condition code, return -1.
-int getCondNoFromDesc(const MCInstrDesc &MCID, bool SkipDefs = false);
+/// Return the source operand # for condition code by \p MCID. If the
+/// instruction doesn't have a condition code, return -1.
+int getCondSrcNoFromDesc(const MCInstrDesc &MCID);
 
-/// Return the condition code of the instruction. If the instruction doesn't have a condition code,
-/// return X86::COND_INVALID.
+/// Return the condition code of the instruction. If the instruction doesn't
+/// have a condition code, return X86::COND_INVALID.
 CondCode getCondFromMI(const MachineInstr &MI);
 
 // Turn JCC instruction into condition code.
 CondCode getCondFromBranch(const MachineInstr &MI);
 
 // Turn SETCC instruction into condition code.
 CondCode getCondFromSETCC(const MachineInstr &MI);
 

llvm/lib/Target/X86/X86InstrInfo.cpp

if (isConvertibleLEA(Inst) && Inst->getParent() == MI.getParent()) {
       Commute = false;
       return true;
     }
   }
 
   return false;
 }
 
-int X86::getCondNoFromDesc(const MCInstrDesc &MCID, bool SkipDefs) {
+int X86::getCondSrcNoFromDesc(const MCInstrDesc &MCID) {
   unsigned Opcode = MCID.getOpcode();
   if (!(X86::isJCC(Opcode) || X86::isSETCC(Opcode) || X86::isCMOVCC(Opcode)))
     return -1;
-  unsigned NumOperands = MCID.getNumOperands();
-  unsigned NumDefs = MCID.getNumDefs();
-  // Assume that condition code is always the last operand
-  unsigned CondNo = NumOperands - 1;
-  if (SkipDefs)
-    return CondNo - NumDefs;
-  return CondNo;
+  // Assume that condition code is always the last use operand.
+  unsigned NumUses = MCID.getNumOperands() - MCID.getNumDefs();
+  return NumUses - 1;
 }
 
 X86::CondCode X86::getCondFromMI(const MachineInstr &MI) {
   const MCInstrDesc &MCID = MI.getDesc();
-  int CondNo = getCondNoFromDesc(MCID);
-  if (CondNo == -1)
+  int CondNo = getCondSrcNoFromDesc(MCID);
+  if (CondNo < 0)
     return X86::COND_INVALID;
-  return static_cast<X86::CondCode>(
-      MI.getOperand(static_cast<unsigned>(CondNo)).getImm());
+  CondNo += MCID.getNumDefs();
+  return static_cast<X86::CondCode>(MI.getOperand(CondNo).getImm());
 }
 
 X86::CondCode X86::getCondFromBranch(const MachineInstr &MI) {
   return X86::isJCC(MI.getOpcode()) ? X86::getCondFromMI(MI)
                                     : X86::COND_INVALID;
 }
 
 X86::CondCode X86::getCondFromSETCC(const MachineInstr &MI) {