[InstCombine] Add general constant support to eq/ne icmp(add(X,C1),add(Y,C2)) -> icmp(add(X,C1-C2),Y) fold

[RKSimon]

Summary

A further extension for Issue #32161

For eq/ne comparisons - the sign mismatch and bounds constraints are redundant, so if the that fold fails, fallback and just fold the constants directly.

https://alive2.llvm.org/ce/z/cdodNQ

The loop rotation test change looks mostly benign - the backend doesn't seem to suffer? https://gcc.godbolt.org/z/dErMY78To

[nikic]

llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp

4138

ImmConstant?

[lebedev.ri]

I guess this looks good other than the constantexpr question.

llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp

4142

Bikeshedding: is the phaseordering test affected similarly if you "swap" A and C,
in other words, do we have transforms elsewhere to move such computations out of loop body?

[RKSimon]

llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp

4138

I guess I should add constexpr tests

[RKSimon]

Use m_ImmConstant

[RKSimon]

llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp

4142

It makes no difference - I checked if we could handle this by using the oneuse binop but that had on effect either.

[lebedev.ri]

Seems good to me.

llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp

if (match(B, m_APIntAllowUndef(AP1)) && match(D, m_APIntAllowUndef(AP2)) &&
         APInt Diff = *AP2 - *AP1;
         bool HasNUW = BO1->hasNoUnsignedWrap() && Diff.ule(*AP2);
         bool HasNSW = BO1->hasNoSignedWrap();
         Constant *C3 = Constant::getIntegerValue(BO0->getType(), Diff);
         Value *NewAdd = Builder.CreateAdd(C, C3, "", HasNUW, HasNSW);
         return new ICmpInst(Pred, A, NewAdd);
       }
     }
+    Constant *Cst1, *Cst2;
+    if (match(B, m_ImmConstant(Cst1)) && match(D, m_ImmConstant(Cst2)) &&
+        ICmpInst::isEquality(Pred)) {
+      Constant *Diff = ConstantExpr::getSub(Cst2, Cst1);
+      Value *NewAdd = Builder.CreateAdd(C, Diff);
+      return new ICmpInst(Pred, A, NewAdd);
+    }
   }
 
   // Analyze the case when either Op0 or Op1 is a sub instruction.
   // Op0 = A - B (or A and B are null); Op1 = C - D (or C and D are null).
   A = nullptr;
   B = nullptr;
   C = nullptr;
   D = nullptr;

llvm/test/Transforms/InstCombine/icmp.ll

;
   %1 = add <2 x i32> %x, <i32 20, i32 20>
   %2 = add <2 x i32> %y, <i32 57, i32 undef>
   %cmp = icmp eq <2 x i32> %1, %2
   ret <2 x i1> %cmp
 }
 
 define <2 x i1> @icmp_add20_eq_add57_vec_nonsplat(<2 x i32> %x, <2 x i32> %y) {
 ; CHECK-LABEL: @icmp_add20_eq_add57_vec_nonsplat(
-; CHECK-NEXT:    [[TMP1:%.*]] = add <2 x i32> [[X:%.*]], <i32 20, i32 19>
-; CHECK-NEXT:    [[TMP2:%.*]] = add <2 x i32> [[Y:%.*]], <i32 57, i32 58>
-; CHECK-NEXT:    [[CMP:%.*]] = icmp eq <2 x i32> [[TMP1]], [[TMP2]]
+; CHECK-NEXT:    [[TMP1:%.*]] = add <2 x i32> [[Y:%.*]], <i32 37, i32 39>
+; CHECK-NEXT:    [[CMP:%.*]] = icmp eq <2 x i32> [[TMP1]], [[X:%.*]]
 ; CHECK-NEXT:    ret <2 x i1> [[CMP]]
 ;
   %1 = add <2 x i32> %x, <i32 20, i32 19>
   %2 = add <2 x i32> %y, <i32 57, i32 58>
   %cmp = icmp eq <2 x i32> %1, %2
   ret <2 x i1> %cmp
 }
 
;
   %1 = add <2 x i32> %x, <i32 -57, i32 undef>
   %2 = add <2 x i32> %y, <i32 -20, i32 undef>
   %cmp = icmp ne <2 x i32> %1, %2
   ret <2 x i1> %cmp
 }
 
 define <2 x i1> @icmp_sub57_ne_sub20_vec_nonsplat(<2 x i32> %x, <2 x i32> %y) {
 ; CHECK-LABEL: @icmp_sub57_ne_sub20_vec_nonsplat(
-; CHECK-NEXT:    [[TMP1:%.*]] = add <2 x i32> [[X:%.*]], <i32 -57, i32 -58>
-; CHECK-NEXT:    [[TMP2:%.*]] = add <2 x i32> [[Y:%.*]], <i32 -20, i32 -21>
-; CHECK-NEXT:    [[CMP:%.*]] = icmp ne <2 x i32> [[TMP1]], [[TMP2]]
+; CHECK-NEXT:    [[TMP1:%.*]] = add <2 x i32> [[Y:%.*]], <i32 37, i32 37>
+; CHECK-NEXT:    [[CMP:%.*]] = icmp ne <2 x i32> [[TMP1]], [[X:%.*]]
 ; CHECK-NEXT:    ret <2 x i1> [[CMP]]
 ;
   %1 = add <2 x i32> %x, <i32 -57, i32 -58>
   %2 = add <2 x i32> %y, <i32 -20, i32 -21>
   %cmp = icmp ne <2 x i32> %1, %2
   ret <2 x i1> %cmp
 }
 

llvm/test/Transforms/PhaseOrdering/loop-rotation-vs-common-code-hoisting.ll

 ; HOIST:       return:
 ; HOIST-NEXT:    ret void
 ;
 ; ROTATE-LABEL: @_Z4loopi(
 ; ROTATE-NEXT:  entry:
 ; ROTATE-NEXT:    [[CMP:%.*]] = icmp slt i32 [[WIDTH:%.*]], 1
 ; ROTATE-NEXT:    br i1 [[CMP]], label [[RETURN:%.*]], label [[FOR_COND_PREHEADER:%.*]]
 ; ROTATE:       for.cond.preheader:
-; ROTATE-NEXT:    [[SUB:%.*]] = add nsw i32 [[WIDTH]], -1
 ; ROTATE-NEXT:    [[CMP13_NOT:%.*]] = icmp eq i32 [[WIDTH]], 1
-; ROTATE-NEXT:    br i1 [[CMP13_NOT]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_BODY:%.*]]
+; ROTATE-NEXT:    br i1 [[CMP13_NOT]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_BODY_PREHEADER:%.*]]
+; ROTATE:       for.body.preheader:
+; ROTATE-NEXT:    [[TMP0:%.*]] = add i32 [[WIDTH]], -2
+; ROTATE-NEXT:    br label [[FOR_BODY:%.*]]
 ; ROTATE:       for.cond.cleanup:
 ; ROTATE-NEXT:    tail call void @f0()
 ; ROTATE-NEXT:    tail call void @f2()
 ; ROTATE-NEXT:    br label [[RETURN]]
 ; ROTATE:       for.body:
-; ROTATE-NEXT:    [[I_04:%.*]] = phi i32 [ [[INC:%.*]], [[FOR_BODY]] ], [ 0, [[FOR_COND_PREHEADER]] ]
+; ROTATE-NEXT:    [[I_04:%.*]] = phi i32 [ [[INC:%.*]], [[FOR_BODY]] ], [ 0, [[FOR_BODY_PREHEADER]] ]
 ; ROTATE-NEXT:    tail call void @f0()
 ; ROTATE-NEXT:    tail call void @f1()
 ; ROTATE-NEXT:    [[INC]] = add nuw nsw i32 [[I_04]], 1
-; ROTATE-NEXT:    [[EXITCOND_NOT:%.*]] = icmp eq i32 [[INC]], [[SUB]]
+; ROTATE-NEXT:    [[EXITCOND_NOT:%.*]] = icmp eq i32 [[I_04]], [[TMP0]]
 ; ROTATE-NEXT:    br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]]
 ; ROTATE:       return:
 ; ROTATE-NEXT:    ret void
 ;
 entry:
   %width.addr = alloca i32, align 4
   %i = alloca i32, align 4
   store i32 %width, i32* %width.addr, align 4