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Differential D12103

MIPS now uses 'or' for move instead of [d]addu.
ClosedPublic

Authored by sdardis on Aug 18 2015, 7:11 AM.

Details

Reviewers
atanasyan
Commits
rG814b70598446: [Mips] Use 'or' for move instead of [d]addu in PLT entries
rLLD245491: [Mips] Use 'or' for move instead of [d]addu in PLT entries
rL245491: [Mips] Use 'or' for move instead of [d]addu in PLT entries
Summary

Update of PLT entries given the recent binutils commit (http://sourceware.org/ml/binutils/2015-08/msg00100.html) that changed the assembly mnemonic 'move' or be 'or' instead of [d]addu. A similar commit for LLVM also exists. (http://reviews.llvm.org/D11796)

Diff Detail

Event Timeline

sdardis updated this revision to Diff 32411.Aug 18 2015, 7:11 AM
sdardis retitled this revision from to MIPS now uses 'or' for move instead of [d]addu..
sdardis updated this object.
sdardis added a reviewer: atanasyan.
sdardis added a project: lld.
sdardis added a subscriber: llvm-commits.
atanasyan accepted this revision.Aug 18 2015, 9:08 AM
atanasyan edited edge metadata.

LGTM But there are three additional test cases require update: la25-stub-npic-shared.test, plt-entry-mixed-2.test, plt-entry-mixed-4.test. Do you have commit access? If you do not, I can commit the patch with the fix for three additional test cases.

This revision is now accepted and ready to land.Aug 18 2015, 9:08 AM
sdardis updated this revision to Diff 32527.Aug 19 2015, 3:04 AM
sdardis edited edge metadata.

Updated la25-stub-npic-shared.test, plt-entry-mixed-2.test, plt-entry-mixed-4.test. I don't have commit access.

Thanks.

Closed by commit rL245491: [Mips] Use 'or' for move instead of [d]addu in PLT entries (authored by atanasyan). · Explain WhyAug 19 2015, 1:21 PM
This revision was automatically updated to reflect the committed changes.
atanasyan added a comment.Aug 19 2015, 1:24 PM

Committed at r245491. Thanks for the patch.

Revision Contents

Diff 32527

lib/ReaderWriter/ELF/Mips/MipsRelocationPass.cpp

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}; };
// Regular big-endian PLT0 entry // Regular big-endian PLT0 entry
static const uint8_t mipsBePlt0AtomContent[] = { static const uint8_t mipsBePlt0AtomContent[] = {
0x3c, 0x1c, 0x00, 0x00, // lui $28, %hi(&GOTPLT[0]) 0x3c, 0x1c, 0x00, 0x00, // lui $28, %hi(&GOTPLT[0])
0x8f, 0x99, 0x00, 0x00, // lw $25, %lo(&GOTPLT[0])($28) 0x8f, 0x99, 0x00, 0x00, // lw $25, %lo(&GOTPLT[0])($28)
0x27, 0x9c, 0x00, 0x00, // addiu $28, $28, %lo(&GOTPLT[0]) 0x27, 0x9c, 0x00, 0x00, // addiu $28, $28, %lo(&GOTPLT[0])
0x03, 0x1c, 0xc0, 0x23, // subu $24, $24, $28 0x03, 0x1c, 0xc0, 0x23, // subu $24, $24, $28
0x03, 0xe0, 0x78, 0x21, // move $15, $31 0x03, 0xe0, 0x78, 0x25, // move $15, $31
0x00, 0x18, 0xc0, 0x82, // srl $24, $24, 2 0x00, 0x18, 0xc0, 0x82, // srl $24, $24, 2
0x03, 0x20, 0xf8, 0x09, // jalr $25 0x03, 0x20, 0xf8, 0x09, // jalr $25
0x27, 0x18, 0xff, 0xfe // subu $24, $24, 2 0x27, 0x18, 0xff, 0xfe // subu $24, $24, 2
}; };
// Regular little-endian PLT0 entry // Regular little-endian PLT0 entry
static const uint8_t mipsLePlt0AtomContent[] = { static const uint8_t mipsLePlt0AtomContent[] = {
0x00, 0x00, 0x1c, 0x3c, // lui $28, %hi(&GOTPLT[0]) 0x00, 0x00, 0x1c, 0x3c, // lui $28, %hi(&GOTPLT[0])
0x00, 0x00, 0x99, 0x8f, // lw $25, %lo(&GOTPLT[0])($28) 0x00, 0x00, 0x99, 0x8f, // lw $25, %lo(&GOTPLT[0])($28)
0x00, 0x00, 0x9c, 0x27, // addiu $28, $28, %lo(&GOTPLT[0]) 0x00, 0x00, 0x9c, 0x27, // addiu $28, $28, %lo(&GOTPLT[0])
0x23, 0xc0, 0x1c, 0x03, // subu $24, $24, $28 0x23, 0xc0, 0x1c, 0x03, // subu $24, $24, $28
0x21, 0x78, 0xe0, 0x03, // move $15, $31 0x25, 0x78, 0xe0, 0x03, // move $15, $31
0x82, 0xc0, 0x18, 0x00, // srl $24, $24, 2 0x82, 0xc0, 0x18, 0x00, // srl $24, $24, 2
0x09, 0xf8, 0x20, 0x03, // jalr $25 0x09, 0xf8, 0x20, 0x03, // jalr $25
0xfe, 0xff, 0x18, 0x27 // subu $24, $24, 2 0xfe, 0xff, 0x18, 0x27 // subu $24, $24, 2
}; };
// microMIPS big-endian PLT0 entry // microMIPS big-endian PLT0 entry
static const uint8_t microMipsBePlt0AtomContent[] = { static const uint8_t microMipsBePlt0AtomContent[] = {
0x79, 0x80, 0x00, 0x00, // addiupc $3, (&GOTPLT[0]) - . 0x79, 0x80, 0x00, 0x00, // addiupc $3, (&GOTPLT[0]) - .
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test/elf/Mips/la25-stub-npic-shared.test

# Check that PLT entries are created for branch relocations # Check that PLT entries are created for branch relocations
# when a PIC shared library function is called from non-pic code. # when a PIC shared library function is called from non-pic code.
# RUN: yaml2obj -format=elf -docnum 1 %s > %t-pic.o # RUN: yaml2obj -format=elf -docnum 1 %s > %t-pic.o
# RUN: yaml2obj -format=elf -docnum 2 %s > %t-reg.o # RUN: yaml2obj -format=elf -docnum 2 %s > %t-reg.o
# RUN: yaml2obj -format=elf -docnum 3 %s > %t-micro.o # RUN: yaml2obj -format=elf -docnum 3 %s > %t-micro.o
# RUN: lld -flavor gnu -target mipsel -shared -o %t.so %t-pic.o # RUN: lld -flavor gnu -target mipsel -shared -o %t.so %t-pic.o
# RUN: lld -flavor gnu -target mipsel -e T0 -o %t.exe %t-reg.o %t-micro.o %t.so # RUN: lld -flavor gnu -target mipsel -e T0 -o %t.exe %t-reg.o %t-micro.o %t.so
# RUN: llvm-objdump -s -t %t.exe | FileCheck %s # RUN: llvm-objdump -s -t %t.exe | FileCheck %s
# CHECK: Contents of section .plt: # CHECK: Contents of section .plt:
# CHECK-NEXT: 400190 40001c3c 0020998f 00209c27 23c01c03 # CHECK-NEXT: 400190 40001c3c 0020998f 00209c27 23c01c03
# CHECK-NEXT: 4001a0 2178e003 82c01800 09f82003 feff1827 # CHECK-NEXT: 4001a0 2578e003 82c01800 09f82003 feff1827
# CHECK-NEXT: 4001b0 40000f3c 0820f98d 08002003 0820f825 # CHECK-NEXT: 4001b0 40000f3c 0820f98d 08002003 0820f825
# ^ PLT.T1 # ^ PLT.T1
# CHECK-NEXT: 4001c0 00799307 22ff0000 9945020f # CHECK-NEXT: 4001c0 00799307 22ff0000 9945020f
# ^ PLT.T2 # ^ PLT.T2
# CHECK: Contents of section .text: # CHECK: Contents of section .text:
# CHECK-NEXT: 4001cc 6c001000 f8ff0000 f7ff1f00 f6ffff03 # CHECK-NEXT: 4001cc 6c001000 f8ff0000 f7ff1f00 f6ffff03
# ^ T0 ^ PLT.T1 (0x4001b0) # ^ T0 ^ PLT.T1 (0x4001b0)
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test/elf/Mips/plt-entry-mixed-1.test

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# RUN: llvm-objdump -d %t.exe | FileCheck %s # RUN: llvm-objdump -d %t.exe | FileCheck %s
# CHECK: Disassembly of section .plt: # CHECK: Disassembly of section .plt:
# CHECK-NEXT: .plt: # CHECK-NEXT: .plt:
# CHECK-NEXT: 400170: 40 00 1c 3c lui $gp, 64 # CHECK-NEXT: 400170: 40 00 1c 3c lui $gp, 64
# CHECK-NEXT: 400174: 00 20 99 8f lw $25, 8192($gp) # CHECK-NEXT: 400174: 00 20 99 8f lw $25, 8192($gp)
# CHECK-NEXT: 400178: 00 20 9c 27 addiu $gp, $gp, 8192 # CHECK-NEXT: 400178: 00 20 9c 27 addiu $gp, $gp, 8192
# CHECK-NEXT: 40017c: 23 c0 1c 03 subu $24, $24, $gp # CHECK-NEXT: 40017c: 23 c0 1c 03 subu $24, $24, $gp
# CHECK-NEXT: 400180: 21 78 e0 03 move $15, $ra # CHECK-NEXT: 400180: 25 78 e0 03 move $15, $ra
# CHECK-NEXT: 400184: 82 c0 18 00 srl $24, $24, 2 # CHECK-NEXT: 400184: 82 c0 18 00 srl $24, $24, 2
# CHECK-NEXT: 400188: 09 f8 20 03 jalr $25 # CHECK-NEXT: 400188: 09 f8 20 03 jalr $25
# CHECK-NEXT: 40018c: fe ff 18 27 addiu $24, $24, -2 # CHECK-NEXT: 40018c: fe ff 18 27 addiu $24, $24, -2
# CHECK-NEXT: 400190: 40 00 0f 3c lui $15, 64 # CHECK-NEXT: 400190: 40 00 0f 3c lui $15, 64
# CHECK-NEXT: 400194: 08 20 f9 8d lw $25, 8200($15) # CHECK-NEXT: 400194: 08 20 f9 8d lw $25, 8200($15)
# CHECK-NEXT: 400198: 08 00 20 03 jr $25 # CHECK-NEXT: 400198: 08 00 20 03 jr $25
# CHECK-NEXT: 40019c: 08 20 f8 25 addiu $24, $15, 8200 # CHECK-NEXT: 40019c: 08 20 f8 25 addiu $24, $15, 8200
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test/elf/Mips/plt-entry-mixed-2.test

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# RUN: lld -flavor gnu -target mipsel -e T0 -o %t.exe %t.o.o %t.so # RUN: lld -flavor gnu -target mipsel -e T0 -o %t.exe %t.o.o %t.so
# RUN: llvm-objdump -s %t.exe | FileCheck %s # RUN: llvm-objdump -s %t.exe | FileCheck %s
# FIXME (simon): Check the disassembler output when llvm-objdump starts # FIXME (simon): Check the disassembler output when llvm-objdump starts
# to support microMIPS instruction encoding. # to support microMIPS instruction encoding.
# CHECK: Contents of section .plt: # CHECK: Contents of section .plt:
# CHECK-NEXT: 400170 40001c3c 0020998f 00209c27 23c01c03 @..<. ... .'#... # CHECK-NEXT: 400170 40001c3c 0020998f 00209c27 23c01c03 @..<. ... .'#...
# CHECK-NEXT: 400180 2178e003 82c01800 09f82003 feff1827 !x........ ....' # CHECK-NEXT: 400180 2578e003 82c01800 09f82003 feff1827 %x........ ....'
# CHECK-NEXT: 400190 40000f3c 0820f98d 08002003 0820f825 @..<. .... .. .% # CHECK-NEXT: 400190 40000f3c 0820f98d 08002003 0820f825 @..<. .... .. .%
# CHECK-NEXT: 4001a0 00799a07 22ff0000 9945020f .y.."....E.. # CHECK-NEXT: 4001a0 00799a07 22ff0000 9945020f .y.."....E..
# so.o # so.o
--- ---
FileHeader: FileHeader:
Class: ELFCLASS32 Class: ELFCLASS32
Data: ELFDATA2LSB Data: ELFDATA2LSB
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test/elf/Mips/plt-entry-mixed-4.test

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# RUN: lld -flavor gnu -target mipsel -e T0 -o %t.exe %t.o.o %t.so # RUN: lld -flavor gnu -target mipsel -e T0 -o %t.exe %t.o.o %t.so
# RUN: llvm-objdump -s %t.exe | FileCheck %s # RUN: llvm-objdump -s %t.exe | FileCheck %s
# FIXME (simon): Check the disassembler output when llvm-objdump starts # FIXME (simon): Check the disassembler output when llvm-objdump starts
# to support microMIPS instruction encoding. # to support microMIPS instruction encoding.
# CHECK: Contents of section .plt: # CHECK: Contents of section .plt:
# CHECK-NEXT: 400170 40001c3c 0020998f 00209c27 23c01c03 @..<. ... .'#... # CHECK-NEXT: 400170 40001c3c 0020998f 00209c27 23c01c03 @..<. ... .'#...
# CHECK-NEXT: 400180 2178e003 82c01800 09f82003 feff1827 !x........ ....' # CHECK-NEXT: 400180 2578e003 82c01800 09f82003 feff1827 %x........ ....'
# CHECK-NEXT: 400190 40000f3c 0820f98d 08002003 0820f825 @..<. .... .. .% # CHECK-NEXT: 400190 40000f3c 0820f98d 08002003 0820f825 @..<. .... .. .%
# so.o # so.o
--- ---
FileHeader: FileHeader:
Class: ELFCLASS32 Class: ELFCLASS32
Data: ELFDATA2LSB Data: ELFDATA2LSB
Type: ET_REL Type: ET_REL
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test/elf/Mips/plt-entry-r6-be.test

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# RUN: llvm-objdump -d %t.exe | FileCheck %s # RUN: llvm-objdump -d %t.exe | FileCheck %s
# CHECK: Disassembly of section .plt: # CHECK: Disassembly of section .plt:
# CHECK-NEXT: .plt: # CHECK-NEXT: .plt:
# CHECK-NEXT: 400160: 3c 1c 00 40 lui $gp, 64 # CHECK-NEXT: 400160: 3c 1c 00 40 lui $gp, 64
# CHECK-NEXT: 400164: 8f 99 20 00 lw $25, 8192($gp) # CHECK-NEXT: 400164: 8f 99 20 00 lw $25, 8192($gp)
# CHECK-NEXT: 400168: 27 9c 20 00 addiu $gp, $gp, 8192 # CHECK-NEXT: 400168: 27 9c 20 00 addiu $gp, $gp, 8192
# CHECK-NEXT: 40016c: 03 1c c0 23 subu $24, $24, $gp # CHECK-NEXT: 40016c: 03 1c c0 23 subu $24, $24, $gp
# CHECK-NEXT: 400170: 03 e0 78 21 move $15, $ra # CHECK-NEXT: 400170: 03 e0 78 25 move $15, $ra
# CHECK-NEXT: 400174: 00 18 c0 82 srl $24, $24, 2 # CHECK-NEXT: 400174: 00 18 c0 82 srl $24, $24, 2
# CHECK-NEXT: 400178: 03 20 f8 09 jalr $25 # CHECK-NEXT: 400178: 03 20 f8 09 jalr $25
# CHECK-NEXT: 40017c: 27 18 ff fe addiu $24, $24, -2 # CHECK-NEXT: 40017c: 27 18 ff fe addiu $24, $24, -2
# CHECK-NEXT: 400180: 3c 0f 00 40 lui $15, 64 # CHECK-NEXT: 400180: 3c 0f 00 40 lui $15, 64
# CHECK-NEXT: 400184: 8d f9 20 08 lw $25, 8200($15) # CHECK-NEXT: 400184: 8d f9 20 08 lw $25, 8200($15)
# CHECK-NEXT: 400188: 03 20 00 09 jr $25 # CHECK-NEXT: 400188: 03 20 00 09 jr $25
# CHECK-NEXT: 40018c: 25 f8 20 08 addiu $24, $15, 8200 # CHECK-NEXT: 40018c: 25 f8 20 08 addiu $24, $15, 8200
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test/elf/Mips/plt-entry-r6.test

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# RUN: llvm-objdump -d %t.exe | FileCheck %s # RUN: llvm-objdump -d %t.exe | FileCheck %s
# CHECK: Disassembly of section .plt: # CHECK: Disassembly of section .plt:
# CHECK-NEXT: .plt: # CHECK-NEXT: .plt:
# CHECK-NEXT: 400160: 40 00 1c 3c lui $gp, 64 # CHECK-NEXT: 400160: 40 00 1c 3c lui $gp, 64
# CHECK-NEXT: 400164: 00 20 99 8f lw $25, 8192($gp) # CHECK-NEXT: 400164: 00 20 99 8f lw $25, 8192($gp)
# CHECK-NEXT: 400168: 00 20 9c 27 addiu $gp, $gp, 8192 # CHECK-NEXT: 400168: 00 20 9c 27 addiu $gp, $gp, 8192
# CHECK-NEXT: 40016c: 23 c0 1c 03 subu $24, $24, $gp # CHECK-NEXT: 40016c: 23 c0 1c 03 subu $24, $24, $gp
# CHECK-NEXT: 400170: 21 78 e0 03 move $15, $ra # CHECK-NEXT: 400170: 25 78 e0 03 move $15, $ra
# CHECK-NEXT: 400174: 82 c0 18 00 srl $24, $24, 2 # CHECK-NEXT: 400174: 82 c0 18 00 srl $24, $24, 2
# CHECK-NEXT: 400178: 09 f8 20 03 jalr $25 # CHECK-NEXT: 400178: 09 f8 20 03 jalr $25
# CHECK-NEXT: 40017c: fe ff 18 27 addiu $24, $24, -2 # CHECK-NEXT: 40017c: fe ff 18 27 addiu $24, $24, -2
# CHECK-NEXT: 400180: 40 00 0f 3c lui $15, 64 # CHECK-NEXT: 400180: 40 00 0f 3c lui $15, 64
# CHECK-NEXT: 400184: 08 20 f9 8d lw $25, 8200($15) # CHECK-NEXT: 400184: 08 20 f9 8d lw $25, 8200($15)
# CHECK-NEXT: 400188: 09 00 20 03 jr $25 # CHECK-NEXT: 400188: 09 00 20 03 jr $25
# CHECK-NEXT: 40018c: 08 20 f8 25 addiu $24, $15, 8200 # CHECK-NEXT: 40018c: 08 20 f8 25 addiu $24, $15, 8200
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test/elf/Mips/plt-header-be.test

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# RUN: llvm-objdump -section-headers -disassemble %t.exe | FileCheck %s # RUN: llvm-objdump -section-headers -disassemble %t.exe | FileCheck %s
# CHECK: Disassembly of section .plt: # CHECK: Disassembly of section .plt:
# CHECK-NEXT: .plt: # CHECK-NEXT: .plt:
# CHECK-NEXT: 400160: 3c 1c 00 40 lui $gp, 64 # CHECK-NEXT: 400160: 3c 1c 00 40 lui $gp, 64
# CHECK-NEXT: 400164: 8f 99 20 00 lw $25, 8192($gp) # CHECK-NEXT: 400164: 8f 99 20 00 lw $25, 8192($gp)
# CHECK-NEXT: 400168: 27 9c 20 00 addiu $gp, $gp, 8192 # CHECK-NEXT: 400168: 27 9c 20 00 addiu $gp, $gp, 8192
# CHECK-NEXT: 40016c: 03 1c c0 23 subu $24, $24, $gp # CHECK-NEXT: 40016c: 03 1c c0 23 subu $24, $24, $gp
# CHECK-NEXT: 400170: 03 e0 78 21 move $15, $ra # CHECK-NEXT: 400170: 03 e0 78 25 move $15, $ra
# CHECK-NEXT: 400174: 00 18 c0 82 srl $24, $24, 2 # CHECK-NEXT: 400174: 00 18 c0 82 srl $24, $24, 2
# CHECK-NEXT: 400178: 03 20 f8 09 jalr $25 # CHECK-NEXT: 400178: 03 20 f8 09 jalr $25
# CHECK-NEXT: 40017c: 27 18 ff fe addiu $24, $24, -2 # CHECK-NEXT: 40017c: 27 18 ff fe addiu $24, $24, -2
# CHECK-NEXT: 400180: 3c 0f 00 40 lui $15, 64 # CHECK-NEXT: 400180: 3c 0f 00 40 lui $15, 64
# CHECK-NEXT: 400184: 8d f9 20 08 lw $25, 8200($15) # CHECK-NEXT: 400184: 8d f9 20 08 lw $25, 8200($15)
# CHECK-NEXT: 400188: 03 20 00 08 jr $25 # CHECK-NEXT: 400188: 03 20 00 08 jr $25
# CHECK-NEXT: 40018c: 25 f8 20 08 addiu $24, $15, 8200 # CHECK-NEXT: 40018c: 25 f8 20 08 addiu $24, $15, 8200
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test/elf/Mips/plt-header-mixed.test

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# RUN: llvm-objdump -section-headers %t.exe | FileCheck -check-prefix=EXE %s # RUN: llvm-objdump -section-headers %t.exe | FileCheck -check-prefix=EXE %s
# DIS: Disassembly of section .plt: # DIS: Disassembly of section .plt:
# DIS-NEXT: .plt: # DIS-NEXT: .plt:
# DIS-NEXT: 400170: 40 00 1c 3c lui $gp, 64 # DIS-NEXT: 400170: 40 00 1c 3c lui $gp, 64
# DIS-NEXT: 400174: 00 20 99 8f lw $25, 8192($gp) # DIS-NEXT: 400174: 00 20 99 8f lw $25, 8192($gp)
# DIS-NEXT: 400178: 00 20 9c 27 addiu $gp, $gp, 8192 # DIS-NEXT: 400178: 00 20 9c 27 addiu $gp, $gp, 8192
# DIS-NEXT: 40017c: 23 c0 1c 03 subu $24, $24, $gp # DIS-NEXT: 40017c: 23 c0 1c 03 subu $24, $24, $gp
# DIS-NEXT: 400180: 21 78 e0 03 move $15, $ra # DIS-NEXT: 400180: 25 78 e0 03 move $15, $ra
# DIS-NEXT: 400184: 82 c0 18 00 srl $24, $24, 2 # DIS-NEXT: 400184: 82 c0 18 00 srl $24, $24, 2
# DIS-NEXT: 400188: 09 f8 20 03 jalr $25 # DIS-NEXT: 400188: 09 f8 20 03 jalr $25
# DIS-NEXT: 40018c: fe ff 18 27 addiu $24, $24, -2 # DIS-NEXT: 40018c: fe ff 18 27 addiu $24, $24, -2
# DIS-NEXT: 400190: 40 00 0f 3c lui $15, 64 # DIS-NEXT: 400190: 40 00 0f 3c lui $15, 64
# DIS-NEXT: 400194: 08 20 f9 8d lw $25, 8200($15) # DIS-NEXT: 400194: 08 20 f9 8d lw $25, 8200($15)
# DIS-NEXT: 400198: 08 00 20 03 jr $25 # DIS-NEXT: 400198: 08 00 20 03 jr $25
# DIS-NEXT: 40019c: 08 20 f8 25 addiu $24, $15, 8200 # DIS-NEXT: 40019c: 08 20 f8 25 addiu $24, $15, 8200
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test/elf/Mips/plt-header.test

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# EXE: Disassembly of section .plt: # EXE: Disassembly of section .plt:
# EXE: .plt: # EXE: .plt:
# PLT0 entry. Points to the .got.plt[0] # PLT0 entry. Points to the .got.plt[0]
# EXE-NEXT: 400160: 40 00 1c 3c lui $gp, 64 # EXE-NEXT: 400160: 40 00 1c 3c lui $gp, 64
# EXE-NEXT: 400164: 00 20 99 8f lw $25, 8192($gp) # EXE-NEXT: 400164: 00 20 99 8f lw $25, 8192($gp)
# EXE-NEXT: 400168: 00 20 9c 27 addiu $gp, $gp, 8192 # EXE-NEXT: 400168: 00 20 9c 27 addiu $gp, $gp, 8192
# EXE-NEXT: 40016c: 23 c0 1c 03 subu $24, $24, $gp # EXE-NEXT: 40016c: 23 c0 1c 03 subu $24, $24, $gp
# EXE-NEXT: 400170: 21 78 e0 03 move $15, $ra # EXE-NEXT: 400170: 25 78 e0 03 move $15, $ra
# EXE-NEXT: 400174: 82 c0 18 00 srl $24, $24, 2 # EXE-NEXT: 400174: 82 c0 18 00 srl $24, $24, 2
# EXE-NEXT: 400178: 09 f8 20 03 jalr $25 # EXE-NEXT: 400178: 09 f8 20 03 jalr $25
# EXE-NEXT: 40017c: fe ff 18 27 addiu $24, $24, -2 # EXE-NEXT: 40017c: fe ff 18 27 addiu $24, $24, -2
# EXE: Sections: # EXE: Sections:
# EXE: Idx Name Size Address Type # EXE: Idx Name Size Address Type
# EXE: 6 .plt 00000030 0000000000400160 TEXT DATA # EXE: 6 .plt 00000030 0000000000400160 TEXT DATA
# EXE: 10 .got.plt 0000000c 0000000000402000 DATA # EXE: 10 .got.plt 0000000c 0000000000402000 DATA
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test/elf/Mips/rel-dynamic-01.test

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# RUN: llvm-readobj -mips-plt-got %t.exe | FileCheck -check-prefix=GOT %s # RUN: llvm-readobj -mips-plt-got %t.exe | FileCheck -check-prefix=GOT %s
# PLT: Disassembly of section .plt: # PLT: Disassembly of section .plt:
# PLT-NEXT: .plt: # PLT-NEXT: .plt:
# PLT-NEXT: 4001f0: 40 00 1c 3c lui $gp, 64 # PLT-NEXT: 4001f0: 40 00 1c 3c lui $gp, 64
# PLT-NEXT: 4001f4: 00 20 99 8f lw $25, 8192($gp) # PLT-NEXT: 4001f4: 00 20 99 8f lw $25, 8192($gp)
# PLT-NEXT: 4001f8: 00 20 9c 27 addiu $gp, $gp, 8192 # PLT-NEXT: 4001f8: 00 20 9c 27 addiu $gp, $gp, 8192
# PLT-NEXT: 4001fc: 23 c0 1c 03 subu $24, $24, $gp # PLT-NEXT: 4001fc: 23 c0 1c 03 subu $24, $24, $gp
# PLT-NEXT: 400200: 21 78 e0 03 move $15, $ra # PLT-NEXT: 400200: 25 78 e0 03 move $15, $ra
# PLT-NEXT: 400204: 82 c0 18 00 srl $24, $24, 2 # PLT-NEXT: 400204: 82 c0 18 00 srl $24, $24, 2
# PLT-NEXT: 400208: 09 f8 20 03 jalr $25 # PLT-NEXT: 400208: 09 f8 20 03 jalr $25
# PLT-NEXT: 40020c: fe ff 18 27 addiu $24, $24, -2 # PLT-NEXT: 40020c: fe ff 18 27 addiu $24, $24, -2
# #
# PLT-NEXT: 400210: 40 00 0f 3c lui $15, 64 # PLT-NEXT: 400210: 40 00 0f 3c lui $15, 64
# PLT-NEXT: 400214: 08 20 f9 8d lw $25, 8200($15) # PLT-NEXT: 400214: 08 20 f9 8d lw $25, 8200($15)
# PLT-NEXT: 400218: 08 00 20 03 jr $25 # PLT-NEXT: 400218: 08 00 20 03 jr $25
# PLT-NEXT: 40021c: 08 20 f8 25 addiu $24, $15, 8200 # PLT-NEXT: 40021c: 08 20 f8 25 addiu $24, $15, 8200
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test/elf/Mips/rel-dynamic-03.test

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# RUN: llvm-readobj -dt -r %t.exe | FileCheck -check-prefix=PLT-SYM %s # RUN: llvm-readobj -dt -r %t.exe | FileCheck -check-prefix=PLT-SYM %s
# PLT: Disassembly of section .plt: # PLT: Disassembly of section .plt:
# PLT-NEXT: .plt: # PLT-NEXT: .plt:
# PLT-NEXT: 400160: 40 00 1c 3c lui $gp, 64 # PLT-NEXT: 400160: 40 00 1c 3c lui $gp, 64
# PLT-NEXT: 400164: 00 20 99 8f lw $25, 8192($gp) # PLT-NEXT: 400164: 00 20 99 8f lw $25, 8192($gp)
# PLT-NEXT: 400168: 00 20 9c 27 addiu $gp, $gp, 8192 # PLT-NEXT: 400168: 00 20 9c 27 addiu $gp, $gp, 8192
# PLT-NEXT: 40016c: 23 c0 1c 03 subu $24, $24, $gp # PLT-NEXT: 40016c: 23 c0 1c 03 subu $24, $24, $gp
# PLT-NEXT: 400170: 21 78 e0 03 move $15, $ra # PLT-NEXT: 400170: 25 78 e0 03 move $15, $ra
# PLT-NEXT: 400174: 82 c0 18 00 srl $24, $24, 2 # PLT-NEXT: 400174: 82 c0 18 00 srl $24, $24, 2
# PLT-NEXT: 400178: 09 f8 20 03 jalr $25 # PLT-NEXT: 400178: 09 f8 20 03 jalr $25
# PLT-NEXT: 40017c: fe ff 18 27 addiu $24, $24, -2 # PLT-NEXT: 40017c: fe ff 18 27 addiu $24, $24, -2
# #
# PLT-NEXT: 400180: 40 00 0f 3c lui $15, 64 # PLT-NEXT: 400180: 40 00 0f 3c lui $15, 64
# PLT-NEXT: 400184: 08 20 f9 8d lw $25, 8200($15) # PLT-NEXT: 400184: 08 20 f9 8d lw $25, 8200($15)
# PLT-NEXT: 400188: 08 00 20 03 jr $25 # PLT-NEXT: 400188: 08 00 20 03 jr $25
# PLT-NEXT: 40018c: 08 20 f8 25 addiu $24, $15, 8200 # PLT-NEXT: 40018c: 08 20 f8 25 addiu $24, $15, 8200
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