[IRSim] Removing length check so first instruction in module is included

[AndrewLitteken]

Summary

Discussed: https://github.com/llvm/llvm-project/issues/54124

If an instruction is first legal instruction in the module, and is the only legal instruction in its basic block, it will be ignored by the outliner due to a length check inherited from the older version of the outliner that was restricted to outlining within a single basic block. This removes that check, and updates any tests that broke because of it.

[paquette]

What is the code size impact on the test suite?

[paquette]

I measured myself and found that this actually exposes *another* bug.

This IR:

https://godbolt.org/z/Wxq5aEsGT

Compiled with this patch using

~/llvm-project/build/bin/opt -iroutliner /tmp/testcase.ll -o -

Gives us

!dbg attachment points at wrong subprogram for function
!12 = distinct !DISubprogram(name: "outlined_ir_func_0", linkageName: "outlined_ir_func_0", scope: !2, file: !2, type: !3, flags: DIFlagArtificial, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !5, retainedNodes: !4)
i1 ()* @outlined_ir_func_0
  br i1 undef, label %bb5, label %bb13.exitStub, !llvm.loop !13
!14 = !DILocation(line: 1655, column: 5, scope: !15)
!15 = distinct !DISubprogram(name: "snork.outlined", linkageName: "snork.outlined", scope: null, file: !2, type: !3, spFlags: DISPFlagLocalToUnit | DISPFlagDefinition | DISPFlagOptimized, unit: !5, retainedNodes: !4)
!15 = distinct !DISubprogram(name: "snork.outlined", linkageName: "snork.outlined", scope: null, file: !2, type: !3, spFlags: DISPFlagLocalToUnit | DISPFlagDefinition | DISPFlagOptimized, unit: !5, retainedNodes: !4)
LLVM ERROR: Broken module found, compilation aborted!

I know this is a real bug because I saw it in a much more complex setting than the test suite. :) This change (thankfully?) exposes it. The bug ought to be independent of this patch.

[AndrewLitteken]

Oh, well I'll add it to the list. It looks like it's due to loop metadata not being stripped, only debug info location info gets stripped at the moment.

[paquette]

I think we can go ahead and land this.

Can you add a new testcase which tests something along the lines of

https://godbolt.org/z/6Pav4hnfh

?

[paquette]

Oh, good news, for the other issue, I managed to repro without the patch:

https://github.com/llvm/llvm-project/issues/54155

[AndrewLitteken]

Adding test

[paquette]

LGTM

llvm/lib/Analysis/IRSimilarityIdentifier.cpp

case InstrType::Illegal:
       mapToIllegalUnsigned(It, IntegerMappingForBB, InstrListForBB);
       break;
     case InstrType::Invisible:
       AddedIllegalLastTime = false;
       break;
     }
   }
 
-  if (HaveLegalRange) {
-    if (AddedIllegalLastTime)
-      mapToIllegalUnsigned(It, IntegerMappingForBB, InstrListForBB, true);
-    for (IRInstructionData *ID : InstrListForBB)
-      this->IDL->push_back(*ID);
-    llvm::append_range(InstrList, InstrListForBB);
-    llvm::append_range(IntegerMapping, IntegerMappingForBB);
-  }
-}
 
 // TODO: This is the same as the MachineOutliner, and should be consolidated
 // into the same interface.
 unsigned IRInstructionMapper::mapToLegalUnsigned(
     BasicBlock::iterator &It, std::vector<unsigned> &IntegerMappingForBB,
     std::vector<IRInstructionData *> &InstrListForBB) {
   // We added something legal, so we should unset the AddedLegalLastTime
   // flag.

llvm/test/Transforms/IROutliner/outlining-basic-branches.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --include-generated-funcs
 ; RUN: opt -S -verify -iroutliner -ir-outlining-no-cost < %s | FileCheck %s
 
 ; This checks that we are able to outline exactly the same structure without
 ; any other items to outline.
 
 define void @outline_outputs1() #0 {
 entry:
   br label %next
 next:
   br label %next2
 next2:
-  br label %next
+  br label %next3
 next3:
   %a = alloca i32, align 4
   br label %next4
 next4:
-  br label %next3
+  br label %next5
 next5:
   br label %next6
 next6:
   %b = alloca i32, align 4
   ret void
 }
 
 ; CHECK-LABEL: @outline_outputs1(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    br label [[NEXT:%.*]]
-; CHECK:       next:
 ; CHECK-NEXT:    call void @outlined_ir_func_0()
-; CHECK-NEXT:    br label [[NEXT]]
+; CHECK-NEXT:    br label [[NEXT3:%.*]]
 ; CHECK:       next3:
 ; CHECK-NEXT:    [[A:%.*]] = alloca i32, align 4
 ; CHECK-NEXT:    call void @outlined_ir_func_0()
-; CHECK-NEXT:    br label [[NEXT3:%.*]]
-; CHECK:       next5:
 ; CHECK-NEXT:    br label [[NEXT6:%.*]]
 ; CHECK:       next6:
 ; CHECK-NEXT:    [[B:%.*]] = alloca i32, align 4
 ; CHECK-NEXT:    ret void
 ;
 ;
 ; CHECK: define internal void @outlined_ir_func_0(
-; CHECK:  newFuncRoot:
-; CHECK-NEXT:    br label [[NEXT_TO_OUTLINE:%.*]]
-; CHECK:       next_to_outline:
+; CHECK-NEXT:  newFuncRoot:
+; CHECK-NEXT:    br label [[ENTRY_TO_OUTLINE:%.*]]
+; CHECK:       entry_to_outline:
+; CHECK-NEXT:    br label [[NEXT:%.*]]
+; CHECK:       next:
 ; CHECK-NEXT:    br label [[NEXT2:%.*]]
 ; CHECK:       next2:
-; CHECK-NEXT:    br label [[NEXT_EXITSTUB:%.*]]
-; CHECK:       next.exitStub:
+; CHECK-NEXT:    br label [[NEXT3_EXITSTUB:%.*]]
+; CHECK:       next3.exitStub:
 ; CHECK-NEXT:    ret void
 ;

llvm/test/Transforms/IROutliner/outlining-first-instruction.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --include-generated-funcs
 ; RUN: opt -S -verify -iroutliner -ir-outlining-no-cost < %s | FileCheck %s
 
-; Make sure that we outline safely from functions with no return instructions.
-
-; The code extractor will insert return instructions in the outer function
-; due to assumptions about the contents of the outlined region.
+; Make sure that we outline from all three of these functions, and that
+; the first instruction in the module is included when it is the only
+; instruction in the first basic block.
 
 define void @f1() {
 bb:
   br label %bb1
 bb1:
-  br label %bb1
+  br label %bb2
+bb2:
+  ret void
 }
 
 define void @f2() {
 bb:
   br label %bb1
 bb1:
-  br label %bb1
+  br label %bb2
+bb2:
+  ret void
 }
 
 define void @f3() {
 bb:
   br label %bb1
 bb1:
-  br label %bb1
+  br label %bb2
+bb2:
+  ret void
 }
 ; CHECK-LABEL: @f1(
 ; CHECK-NEXT:  bb:
-; CHECK-NEXT:    br label [[BB1:%.*]]
-; CHECK:       bb1:
-; CHECK-NEXT:    br label [[BB1]]
+; CHECK-NEXT:    call void @outlined_ir_func_0()
+; CHECK-NEXT:    br label [[BB2:%.*]]
+; CHECK:       bb2:
+; CHECK-NEXT:    ret void
 ;
 ;
 ; CHECK-LABEL: @f2(
 ; CHECK-NEXT:  bb:
 ; CHECK-NEXT:    call void @outlined_ir_func_0()
+; CHECK-NEXT:    br label [[BB2:%.*]]
+; CHECK:       bb2:
 ; CHECK-NEXT:    ret void
 ;
 ;
 ; CHECK-LABEL: @f3(
 ; CHECK-NEXT:  bb:
 ; CHECK-NEXT:    call void @outlined_ir_func_0()
+; CHECK-NEXT:    br label [[BB2:%.*]]
+; CHECK:       bb2:
 ; CHECK-NEXT:    ret void
 ;
 ;
 ; CHECK-LABEL: define internal void @outlined_ir_func_0(
 ; CHECK-NEXT:  newFuncRoot:
 ; CHECK-NEXT:    br label [[BB_TO_OUTLINE:%.*]]
 ; CHECK:       bb_to_outline:
 ; CHECK-NEXT:    br label [[BB1:%.*]]
 ; CHECK:       bb1:
-; CHECK-NEXT:    br label [[BB1]]
+; CHECK-NEXT:    br label [[BB2_EXITSTUB:%.*]]
+; CHECK:       bb2.exitStub:
+; CHECK-NEXT:    ret void
 ;

llvm/test/Transforms/IROutliner/outlining-no-return-functions.ll

 define void @f3() {
 bb:
   br label %bb1
 bb1:
   br label %bb1
 }
 ; CHECK-LABEL: @f1(
 ; CHECK-NEXT:  bb:
-; CHECK-NEXT:    br label [[BB1:%.*]]
-; CHECK:       bb1:
-; CHECK-NEXT:    br label [[BB1]]
+; CHECK-NEXT:    call void @outlined_ir_func_0()
+; CHECK-NEXT:    ret void
 ;
 ;
 ; CHECK-LABEL: @f2(
 ; CHECK-NEXT:  bb:
 ; CHECK-NEXT:    call void @outlined_ir_func_0()
 ; CHECK-NEXT:    ret void
 ;
 ;

llvm/test/Transforms/IROutliner/phi-nodes-simple.ll

 first:
   %0 = phi i32 [ 0, %test ]
   store i32 2, i32* %a, align 4
   store i32 3, i32* %b, align 4
   ret void
 }
 ; CHECK-LABEL: @function1(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    br label [[TEST:%.*]]
-; CHECK:       test:
 ; CHECK-NEXT:    call void @outlined_ir_func_0(i32* [[A:%.*]], i32* [[B:%.*]])
 ; CHECK-NEXT:    ret void
 ;
 ;
 ; CHECK-LABEL: @function2(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    br label [[TEST:%.*]]
-; CHECK:       test:
 ; CHECK-NEXT:    call void @outlined_ir_func_0(i32* [[A:%.*]], i32* [[B:%.*]])
 ; CHECK-NEXT:    ret void
 ;
 ;
 ; CHECK: define internal void @outlined_ir_func_0(
 ; CHECK-NEXT:  newFuncRoot:
-; CHECK-NEXT:    br label [[TEST_TO_OUTLINE:%.*]]
-; CHECK:       test_to_outline:
+; CHECK-NEXT:    br label [[ENTRY_TO_OUTLINE:%.*]]
+; CHECK:       entry_to_outline:
+; CHECK-NEXT:    br label [[TEST:%.*]]
+; CHECK:       test:
 ; CHECK-NEXT:    br label [[FIRST:%.*]]
 ; CHECK:       first:
-; CHECK-NEXT:    [[TMP2:%.*]] = phi i32 [ 0, [[TEST_TO_OUTLINE]] ]
+; CHECK-NEXT:    [[TMP2:%.*]] = phi i32 [ 0, [[TEST]] ]
 ; CHECK-NEXT:    store i32 2, i32* [[TMP0:%.*]], align 4
 ; CHECK-NEXT:    store i32 3, i32* [[TMP1:%.*]], align 4
-; CHECK-NEXT:    br label [[TEST_AFTER_OUTLINE_EXITSTUB:%.*]]
-; CHECK:       test_after_outline.exitStub:
+; CHECK-NEXT:    br label [[ENTRY_AFTER_OUTLINE_EXITSTUB:%.*]]
+; CHECK:       entry_after_outline.exitStub:
 ; CHECK-NEXT:    ret void
 ;

llvm/unittests/Analysis/IRSimilarityIdentifierTest.cpp

TEST(IRInstructionMapper, PhiIllegal) {
 
   SpecificBumpPtrAllocator<IRInstructionData> InstDataAllocator;
   SpecificBumpPtrAllocator<IRInstructionDataList> IDLAllocator;
   IRInstructionMapper Mapper(&InstDataAllocator, &IDLAllocator);
   Mapper.initializeForBBs(*M);
   getVectors(*M, Mapper, InstrList, UnsignedVec);
 
   ASSERT_EQ(InstrList.size(), UnsignedVec.size());
-  ASSERT_EQ(UnsignedVec.size(), static_cast<unsigned>(0));
+  ASSERT_EQ(UnsignedVec.size(), static_cast<unsigned>(3));
+  ASSERT_GT(UnsignedVec[0], Mapper.IllegalInstrNumber);
 }
 
 // In most cases, the illegal instructions we are collecting don't require any
 // sort of setup.  In these cases, we can just only have illegal instructions,
 // and the mapper will create 0 length vectors, and we can check that.
 
 // In cases where we have legal instructions needed to set up the illegal
 // instruction, to check illegal instructions are assigned unsigned integers
TEST(IRInstructionMapper, AllocaIllegal) {
   std::vector<unsigned> UnsignedVec;
 
   SpecificBumpPtrAllocator<IRInstructionData> InstDataAllocator;
   SpecificBumpPtrAllocator<IRInstructionDataList> IDLAllocator;
   IRInstructionMapper Mapper(&InstDataAllocator, &IDLAllocator);
   getVectors(*M, Mapper, InstrList, UnsignedVec);
 
   ASSERT_EQ(InstrList.size(), UnsignedVec.size());
-  ASSERT_EQ(UnsignedVec.size(), static_cast<unsigned>(0));
+  ASSERT_EQ(UnsignedVec.size(), static_cast<unsigned>(1));
+  ASSERT_GT(UnsignedVec[0], Mapper.IllegalInstrNumber);
 }
 
 // Checks that an getelementptr instruction is mapped to be legal.  And that
 // the operands in getelementpointer instructions are the exact same after the
 // first element operand, which only requires the same type.
 TEST(IRInstructionMapper, GetElementPtrSameEndOperands) {
   StringRef ModuleString = R"(
     %struct.RT = type { i8, [10 x [20 x i32]], i8 }
TEST(IRInstructionMapper, CallsIllegalIndirect) {
 
   SpecificBumpPtrAllocator<IRInstructionData> InstDataAllocator;
   SpecificBumpPtrAllocator<IRInstructionDataList> IDLAllocator;
   IRInstructionMapper Mapper(&InstDataAllocator, &IDLAllocator);
   Mapper.InstClassifier.EnableIndirectCalls = false;
   getVectors(*M, Mapper, InstrList, UnsignedVec);
 
   ASSERT_EQ(InstrList.size(), UnsignedVec.size());
-  ASSERT_EQ(UnsignedVec.size(), static_cast<unsigned>(0));
+  ASSERT_EQ(UnsignedVec.size(), static_cast<unsigned>(1));
+  ASSERT_GT(UnsignedVec[0], Mapper.IllegalInstrNumber);
 }
 
 // Checks that indirect call instructions are mapped to be legal when it is not
 // specified to disallow them.
 TEST(IRInstructionMapper, CallsLegalIndirect) {
   StringRef ModuleString = R"(
                           define i32 @f(void()* %func) {
                           bb0:
TEST(IRInstructionMapper, InvokeIllegal) {
   std::vector<unsigned> UnsignedVec;
 
   SpecificBumpPtrAllocator<IRInstructionData> InstDataAllocator;
   SpecificBumpPtrAllocator<IRInstructionDataList> IDLAllocator;
   IRInstructionMapper Mapper(&InstDataAllocator, &IDLAllocator);
   getVectors(*M, Mapper, InstrList, UnsignedVec);
 
   ASSERT_EQ(InstrList.size(), UnsignedVec.size());
-  ASSERT_EQ(UnsignedVec.size(), static_cast<unsigned>(0));
+  ASSERT_EQ(UnsignedVec.size(), static_cast<unsigned>(1));
+  ASSERT_GT(UnsignedVec[0], Mapper.IllegalInstrNumber);
 }
 
 // Checks that an callbr instructions are considered to be illegal.  Callbr
 // instructions are considered to be illegal because of the change in the
 // control flow that is currently not recognized.
 TEST(IRInstructionMapper, CallBrInstIllegal) {
   StringRef ModuleString = R"(
   define void @test() {
TEST(IRInstructionMapper, CallBrInstIllegal) {
   std::vector<unsigned> UnsignedVec;
 
   SpecificBumpPtrAllocator<IRInstructionData> InstDataAllocator;
   SpecificBumpPtrAllocator<IRInstructionDataList> IDLAllocator;
   IRInstructionMapper Mapper(&InstDataAllocator, &IDLAllocator);
   getVectors(*M, Mapper, InstrList, UnsignedVec);
 
   ASSERT_EQ(InstrList.size(), UnsignedVec.size());
-  ASSERT_EQ(UnsignedVec.size(), static_cast<unsigned>(0));
+  ASSERT_EQ(UnsignedVec.size(), static_cast<unsigned>(1));
+  ASSERT_GT(UnsignedVec[0], Mapper.IllegalInstrNumber);
 }
 
 // Checks that an debuginfo intrinsics are mapped to be invisible.  Since they
 // do not semantically change the program, they can be recognized as similar.
 TEST(IRInstructionMapper, DebugInfoInvisible) {
   StringRef ModuleString = R"(
                           define i32 @f(i32 %a, i32 %b) {
                           then:
TEST(IRInstructionMapper, ExceptionHandlingTypeIdIllegal) {
   std::vector<unsigned> UnsignedVec;
 
   SpecificBumpPtrAllocator<IRInstructionData> InstDataAllocator;
   SpecificBumpPtrAllocator<IRInstructionDataList> IDLAllocator;
   IRInstructionMapper Mapper(&InstDataAllocator, &IDLAllocator);
   getVectors(*M, Mapper, InstrList, UnsignedVec);
 
   ASSERT_EQ(InstrList.size(), UnsignedVec.size());
-  ASSERT_EQ(UnsignedVec.size(), static_cast<unsigned>(0));
+  ASSERT_EQ(UnsignedVec.size(), static_cast<unsigned>(1));
+  ASSERT_GT(UnsignedVec[0], Mapper.IllegalInstrNumber);
 }
 
 // Checks that an eh.exceptioncode intrinsic is mapped to be illegal.
 TEST(IRInstructionMapper, ExceptionHandlingExceptionCodeIllegal) {
   StringRef ModuleString = R"(
     define i32 @f(i32 %a, i32 %b) {
     entry:
       %0 = catchswitch within none [label %__except] unwind to caller
TEST(IRInstructionMapper, ExceptionHandlingExceptionCodeIllegal) {
   std::vector<unsigned> UnsignedVec;
 
   SpecificBumpPtrAllocator<IRInstructionData> InstDataAllocator;
   SpecificBumpPtrAllocator<IRInstructionDataList> IDLAllocator;
   IRInstructionMapper Mapper(&InstDataAllocator, &IDLAllocator);
   getVectors(*M, Mapper, InstrList, UnsignedVec);
 
   ASSERT_EQ(InstrList.size(), UnsignedVec.size());
-  ASSERT_EQ(UnsignedVec.size(), static_cast<unsigned>(0));
+  ASSERT_EQ(UnsignedVec.size(), static_cast<unsigned>(1));
+  ASSERT_GT(UnsignedVec[0], Mapper.IllegalInstrNumber);
 }
 
 // Checks that an eh.unwind intrinsic is mapped to be illegal.
 TEST(IRInstructionMapper, ExceptionHandlingUnwindIllegal) {
   StringRef ModuleString = R"(
                           define i32 @f(i32 %a, i32 %b) {
                           entry:
                             call void @llvm.eh.unwind.init()
                             ret i32 0
                           }
 
                           declare void @llvm.eh.unwind.init())";
   LLVMContext Context;
   std::unique_ptr<Module> M = makeLLVMModule(Context, ModuleString);
 
   std::vector<IRInstructionData *> InstrList;
   std::vector<unsigned> UnsignedVec;
 
   SpecificBumpPtrAllocator<IRInstructionData> InstDataAllocator;
   SpecificBumpPtrAllocator<IRInstructionDataList> IDLAllocator;
   IRInstructionMapper Mapper(&InstDataAllocator, &IDLAllocator);
   getVectors(*M, Mapper, InstrList, UnsignedVec);
 
   ASSERT_EQ(InstrList.size(), UnsignedVec.size());
-  ASSERT_EQ(UnsignedVec.size(), static_cast<unsigned>(0));
+  ASSERT_EQ(UnsignedVec.size(), static_cast<unsigned>(1));
+  ASSERT_GT(UnsignedVec[0], Mapper.IllegalInstrNumber);
 }
 
 // Checks that an eh.exceptionpointer intrinsic is mapped to be illegal.
 TEST(IRInstructionMapper, ExceptionHandlingExceptionPointerIllegal) {
   StringRef ModuleString = R"(
                           define i32 @f(i32 %a, i32 %b) {
                           entry:
                             %0 = call i8* @llvm.eh.exceptionpointer.p0i8(i32 0)
                             ret i32 0
                           }
 
                           declare i8* @llvm.eh.exceptionpointer.p0i8(i32))";
   LLVMContext Context;
   std::unique_ptr<Module> M = makeLLVMModule(Context, ModuleString);
 
   std::vector<IRInstructionData *> InstrList;
   std::vector<unsigned> UnsignedVec;
 
   SpecificBumpPtrAllocator<IRInstructionData> InstDataAllocator;
   SpecificBumpPtrAllocator<IRInstructionDataList> IDLAllocator;
   IRInstructionMapper Mapper(&InstDataAllocator, &IDLAllocator);
   getVectors(*M, Mapper, InstrList, UnsignedVec);
 
   ASSERT_EQ(InstrList.size(), UnsignedVec.size());
-  ASSERT_EQ(UnsignedVec.size(), static_cast<unsigned>(0));
+  ASSERT_EQ(UnsignedVec.size(), static_cast<unsigned>(1));
+  ASSERT_GT(UnsignedVec[0], Mapper.IllegalInstrNumber);
 }
 
 // Checks that a catchpad instruction is mapped to an illegal value.
 TEST(IRInstructionMapper, CatchpadIllegal) {
   StringRef ModuleString = R"(
     declare void @llvm.donothing() nounwind readnone
 
     define void @function() personality i8 3 {
TEST(IRInstructionMapper, CatchpadIllegal) {
   std::vector<unsigned> UnsignedVec;
 
   SpecificBumpPtrAllocator<IRInstructionData> InstDataAllocator;
   SpecificBumpPtrAllocator<IRInstructionDataList> IDLAllocator;
   IRInstructionMapper Mapper(&InstDataAllocator, &IDLAllocator);
   getVectors(*M, Mapper, InstrList, UnsignedVec);
 
   ASSERT_EQ(InstrList.size(), UnsignedVec.size());
-  ASSERT_EQ(UnsignedVec.size(), static_cast<unsigned>(0));
+  ASSERT_EQ(UnsignedVec.size(), static_cast<unsigned>(1));
+  ASSERT_GT(UnsignedVec[0], Mapper.IllegalInstrNumber);
 }
 
 // Checks that a cleanuppad instruction is mapped to an illegal value.
 TEST(IRInstructionMapper, CleanuppadIllegal) {
   StringRef ModuleString = R"(
     declare void @llvm.donothing() nounwind readnone
 
     define void @function() personality i8 3 {
TEST(IRInstructionMapper, CleanuppadIllegal) {
   std::vector<unsigned> UnsignedVec;
 
   SpecificBumpPtrAllocator<IRInstructionData> InstDataAllocator;
   SpecificBumpPtrAllocator<IRInstructionDataList> IDLAllocator;
   IRInstructionMapper Mapper(&InstDataAllocator, &IDLAllocator);
   getVectors(*M, Mapper, InstrList, UnsignedVec);
 
   ASSERT_EQ(InstrList.size(), UnsignedVec.size());
-  ASSERT_EQ(UnsignedVec.size(), static_cast<unsigned>(0));
+  ASSERT_EQ(UnsignedVec.size(), static_cast<unsigned>(1));
+  ASSERT_GT(UnsignedVec[0], Mapper.IllegalInstrNumber);
 }
 
 // The following three instructions are memory transfer and setting based, which
 // are considered illegal since is extra checking needed to handle the address
 // space checking.
 
 // Checks that a memset instruction is mapped to an illegal value when
 // specified.
TEST(IRSimilarityCandidate, SamePHIStructureInternal) {
   SpecificBumpPtrAllocator<IRInstructionData> InstDataAllocator;
   SpecificBumpPtrAllocator<IRInstructionDataList> IDLAllocator;
   IRInstructionMapper Mapper(&InstDataAllocator, &IDLAllocator);
   Mapper.InstClassifier.EnableBranches = true;
   Mapper.initializeForBBs(*M);
   getVectors(*M, Mapper, InstrList, UnsignedVec);
 
   // Check to make sure that we have a long enough region.
-  ASSERT_EQ(InstrList.size(), static_cast<unsigned>(11));
+  ASSERT_EQ(InstrList.size(), static_cast<unsigned>(12));
   // Check that the instructions were added correctly to both vectors.
   ASSERT_TRUE(InstrList.size() == UnsignedVec.size());
 
   ASSERT_TRUE(longSimCandCompare(InstrList, true, 4, 0, 6));
 }
 
 // Checks that the different structure is recognized between two candidates,
 // when the phi predecessor are other blocks inside the same region,
TEST(IRSimilarityCandidate, DifferentPHIStructureInternal) {
   SpecificBumpPtrAllocator<IRInstructionData> InstDataAllocator;
   SpecificBumpPtrAllocator<IRInstructionDataList> IDLAllocator;
   IRInstructionMapper Mapper(&InstDataAllocator, &IDLAllocator);
   Mapper.InstClassifier.EnableBranches = true;
   Mapper.initializeForBBs(*M);
   getVectors(*M, Mapper, InstrList, UnsignedVec);
 
   // Check to make sure that we have a long enough region.
-  ASSERT_EQ(InstrList.size(), static_cast<unsigned>(13));
+  ASSERT_EQ(InstrList.size(), static_cast<unsigned>(14));
   // Check that the instructions were added correctly to both vectors.
   ASSERT_TRUE(InstrList.size() == UnsignedVec.size());
 
   ASSERT_FALSE(longSimCandCompare(InstrList, true, 5, 0, 7));
 }
 
 // Checks that two sets of identical instructions are found to be the same.
 // Both sequences of adds have the same operand ordering, and the same