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Differential D119223

[VE] v256.32|64 setcc isel and tests
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Authored by simoll on Feb 8 2022, 1:32 AM.

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kaz7
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rGae1bb44ed80b: [VE] v256.32|64 setcc isel and tests

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simoll created this revision.Feb 8 2022, 1:32 AM
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Harbormaster completed remote builds in B148184: Diff 406729.Feb 8 2022, 2:05 AM
kaz7 accepted this revision.Feb 8 2022, 4:09 AM

LGTM.

This revision is now accepted and ready to land.Feb 8 2022, 4:09 AM
Closed by commit rGae1bb44ed80b: [VE] v256.32|64 setcc isel and tests (authored by simoll). · Explain WhyFeb 8 2022, 4:22 AM
This revision was automatically updated to reflect the committed changes.
simoll added a commit: rGae1bb44ed80b: [VE] v256.32|64 setcc isel and tests.

Revision Contents

PathSize
llvm/
lib/
Target/
VE/
6 lines
16 lines
27 lines
2 lines
test/
CodeGen/
VE/
Vector/
681 lines
934 lines

Diff 406768

llvm/lib/Target/VE/VEISelLowering.cpp

Show First 20 Lines • Show All 2,722 Lines • ▼ Show 20 Lines return CDAG.getNode(VVPOpcode, LegalVecVT,
{Op->getOperand(0), Op->getOperand(1), Mask, AVL}); {Op->getOperand(0), Op->getOperand(1), Mask, AVL});
} }
if (VVPOpcode == VEISD::VVP_SELECT) { if (VVPOpcode == VEISD::VVP_SELECT) {
auto Mask = Op->getOperand(0); auto Mask = Op->getOperand(0);
auto OnTrue = Op->getOperand(1); auto OnTrue = Op->getOperand(1);
auto OnFalse = Op->getOperand(2); auto OnFalse = Op->getOperand(2);
return CDAG.getNode(VVPOpcode, LegalVecVT, {OnTrue, OnFalse, Mask, AVL}); return CDAG.getNode(VVPOpcode, LegalVecVT, {OnTrue, OnFalse, Mask, AVL});
} }
if (VVPOpcode == VEISD::VVP_SETCC) {
auto LHS = Op->getOperand(0);
auto RHS = Op->getOperand(1);
auto Pred = Op->getOperand(2);
return CDAG.getNode(VVPOpcode, LegalVecVT, {LHS, RHS, Pred, Mask, AVL});
}
llvm_unreachable("lowerToVVP called for unexpected SDNode."); llvm_unreachable("lowerToVVP called for unexpected SDNode.");
} }
SDValue VETargetLowering::lowerEXTRACT_VECTOR_ELT(SDValue Op, SDValue VETargetLowering::lowerEXTRACT_VECTOR_ELT(SDValue Op,
SelectionDAG &DAG) const { SelectionDAG &DAG) const {
assert(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && "Unknown opcode!"); assert(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && "Unknown opcode!");
MVT VT = Op.getOperand(0).getSimpleValueType(); MVT VT = Op.getOperand(0).getSimpleValueType();
▲ Show 20 Lines • Show All 93 Lines • Show Last 20 Lines

llvm/lib/Target/VE/VVPInstrInfo.td

Show First 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
def SDTSelectVVP : SDTypeProfile<1, 4, [ // vp_select, vp_merge def SDTSelectVVP : SDTypeProfile<1, 4, [ // vp_select, vp_merge
SDTCisVec<0>, SDTCisVec<0>,
SDTCisSameNumEltsAs<0, 3>, SDTCisSameNumEltsAs<0, 3>,
SDTCisSameAs<0, 1>, SDTCisSameAs<0, 1>,
SDTCisSameAs<1, 2>, SDTCisSameAs<1, 2>,
IsVLVT<4> IsVLVT<4>
]>; ]>;
// SetCC (lhs, rhs, cc, mask, vl)
def SDTSetCCVVP : SDTypeProfile<1, 5, [ // vp_setcc
SDTCisVec<0>,
SDTCisVec<1>,
SDTCisSameNumEltsAs<0, 1>,
SDTCisSameAs<1, 2>,
SDTCisVT<3, OtherVT>,
SDTCisInt<4>,
SDTCisSameNumEltsAs<0, 4>,
IsVLVT<5>
]>;
// Binary operator commutative pattern. // Binary operator commutative pattern.
class vvp_commutative<SDNode RootOp> : class vvp_commutative<SDNode RootOp> :
PatFrags< PatFrags<
(ops node:$lhs, node:$rhs, node:$mask, node:$vlen), (ops node:$lhs, node:$rhs, node:$mask, node:$vlen),
[(RootOp node:$lhs, node:$rhs, node:$mask, node:$vlen), [(RootOp node:$lhs, node:$rhs, node:$mask, node:$vlen),
(RootOp node:$rhs, node:$lhs, node:$mask, node:$vlen)]>; (RootOp node:$rhs, node:$lhs, node:$mask, node:$vlen)]>;
// VVP node definitions. // VVP node definitions.
Show All 26 Lines
def vvp_fsub : SDNode<"VEISD::VVP_FSUB", SDTFPBinOpVVP>; def vvp_fsub : SDNode<"VEISD::VVP_FSUB", SDTFPBinOpVVP>;
def vvp_fmul : SDNode<"VEISD::VVP_FMUL", SDTFPBinOpVVP>; def vvp_fmul : SDNode<"VEISD::VVP_FMUL", SDTFPBinOpVVP>;
def c_vvp_fmul : vvp_commutative<vvp_fmul>; def c_vvp_fmul : vvp_commutative<vvp_fmul>;
def vvp_fdiv : SDNode<"VEISD::VVP_FDIV", SDTFPBinOpVVP>; def vvp_fdiv : SDNode<"VEISD::VVP_FDIV", SDTFPBinOpVVP>;
// } Binary Operators // } Binary Operators
def vvp_select : SDNode<"VEISD::VVP_SELECT", SDTSelectVVP>; def vvp_select : SDNode<"VEISD::VVP_SELECT", SDTSelectVVP>;
// setcc (lhs, rhs, cc, mask, vl)
def vvp_setcc : SDNode<"VEISD::VVP_SETCC", SDTSetCCVVP>;

llvm/lib/Target/VE/VVPInstrPatternsVec.td

Show First 20 Lines • Show All 287 Lines • ▼ Show 20 Lines
} }
defm : Merge_mvv_ShortLong<vvp_select, defm : Merge_mvv_ShortLong<vvp_select,
v256f64, v256f64,
v256f32, "VMRG">; v256f32, "VMRG">;
defm : Merge_mvv_ShortLong<vvp_select, defm : Merge_mvv_ShortLong<vvp_select,
v256i64, v256i64,
v256i32, "VMRG">; v256i32, "VMRG">;
multiclass Set_CC<ValueType DataVT, string FmkBaseName, string CmpBaseName, SDPatternOperator CCMatcher, SDNodeXForm CCConv> {
// Unmasked.
def : Pat<(v256i1 (vvp_setcc
DataVT:$LHS, DataVT:$RHS, CCMatcher:$cond, (v256i1 true_mask), i32:$vl)),
(!cast<Instruction>(FmkBaseName#"vl")
(CCConv $cond),
(!cast<Instruction>(CmpBaseName#"vvl")
$LHS, $RHS, $vl),
$vl)>;
// Masked.
def : Pat<(v256i1 (vvp_setcc
DataVT:$LHS, DataVT:$RHS, CCMatcher:$cond, v256i1:$vm, i32:$vl)),
(!cast<Instruction>(FmkBaseName#"vml")
(CCConv $cond),
(!cast<Instruction>(CmpBaseName#"vvl")
$LHS, $RHS, $vl),
$vm, $vl)>;
}
defm : Set_CC<v256i64,"VFMKL","VCMPUL",CCUIOp,icond2cc>;
defm : Set_CC<v256i64,"VFMKL","VCMPSL",CCSIOp,icond2cc>;
defm : Set_CC<v256f64,"VFMKL","VFCMPD",cond,fcond2cc>;
defm : Set_CC<v256i32,"VFMKW","VCMPUW",CCUIOp,icond2cc>;
defm : Set_CC<v256i32,"VFMKW","VCMPSWZX",CCSIOp,icond2cc>;
defm : Set_CC<v256f32,"VFMKS","VFCMPS",cond,fcond2cc>;

llvm/lib/Target/VE/VVPNodes.def

Show First 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
ADD_BINARY_VVP_OP_COMPACT(XOR) ADD_BINARY_VVP_OP_COMPACT(XOR)
// FP arithmetic. // FP arithmetic.
ADD_BINARY_VVP_OP_COMPACT(FADD) ADD_BINARY_VVP_OP_COMPACT(FADD)
ADD_BINARY_VVP_OP_COMPACT(FSUB) ADD_BINARY_VVP_OP_COMPACT(FSUB)
ADD_BINARY_VVP_OP_COMPACT(FMUL) ADD_BINARY_VVP_OP_COMPACT(FMUL)
ADD_BINARY_VVP_OP_COMPACT(FDIV) ADD_BINARY_VVP_OP_COMPACT(FDIV)
ADD_VVP_OP(VVP_SETCC, SETCC)
// Shuffles. // Shuffles.
ADD_VVP_OP(VVP_SELECT,VSELECT) ADD_VVP_OP(VVP_SELECT,VSELECT)
HANDLE_VP_TO_VVP(VP_SELECT, VVP_SELECT) HANDLE_VP_TO_VVP(VP_SELECT, VVP_SELECT)
HANDLE_VP_TO_VVP(VP_MERGE, VVP_SELECT) HANDLE_VP_TO_VVP(VP_MERGE, VVP_SELECT)
#undef ADD_BINARY_VVP_OP #undef ADD_BINARY_VVP_OP
#undef ADD_BINARY_VVP_OP_COMPACT #undef ADD_BINARY_VVP_OP_COMPACT
#undef ADD_VVP_OP #undef ADD_VVP_OP
#undef HANDLE_VP_TO_VVP #undef HANDLE_VP_TO_VVP

llvm/test/CodeGen/VE/Vector/vec_fcmp.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
; <256 x float>
;; TODO v256i1 zero-mask isel
;; ; Function Attrs: nounwind
;; define fastcc <256 x i1> @fcmp_false_vv_v256f32(<256 x float> %x, <256 x float> %y) {
;; %z = fcmp false <256 x float> %x, %y
;; ret <256 x i1> %z
;; }
;;
;; ; Function Attrs: nounwind
;; define fastcc <256 x i1> @fcmp_false_sv_v256f32(float %x, <256 x float> %y) {
;; %xins = insertelement <256 x float> undef, float %x, i32 0
;; %vx = shufflevector <256 x float> %xins, <256 x float> undef, <256 x i32> zeroinitializer
;; %z = fcmp false <256 x float> %vx, %y
;; ret <256 x i1> %z
;; }
;;
;; ; Function Attrs: nounwind
;; define fastcc <256 x i1> @fcmp_false_vs_v256f32(<256 x float> %x, float %y) {
;; %yins = insertelement <256 x float> undef, float %y, i32 0
;; %vy = shufflevector <256 x float> %yins, <256 x float> undef, <256 x i32> zeroinitializer
;; %z = fcmp false <256 x float> %x, %vy
;; ret <256 x i1> %z
;; }
; Function Attrs: nounwind
define fastcc <256 x i1> @fcmp_oeq_vv_v256f32(<256 x float> %x, <256 x float> %y) {
; CHECK-LABEL: fcmp_oeq_vv_v256f32:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 256
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vfcmp.s %v0, %v0, %v1
; CHECK-NEXT: vfmk.s.eq %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%z = fcmp oeq <256 x float> %x, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @fcmp_oeq_sv_v256f32(float %x, <256 x float> %y) {
; CHECK-LABEL: fcmp_oeq_sv_v256f32:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vfcmp.s %v0, %v1, %v0
; CHECK-NEXT: vfmk.s.eq %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%xins = insertelement <256 x float> undef, float %x, i32 0
%vx = shufflevector <256 x float> %xins, <256 x float> undef, <256 x i32> zeroinitializer
%z = fcmp oeq <256 x float> %vx, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @fcmp_oeq_vs_v256f32(<256 x float> %x, float %y) {
; CHECK-LABEL: fcmp_oeq_vs_v256f32:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vfcmp.s %v0, %v0, %v1
; CHECK-NEXT: vfmk.s.eq %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%yins = insertelement <256 x float> undef, float %y, i32 0
%vy = shufflevector <256 x float> %yins, <256 x float> undef, <256 x i32> zeroinitializer
%z = fcmp oeq <256 x float> %x, %vy
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @fcmp_ogt_vv_v256f32(<256 x float> %x, <256 x float> %y) {
; CHECK-LABEL: fcmp_ogt_vv_v256f32:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 256
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vfcmp.s %v0, %v0, %v1
; CHECK-NEXT: vfmk.s.gt %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%z = fcmp ogt <256 x float> %x, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @fcmp_ogt_sv_v256f32(float %x, <256 x float> %y) {
; CHECK-LABEL: fcmp_ogt_sv_v256f32:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vfcmp.s %v0, %v1, %v0
; CHECK-NEXT: vfmk.s.gt %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%xins = insertelement <256 x float> undef, float %x, i32 0
%vx = shufflevector <256 x float> %xins, <256 x float> undef, <256 x i32> zeroinitializer
%z = fcmp ogt <256 x float> %vx, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @fcmp_ogt_vs_v256f32(<256 x float> %x, float %y) {
; CHECK-LABEL: fcmp_ogt_vs_v256f32:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vfcmp.s %v0, %v0, %v1
; CHECK-NEXT: vfmk.s.gt %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%yins = insertelement <256 x float> undef, float %y, i32 0
%vy = shufflevector <256 x float> %yins, <256 x float> undef, <256 x i32> zeroinitializer
%z = fcmp ogt <256 x float> %x, %vy
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @fcmp_oge_vv_v256f32(<256 x float> %x, <256 x float> %y) {
; CHECK-LABEL: fcmp_oge_vv_v256f32:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 256
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vfcmp.s %v0, %v0, %v1
; CHECK-NEXT: vfmk.s.ge %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%z = fcmp oge <256 x float> %x, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @fcmp_oge_sv_v256f32(float %x, <256 x float> %y) {
; CHECK-LABEL: fcmp_oge_sv_v256f32:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vfcmp.s %v0, %v1, %v0
; CHECK-NEXT: vfmk.s.ge %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%xins = insertelement <256 x float> undef, float %x, i32 0
%vx = shufflevector <256 x float> %xins, <256 x float> undef, <256 x i32> zeroinitializer
%z = fcmp oge <256 x float> %vx, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @fcmp_oge_vs_v256f32(<256 x float> %x, float %y) {
; CHECK-LABEL: fcmp_oge_vs_v256f32:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vfcmp.s %v0, %v0, %v1
; CHECK-NEXT: vfmk.s.ge %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%yins = insertelement <256 x float> undef, float %y, i32 0
%vy = shufflevector <256 x float> %yins, <256 x float> undef, <256 x i32> zeroinitializer
%z = fcmp oge <256 x float> %x, %vy
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @fcmp_olt_vv_v256f32(<256 x float> %x, <256 x float> %y) {
; CHECK-LABEL: fcmp_olt_vv_v256f32:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 256
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vfcmp.s %v0, %v0, %v1
; CHECK-NEXT: vfmk.s.lt %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%z = fcmp olt <256 x float> %x, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @fcmp_olt_sv_v256f32(float %x, <256 x float> %y) {
; CHECK-LABEL: fcmp_olt_sv_v256f32:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vfcmp.s %v0, %v1, %v0
; CHECK-NEXT: vfmk.s.lt %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%xins = insertelement <256 x float> undef, float %x, i32 0
%vx = shufflevector <256 x float> %xins, <256 x float> undef, <256 x i32> zeroinitializer
%z = fcmp olt <256 x float> %vx, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @fcmp_olt_vs_v256f32(<256 x float> %x, float %y) {
; CHECK-LABEL: fcmp_olt_vs_v256f32:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vfcmp.s %v0, %v0, %v1
; CHECK-NEXT: vfmk.s.lt %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%yins = insertelement <256 x float> undef, float %y, i32 0
%vy = shufflevector <256 x float> %yins, <256 x float> undef, <256 x i32> zeroinitializer
%z = fcmp olt <256 x float> %x, %vy
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @fcmp_ole_vv_v256f32(<256 x float> %x, <256 x float> %y) {
; CHECK-LABEL: fcmp_ole_vv_v256f32:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 256
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vfcmp.s %v0, %v0, %v1
; CHECK-NEXT: vfmk.s.le %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%z = fcmp ole <256 x float> %x, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @fcmp_ole_sv_v256f32(float %x, <256 x float> %y) {
; CHECK-LABEL: fcmp_ole_sv_v256f32:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vfcmp.s %v0, %v1, %v0
; CHECK-NEXT: vfmk.s.le %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%xins = insertelement <256 x float> undef, float %x, i32 0
%vx = shufflevector <256 x float> %xins, <256 x float> undef, <256 x i32> zeroinitializer
%z = fcmp ole <256 x float> %vx, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @fcmp_ole_vs_v256f32(<256 x float> %x, float %y) {
; CHECK-LABEL: fcmp_ole_vs_v256f32:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vfcmp.s %v0, %v0, %v1
; CHECK-NEXT: vfmk.s.le %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%yins = insertelement <256 x float> undef, float %y, i32 0
%vy = shufflevector <256 x float> %yins, <256 x float> undef, <256 x i32> zeroinitializer
%z = fcmp ole <256 x float> %x, %vy
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @fcmp_one_vv_v256f32(<256 x float> %x, <256 x float> %y) {
; CHECK-LABEL: fcmp_one_vv_v256f32:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 256
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vfcmp.s %v0, %v0, %v1
; CHECK-NEXT: vfmk.s.ne %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%z = fcmp one <256 x float> %x, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @fcmp_one_sv_v256f32(float %x, <256 x float> %y) {
; CHECK-LABEL: fcmp_one_sv_v256f32:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vfcmp.s %v0, %v1, %v0
; CHECK-NEXT: vfmk.s.ne %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%xins = insertelement <256 x float> undef, float %x, i32 0
%vx = shufflevector <256 x float> %xins, <256 x float> undef, <256 x i32> zeroinitializer
%z = fcmp one <256 x float> %vx, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @fcmp_one_vs_v256f32(<256 x float> %x, float %y) {
; CHECK-LABEL: fcmp_one_vs_v256f32:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vfcmp.s %v0, %v0, %v1
; CHECK-NEXT: vfmk.s.ne %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%yins = insertelement <256 x float> undef, float %y, i32 0
%vy = shufflevector <256 x float> %yins, <256 x float> undef, <256 x i32> zeroinitializer
%z = fcmp one <256 x float> %x, %vy
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @fcmp_ord_vv_v256f32(<256 x float> %x, <256 x float> %y) {
; CHECK-LABEL: fcmp_ord_vv_v256f32:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 256
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vfcmp.s %v0, %v0, %v1
; CHECK-NEXT: vfmk.s.num %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%z = fcmp ord <256 x float> %x, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @fcmp_ord_sv_v256f32(float %x, <256 x float> %y) {
; CHECK-LABEL: fcmp_ord_sv_v256f32:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vfcmp.s %v0, %v1, %v0
; CHECK-NEXT: vfmk.s.num %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%xins = insertelement <256 x float> undef, float %x, i32 0
%vx = shufflevector <256 x float> %xins, <256 x float> undef, <256 x i32> zeroinitializer
%z = fcmp ord <256 x float> %vx, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @fcmp_ord_vs_v256f32(<256 x float> %x, float %y) {
; CHECK-LABEL: fcmp_ord_vs_v256f32:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vfcmp.s %v0, %v0, %v1
; CHECK-NEXT: vfmk.s.num %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%yins = insertelement <256 x float> undef, float %y, i32 0
%vy = shufflevector <256 x float> %yins, <256 x float> undef, <256 x i32> zeroinitializer
%z = fcmp ord <256 x float> %x, %vy
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @fcmp_uno_vv_v256f32(<256 x float> %x, <256 x float> %y) {
; CHECK-LABEL: fcmp_uno_vv_v256f32:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 256
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vfcmp.s %v0, %v0, %v1
; CHECK-NEXT: vfmk.s.nan %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%z = fcmp uno <256 x float> %x, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @fcmp_uno_sv_v256f32(float %x, <256 x float> %y) {
; CHECK-LABEL: fcmp_uno_sv_v256f32:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vfcmp.s %v0, %v1, %v0
; CHECK-NEXT: vfmk.s.nan %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%xins = insertelement <256 x float> undef, float %x, i32 0
%vx = shufflevector <256 x float> %xins, <256 x float> undef, <256 x i32> zeroinitializer
%z = fcmp uno <256 x float> %vx, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @fcmp_uno_vs_v256f32(<256 x float> %x, float %y) {
; CHECK-LABEL: fcmp_uno_vs_v256f32:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vfcmp.s %v0, %v0, %v1
; CHECK-NEXT: vfmk.s.nan %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%yins = insertelement <256 x float> undef, float %y, i32 0
%vy = shufflevector <256 x float> %yins, <256 x float> undef, <256 x i32> zeroinitializer
%z = fcmp uno <256 x float> %x, %vy
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @fcmp_ueq_vv_v256f32(<256 x float> %x, <256 x float> %y) {
; CHECK-LABEL: fcmp_ueq_vv_v256f32:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 256
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vfcmp.s %v0, %v0, %v1
; CHECK-NEXT: vfmk.s.eqnan %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%z = fcmp ueq <256 x float> %x, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @fcmp_ueq_sv_v256f32(float %x, <256 x float> %y) {
; CHECK-LABEL: fcmp_ueq_sv_v256f32:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vfcmp.s %v0, %v1, %v0
; CHECK-NEXT: vfmk.s.eqnan %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%xins = insertelement <256 x float> undef, float %x, i32 0
%vx = shufflevector <256 x float> %xins, <256 x float> undef, <256 x i32> zeroinitializer
%z = fcmp ueq <256 x float> %vx, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @fcmp_ueq_vs_v256f32(<256 x float> %x, float %y) {
; CHECK-LABEL: fcmp_ueq_vs_v256f32:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vfcmp.s %v0, %v0, %v1
; CHECK-NEXT: vfmk.s.eqnan %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%yins = insertelement <256 x float> undef, float %y, i32 0
%vy = shufflevector <256 x float> %yins, <256 x float> undef, <256 x i32> zeroinitializer
%z = fcmp ueq <256 x float> %x, %vy
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @fcmp_ugt_vv_v256f32(<256 x float> %x, <256 x float> %y) {
; CHECK-LABEL: fcmp_ugt_vv_v256f32:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 256
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vfcmp.s %v0, %v0, %v1
; CHECK-NEXT: vfmk.s.gtnan %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%z = fcmp ugt <256 x float> %x, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @fcmp_ugt_sv_v256f32(float %x, <256 x float> %y) {
; CHECK-LABEL: fcmp_ugt_sv_v256f32:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vfcmp.s %v0, %v1, %v0
; CHECK-NEXT: vfmk.s.gtnan %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%xins = insertelement <256 x float> undef, float %x, i32 0
%vx = shufflevector <256 x float> %xins, <256 x float> undef, <256 x i32> zeroinitializer
%z = fcmp ugt <256 x float> %vx, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @fcmp_ugt_vs_v256f32(<256 x float> %x, float %y) {
; CHECK-LABEL: fcmp_ugt_vs_v256f32:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vfcmp.s %v0, %v0, %v1
; CHECK-NEXT: vfmk.s.gtnan %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%yins = insertelement <256 x float> undef, float %y, i32 0
%vy = shufflevector <256 x float> %yins, <256 x float> undef, <256 x i32> zeroinitializer
%z = fcmp ugt <256 x float> %x, %vy
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @fcmp_uge_vv_v256f32(<256 x float> %x, <256 x float> %y) {
; CHECK-LABEL: fcmp_uge_vv_v256f32:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 256
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vfcmp.s %v0, %v0, %v1
; CHECK-NEXT: vfmk.s.genan %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%z = fcmp uge <256 x float> %x, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @fcmp_uge_sv_v256f32(float %x, <256 x float> %y) {
; CHECK-LABEL: fcmp_uge_sv_v256f32:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vfcmp.s %v0, %v1, %v0
; CHECK-NEXT: vfmk.s.genan %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%xins = insertelement <256 x float> undef, float %x, i32 0
%vx = shufflevector <256 x float> %xins, <256 x float> undef, <256 x i32> zeroinitializer
%z = fcmp uge <256 x float> %vx, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @fcmp_uge_vs_v256f32(<256 x float> %x, float %y) {
; CHECK-LABEL: fcmp_uge_vs_v256f32:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vfcmp.s %v0, %v0, %v1
; CHECK-NEXT: vfmk.s.genan %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%yins = insertelement <256 x float> undef, float %y, i32 0
%vy = shufflevector <256 x float> %yins, <256 x float> undef, <256 x i32> zeroinitializer
%z = fcmp uge <256 x float> %x, %vy
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @fcmp_ult_vv_v256f32(<256 x float> %x, <256 x float> %y) {
; CHECK-LABEL: fcmp_ult_vv_v256f32:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 256
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vfcmp.s %v0, %v0, %v1
; CHECK-NEXT: vfmk.s.ltnan %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%z = fcmp ult <256 x float> %x, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @fcmp_ult_sv_v256f32(float %x, <256 x float> %y) {
; CHECK-LABEL: fcmp_ult_sv_v256f32:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vfcmp.s %v0, %v1, %v0
; CHECK-NEXT: vfmk.s.ltnan %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%xins = insertelement <256 x float> undef, float %x, i32 0
%vx = shufflevector <256 x float> %xins, <256 x float> undef, <256 x i32> zeroinitializer
%z = fcmp ult <256 x float> %vx, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @fcmp_ult_vs_v256f32(<256 x float> %x, float %y) {
; CHECK-LABEL: fcmp_ult_vs_v256f32:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vfcmp.s %v0, %v0, %v1
; CHECK-NEXT: vfmk.s.ltnan %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%yins = insertelement <256 x float> undef, float %y, i32 0
%vy = shufflevector <256 x float> %yins, <256 x float> undef, <256 x i32> zeroinitializer
%z = fcmp ult <256 x float> %x, %vy
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @fcmp_ule_vv_v256f32(<256 x float> %x, <256 x float> %y) {
; CHECK-LABEL: fcmp_ule_vv_v256f32:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 256
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vfcmp.s %v0, %v0, %v1
; CHECK-NEXT: vfmk.s.lenan %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%z = fcmp ule <256 x float> %x, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @fcmp_ule_sv_v256f32(float %x, <256 x float> %y) {
; CHECK-LABEL: fcmp_ule_sv_v256f32:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vfcmp.s %v0, %v1, %v0
; CHECK-NEXT: vfmk.s.lenan %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%xins = insertelement <256 x float> undef, float %x, i32 0
%vx = shufflevector <256 x float> %xins, <256 x float> undef, <256 x i32> zeroinitializer
%z = fcmp ule <256 x float> %vx, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @fcmp_ule_vs_v256f32(<256 x float> %x, float %y) {
; CHECK-LABEL: fcmp_ule_vs_v256f32:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vfcmp.s %v0, %v0, %v1
; CHECK-NEXT: vfmk.s.lenan %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%yins = insertelement <256 x float> undef, float %y, i32 0
%vy = shufflevector <256 x float> %yins, <256 x float> undef, <256 x i32> zeroinitializer
%z = fcmp ule <256 x float> %x, %vy
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @fcmp_une_vv_v256f32(<256 x float> %x, <256 x float> %y) {
; CHECK-LABEL: fcmp_une_vv_v256f32:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 256
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vfcmp.s %v0, %v0, %v1
; CHECK-NEXT: vfmk.s.nenan %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%z = fcmp une <256 x float> %x, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @fcmp_une_sv_v256f32(float %x, <256 x float> %y) {
; CHECK-LABEL: fcmp_une_sv_v256f32:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vfcmp.s %v0, %v1, %v0
; CHECK-NEXT: vfmk.s.nenan %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%xins = insertelement <256 x float> undef, float %x, i32 0
%vx = shufflevector <256 x float> %xins, <256 x float> undef, <256 x i32> zeroinitializer
%z = fcmp une <256 x float> %vx, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @fcmp_une_vs_v256f32(<256 x float> %x, float %y) {
; CHECK-LABEL: fcmp_une_vs_v256f32:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vfcmp.s %v0, %v0, %v1
; CHECK-NEXT: vfmk.s.nenan %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%yins = insertelement <256 x float> undef, float %y, i32 0
%vy = shufflevector <256 x float> %yins, <256 x float> undef, <256 x i32> zeroinitializer
%z = fcmp une <256 x float> %x, %vy
ret <256 x i1> %z
}
;; TODO v256i1 all-one mask isel.
;; ; Function Attrs: nounwind
;; define fastcc <256 x i1> @fcmp_true_vv_v256f32(<256 x float> %x, <256 x float> %y) {
;; %z = fcmp true <256 x float> %x, %y
;; ret <256 x i1> %z
;; }
;;
;; ; Function Attrs: nounwind
;; define fastcc <256 x i1> @fcmp_true_sv_v256f32(float %x, <256 x float> %y) {
;; %xins = insertelement <256 x float> undef, float %x, i32 0
;; %vx = shufflevector <256 x float> %xins, <256 x float> undef, <256 x i32> zeroinitializer
;; %z = fcmp true <256 x float> %vx, %y
;; ret <256 x i1> %z
;; }
;;
;; ; Function Attrs: nounwind
;; define fastcc <256 x i1> @fcmp_true_vs_v256f32(<256 x float> %x, float %y) {
;; %yins = insertelement <256 x float> undef, float %y, i32 0
;; %vy = shufflevector <256 x float> %yins, <256 x float> undef, <256 x i32> zeroinitializer
;; %z = fcmp true <256 x float> %x, %vy
;; ret <256 x i1> %z
;; }

llvm/test/CodeGen/VE/Vector/vec_icmp.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
; <256 x i32>
; Function Attrs: nounwind
define fastcc <256 x i1> @icmp_sgt_vv_v256i32(<256 x i32> %x, <256 x i32> %y) {
; CHECK-LABEL: icmp_sgt_vv_v256i32:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 256
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vcmps.w.zx %v0, %v0, %v1
; CHECK-NEXT: vfmk.w.gt %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%z = icmp sgt <256 x i32> %x, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @icmp_sgt_sv_v256i32(i32 %x, <256 x i32> %y) {
; CHECK-LABEL: icmp_sgt_sv_v256i32:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vcmps.w.zx %v0, %v1, %v0
; CHECK-NEXT: vfmk.w.gt %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%xins = insertelement <256 x i32> undef, i32 %x, i32 0
%vx = shufflevector <256 x i32> %xins, <256 x i32> undef, <256 x i32> zeroinitializer
%z = icmp sgt <256 x i32> %vx, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @icmp_sgt_vs_v256i32(<256 x i32> %x, i32 %y) {
; CHECK-LABEL: icmp_sgt_vs_v256i32:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vcmps.w.zx %v0, %v0, %v1
; CHECK-NEXT: vfmk.w.gt %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%yins = insertelement <256 x i32> undef, i32 %y, i32 0
%vy = shufflevector <256 x i32> %yins, <256 x i32> undef, <256 x i32> zeroinitializer
%z = icmp sgt <256 x i32> %x, %vy
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @icmp_sge_vv_v256i32(<256 x i32> %x, <256 x i32> %y) {
; CHECK-LABEL: icmp_sge_vv_v256i32:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 256
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vcmps.w.zx %v0, %v0, %v1
; CHECK-NEXT: vfmk.w.ge %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%z = icmp sge <256 x i32> %x, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @icmp_sge_sv_v256i32(i32 %x, <256 x i32> %y) {
; CHECK-LABEL: icmp_sge_sv_v256i32:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vcmps.w.zx %v0, %v1, %v0
; CHECK-NEXT: vfmk.w.ge %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%xins = insertelement <256 x i32> undef, i32 %x, i32 0
%vx = shufflevector <256 x i32> %xins, <256 x i32> undef, <256 x i32> zeroinitializer
%z = icmp sge <256 x i32> %vx, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @icmp_sge_vs_v256i32(<256 x i32> %x, i32 %y) {
; CHECK-LABEL: icmp_sge_vs_v256i32:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vcmps.w.zx %v0, %v0, %v1
; CHECK-NEXT: vfmk.w.ge %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%yins = insertelement <256 x i32> undef, i32 %y, i32 0
%vy = shufflevector <256 x i32> %yins, <256 x i32> undef, <256 x i32> zeroinitializer
%z = icmp sge <256 x i32> %x, %vy
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @icmp_eq_vv_v256i32(<256 x i32> %x, <256 x i32> %y) {
; CHECK-LABEL: icmp_eq_vv_v256i32:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 256
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vcmpu.w %v0, %v0, %v1
; CHECK-NEXT: vfmk.w.eq %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%z = icmp eq <256 x i32> %x, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @icmp_eq_sv_v256i32(i32 %x, <256 x i32> %y) {
; CHECK-LABEL: icmp_eq_sv_v256i32:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vcmpu.w %v0, %v1, %v0
; CHECK-NEXT: vfmk.w.eq %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%xins = insertelement <256 x i32> undef, i32 %x, i32 0
%vx = shufflevector <256 x i32> %xins, <256 x i32> undef, <256 x i32> zeroinitializer
%z = icmp eq <256 x i32> %vx, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @icmp_eq_vs_v256i32(<256 x i32> %x, i32 %y) {
; CHECK-LABEL: icmp_eq_vs_v256i32:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vcmpu.w %v0, %v0, %v1
; CHECK-NEXT: vfmk.w.eq %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%yins = insertelement <256 x i32> undef, i32 %y, i32 0
%vy = shufflevector <256 x i32> %yins, <256 x i32> undef, <256 x i32> zeroinitializer
%z = icmp eq <256 x i32> %x, %vy
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @icmp_ne_vv_v256i32(<256 x i32> %x, <256 x i32> %y) {
; CHECK-LABEL: icmp_ne_vv_v256i32:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 256
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vcmpu.w %v0, %v0, %v1
; CHECK-NEXT: vfmk.w.ne %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%z = icmp ne <256 x i32> %x, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @icmp_ne_sv_v256i32(i32 %x, <256 x i32> %y) {
; CHECK-LABEL: icmp_ne_sv_v256i32:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vcmpu.w %v0, %v1, %v0
; CHECK-NEXT: vfmk.w.ne %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%xins = insertelement <256 x i32> undef, i32 %x, i32 0
%vx = shufflevector <256 x i32> %xins, <256 x i32> undef, <256 x i32> zeroinitializer
%z = icmp ne <256 x i32> %vx, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @icmp_ne_vs_v256i32(<256 x i32> %x, i32 %y) {
; CHECK-LABEL: icmp_ne_vs_v256i32:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vcmpu.w %v0, %v0, %v1
; CHECK-NEXT: vfmk.w.ne %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%yins = insertelement <256 x i32> undef, i32 %y, i32 0
%vy = shufflevector <256 x i32> %yins, <256 x i32> undef, <256 x i32> zeroinitializer
%z = icmp ne <256 x i32> %x, %vy
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @icmp_sle_vv_v256i32(<256 x i32> %x, <256 x i32> %y) {
; CHECK-LABEL: icmp_sle_vv_v256i32:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 256
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vcmps.w.zx %v0, %v0, %v1
; CHECK-NEXT: vfmk.w.le %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%z = icmp sle <256 x i32> %x, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @icmp_sle_sv_v256i32(i32 %x, <256 x i32> %y) {
; CHECK-LABEL: icmp_sle_sv_v256i32:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vcmps.w.zx %v0, %v1, %v0
; CHECK-NEXT: vfmk.w.le %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%xins = insertelement <256 x i32> undef, i32 %x, i32 0
%vx = shufflevector <256 x i32> %xins, <256 x i32> undef, <256 x i32> zeroinitializer
%z = icmp sle <256 x i32> %vx, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @icmp_sle_vs_v256i32(<256 x i32> %x, i32 %y) {
; CHECK-LABEL: icmp_sle_vs_v256i32:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vcmps.w.zx %v0, %v0, %v1
; CHECK-NEXT: vfmk.w.le %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%yins = insertelement <256 x i32> undef, i32 %y, i32 0
%vy = shufflevector <256 x i32> %yins, <256 x i32> undef, <256 x i32> zeroinitializer
%z = icmp sle <256 x i32> %x, %vy
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @icmp_slt_vv_v256i32(<256 x i32> %x, <256 x i32> %y) {
; CHECK-LABEL: icmp_slt_vv_v256i32:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 256
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vcmps.w.zx %v0, %v0, %v1
; CHECK-NEXT: vfmk.w.lt %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%z = icmp slt <256 x i32> %x, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @icmp_slt_sv_v256i32(i32 %x, <256 x i32> %y) {
; CHECK-LABEL: icmp_slt_sv_v256i32:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vcmps.w.zx %v0, %v1, %v0
; CHECK-NEXT: vfmk.w.lt %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%xins = insertelement <256 x i32> undef, i32 %x, i32 0
%vx = shufflevector <256 x i32> %xins, <256 x i32> undef, <256 x i32> zeroinitializer
%z = icmp slt <256 x i32> %vx, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @icmp_slt_vs_v256i32(<256 x i32> %x, i32 %y) {
; CHECK-LABEL: icmp_slt_vs_v256i32:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vcmps.w.zx %v0, %v0, %v1
; CHECK-NEXT: vfmk.w.lt %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%yins = insertelement <256 x i32> undef, i32 %y, i32 0
%vy = shufflevector <256 x i32> %yins, <256 x i32> undef, <256 x i32> zeroinitializer
%z = icmp slt <256 x i32> %x, %vy
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @icmp_ugt_vv_v256i32(<256 x i32> %x, <256 x i32> %y) {
; CHECK-LABEL: icmp_ugt_vv_v256i32:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 256
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vcmpu.w %v0, %v0, %v1
; CHECK-NEXT: vfmk.w.gt %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%z = icmp ugt <256 x i32> %x, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @icmp_ugt_sv_v256i32(i32 %x, <256 x i32> %y) {
; CHECK-LABEL: icmp_ugt_sv_v256i32:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vcmpu.w %v0, %v1, %v0
; CHECK-NEXT: vfmk.w.gt %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%xins = insertelement <256 x i32> undef, i32 %x, i32 0
%vx = shufflevector <256 x i32> %xins, <256 x i32> undef, <256 x i32> zeroinitializer
%z = icmp ugt <256 x i32> %vx, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @icmp_ugt_vs_v256i32(<256 x i32> %x, i32 %y) {
; CHECK-LABEL: icmp_ugt_vs_v256i32:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vcmpu.w %v0, %v0, %v1
; CHECK-NEXT: vfmk.w.gt %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%yins = insertelement <256 x i32> undef, i32 %y, i32 0
%vy = shufflevector <256 x i32> %yins, <256 x i32> undef, <256 x i32> zeroinitializer
%z = icmp ugt <256 x i32> %x, %vy
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @icmp_uge_vv_v256i32(<256 x i32> %x, <256 x i32> %y) {
; CHECK-LABEL: icmp_uge_vv_v256i32:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 256
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vcmpu.w %v0, %v0, %v1
; CHECK-NEXT: vfmk.w.ge %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%z = icmp uge <256 x i32> %x, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @icmp_uge_sv_v256i32(i32 %x, <256 x i32> %y) {
; CHECK-LABEL: icmp_uge_sv_v256i32:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vcmpu.w %v0, %v1, %v0
; CHECK-NEXT: vfmk.w.ge %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%xins = insertelement <256 x i32> undef, i32 %x, i32 0
%vx = shufflevector <256 x i32> %xins, <256 x i32> undef, <256 x i32> zeroinitializer
%z = icmp uge <256 x i32> %vx, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @icmp_uge_vs_v256i32(<256 x i32> %x, i32 %y) {
; CHECK-LABEL: icmp_uge_vs_v256i32:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vcmpu.w %v0, %v0, %v1
; CHECK-NEXT: vfmk.w.ge %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%yins = insertelement <256 x i32> undef, i32 %y, i32 0
%vy = shufflevector <256 x i32> %yins, <256 x i32> undef, <256 x i32> zeroinitializer
%z = icmp uge <256 x i32> %x, %vy
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @icmp_ule_vv_v256i32(<256 x i32> %x, <256 x i32> %y) {
; CHECK-LABEL: icmp_ule_vv_v256i32:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 256
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vcmpu.w %v0, %v0, %v1
; CHECK-NEXT: vfmk.w.le %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%z = icmp ule <256 x i32> %x, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @icmp_ule_sv_v256i32(i32 %x, <256 x i32> %y) {
; CHECK-LABEL: icmp_ule_sv_v256i32:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vcmpu.w %v0, %v1, %v0
; CHECK-NEXT: vfmk.w.le %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%xins = insertelement <256 x i32> undef, i32 %x, i32 0
%vx = shufflevector <256 x i32> %xins, <256 x i32> undef, <256 x i32> zeroinitializer
%z = icmp ule <256 x i32> %vx, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @icmp_ule_vs_v256i32(<256 x i32> %x, i32 %y) {
; CHECK-LABEL: icmp_ule_vs_v256i32:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vcmpu.w %v0, %v0, %v1
; CHECK-NEXT: vfmk.w.le %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%yins = insertelement <256 x i32> undef, i32 %y, i32 0
%vy = shufflevector <256 x i32> %yins, <256 x i32> undef, <256 x i32> zeroinitializer
%z = icmp ule <256 x i32> %x, %vy
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @icmp_ult_vv_v256i32(<256 x i32> %x, <256 x i32> %y) {
; CHECK-LABEL: icmp_ult_vv_v256i32:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 256
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vcmpu.w %v0, %v0, %v1
; CHECK-NEXT: vfmk.w.lt %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%z = icmp ult <256 x i32> %x, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @icmp_ult_sv_v256i32(i32 %x, <256 x i32> %y) {
; CHECK-LABEL: icmp_ult_sv_v256i32:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vcmpu.w %v0, %v1, %v0
; CHECK-NEXT: vfmk.w.lt %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%xins = insertelement <256 x i32> undef, i32 %x, i32 0
%vx = shufflevector <256 x i32> %xins, <256 x i32> undef, <256 x i32> zeroinitializer
%z = icmp ult <256 x i32> %vx, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @icmp_ult_vs_v256i32(<256 x i32> %x, i32 %y) {
; CHECK-LABEL: icmp_ult_vs_v256i32:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vcmpu.w %v0, %v0, %v1
; CHECK-NEXT: vfmk.w.lt %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%yins = insertelement <256 x i32> undef, i32 %y, i32 0
%vy = shufflevector <256 x i32> %yins, <256 x i32> undef, <256 x i32> zeroinitializer
%z = icmp ult <256 x i32> %x, %vy
ret <256 x i1> %z
}
; <256 x i64>
; Function Attrs: nounwind
define fastcc <256 x i1> @icmp_sgt_vv_v256i64(<256 x i64> %x, <256 x i64> %y) {
; CHECK-LABEL: icmp_sgt_vv_v256i64:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 256
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vcmps.l %v0, %v0, %v1
; CHECK-NEXT: vfmk.l.gt %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%z = icmp sgt <256 x i64> %x, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @icmp_sgt_sv_v256i64(i64 %x, <256 x i64> %y) {
; CHECK-LABEL: icmp_sgt_sv_v256i64:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vcmps.l %v0, %v1, %v0
; CHECK-NEXT: vfmk.l.gt %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%xins = insertelement <256 x i64> undef, i64 %x, i32 0
%vx = shufflevector <256 x i64> %xins, <256 x i64> undef, <256 x i32> zeroinitializer
%z = icmp sgt <256 x i64> %vx, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @icmp_sgt_vs_v256i64(<256 x i64> %x, i64 %y) {
; CHECK-LABEL: icmp_sgt_vs_v256i64:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vcmps.l %v0, %v0, %v1
; CHECK-NEXT: vfmk.l.gt %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%yins = insertelement <256 x i64> undef, i64 %y, i32 0
%vy = shufflevector <256 x i64> %yins, <256 x i64> undef, <256 x i32> zeroinitializer
%z = icmp sgt <256 x i64> %x, %vy
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @icmp_sge_vv_v256i64(<256 x i64> %x, <256 x i64> %y) {
; CHECK-LABEL: icmp_sge_vv_v256i64:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 256
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vcmps.l %v0, %v0, %v1
; CHECK-NEXT: vfmk.l.ge %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%z = icmp sge <256 x i64> %x, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @icmp_sge_sv_v256i64(i64 %x, <256 x i64> %y) {
; CHECK-LABEL: icmp_sge_sv_v256i64:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vcmps.l %v0, %v1, %v0
; CHECK-NEXT: vfmk.l.ge %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%xins = insertelement <256 x i64> undef, i64 %x, i32 0
%vx = shufflevector <256 x i64> %xins, <256 x i64> undef, <256 x i32> zeroinitializer
%z = icmp sge <256 x i64> %vx, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @icmp_sge_vs_v256i64(<256 x i64> %x, i64 %y) {
; CHECK-LABEL: icmp_sge_vs_v256i64:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vcmps.l %v0, %v0, %v1
; CHECK-NEXT: vfmk.l.ge %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%yins = insertelement <256 x i64> undef, i64 %y, i32 0
%vy = shufflevector <256 x i64> %yins, <256 x i64> undef, <256 x i32> zeroinitializer
%z = icmp sge <256 x i64> %x, %vy
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @icmp_eq_vv_v256i64(<256 x i64> %x, <256 x i64> %y) {
; CHECK-LABEL: icmp_eq_vv_v256i64:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 256
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vcmpu.l %v0, %v0, %v1
; CHECK-NEXT: vfmk.l.eq %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%z = icmp eq <256 x i64> %x, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @icmp_eq_sv_v256i64(i64 %x, <256 x i64> %y) {
; CHECK-LABEL: icmp_eq_sv_v256i64:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vcmpu.l %v0, %v1, %v0
; CHECK-NEXT: vfmk.l.eq %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%xins = insertelement <256 x i64> undef, i64 %x, i32 0
%vx = shufflevector <256 x i64> %xins, <256 x i64> undef, <256 x i32> zeroinitializer
%z = icmp eq <256 x i64> %vx, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @icmp_eq_vs_v256i64(<256 x i64> %x, i64 %y) {
; CHECK-LABEL: icmp_eq_vs_v256i64:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vcmpu.l %v0, %v0, %v1
; CHECK-NEXT: vfmk.l.eq %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%yins = insertelement <256 x i64> undef, i64 %y, i32 0
%vy = shufflevector <256 x i64> %yins, <256 x i64> undef, <256 x i32> zeroinitializer
%z = icmp eq <256 x i64> %x, %vy
ret <256 x i1> %z
}
define fastcc <256 x i1> @icmp_ne_vv_v256i64(<256 x i64> %x, <256 x i64> %y) {
; CHECK-LABEL: icmp_ne_vv_v256i64:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 256
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vcmpu.l %v0, %v0, %v1
; CHECK-NEXT: vfmk.l.ne %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%z = icmp ne <256 x i64> %x, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @icmp_ne_sv_v256i64(i64 %x, <256 x i64> %y) {
; CHECK-LABEL: icmp_ne_sv_v256i64:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vcmpu.l %v0, %v1, %v0
; CHECK-NEXT: vfmk.l.ne %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%xins = insertelement <256 x i64> undef, i64 %x, i32 0
%vx = shufflevector <256 x i64> %xins, <256 x i64> undef, <256 x i32> zeroinitializer
%z = icmp ne <256 x i64> %vx, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @icmp_ne_vs_v256i64(<256 x i64> %x, i64 %y) {
; CHECK-LABEL: icmp_ne_vs_v256i64:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vcmpu.l %v0, %v0, %v1
; CHECK-NEXT: vfmk.l.ne %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%yins = insertelement <256 x i64> undef, i64 %y, i32 0
%vy = shufflevector <256 x i64> %yins, <256 x i64> undef, <256 x i32> zeroinitializer
%z = icmp ne <256 x i64> %x, %vy
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @icmp_sle_vv_v256i64(<256 x i64> %x, <256 x i64> %y) {
; CHECK-LABEL: icmp_sle_vv_v256i64:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 256
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vcmps.l %v0, %v0, %v1
; CHECK-NEXT: vfmk.l.le %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%z = icmp sle <256 x i64> %x, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @icmp_sle_sv_v256i64(i64 %x, <256 x i64> %y) {
; CHECK-LABEL: icmp_sle_sv_v256i64:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vcmps.l %v0, %v1, %v0
; CHECK-NEXT: vfmk.l.le %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%xins = insertelement <256 x i64> undef, i64 %x, i32 0
%vx = shufflevector <256 x i64> %xins, <256 x i64> undef, <256 x i32> zeroinitializer
%z = icmp sle <256 x i64> %vx, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @icmp_sle_vs_v256i64(<256 x i64> %x, i64 %y) {
; CHECK-LABEL: icmp_sle_vs_v256i64:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vcmps.l %v0, %v0, %v1
; CHECK-NEXT: vfmk.l.le %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%yins = insertelement <256 x i64> undef, i64 %y, i32 0
%vy = shufflevector <256 x i64> %yins, <256 x i64> undef, <256 x i32> zeroinitializer
%z = icmp sle <256 x i64> %x, %vy
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @icmp_slt_vv_v256i64(<256 x i64> %x, <256 x i64> %y) {
; CHECK-LABEL: icmp_slt_vv_v256i64:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 256
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vcmps.l %v0, %v0, %v1
; CHECK-NEXT: vfmk.l.lt %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%z = icmp slt <256 x i64> %x, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @icmp_slt_sv_v256i64(i64 %x, <256 x i64> %y) {
; CHECK-LABEL: icmp_slt_sv_v256i64:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vcmps.l %v0, %v1, %v0
; CHECK-NEXT: vfmk.l.lt %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%xins = insertelement <256 x i64> undef, i64 %x, i32 0
%vx = shufflevector <256 x i64> %xins, <256 x i64> undef, <256 x i32> zeroinitializer
%z = icmp slt <256 x i64> %vx, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @icmp_slt_vs_v256i64(<256 x i64> %x, i64 %y) {
; CHECK-LABEL: icmp_slt_vs_v256i64:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vcmps.l %v0, %v0, %v1
; CHECK-NEXT: vfmk.l.lt %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%yins = insertelement <256 x i64> undef, i64 %y, i32 0
%vy = shufflevector <256 x i64> %yins, <256 x i64> undef, <256 x i32> zeroinitializer
%z = icmp slt <256 x i64> %x, %vy
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @icmp_ugt_vv_v256i64(<256 x i64> %x, <256 x i64> %y) {
; CHECK-LABEL: icmp_ugt_vv_v256i64:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 256
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vcmpu.l %v0, %v0, %v1
; CHECK-NEXT: vfmk.l.gt %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%z = icmp ugt <256 x i64> %x, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @icmp_ugt_sv_v256i64(i64 %x, <256 x i64> %y) {
; CHECK-LABEL: icmp_ugt_sv_v256i64:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vcmpu.l %v0, %v1, %v0
; CHECK-NEXT: vfmk.l.gt %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%xins = insertelement <256 x i64> undef, i64 %x, i32 0
%vx = shufflevector <256 x i64> %xins, <256 x i64> undef, <256 x i32> zeroinitializer
%z = icmp ugt <256 x i64> %vx, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @icmp_ugt_vs_v256i64(<256 x i64> %x, i64 %y) {
; CHECK-LABEL: icmp_ugt_vs_v256i64:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vcmpu.l %v0, %v0, %v1
; CHECK-NEXT: vfmk.l.gt %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%yins = insertelement <256 x i64> undef, i64 %y, i32 0
%vy = shufflevector <256 x i64> %yins, <256 x i64> undef, <256 x i32> zeroinitializer
%z = icmp ugt <256 x i64> %x, %vy
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @icmp_uge_vv_v256i64(<256 x i64> %x, <256 x i64> %y) {
; CHECK-LABEL: icmp_uge_vv_v256i64:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 256
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vcmpu.l %v0, %v0, %v1
; CHECK-NEXT: vfmk.l.ge %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%z = icmp uge <256 x i64> %x, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @icmp_uge_sv_v256i64(i64 %x, <256 x i64> %y) {
; CHECK-LABEL: icmp_uge_sv_v256i64:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vcmpu.l %v0, %v1, %v0
; CHECK-NEXT: vfmk.l.ge %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%xins = insertelement <256 x i64> undef, i64 %x, i32 0
%vx = shufflevector <256 x i64> %xins, <256 x i64> undef, <256 x i32> zeroinitializer
%z = icmp uge <256 x i64> %vx, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @icmp_uge_vs_v256i64(<256 x i64> %x, i64 %y) {
; CHECK-LABEL: icmp_uge_vs_v256i64:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vcmpu.l %v0, %v0, %v1
; CHECK-NEXT: vfmk.l.ge %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%yins = insertelement <256 x i64> undef, i64 %y, i32 0
%vy = shufflevector <256 x i64> %yins, <256 x i64> undef, <256 x i32> zeroinitializer
%z = icmp uge <256 x i64> %x, %vy
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @icmp_ule_vv_v256i64(<256 x i64> %x, <256 x i64> %y) {
; CHECK-LABEL: icmp_ule_vv_v256i64:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 256
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vcmpu.l %v0, %v0, %v1
; CHECK-NEXT: vfmk.l.le %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%z = icmp ule <256 x i64> %x, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @icmp_ule_sv_v256i64(i64 %x, <256 x i64> %y) {
; CHECK-LABEL: icmp_ule_sv_v256i64:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vcmpu.l %v0, %v1, %v0
; CHECK-NEXT: vfmk.l.le %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%xins = insertelement <256 x i64> undef, i64 %x, i32 0
%vx = shufflevector <256 x i64> %xins, <256 x i64> undef, <256 x i32> zeroinitializer
%z = icmp ule <256 x i64> %vx, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @icmp_ule_vs_v256i64(<256 x i64> %x, i64 %y) {
; CHECK-LABEL: icmp_ule_vs_v256i64:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vcmpu.l %v0, %v0, %v1
; CHECK-NEXT: vfmk.l.le %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%yins = insertelement <256 x i64> undef, i64 %y, i32 0
%vy = shufflevector <256 x i64> %yins, <256 x i64> undef, <256 x i32> zeroinitializer
%z = icmp ule <256 x i64> %x, %vy
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @icmp_ult_vv_v256i64(<256 x i64> %x, <256 x i64> %y) {
; CHECK-LABEL: icmp_ult_vv_v256i64:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 256
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vcmpu.l %v0, %v0, %v1
; CHECK-NEXT: vfmk.l.lt %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%z = icmp ult <256 x i64> %x, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @icmp_ult_sv_v256i64(i64 %x, <256 x i64> %y) {
; CHECK-LABEL: icmp_ult_sv_v256i64:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vcmpu.l %v0, %v1, %v0
; CHECK-NEXT: vfmk.l.lt %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%xins = insertelement <256 x i64> undef, i64 %x, i32 0
%vx = shufflevector <256 x i64> %xins, <256 x i64> undef, <256 x i32> zeroinitializer
%z = icmp ult <256 x i64> %vx, %y
ret <256 x i1> %z
}
; Function Attrs: nounwind
define fastcc <256 x i1> @icmp_ult_vs_v256i64(<256 x i64> %x, i64 %y) {
; CHECK-LABEL: icmp_ult_vs_v256i64:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vbrd %v1, %s0
; CHECK-NEXT: vcmpu.l %v0, %v0, %v1
; CHECK-NEXT: vfmk.l.lt %vm1, %v0
; CHECK-NEXT: b.l.t (, %s10)
%yins = insertelement <256 x i64> undef, i64 %y, i32 0
%vy = shufflevector <256 x i64> %yins, <256 x i64> undef, <256 x i32> zeroinitializer
%z = icmp ult <256 x i64> %x, %vy
ret <256 x i1> %z
}