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Differential D117991

[AVR][NFC] Make atomics tests easier to read
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Authored by aykevl on Jan 23 2022, 9:02 AM.

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Reviewers
benshi001
Commits
rG44ee9864a456: [AVR][NFC] Make atomics tests easier to read
Summary

Use the same mnemonics in the tests that are used in the AtomicLoadOp pattern ($rd, $rr) but use RR1 instead of $operand. This matches similar tests in load8.ll.

Diff Detail

Event Timeline

aykevl created this revision.Jan 23 2022, 9:02 AM
Herald added subscribers: Jim, dylanmckay. · View Herald TranscriptJan 23 2022, 9:02 AM
aykevl requested review of this revision.Jan 23 2022, 9:02 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 23 2022, 9:02 AM
Herald added a subscriber: llvm-commits. · View Herald Transcript
Harbormaster completed remote builds in B145114: Diff 402344.Jan 23 2022, 9:02 AM
aykevl mentioned this in D117725: [AVR] Fix atomicrmw result value.Jan 23 2022, 9:05 AM
benshi001 accepted this revision.Jan 23 2022, 7:32 PM
This revision is now accepted and ready to land.Jan 23 2022, 7:32 PM
This revision was landed with ongoing or failed builds.Feb 2 2022, 12:10 AM
Closed by commit rG44ee9864a456: [AVR][NFC] Make atomics tests easier to read (authored by aykevl). · Explain Why
This revision was automatically updated to reflect the committed changes.
aykevl added a commit: rG44ee9864a456: [AVR][NFC] Make atomics tests easier to read.

Revision Contents

PathSize
llvm/
test/
CodeGen/
AVR/
atomics/
62 lines

Diff 405159

llvm/test/CodeGen/AVR/atomics/load16.ll

Show All 23 Linesdefine i16 @atomic_load_cmp_swap16(i16* %foo) {
%val = cmpxchg i16* %foo, i16 5, i16 10 acq_rel monotonic %val = cmpxchg i16* %foo, i16 5, i16 10 acq_rel monotonic
%value_loaded = extractvalue { i16, i1 } %val, 0 %value_loaded = extractvalue { i16, i1 } %val, 0
ret i16 %value_loaded ret i16 %value_loaded
} }
; CHECK-LABEL: atomic_load_add16 ; CHECK-LABEL: atomic_load_add16
; CHECK: in r0, 63 ; CHECK: in r0, 63
; CHECK-NEXT: cli ; CHECK-NEXT: cli
; CHECK-NEXT: ld [[RR1:r[0-9]+]], [[RD:(X|Y|Z)]] ; CHECK-NEXT: ld [[RDL:r[0-9]+]], [[RR:(X|Y|Z)]]
; CHECK-NEXT: ldd [[RR2:r[0-9]+]], [[RD]]+1 ; CHECK-NEXT: ldd [[RDH:r[0-9]+]], [[RR]]+1
; CHECK-NEXT: add [[TMP1:r[0-9]+]], [[RR1]] ; CHECK-NEXT: add [[RR1L:r[0-9]+]], [[RDL]]
; CHECK-NEXT: adc [[TMP2:r[0-9]+]], [[RR2]] ; CHECK-NEXT: adc [[RR1H:r[0-9]+]], [[RDH]]
; CHECK-NEXT: st [[RD]], [[TMP1]] ; CHECK-NEXT: st [[RR]], [[RR1L]]
; CHECK-NEXT: std [[RD]]+1, [[TMP2]] ; CHECK-NEXT: std [[RR]]+1, [[RR1H]]
; CHECK-NEXT: out 63, r0 ; CHECK-NEXT: out 63, r0
define i16 @atomic_load_add16(i16* %foo) { define i16 @atomic_load_add16(i16* %foo) {
%val = atomicrmw add i16* %foo, i16 13 seq_cst %val = atomicrmw add i16* %foo, i16 13 seq_cst
ret i16 %val ret i16 %val
} }
; CHECK-LABEL: atomic_load_sub16 ; CHECK-LABEL: atomic_load_sub16
; CHECK: in r0, 63 ; CHECK: in r0, 63
; CHECK-NEXT: cli ; CHECK-NEXT: cli
; CHECK-NEXT: ld [[RR1:r[0-9]+]], [[RD:(X|Y|Z)]] ; CHECK-NEXT: ld [[RDL:r[0-9]+]], [[RR:(X|Y|Z)]]
; CHECK-NEXT: ldd [[RR2:r[0-9]+]], [[RD]]+1 ; CHECK-NEXT: ldd [[RDH:r[0-9]+]], [[RR]]+1
; CHECK-NEXT: movw ; CHECK-NEXT: movw [[TMPL:r[0-9]+]], [[RDL]]
; CHECK-NEXT: sub [[TMP1:r[0-9]+]], [[IN1:r[0-9]+]] ; CHECK-NEXT: sub [[TMPL]], [[RR1L:r[0-9]+]]
; CHECK-NEXT: sbc [[TMP2:r[0-9]+]], [[IN2:r[0-9]+]] ; CHECK-NEXT: sbc [[TMPH:r[0-9]+]], [[RR1H:r[0-9]+]]
; CHECK-NEXT: st [[RD]], [[TMP1]] ; CHECK-NEXT: st [[RR]], [[TMPL]]
; CHECK-NEXT: std [[RD]]+1, [[TMP2]] ; CHECK-NEXT: std [[RR]]+1, [[TMPH]]
; CHECK-NEXT: out 63, r0 ; CHECK-NEXT: out 63, r0
define i16 @atomic_load_sub16(i16* %foo) { define i16 @atomic_load_sub16(i16* %foo) {
%val = atomicrmw sub i16* %foo, i16 13 seq_cst %val = atomicrmw sub i16* %foo, i16 13 seq_cst
ret i16 %val ret i16 %val
} }
; CHECK-LABEL: atomic_load_and16 ; CHECK-LABEL: atomic_load_and16
; CHECK: in r0, 63 ; CHECK: in r0, 63
; CHECK-NEXT: cli ; CHECK-NEXT: cli
; CHECK-NEXT: ld [[RR1:r[0-9]+]], [[RD:(X|Y|Z)]] ; CHECK-NEXT: ld [[RDL:r[0-9]+]], [[RR:(X|Y|Z)]]
; CHECK-NEXT: ldd [[RR2:r[0-9]+]], [[RD]]+1 ; CHECK-NEXT: ldd [[RDH:r[0-9]+]], [[RR]]+1
; CHECK-NEXT: and [[TMP1:r[0-9]+]], [[RR1]] ; CHECK-NEXT: and [[RD1L:r[0-9]+]], [[RDL]]
; CHECK-NEXT: and [[TMP2:r[0-9]+]], [[RR2]] ; CHECK-NEXT: and [[RD1H:r[0-9]+]], [[RDH]]
; CHECK-NEXT: st [[RD]], [[TMP1]] ; CHECK-NEXT: st [[RR]], [[RD1L]]
; CHECK-NEXT: std [[RD]]+1, [[TMP2]] ; CHECK-NEXT: std [[RR]]+1, [[RD1H]]
; CHECK-NEXT: out 63, r0 ; CHECK-NEXT: out 63, r0
define i16 @atomic_load_and16(i16* %foo) { define i16 @atomic_load_and16(i16* %foo) {
%val = atomicrmw and i16* %foo, i16 13 seq_cst %val = atomicrmw and i16* %foo, i16 13 seq_cst
ret i16 %val ret i16 %val
} }
; CHECK-LABEL: atomic_load_or16 ; CHECK-LABEL: atomic_load_or16
; CHECK: in r0, 63 ; CHECK: in r0, 63
; CHECK-NEXT: cli ; CHECK-NEXT: cli
; CHECK-NEXT: ld [[RR1:r[0-9]+]], [[RD:(X|Y|Z)]] ; CHECK-NEXT: ld [[RDL:r[0-9]+]], [[RR:(X|Y|Z)]]
; CHECK-NEXT: ldd [[RR2:r[0-9]+]], [[RD]]+1 ; CHECK-NEXT: ldd [[RDH:r[0-9]+]], [[RR]]+1
; CHECK-NEXT: or [[TMP1:r[0-9]+]], [[RR1]] ; CHECK-NEXT: or [[RD1L:r[0-9]+]], [[RDL]]
; CHECK-NEXT: or [[TMP2:r[0-9]+]], [[RR2]] ; CHECK-NEXT: or [[RD1H:r[0-9]+]], [[RDH]]
; CHECK-NEXT: st [[RD]], [[TMP1]] ; CHECK-NEXT: st [[RR]], [[RD1L]]
; CHECK-NEXT: std [[RD]]+1, [[TMP2]] ; CHECK-NEXT: std [[RR]]+1, [[RD1H]]
; CHECK-NEXT: out 63, r0 ; CHECK-NEXT: out 63, r0
define i16 @atomic_load_or16(i16* %foo) { define i16 @atomic_load_or16(i16* %foo) {
%val = atomicrmw or i16* %foo, i16 13 seq_cst %val = atomicrmw or i16* %foo, i16 13 seq_cst
ret i16 %val ret i16 %val
} }
; CHECK-LABEL: atomic_load_xor16 ; CHECK-LABEL: atomic_load_xor16
; CHECK: in r0, 63 ; CHECK: in r0, 63
; CHECK-NEXT: cli ; CHECK-NEXT: cli
; CHECK-NEXT: ld [[RR1:r[0-9]+]], [[RD:(X|Y|Z)]] ; CHECK-NEXT: ld [[RDL:r[0-9]+]], [[RR:(X|Y|Z)]]
; CHECK-NEXT: ldd [[RR2:r[0-9]+]], [[RD]]+1 ; CHECK-NEXT: ldd [[RDH:r[0-9]+]], [[RR]]+1
; CHECK-NEXT: eor [[TMP1:r[0-9]+]], [[RR1]] ; CHECK-NEXT: eor [[RD1L:r[0-9]+]], [[RDL]]
; CHECK-NEXT: eor [[TMP2:r[0-9]+]], [[RR2]] ; CHECK-NEXT: eor [[RD1H:r[0-9]+]], [[RDH]]
; CHECK-NEXT: st [[RD]], [[TMP1]] ; CHECK-NEXT: st [[RR]], [[RD1L]]
; CHECK-NEXT: std [[RD]]+1, [[TMP2]] ; CHECK-NEXT: std [[RR]]+1, [[RD1H]]
; CHECK-NEXT: out 63, r0 ; CHECK-NEXT: out 63, r0
define i16 @atomic_load_xor16(i16* %foo) { define i16 @atomic_load_xor16(i16* %foo) {
%val = atomicrmw xor i16* %foo, i16 13 seq_cst %val = atomicrmw xor i16* %foo, i16 13 seq_cst
ret i16 %val ret i16 %val
} }
; CHECK-LABEL: atomic_load_nand16 ; CHECK-LABEL: atomic_load_nand16
; CHECK: call __sync_fetch_and_nand_2 ; CHECK: call __sync_fetch_and_nand_2
Show All 32 Lines