This is an archive of the discontinued LLVM Phabricator instance.

In D116212#3207838, @kaz7 wrote:

LGTM.

In addition, I've also read following manuals often.

ABI: https://www.hpc.nec/documents/guide/pdfs/VE-ABI_v2.1.pdf
TLS: https://www.hpc.nec/documents/guide/pdfs/VE-tls_v1.2.pdf

Yep. They are linked from the documents website in the NEC SDK table. I explicitly mention the ISA guide because the link doesn't have a version number in it so should be stable under updates and the ISA documentation was the most important resource for me so far.

This revision was landed with ongoing or failed builds.Dec 23 2021, 5:15 AM

Closed by commit rG3d36da77020b: [VE] Add manuals to CompilerWriterInfo (authored by simoll). · Explain Why

This revision was automatically updated to reflect the committed changes.

simoll added a commit: rG3d36da77020b: [VE] Add manuals to CompilerWriterInfo.

Revision Contents

Path

Size

llvm/

docs/

CompilerWriterInfo.rst

6 lines

Diff 396013

llvm/docs/CompilerWriterInfo.rst

	Show First 20 Lines • Show All 113 Lines • ▼ Show 20 Lines
	* `SPARC V9 ABI <http://sparc.org/standards/64.psabi.1.35.ps.Z>`_			* `SPARC V9 ABI <http://sparc.org/standards/64.psabi.1.35.ps.Z>`_
	* `SPARC V8 ABI <http://sparc.org/standards/psABI3rd.pdf>`_			* `SPARC V8 ABI <http://sparc.org/standards/psABI3rd.pdf>`_

	SystemZ			SystemZ
	-------			-------

	* `z/Architecture Principles of Operation (registration required, free sign-up) <http://www-01.ibm.com/support/docview.wss?uid=isg2b9de5f05a9d57819852571c500428f9a>`_			* `z/Architecture Principles of Operation (registration required, free sign-up) <http://www-01.ibm.com/support/docview.wss?uid=isg2b9de5f05a9d57819852571c500428f9a>`_

				VE
				--

				* `NEC SX-Aurora TSUBASA ISA Guide <https://www.hpc.nec/documents/guide/pdfs/Aurora_ISA_guide.pdf>`_
				* `NEC SX-Aurora TSUBASA manuals and documentation <https://www.hpc.nec/documentation>`_

	X86			X86
	---			---

	* `AMD processor manuals <http://developer.amd.com/resources/developer-guides-manuals/>`_			* `AMD processor manuals <http://developer.amd.com/resources/developer-guides-manuals/>`_
	* `Intel 64 and IA-32 manuals <http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html>`_			* `Intel 64 and IA-32 manuals <http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html>`_
	* `Intel Itanium documentation <http://www.intel.com/design/itanium/documentation.htm?iid=ipp_srvr_proc_itanium2+techdocs>`_			* `Intel Itanium documentation <http://www.intel.com/design/itanium/documentation.htm?iid=ipp_srvr_proc_itanium2+techdocs>`_
	* `X86 and X86-64 SysV psABI <https://github.com/hjl-tools/x86-psABI/wiki/X86-psABI>`_			* `X86 and X86-64 SysV psABI <https://github.com/hjl-tools/x86-psABI/wiki/X86-psABI>`_
	* `Calling conventions for different C++ compilers and operating systems <http://www.agner.org/optimize/calling_conventions.pdf>`_			* `Calling conventions for different C++ compilers and operating systems <http://www.agner.org/optimize/calling_conventions.pdf>`_
	▲ Show 20 Lines • Show All 68 Lines • Show Last 20 Lines

This is an archive of the discontinued LLVM Phabricator instance.

[VE] Add manuals to CompilerWriterInfoClosedPublic

Details

Diff Detail

Event Timeline

Revision Contents

Diff 396013

llvm/docs/CompilerWriterInfo.rst

[VE] Add manuals to CompilerWriterInfo
ClosedPublic