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Differential D115643

[VE] MUL,SUB,OR,XOR v256i32|64 isel
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Authored by simoll on Dec 13 2021, 9:29 AM.

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kaz7
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rG6847379e895b: [VE] MUL,SUB,OR,XOR v256i32|64 isel
Summary

v256i32|i64 isel patterns and tests.

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simoll created this revision.Dec 13 2021, 9:29 AM
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Harbormaster completed remote builds in B138993: Diff 393926.Dec 13 2021, 10:24 AM
kaz7 accepted this revision.Dec 14 2021, 1:40 AM

LGTM

This revision is now accepted and ready to land.Dec 14 2021, 1:40 AM
This revision was landed with ongoing or failed builds.Dec 14 2021, 4:25 AM
Closed by commit rG6847379e895b: [VE] MUL,SUB,OR,XOR v256i32|64 isel (authored by simoll). · Explain Why
This revision was automatically updated to reflect the committed changes.
simoll added a commit: rG6847379e895b: [VE] MUL,SUB,OR,XOR v256i32|64 isel.

Revision Contents

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llvm/
lib/
Target/
VE/
11 lines
12 lines
4 lines
test/
CodeGen/
VE/
Vector/
33 lines
34 lines
33 lines
33 lines

Diff 394207

llvm/lib/Target/VE/VVPInstrInfo.td

Show All 34 Linesclass vvp_commutative<SDNode RootOp> :
(ops node:$lhs, node:$rhs, node:$mask, node:$vlen), (ops node:$lhs, node:$rhs, node:$mask, node:$vlen),
[(RootOp node:$lhs, node:$rhs, node:$mask, node:$vlen), [(RootOp node:$lhs, node:$rhs, node:$mask, node:$vlen),
(RootOp node:$rhs, node:$lhs, node:$mask, node:$vlen)]>; (RootOp node:$rhs, node:$lhs, node:$mask, node:$vlen)]>;
// VVP node definitions. // VVP node definitions.
def vvp_add : SDNode<"VEISD::VVP_ADD", SDTIntBinOpVVP>; def vvp_add : SDNode<"VEISD::VVP_ADD", SDTIntBinOpVVP>;
def c_vvp_add : vvp_commutative<vvp_add>; def c_vvp_add : vvp_commutative<vvp_add>;
def vvp_sub : SDNode<"VEISD::VVP_SUB", SDTIntBinOpVVP>;
def vvp_mul : SDNode<"VEISD::VVP_MUL", SDTIntBinOpVVP>;
def c_vvp_mul : vvp_commutative<vvp_mul>;
def vvp_and : SDNode<"VEISD::VVP_AND", SDTIntBinOpVVP>; def vvp_and : SDNode<"VEISD::VVP_AND", SDTIntBinOpVVP>;
def c_vvp_and : vvp_commutative<vvp_and>; def c_vvp_and : vvp_commutative<vvp_and>;
def vvp_or : SDNode<"VEISD::VVP_OR", SDTIntBinOpVVP>;
def c_vvp_or : vvp_commutative<vvp_or>;
def vvp_xor : SDNode<"VEISD::VVP_XOR", SDTIntBinOpVVP>;
def c_vvp_xor : vvp_commutative<vvp_xor>;
// } Binary Operators // } Binary Operators

llvm/lib/Target/VE/VVPInstrPatternsVec.td

Show First 20 Lines • Show All 81 Lines • ▼ Show 20 Lines defm : Binary_rv_vv<OpNode,
ShortScalarVT, ShortDataVT, v256i1, ShortScalarVT, ShortDataVT, v256i1,
ShortOpBaseName>; ShortOpBaseName>;
} }
defm : Binary_rv_vv_ShortLong<c_vvp_add, defm : Binary_rv_vv_ShortLong<c_vvp_add,
i64, v256i64, "VADDSL", i64, v256i64, "VADDSL",
i32, v256i32, "VADDSWSX">; i32, v256i32, "VADDSWSX">;
defm : Binary_rv_vv_ShortLong<vvp_sub,
i64, v256i64, "VSUBSL",
i32, v256i32, "VSUBSWSX">;
defm : Binary_rv_vv_ShortLong<c_vvp_mul,
i64, v256i64, "VMULSL",
i32, v256i32, "VMULSWSX">;
defm : Binary_rv_vv_ShortLong<c_vvp_and, defm : Binary_rv_vv_ShortLong<c_vvp_and,
i64, v256i64, "VAND", i64, v256i64, "VAND",
i32, v256i32, "PVANDLO">; i32, v256i32, "PVANDLO">;
defm : Binary_rv_vv_ShortLong<c_vvp_or,
i64, v256i64, "VOR",
i32, v256i32, "PVORLO">;
defm : Binary_rv_vv_ShortLong<c_vvp_xor,
i64, v256i64, "VXOR",
i32, v256i32, "PVXORLO">;

llvm/lib/Target/VE/VVPNodes.def

Show All 27 Lines
/// \p VVPName is a VVP Binary operator. /// \p VVPName is a VVP Binary operator.
/// \p SDNAME is the generic SD opcode corresponding to \p VVPName. /// \p SDNAME is the generic SD opcode corresponding to \p VVPName.
#ifndef ADD_BINARY_VVP_OP #ifndef ADD_BINARY_VVP_OP
#define ADD_BINARY_VVP_OP(X,Y) ADD_VVP_OP(X,Y) HANDLE_VP_TO_VVP(VP_##Y, X) #define ADD_BINARY_VVP_OP(X,Y) ADD_VVP_OP(X,Y) HANDLE_VP_TO_VVP(VP_##Y, X)
#endif #endif
// Integer arithmetic. // Integer arithmetic.
ADD_BINARY_VVP_OP(VVP_ADD,ADD) ADD_BINARY_VVP_OP(VVP_ADD,ADD)
ADD_BINARY_VVP_OP(VVP_SUB,SUB)
ADD_BINARY_VVP_OP(VVP_MUL,MUL)
ADD_BINARY_VVP_OP(VVP_AND,AND) ADD_BINARY_VVP_OP(VVP_AND,AND)
ADD_BINARY_VVP_OP(VVP_OR,OR)
ADD_BINARY_VVP_OP(VVP_XOR,XOR)
#undef HANDLE_VP_TO_VVP #undef HANDLE_VP_TO_VVP
#undef ADD_BINARY_VVP_OP #undef ADD_BINARY_VVP_OP
#undef ADD_VVP_OP #undef ADD_VVP_OP

llvm/test/CodeGen/VE/Vector/vp_mul.ll

; REQUIRES: asserts ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: not --crash llc < %s -march=ve -mattr=+vpu -o /dev/null 2>&1 | FileCheck %s ; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
; CHECK: t{{[0-9]+}}: v256i32 = vp_mul [[A:t[0-9]+]], [[B:t[0-9]+]], [[MASK:t[0-9]+]], [[EVL:t[0-9]+]] declare <256 x i32> @llvm.vp.mul.v256i32(<256 x i32>, <256 x i32>, <256 x i1>, i32)
; CHECK: [[A]]: v256i32
; CHECK: [[B]]: v256i32
; CHECK: [[MASK]]: v256i1
; CHECK: [[EVL]]: i32
define <256 x i32> @test_vp_int(<256 x i32> %i0, <256 x i32> %i1, <256 x i1> %m, i32 %n) { define fastcc <256 x i32> @test_vp_v256i32(<256 x i32> %i0, <256 x i32> %i1, <256 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_v256i32:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vmuls.w.sx %v0, %v0, %v1, %vm1
; CHECK-NEXT: b.l.t (, %s10)
%r0 = call <256 x i32> @llvm.vp.mul.v256i32(<256 x i32> %i0, <256 x i32> %i1, <256 x i1> %m, i32 %n) %r0 = call <256 x i32> @llvm.vp.mul.v256i32(<256 x i32> %i0, <256 x i32> %i1, <256 x i1> %m, i32 %n)
ret <256 x i32> %r0 ret <256 x i32> %r0
} }
; integer arith
declare <256 x i32> @llvm.vp.mul.v256i32(<256 x i32>, <256 x i32>, <256 x i1>, i32) declare <256 x i64> @llvm.vp.mul.v256i64(<256 x i64>, <256 x i64>, <256 x i1>, i32)
define fastcc <256 x i64> @test_vp_v256i64(<256 x i64> %i0, <256 x i64> %i1, <256 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_v256i64:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vmuls.l %v0, %v0, %v1, %vm1
; CHECK-NEXT: b.l.t (, %s10)
%r0 = call <256 x i64> @llvm.vp.mul.v256i64(<256 x i64> %i0, <256 x i64> %i1, <256 x i1> %m, i32 %n)
ret <256 x i64> %r0
}

llvm/test/CodeGen/VE/Vector/vp_or.ll

; REQUIRES: asserts ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: not --crash llc < %s -march=ve -mattr=+vpu -o /dev/null 2>&1 | FileCheck %s ; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
; CHECK: t{{[0-9]+}}: v256i32 = vp_or [[A:t[0-9]+]], [[B:t[0-9]+]], [[MASK:t[0-9]+]], [[EVL:t[0-9]+]] declare <256 x i32> @llvm.vp.or.v256i32(<256 x i32>, <256 x i32>, <256 x i1>, i32)
; CHECK: [[A]]: v256i32
; CHECK: [[B]]: v256i32
; CHECK: [[MASK]]: v256i1
; CHECK: [[EVL]]: i32
define <256 x i32> @test_vp_int(<256 x i32> %i0, <256 x i32> %i1, <256 x i1> %m, i32 %n) { define fastcc <256 x i32> @test_vp_v256i32(<256 x i32> %i0, <256 x i32> %i1, <256 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_v256i32:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: pvor.lo %v0, %v0, %v1, %vm1
; CHECK-NEXT: b.l.t (, %s10)
%r0 = call <256 x i32> @llvm.vp.or.v256i32(<256 x i32> %i0, <256 x i32> %i1, <256 x i1> %m, i32 %n) %r0 = call <256 x i32> @llvm.vp.or.v256i32(<256 x i32> %i0, <256 x i32> %i1, <256 x i1> %m, i32 %n)
ret <256 x i32> %r0 ret <256 x i32> %r0
} }
; integer arith
declare <256 x i32> @llvm.vp.or.v256i32(<256 x i32>, <256 x i32>, <256 x i1>, i32) declare <256 x i64> @llvm.vp.or.v256i64(<256 x i64>, <256 x i64>, <256 x i1>, i32)
define fastcc <256 x i64> @test_vp_v256i64(<256 x i64> %i0, <256 x i64> %i1, <256 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_v256i64:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vor %v0, %v0, %v1, %vm1
; CHECK-NEXT: b.l.t (, %s10)
%r0 = call <256 x i64> @llvm.vp.or.v256i64(<256 x i64> %i0, <256 x i64> %i1, <256 x i1> %m, i32 %n)
ret <256 x i64> %r0
}

llvm/test/CodeGen/VE/Vector/vp_sub.ll

; REQUIRES: asserts ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: not --crash llc < %s -march=ve -mattr=+vpu -o /dev/null 2>&1 | FileCheck %s ; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
; CHECK: t{{[0-9]+}}: v256i32 = vp_sub [[A:t[0-9]+]], [[B:t[0-9]+]], [[MASK:t[0-9]+]], [[EVL:t[0-9]+]] declare <256 x i32> @llvm.vp.sub.v256i32(<256 x i32>, <256 x i32>, <256 x i1>, i32)
; CHECK: [[A]]: v256i32
; CHECK: [[B]]: v256i32
; CHECK: [[MASK]]: v256i1
; CHECK: [[EVL]]: i32
define <256 x i32> @test_vp_int(<256 x i32> %i0, <256 x i32> %i1, <256 x i1> %m, i32 %n) { define fastcc <256 x i32> @test_vp_v256i32(<256 x i32> %i0, <256 x i32> %i1, <256 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_v256i32:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vsubs.w.sx %v0, %v0, %v1, %vm1
; CHECK-NEXT: b.l.t (, %s10)
%r0 = call <256 x i32> @llvm.vp.sub.v256i32(<256 x i32> %i0, <256 x i32> %i1, <256 x i1> %m, i32 %n) %r0 = call <256 x i32> @llvm.vp.sub.v256i32(<256 x i32> %i0, <256 x i32> %i1, <256 x i1> %m, i32 %n)
ret <256 x i32> %r0 ret <256 x i32> %r0
} }
; integer arith
declare <256 x i32> @llvm.vp.sub.v256i32(<256 x i32>, <256 x i32>, <256 x i1>, i32) declare <256 x i64> @llvm.vp.sub.v256i64(<256 x i64>, <256 x i64>, <256 x i1>, i32)
define fastcc <256 x i64> @test_vp_v256i64(<256 x i64> %i0, <256 x i64> %i1, <256 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_v256i64:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vsubs.l %v0, %v0, %v1, %vm1
; CHECK-NEXT: b.l.t (, %s10)
%r0 = call <256 x i64> @llvm.vp.sub.v256i64(<256 x i64> %i0, <256 x i64> %i1, <256 x i1> %m, i32 %n)
ret <256 x i64> %r0
}

llvm/test/CodeGen/VE/Vector/vp_xor.ll

; REQUIRES: asserts ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: not --crash llc < %s -march=ve -mattr=+vpu -o /dev/null 2>&1 | FileCheck %s ; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
; CHECK: t{{[0-9]+}}: v256i32 = vp_xor [[A:t[0-9]+]], [[B:t[0-9]+]], [[MASK:t[0-9]+]], [[EVL:t[0-9]+]] declare <256 x i32> @llvm.vp.xor.v256i32(<256 x i32>, <256 x i32>, <256 x i1>, i32)
; CHECK: [[A]]: v256i32
; CHECK: [[B]]: v256i32
; CHECK: [[MASK]]: v256i1
; CHECK: [[EVL]]: i32
define <256 x i32> @test_vp_int(<256 x i32> %i0, <256 x i32> %i1, <256 x i1> %m, i32 %n) { define fastcc <256 x i32> @test_vp_v256i32(<256 x i32> %i0, <256 x i32> %i1, <256 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_v256i32:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: pvxor.lo %v0, %v0, %v1, %vm1
; CHECK-NEXT: b.l.t (, %s10)
%r0 = call <256 x i32> @llvm.vp.xor.v256i32(<256 x i32> %i0, <256 x i32> %i1, <256 x i1> %m, i32 %n) %r0 = call <256 x i32> @llvm.vp.xor.v256i32(<256 x i32> %i0, <256 x i32> %i1, <256 x i1> %m, i32 %n)
ret <256 x i32> %r0 ret <256 x i32> %r0
} }
; integer arith
declare <256 x i32> @llvm.vp.xor.v256i32(<256 x i32>, <256 x i32>, <256 x i1>, i32) declare <256 x i64> @llvm.vp.xor.v256i64(<256 x i64>, <256 x i64>, <256 x i1>, i32)
define fastcc <256 x i64> @test_vp_v256i64(<256 x i64> %i0, <256 x i64> %i1, <256 x i1> %m, i32 %n) {
; CHECK-LABEL: test_vp_v256i64:
; CHECK: # %bb.0:
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vxor %v0, %v0, %v1, %vm1
; CHECK-NEXT: b.l.t (, %s10)
%r0 = call <256 x i64> @llvm.vp.xor.v256i64(<256 x i64> %i0, <256 x i64> %i1, <256 x i1> %m, i32 %n)
ret <256 x i64> %r0
}