WebAssembly: basic bitcode → assembly CodeGen test

[jfb]

Summary

Add a basic CodeGen bitcode test which (for now) only prints out the function name and nothing else. The current code merely implements the basic needed for the test run to not crash / assert. Getting to that point required:

• Basic InstPrinter.
• Basic AsmPrinter.
• DiagnosticInfoUnsupported (not strictly required, but nice to have, duplicated from AMDGPU/BPF's ISelLowering).
• Some SP and register setup in WebAssemblyTargetLowering.
• Basic LowerFormalArguments.
• GenInstrInfo.
• Placeholder LowerFormalArguments.
• Placeholder CanLowerReturn and LowerReturn.
• Basic DAGToDAGISel::Select, which requiresGenDAGISel.inc as well as GET_INSTRINFO_ENUM with GenInstrInfo.inc.
• Remove WebAssemblyFrameLowering::determineCalleeSaves and rely on default.
• Implement WebAssemblyFrameLowering::hasFP, same as AArch64's implementation.

Follow-up patches will implement a real AsmPrinter, which will require adding MI opcodes specific to WebAssembly.

[sunfish]

lgtm, with comments

lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp

69

"end anonymous namespace" seems more popular in LLVM.

79

This line should probably be in a DEBUG macro.

lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp

39

LLVM style now recommends against starting the comment with the function name now.

45

Don't over-parenthesize return values.

lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

21

It doesn't seem common in LLVM to separate #includes with blank lines. Is there a reason for doing this?

103

This should check the target and set *either* SP32 or SP64 as the stack pointer.

132

It's actually likely that CallingConvention.td isn't appropriate. We don't have physical registers or stack arguments to deal with, which are the main things that file handles.

143

We can assert this, since CanLowerReturn only returns true if there's at most one output value, right?

157

It'd be nice to have a corresponding check in LowerReturn too.

159

"yet". Even if we're planning to lower them in a different way, we should let people know that varargs are still planned to be supported :-).

161

"yet" here too, because I don't ultimately see any reason we shouldn't support this.

[sunfish]

lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp

36

Should this be "wasm-asm-printer"? And should the one in InstPrinter/WebAssemblyInstPrinter.cpp be that too?

[jfb]

• Address sunfish's comments.

[jfb]

I did a bit of grep-fu and found the following:

git grep "^#define DEBUG_TYPE" | cut -f3 -d' '| sort | uniq -c | sort -h | grep -v " 1 "
      2 "aarch64-disassembler"
      2 "arm-isel"
      2 "bugpoint"
      2 "codegen"
      2 "coverage-mapping"
      2 "delay-slot-filler"
      2 "flattencfg"
      2 "hexagon-shuffle"
      2 "indvars"
      2 "instsimplify"
      2 "jit"
      2 "mem2reg"
      2 "mips-lower"
      2 "mips-reg-info"
      2 "packets"
      2 "scheduler"
      2 "simplifycfg"
      2 "ssaupdater"
      2 "stackmaps"
      2 "subtarget-emitter"
      2 "x86-isel"
      3 "inline"
      3 "ir"
      3 "isel"
      3 "lli"
      3 "loop-unroll"
      3 "post-RA-sched"
      3 "region"
      4 "block-freq"
      4 "dwarfdebug"
      4 "misched"
      5 "legalize-types"
      5 "mips-isel"
      6 "pre-RA-sched"
      9 "mccodeemitter"
     11 "dyld"
     15 "instcombine"
     17 "regalloc"
     25 "asm-printer"

Is this worth fixing?

lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp

36

That doesn't seem to be what other targets do:

git grep DEBUG_TYPE ./lib/Target/*/*AsmPrinter.cpp
lib/Target/AArch64/AArch64AsmPrinter.cpp:#define DEBUG_TYPE "asm-printer"
lib/Target/ARM/ARMAsmPrinter.cpp:#define DEBUG_TYPE "asm-printer"
lib/Target/BPF/BPFAsmPrinter.cpp:#define DEBUG_TYPE "asm-printer"
lib/Target/Hexagon/HexagonAsmPrinter.cpp:#define DEBUG_TYPE "asm-printer"
lib/Target/MSP430/MSP430AsmPrinter.cpp:#define DEBUG_TYPE "asm-printer"
lib/Target/Mips/MipsAsmPrinter.cpp:#define DEBUG_TYPE "mips-asm-printer"
lib/Target/PowerPC/PPCAsmPrinter.cpp:#define DEBUG_TYPE "asmprinter"
lib/Target/Sparc/SparcAsmPrinter.cpp:#define DEBUG_TYPE "asm-printer"
lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp:#define DEBUG_TYPE "asm-printer"
lib/Target/XCore/XCoreAsmPrinter.cpp:#define DEBUG_TYPE "asm-printer"

Should they? I can change all of them if so, probably in a different change.

[jfb]

It actually seems to be on purpose:
http://llvm.org/docs/ProgrammersManual.html#fine-grained-debug-info-with-debug-type-and-the-debug-only-option
So different targets enable their diagnostic with the same debug flag.

[sunfish]

That's a good reason to leave it then. Thanks,

Dan

lib/Target/WebAssembly/CMakeLists.txt

 set(LLVM_TARGET_DEFINITIONS WebAssembly.td)
 
+tablegen(LLVM WebAssemblyGenAsmWriter.inc -gen-asm-writer)
+tablegen(LLVM WebAssemblyGenDAGISel.inc -gen-dag-isel)
+tablegen(LLVM WebAssemblyGenInstrInfo.inc -gen-instr-info)
 tablegen(LLVM WebAssemblyGenMCCodeEmitter.inc -gen-emitter)
 tablegen(LLVM WebAssemblyGenRegisterInfo.inc -gen-register-info)
 tablegen(LLVM WebAssemblyGenSubtargetInfo.inc -gen-subtarget)
 add_public_tablegen_target(WebAssemblyCommonTableGen)
 
 add_llvm_target(WebAssemblyCodeGen
+  WebAssemblyAsmPrinter.cpp
   WebAssemblyFrameLowering.cpp
-  WebAssemblyInstrInfo.cpp
   WebAssemblyISelDAGToDAG.cpp
   WebAssemblyISelLowering.cpp
+  WebAssemblyInstrInfo.cpp
   WebAssemblyMachineFunctionInfo.cpp
   WebAssemblyRegisterInfo.cpp
   WebAssemblySelectionDAGInfo.cpp
   WebAssemblySubtarget.cpp
   WebAssemblyTargetMachine.cpp
   WebAssemblyTargetTransformInfo.cpp
 )
 
 add_dependencies(LLVMWebAssemblyCodeGen intrinsics_gen)
 
 add_subdirectory(InstPrinter)
 add_subdirectory(TargetInfo)
 add_subdirectory(MCTargetDesc)

lib/Target/WebAssembly/InstPrinter/WebAssemblyInstPrinter.h

 class WebAssemblyInstPrinter : public MCInstPrinter {
 public:
   WebAssemblyInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
                          const MCRegisterInfo &MRI);
 
   void printRegName(raw_ostream &OS, unsigned RegNo) const override;
   void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot,
                  const MCSubtargetInfo &STI) override;
+
+  // Autogenerated by tblgen.
+  void printInstruction(const MCInst *MI, raw_ostream &O);
+  static const char *getRegisterName(unsigned RegNo);
 };
 
 } // end namespace llvm
 
 #endif

lib/Target/WebAssembly/InstPrinter/WebAssemblyInstPrinter.cpp

 #include "llvm/MC/MCSymbol.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/FormattedStream.h"
 #include <cctype>
 using namespace llvm;
 
 #define DEBUG_TYPE "asm-printer"
 
+#include "WebAssemblyGenAsmWriter.inc"
+
 WebAssemblyInstPrinter::WebAssemblyInstPrinter(const MCAsmInfo &MAI,
                                                const MCInstrInfo &MII,
                                                const MCRegisterInfo &MRI)
     : MCInstPrinter(MAI, MII, MRI) {}
 
 void WebAssemblyInstPrinter::printRegName(raw_ostream &OS,
                                           unsigned RegNo) const {
-  llvm_unreachable("TODO: implement printRegName");
+  OS << getRegisterName(RegNo);
 }
 
 void WebAssemblyInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
                                        StringRef Annot,
                                        const MCSubtargetInfo &STI) {
-  llvm_unreachable("TODO: implement printInst");
+  printInstruction(MI, OS);
+  printAnnotation(OS, Annot);
 }

lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h

 } // end namespace llvm
 
 // Defines symbolic names for WebAssembly registers. This defines a mapping from
 // register name to register number.
 //
 #define GET_REGINFO_ENUM
 #include "WebAssemblyGenRegisterInfo.inc"
 
+// Defines symbolic names for the WebAssembly instructions.
+//
+#define GET_INSTRINFO_ENUM
+#include "WebAssemblyGenInstrInfo.inc"
+
 #define GET_SUBTARGETINFO_ENUM
 #include "WebAssemblyGenSubtargetInfo.inc"
 
 #endif

lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.cpp

 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/TargetRegistry.h"
 using namespace llvm;
 
 #define DEBUG_TYPE "wasm-mc-target-desc"
 
+#define GET_INSTRINFO_MC_DESC
+#include "WebAssemblyGenInstrInfo.inc"
+
 #define GET_SUBTARGETINFO_MC_DESC
 #include "WebAssemblyGenSubtargetInfo.inc"
 
 #define GET_REGINFO_MC_DESC
 #include "WebAssemblyGenRegisterInfo.inc"
 
 static MCAsmInfo *createWebAssemblyMCAsmInfo(const MCRegisterInfo &MRI,
                                              const Triple &TT) {

lib/Target/WebAssembly/Makefile

 ##===- lib/Target/WebAssembly/Makefile ---------------------*- Makefile -*-===##
 #
 #                     The LLVM Compiler Infrastructure
 #
 # This file is distributed under the University of Illinois Open Source
 # License. See LICENSE.TXT for details.
 #
 ##===----------------------------------------------------------------------===##
 
 LEVEL = ../../..
 LIBRARYNAME = LLVMWebAssemblyCodeGen
 TARGET = WebAssembly
 
 # Make sure that tblgen is run, first thing.
-BUILT_SOURCES = WebAssemblyGenRegisterInfo.inc WebAssemblyGenSubtargetInfo.inc \
-    WebAssemblyGenMCCodeEmitter.inc
+BUILT_SOURCES = \
+  WebAssemblyGenAsmWriter.inc \
+  WebAssemblyGenDAGISel.inc \
+  WebAssemblyGenInstrInfo.inc \
+  WebAssemblyGenMCCodeEmitter.inc \
+  WebAssemblyGenRegisterInfo.inc \
+  WebAssemblyGenSubtargetInfo.inc
 
 DIRS = InstPrinter TargetInfo MCTargetDesc
 
 include $(LEVEL)/Makefile.common

lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp

+//===-- WebAssemblyAsmPrinter.cpp - WebAssembly LLVM assembly writer ------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+///
+/// \file
+/// \brief This file contains a printer that converts from our internal
+/// representation of machine-dependent LLVM code to the WebAssembly assembly
+/// language.
+///
+//===----------------------------------------------------------------------===//
+
+#include "WebAssembly.h"
+#include "WebAssemblyMachineFunctionInfo.h"
+#include "WebAssemblyRegisterInfo.h"
+#include "WebAssemblySubtarget.h"
+#include "InstPrinter/WebAssemblyInstPrinter.h"
+#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
+
+#include "llvm/ADT/SmallString.h"
+#include "llvm/CodeGen/AsmPrinter.h"
+#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/IR/DataLayout.h"
+#include "llvm/IR/DebugInfo.h"
+#include "llvm/MC/MCStreamer.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/TargetRegistry.h"
+#include "llvm/Support/raw_ostream.h"
+
+using namespace llvm;
+
+#define DEBUG_TYPE "asm-printer"
+
+namespace {
+
+class WebAssemblyAsmPrinter final : public AsmPrinter {
+public:
+  WebAssemblyAsmPrinter(TargetMachine &TM, std::unique_ptr<MCStreamer> Streamer)
+      : AsmPrinter(TM, std::move(Streamer)) {}
+
+private:
+  const char *getPassName() const override {
+    return "WebAssembly Assembly Printer";
+  }
+
+  //===------------------------------------------------------------------===//
+  // MachineFunctionPass Implementation.
+  //===------------------------------------------------------------------===//
+
+  void getAnalysisUsage(AnalysisUsage &AU) const override {
+    AsmPrinter::getAnalysisUsage(AU);
+  }
+
+  bool runOnMachineFunction(MachineFunction &F) override {
+    return AsmPrinter::runOnMachineFunction(F);
+  }
+
+  //===------------------------------------------------------------------===//
+  // AsmPrinter Implementation.
+  //===------------------------------------------------------------------===//
+
+  void EmitInstruction(const MachineInstr *MI) override;
+};
+
+} // end of anonymous namespace
+
+//===----------------------------------------------------------------------===//
+
+void WebAssemblyAsmPrinter::EmitInstruction(const MachineInstr *MI) {
+  SmallString<128> Str;
+  raw_svector_ostream OS(Str);
+
+  switch (MI->getOpcode()) {
+  default:
+    MI->print(dbgs());
+    llvm_unreachable("Unhandled instruction");
+    break;
+  }
+
+  OutStreamer->EmitRawText(OS.str());
+}
+
+// Force static initialization.
+extern "C" void LLVMInitializeWebAssemblyAsmPrinter() {
+  RegisterAsmPrinter<WebAssemblyAsmPrinter> X(TheWebAssemblyTarget32);
+  RegisterAsmPrinter<WebAssemblyAsmPrinter> Y(TheWebAssemblyTarget64);
+}

lib/Target/WebAssembly/WebAssemblyFrameLowering.h

eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
                                 MachineBasicBlock::iterator I) const override;
 
   /// These methods insert prolog and epilog code into the function.
   void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
   void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
 
   bool hasFP(const MachineFunction &MF) const override;
   bool hasReservedCallFrame(const MachineFunction &MF) const override;
-
-  void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
-                            RegScavenger *RS = nullptr) const override;
 };
 
 } // end namespace llvm
 
 #endif

lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp

 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/Support/Debug.h"
 using namespace llvm;
 
 #define DEBUG_TYPE "wasm-frame-info"
 
 // TODO: Implement a red zone?
 
-/// Return true if the specified function should have a dedicated frame pointer
-/// register.
+/// hasFP - Return true if the specified function should have a dedicated frame
+/// pointer register.
 bool WebAssemblyFrameLowering::hasFP(const MachineFunction &MF) const {
-  llvm_unreachable("TODO: implement hasFP");
+  const MachineFrameInfo *MFI = MF.getFrameInfo();
+  const auto *RegInfo = static_cast<const WebAssemblyRegisterInfo *>(
+      MF.getSubtarget().getRegisterInfo());
+  return (MFI->hasCalls() || MFI->hasVarSizedObjects() ||
+          MFI->isFrameAddressTaken() || MFI->hasStackMap() ||
+          MFI->hasPatchPoint() || RegInfo->needsStackRealignment(MF));
 }
 
 /// Under normal circumstances, when a frame pointer is not required, we reserve
 /// argument space for call sites in the function immediately on entry to the
 /// current function. This eliminates the need for add/sub sp brackets around
 /// call sites. Returns true if the call frame is included as part of the stack
 /// frame.
 bool WebAssemblyFrameLowering::hasReservedCallFrame(
     const MachineFunction &MF) const {
   return !MF.getFrameInfo()->hasVarSizedObjects();
 }
 
 void WebAssemblyFrameLowering::eliminateCallFramePseudoInstr(
     MachineFunction &MF, MachineBasicBlock &MBB,
     MachineBasicBlock::iterator I) const {
   llvm_unreachable("TODO: implement eliminateCallFramePseudoInstr");
 }
 
 void WebAssemblyFrameLowering::emitPrologue(MachineFunction &MF,
                                             MachineBasicBlock &MBB) const {
-  llvm_unreachable("TODO: implement emitPrologue");
+  // FIXME: Implement WebAssemblyFrameLowering::emitPrologue.
 }
 
 void WebAssemblyFrameLowering::emitEpilogue(MachineFunction &MF,
                                             MachineBasicBlock &MBB) const {
   llvm_unreachable("TODO: implement emitEpilogue");
 }
-
-void WebAssemblyFrameLowering::determineCalleeSaves(MachineFunction &MF,
-                                                    BitVector &SavedRegs,
-                                                    RegScavenger *RS) const {
-  llvm_unreachable("TODO: implement determineCalleeSaves");
-}

lib/Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp

ForCodeSize =
         MF.getFunction()->hasFnAttribute(Attribute::OptimizeForSize) ||
         MF.getFunction()->hasFnAttribute(Attribute::MinSize);
     Subtarget = &MF.getSubtarget<WebAssemblySubtarget>();
     return SelectionDAGISel::runOnMachineFunction(MF);
   }
 
   SDNode *Select(SDNode *Node) override;
 
+// Include the pieces autogenerated from the target description.
+#include "WebAssemblyGenDAGISel.inc"
+
 private:
   // add select functions here...
 };
 } // end anonymous namespace
 
 SDNode *WebAssemblyDAGToDAGISel::Select(SDNode *Node) {
-  llvm_unreachable("TODO: implement Select");
+  // Dump information about the Node being selected.
+  DEBUG(errs() << "Selecting: ");
+  DEBUG(Node->dump(CurDAG));
+  DEBUG(errs() << "\n");
+
+  // If we have a custom node, we already have selected!
+  if (Node->isMachineOpcode()) {
+    DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
+    Node->setNodeId(-1);
+    return nullptr;
+  }
+
+  // Few custom selection stuff.
+  SDNode *ResNode = nullptr;
+  EVT VT = Node->getValueType(0);
+
+  switch (Node->getOpcode()) {
+  default:
+    break;
+    // FIXME: Implement WebAssembly-specific selection.
+    (void)VT;
+  }
+
+  // Select the default instruction.
+  ResNode = SelectCode(Node);
+
+  DEBUG(errs() << "=> ");
+  if (ResNode == nullptr || ResNode == Node)
+    DEBUG(Node->dump(CurDAG));
+  else
+    DEBUG(ResNode->dump(CurDAG));
+  DEBUG(errs() << "\n");
+
+  return ResNode;
 }
 
 /// This pass converts a legalized DAG into a WebAssembly-specific DAG, ready
 /// for instruction scheduling.
 FunctionPass *llvm::createWebAssemblyISelDag(WebAssemblyTargetMachine &TM,
                                              CodeGenOpt::Level OptLevel) {
   return new WebAssemblyDAGToDAGISel(TM, OptLevel);
 }

lib/Target/WebAssembly/WebAssemblyISelLowering.h

 public:
   WebAssemblyTargetLowering(const TargetMachine &TM,
                             const WebAssemblySubtarget &STI);
 
 private:
   /// Keep a pointer to the WebAssemblySubtarget around so that we can make the
   /// right decision when generating code for different targets.
   const WebAssemblySubtarget *Subtarget;
+
+  bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
+                      bool isVarArg,
+                      const SmallVectorImpl<ISD::OutputArg> &Outs,
+                      LLVMContext &Context) const override;
+
+  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
+                      const SmallVectorImpl<ISD::OutputArg> &Outs,
+                      const SmallVectorImpl<SDValue> &OutVals, SDLoc dl,
+                      SelectionDAG &DAG) const override;
+
+  SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
+                               bool IsVarArg,
+                               const SmallVectorImpl<ISD::InputArg> &Ins,
+                               SDLoc DL, SelectionDAG &DAG,
+                               SmallVectorImpl<SDValue> &InVals) const override;
 };
 
 } // end namespace llvm
 
 #endif

lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

 //===----------------------------------------------------------------------===//
 
 #include "WebAssemblyISelLowering.h"
 #include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
 #include "WebAssemblyMachineFunctionInfo.h"
 #include "WebAssemblySubtarget.h"
 #include "WebAssemblyTargetMachine.h"
 #include "WebAssemblyTargetObjectFile.h"
+
 #include "llvm/CodeGen/Analysis.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/SelectionDAG.h"
+#include "llvm/IR/DiagnosticInfo.h"
+#include "llvm/IR/DiagnosticPrinter.h"
 #include "llvm/IR/Function.h"
 #include "llvm/IR/Intrinsics.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/Target/TargetOptions.h"
+
 using namespace llvm;
 
 #define DEBUG_TYPE "wasm-lower"
 
+namespace {
+// Diagnostic information for unimplemented or unsupported feature reporting.
+// FIXME copied from BPF and AMDGPU.
+class DiagnosticInfoUnsupported : public DiagnosticInfo {
+private:
+  // Debug location where this diagnostic is triggered.
+  DebugLoc DLoc;
+  const Twine &Description;
+  const Function &Fn;
+  SDValue Value;
+
+  static int KindID;
+
+  static int getKindID() {
+    if (KindID == 0)
+      KindID = llvm::getNextAvailablePluginDiagnosticKind();
+    return KindID;
+  }
+
+public:
+  DiagnosticInfoUnsupported(SDLoc DLoc, const Function &Fn, const Twine &Desc,
+                            SDValue Value)
+      : DiagnosticInfo(getKindID(), DS_Error), DLoc(DLoc.getDebugLoc()),
+        Description(Desc), Fn(Fn), Value(Value) {}
+
+  void print(DiagnosticPrinter &DP) const override {
+    std::string Str;
+    raw_string_ostream OS(Str);
+
+    if (DLoc) {
+      auto DIL = DLoc.get();
+      StringRef Filename = DIL->getFilename();
+      unsigned Line = DIL->getLine();
+      unsigned Column = DIL->getColumn();
+      OS << Filename << ':' << Line << ':' << Column << ' ';
+    }
+
+    OS << "in function " << Fn.getName() << ' ' << *Fn.getFunctionType() << '\n'
+       << Description;
+    if (Value)
+      Value->print(OS);
+    OS << '\n';
+    OS.flush();
+    DP << Str;
+  }
+
+  static bool classof(const DiagnosticInfo *DI) {
+    return DI->getKind() == getKindID();
+  }
+};
+
+int DiagnosticInfoUnsupported::KindID = 0;
+} // end anonymous namespace
+
 WebAssemblyTargetLowering::WebAssemblyTargetLowering(
     const TargetMachine &TM, const WebAssemblySubtarget &STI)
     : TargetLowering(TM), Subtarget(&STI) {
   // WebAssembly does not produce floating-point exceptions on normal floating
   // point operations.
   setHasFloatingPointExceptions(false);
   // We don't know the microarchitecture here, so just reduce register pressure.
   setSchedulingPreference(Sched::RegPressure);
+  // Tell ISel that we have a stack pointer.
+  setStackPointerRegisterToSaveRestore(WebAssembly::SP32);
+  setStackPointerRegisterToSaveRestore(WebAssembly::SP64);
+  // Set up the register classes.
+  addRegisterClass(MVT::i32, &WebAssembly::Int32RegClass);
+  addRegisterClass(MVT::i64, &WebAssembly::Int64RegClass);
+  addRegisterClass(MVT::f32, &WebAssembly::Float32RegClass);
+  addRegisterClass(MVT::f64, &WebAssembly::Float64RegClass);
+  // Compute derived properties from the register classes.
+  computeRegisterProperties(Subtarget->getRegisterInfo());
+
+  // FIXME: setOperationAction...
 }
 
 //===----------------------------------------------------------------------===//
 // WebAssembly Lowering private implementation.
 //===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//
 // Lowering Code
 //===----------------------------------------------------------------------===//
 
+static void fail(SDLoc DL, SelectionDAG &DAG, const char *msg) {
+  MachineFunction &MF = DAG.getMachineFunction();
+  DAG.getContext()->diagnose(
+      DiagnosticInfoUnsupported(DL, *MF.getFunction(), msg, SDValue()));
+}
+
+bool WebAssemblyTargetLowering::CanLowerReturn(
+    CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
+    const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
+  // FIXME: Implement using CallingConvention.td, similar to AArch64.
+  return Outs.size() <= 1;
+}
+
+SDValue WebAssemblyTargetLowering::LowerReturn(
+    SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
+    const SmallVectorImpl<ISD::OutputArg> &Outs,
+    const SmallVectorImpl<SDValue> &OutVals, SDLoc DL,
+    SelectionDAG &DAG) const {
+
+  if (Outs.size() > 1)
+    fail(DL, DAG, "WebAssembly can only return up to one value");
+
+  // FIXME: Implement LowerReturn.
+
+  return Chain;
+}
+
+SDValue WebAssemblyTargetLowering::LowerFormalArguments(
+    SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
+    const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
+    SmallVectorImpl<SDValue> &InVals) const {
+  MachineFunction &MF = DAG.getMachineFunction();
+
+  if (CallConv != CallingConv::C)
+    fail(DL, DAG, "WebAssembly doesn't support non-C calling conventions");
+  if (IsVarArg)
+    fail(DL, DAG, "WebAssembly doesn't support varargs");
+  if (MF.getFunction()->hasStructRetAttr())
+    fail(DL, DAG, "WebAssembly doesn't support struct return");
+
+  // FIXME: Implement LowerFormalArguments.
+  for (const ISD::InputArg &In : Ins)
+    InVals.push_back(DAG.getNode(ISD::UNDEF, DL, In.VT));
+
+  return Chain;
+}
+
 //===----------------------------------------------------------------------===//
 //  Other Lowering Code
 //===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//
 //                          WebAssembly Optimization Hooks
 //===----------------------------------------------------------------------===//
 
 MCSection *WebAssemblyTargetObjectFile::SelectSectionForGlobal(
     const GlobalValue *GV, SectionKind Kind, Mangler &Mang,
     const TargetMachine &TM) const {
   return getDataSection();
 }

lib/Target/WebAssembly/WebAssemblyInstrInfo.h

 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYINSTRINFO_H
 #define LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYINSTRINFO_H
 
 #include "WebAssemblyRegisterInfo.h"
 #include "llvm/Target/TargetInstrInfo.h"
 
+#define GET_INSTRINFO_HEADER
+#include "WebAssemblyGenInstrInfo.inc"
+
 namespace llvm {
 
 class WebAssemblySubtarget;
 
-class WebAssemblyInstrInfo final {
+class WebAssemblyInstrInfo final : public WebAssemblyGenInstrInfo {
   const WebAssemblyRegisterInfo RI;
 
 public:
   explicit WebAssemblyInstrInfo(const WebAssemblySubtarget &STI);
 
   const WebAssemblyRegisterInfo &getRegisterInfo() const { return RI; }
 };
 
 } // end namespace llvm
 
 #endif

lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp

 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineMemOperand.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 using namespace llvm;
 
 #define DEBUG_TYPE "wasm-instr-info"
 
+#define GET_INSTRINFO_CTOR_DTOR
+#include "WebAssemblyGenInstrInfo.inc"
+
 WebAssemblyInstrInfo::WebAssemblyInstrInfo(const WebAssemblySubtarget &STI)
     : RI(STI.getTargetTriple()) {}

lib/Target/WebAssembly/WebAssemblySubtarget.h

const WebAssemblySelectionDAGInfo *getSelectionDAGInfo() const override {
     return &TSInfo;
   }
   const WebAssemblyFrameLowering *getFrameLowering() const override {
     return &FrameLowering;
   }
   const WebAssemblyTargetLowering *getTargetLowering() const override {
     return &TLInfo;
   }
+  const WebAssemblyInstrInfo *getInstrInfo() const override {
+    return &InstrInfo;
+  }
+  const WebAssemblyRegisterInfo *getRegisterInfo() const override {
+    return &getInstrInfo()->getRegisterInfo();
+  }
   const Triple &getTargetTriple() const { return TargetTriple; }
   bool enableMachineScheduler() const override;
   bool useAA() const override { return true; }
 
   // Predicates used by WebAssemblyInstrInfo.td.
   bool hasAddr64() const { return TargetTriple.isArch64Bit(); }
   bool hasSIMD128() const { return HasSIMD128; }
 
   /// Parses features string setting specified subtarget options. Definition of
   /// function is auto generated by tblgen.
   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
 };
 
 } // end namespace llvm
 
 #endif

test/CodeGen/WebAssembly/integer.ll

+; RUN: llc < %s -asm-verbose=false | FileCheck %s
+
+target datalayout = "e-p:32:32-i64:64-v128:8:128-n32:64-S128"
+target triple = "wasm32-unknown-unknown"
+
+; CHECK-LABEL: add32:
+define i32 @add32(i32 %x, i32 %y) {
+  %a = add i32 %x, %y
+  ret i32 %a
+}