[PowerPC] Exploit XXPERM Instruction

[Conanap]

Summary

When a vector input is dead, we can use it as the target
instead of using extra registers. This is the first part of a
two part patch. This patch checks only if the first
input is dead, and if it is, to replace VPERM with XXPERM.

[Conanap]

Fixed unintended changes

[Conanap]

Rebase

[Conanap]

Updated the SDT definition for PPCxxperm to allow for different types of masks

llvm/lib/Target/PowerPC/PPCISelLowering.h

enum NodeType : unsigned {
 
     /// VECSHL - The PPC vector shift left instruction
     ///
     VECSHL,
 
     /// XXPERMDI - The PPC XXPERMDI instruction
     ///
     XXPERMDI,
+    XXPERM,
 
     /// The CMPB instruction (takes two operands of i32 or i64).
     CMPB,
 
     /// Hi/Lo - These represent the high and low 16-bit parts of a global
     /// address respectively.  These nodes have two operands, the first of
     /// which must be a TargetGlobalAddress, and the second of which must be a
     /// Constant.  Selected naively, these turn into 'lis G+C' and 'li G+C',
private:
     SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerFunnelShift(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
+    SDValue LowerVPERM(SDValue Op, SelectionDAG &DAG, SDValue VPermMask,
+                       SDValue V1, SDValue V2) const;
     SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerBSWAP(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerATOMIC_LOAD_STORE(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

 
 static cl::opt<bool> EnableQuadwordAtomics(
     "ppc-quadword-atomics",
     cl::desc("enable quadword lock-free atomic operations"), cl::init(false),
     cl::Hidden);
 
 STATISTIC(NumTailCalls, "Number of tail calls");
 STATISTIC(NumSiblingCalls, "Number of sibling calls");
-STATISTIC(ShufflesHandledWithVPERM, "Number of shuffles lowered to a VPERM");
+STATISTIC(ShufflesHandledWithVPERM,
+          "Number of shuffles lowered to a VPERM or XXPERM");
 STATISTIC(NumDynamicAllocaProbed, "Number of dynamic stack allocation probed");
 
 static bool isNByteElemShuffleMask(ShuffleVectorSDNode *, unsigned, int);
 
 static SDValue widenVec(SelectionDAG &DAG, SDValue Vec, const SDLoc &dl);
 
 static const char AIXSSPCanaryWordName[] = "__ssp_canary_word";
 
const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
   case PPCISD::VPERM:           return "PPCISD::VPERM";
   case PPCISD::XXSPLT:          return "PPCISD::XXSPLT";
   case PPCISD::XXSPLTI_SP_TO_DP:
     return "PPCISD::XXSPLTI_SP_TO_DP";
   case PPCISD::XXSPLTI32DX:
     return "PPCISD::XXSPLTI32DX";
   case PPCISD::VECINSERT:       return "PPCISD::VECINSERT";
   case PPCISD::XXPERMDI:        return "PPCISD::XXPERMDI";
+  case PPCISD::XXPERM:          return "PPCISD::XXPERM";
   case PPCISD::VECSHL:          return "PPCISD::VECSHL";
   case PPCISD::CMPB:            return "PPCISD::CMPB";
   case PPCISD::Hi:              return "PPCISD::Hi";
   case PPCISD::Lo:              return "PPCISD::Lo";
   case PPCISD::TOC_ENTRY:       return "PPCISD::TOC_ENTRY";
   case PPCISD::ATOMIC_CMP_SWAP_8: return "PPCISD::ATOMIC_CMP_SWAP_8";
   case PPCISD::ATOMIC_CMP_SWAP_16: return "PPCISD::ATOMIC_CMP_SWAP_16";
   case PPCISD::DYNALLOC:        return "PPCISD::DYNALLOC";
SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
 
   ShufflesHandledWithVPERM++;
   SDValue VPermMask = DAG.getBuildVector(MVT::v16i8, dl, ResultMask);
   LLVM_DEBUG(dbgs() << "Emitting a VPERM for the following shuffle:\n");
   LLVM_DEBUG(SVOp->dump());
   LLVM_DEBUG(dbgs() << "With the following permute control vector:\n");
   LLVM_DEBUG(VPermMask.dump());
 
-  if (isLittleEndian)
-    return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
-                       V2, V1, VPermMask);
-  else
-    return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
-                       V1, V2, VPermMask);
+  return LowerVPERM(Op, DAG, VPermMask, V1, V2);
+}
+
+SDValue PPCTargetLowering::LowerVPERM(SDValue Op, SelectionDAG &DAG,
+                                      SDValue VPermMask, SDValue V1,
+                                      SDValue V2) const {
+  unsigned Opcode = PPCISD::VPERM;
+  auto ValType = V1.getValueType();
+  SDLoc dl(Op);
+
+  if (Subtarget.isLittleEndian())
+    std::swap(V1, V2);
+
+  if (Subtarget.isISA3_0() && V1->hasOneUse()) {
+    LLVM_DEBUG(
+        dbgs()
+        << "At least one of two input vector is dead - using XXPERM instead\n");
+    Opcode = PPCISD::XXPERM;
+
+    // TODO along with future XXSWAPD patch
+    // If V2 is dead and V1 is not, swap them
+    // but also will need to fix up the mask
+    if (ValType != MVT::v2f64)
+      V1 = DAG.getBitcast(MVT::v2f64, V1);
+    if (V2.getValueType() != MVT::v2f64)
+      V2 = DAG.getBitcast(MVT::v2f64, V2);
+  }
+
+  SDValue VPERMNode =
+      DAG.getNode(Opcode, dl, V1.getValueType(), V1, V2, VPermMask);
+
+  if (ValType != MVT::v2f64 && Opcode == PPCISD::XXPERM)
+    VPERMNode = DAG.getBitcast(ValType, VPERMNode);
+
+  return VPERMNode;
 }
 
 /// getVectorCompareInfo - Given an intrinsic, return false if it is not a
 /// vector comparison.  If it is, return true and fill in Opc/isDot with
 /// information about the intrinsic.
 static bool getVectorCompareInfo(SDValue Intrin, int &CompareOpc,
                                  bool &isDot, const PPCSubtarget &Subtarget) {
   unsigned IntrinsicID =

llvm/lib/Target/PowerPC/PPCInstrVSX.td

def PPCldsplat : SDNode<"PPCISD::LD_SPLAT", SDT_PPCldsplat,
                         [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
 def PPCzextldsplat : SDNode<"PPCISD::ZEXT_LD_SPLAT", SDT_PPCldsplat,
                         [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
 def PPCsextldsplat : SDNode<"PPCISD::SEXT_LD_SPLAT", SDT_PPCldsplat,
                         [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
 def PPCSToV : SDNode<"PPCISD::SCALAR_TO_VECTOR_PERMUTED",
                      SDTypeProfile<1, 1, []>, []>;
 
+def SDT_PPCxxperm : SDTypeProfile<1, 3,
+                                  [SDTCisVT<0, v2f64>, SDTCisVT<1, v2f64>,
+                                   SDTCisVT<2, v2f64>]>;
+def PPCxxperm : SDNode<"PPCISD::XXPERM", SDT_PPCxxperm, []>;
 //-------------------------- Predicate definitions ---------------------------//
 def HasVSX : Predicate<"Subtarget->hasVSX()">;
 def IsLittleEndian : Predicate<"Subtarget->isLittleEndian()">;
 def IsBigEndian : Predicate<"!Subtarget->isLittleEndian()">;
 def IsPPC64 : Predicate<"Subtarget->isPPC64()">;
 def HasOnlySwappingMemOps : Predicate<"!Subtarget->hasP9Vector()">;
 def HasP8Vector : Predicate<"Subtarget->hasP8Vector()">;
 def HasDirectMove : Predicate<"Subtarget->hasDirectMove()">;
def XXBRD : XX2_XT6_XO5_XB6<60, 23, 475, "xxbrd", vsrc,
     [(set v2i64:$XT, (bswap v2i64:$XB))]>;
   // FIXME: Setting the hasSideEffects flag here to match current behaviour.
   let hasSideEffects = 1 in
   def XXBRQ : XX2_XT6_XO5_XB6<60, 31, 475, "xxbrq", vsrc, []>;
 
   // Vector Permute
   // FIXME: Setting the hasSideEffects flag here to match current behaviour.
   let hasSideEffects = 1 in {
-    def XXPERM  : XX3_XT5_XA5_XB5<60, 26, "xxperm" , vsrc, vsrc, vsrc,
-                                  IIC_VecPerm, []>;
-    def XXPERMR : XX3_XT5_XA5_XB5<60, 58, "xxpermr", vsrc, vsrc, vsrc,
-                                  IIC_VecPerm, []>;
+    def XXPERM  : XX3Form<60, 26, (outs vsrc:$XT),
+                                  (ins vsrc:$XA, vsrc:$XTi, vsrc:$XB),
+                          "xxperm $XT, $XA, $XB", IIC_VecPerm, []>,
+                          RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">;
+    def XXPERMR : XX3Form<60, 58, (outs vsrc:$XT),
+                                  (ins vsrc:$XA, vsrc:$XTi, vsrc:$XB),
+                          "xxpermr $XT, $XA, $XB", IIC_VecPerm, []>,
+                          RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">;
   }
 
   // Vector Splat Immediate Byte
   // FIXME: Setting the hasSideEffects flag here to match current behaviour.
   let hasSideEffects = 1 in
   def XXSPLTIB : X_RD6_IMM8<60, 360, (outs vsrc:$XT), (ins u8imm:$IMM8),
                             "xxspltib $XT, $IMM8", IIC_VecPerm, []>;
 

 def : Pat<(v4f32 (PPCldsplat ForceXForm:$A)),
           (v4f32 (LXVWSX ForceXForm:$A))>;
 def : Pat<(v4i32 (PPCldsplat ForceXForm:$A)),
           (v4i32 (LXVWSX ForceXForm:$A))>;
 def : Pat<(v8i16 (PPCldsplat ForceXForm:$A)),
           (v8i16 (VSPLTHs 3, (LXSIHZX ForceXForm:$A)))>;
 def : Pat<(v16i8 (PPCldsplat ForceXForm:$A)),
           (v16i8 (VSPLTBs 7, (LXSIBZX ForceXForm:$A)))>;
+def : Pat<(v2f64 (PPCxxperm v2f64:$XT, v2f64:$XB, (v16i8 (bitconvert v4i32:$C)))),
+          (XXPERM v2f64:$XT, v2f64:$XB, v4i32:$C)>;
 } // HasVSX, HasP9Vector
 
 // Any Power9 VSX subtarget with equivalent length but better Power10 VSX
 // patterns.
 // Two identical blocks are required due to the slightly different predicates:
 // One without P10 instructions, the other is BigEndian only with P10 instructions.
 let Predicates = [HasVSX, HasP9Vector, NoP10Vector] in {
 // Little endian Power10 subtargets produce a shorter pattern but require a

llvm/test/CodeGen/PowerPC/aix-p9-insert-extract.ll

entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 0>
   ret <8 x i16> %vecins
 }
 
 ; The following testcases use the same vector in both arguments of the
 ; shufflevector.  If halfword element 3 in BE mode(or 4 in LE mode) is the one
 ; we're attempting to insert, then we can use the vector insert instruction
 define <8 x i16> @shuffle_vector_halfword_0_4(<8 x i16> %a) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vinserth 2, 2, 14
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_halfword_0_4:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis 3, 2, .LCPI16_0@toc@ha
-; CHECK-BE-NEXT:    addi 3, 3, .LCPI16_0@toc@l
-; CHECK-BE-NEXT:    lxvx 35, 0, 3
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_halfword_0_4:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    ld 3, L..C0(2)
-; CHECK-64-NEXT:    lxv 35, 0(3)
-; CHECK-64-NEXT:    vperm 2, 2, 2, 3
+; CHECK-64-NEXT:    ld 3, L..C0(2) # %const.0
+; CHECK-64-NEXT:    lxv 0, 0(3)
+; CHECK-64-NEXT:    xxperm 34, 34, 0
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_halfword_0_4:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    lwz 3, L..C0(2)
-; CHECK-32-NEXT:    lxv 35, 0(3)
-; CHECK-32-NEXT:    vperm 2, 2, 2, 3
+; CHECK-32-NEXT:    lwz 3, L..C0(2) # %const.0
+; CHECK-32-NEXT:    lxv 0, 0(3)
+; CHECK-32-NEXT:    xxperm 34, 34, 0
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 4, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_1_3(<8 x i16> %a) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addis 3, 2, .LCPI17_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI17_0@toc@l
-; CHECK-NEXT:    lxvx 35, 0, 3
-; CHECK-NEXT:    vperm 2, 2, 2, 3
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_halfword_1_3:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vinserth 2, 2, 2
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_halfword_1_3:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    vinserth 2, 2, 2
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_halfword_1_3:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    vinserth 2, 2, 2
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 3, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_2_3(<8 x i16> %a) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addis 3, 2, .LCPI18_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI18_0@toc@l
-; CHECK-NEXT:    lxvx 35, 0, 3
-; CHECK-NEXT:    vperm 2, 2, 2, 3
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_halfword_2_3:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vinserth 2, 2, 4
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_halfword_2_3:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    vinserth 2, 2, 4
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_halfword_2_3:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    vinserth 2, 2, 4
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 3, i32 3, i32 4, i32 5, i32 6, i32 7>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_3_4(<8 x i16> %a) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vinserth 2, 2, 8
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_halfword_3_4:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis 3, 2, .LCPI19_0@toc@ha
-; CHECK-BE-NEXT:    addi 3, 3, .LCPI19_0@toc@l
-; CHECK-BE-NEXT:    lxvx 35, 0, 3
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_halfword_3_4:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    ld 3, L..C1(2)
-; CHECK-64-NEXT:    lxv 35, 0(3)
-; CHECK-64-NEXT:    vperm 2, 2, 2, 3
+; CHECK-64-NEXT:    ld 3, L..C1(2) # %const.0
+; CHECK-64-NEXT:    lxv 0, 0(3)
+; CHECK-64-NEXT:    xxperm 34, 34, 0
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_halfword_3_4:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    lwz 3, L..C1(2)
-; CHECK-32-NEXT:    lxv 35, 0(3)
-; CHECK-32-NEXT:    vperm 2, 2, 2, 3
+; CHECK-32-NEXT:    lwz 3, L..C1(2) # %const.0
+; CHECK-32-NEXT:    lxv 0, 0(3)
+; CHECK-32-NEXT:    xxperm 34, 34, 0
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 4, i32 4, i32 5, i32 6, i32 7>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_4_3(<8 x i16> %a) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addis 3, 2, .LCPI20_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI20_0@toc@l
-; CHECK-NEXT:    lxvx 35, 0, 3
-; CHECK-NEXT:    vperm 2, 2, 2, 3
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_halfword_4_3:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vinserth 2, 2, 8
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_halfword_4_3:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    vinserth 2, 2, 8
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_halfword_4_3:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    vinserth 2, 2, 8
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 3, i32 5, i32 6, i32 7>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_5_3(<8 x i16> %a) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addis 3, 2, .LCPI21_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI21_0@toc@l
-; CHECK-NEXT:    lxvx 35, 0, 3
-; CHECK-NEXT:    vperm 2, 2, 2, 3
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_halfword_5_3:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vinserth 2, 2, 10
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_halfword_5_3:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    vinserth 2, 2, 10
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_halfword_5_3:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    vinserth 2, 2, 10
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 3, i32 6, i32 7>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_6_4(<8 x i16> %a) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vinserth 2, 2, 2
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_halfword_6_4:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis 3, 2, .LCPI22_0@toc@ha
-; CHECK-BE-NEXT:    addi 3, 3, .LCPI22_0@toc@l
-; CHECK-BE-NEXT:    lxvx 35, 0, 3
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_halfword_6_4:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    ld 3, L..C2(2)
-; CHECK-64-NEXT:    lxv 35, 0(3)
-; CHECK-64-NEXT:    vperm 2, 2, 2, 3
+; CHECK-64-NEXT:    ld 3, L..C2(2) # %const.0
+; CHECK-64-NEXT:    lxv 0, 0(3)
+; CHECK-64-NEXT:    xxperm 34, 34, 0
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_halfword_6_4:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    lwz 3, L..C2(2)
-; CHECK-32-NEXT:    lxv 35, 0(3)
-; CHECK-32-NEXT:    vperm 2, 2, 2, 3
+; CHECK-32-NEXT:    lwz 3, L..C2(2) # %const.0
+; CHECK-32-NEXT:    lxv 0, 0(3)
+; CHECK-32-NEXT:    xxperm 34, 34, 0
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 4, i32 7>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_7_4(<8 x i16> %a) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vinserth 2, 2, 0
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_halfword_7_4:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis 3, 2, .LCPI23_0@toc@ha
-; CHECK-BE-NEXT:    addi 3, 3, .LCPI23_0@toc@l
-; CHECK-BE-NEXT:    lxvx 35, 0, 3
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_halfword_7_4:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    ld 3, L..C3(2)
-; CHECK-64-NEXT:    lxv 35, 0(3)
-; CHECK-64-NEXT:    vperm 2, 2, 2, 3
+; CHECK-64-NEXT:    ld 3, L..C3(2) # %const.0
+; CHECK-64-NEXT:    lxv 0, 0(3)
+; CHECK-64-NEXT:    xxperm 34, 34, 0
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_halfword_7_4:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    lwz 3, L..C3(2)
-; CHECK-32-NEXT:    lxv 35, 0(3)
-; CHECK-32-NEXT:    vperm 2, 2, 2, 3
+; CHECK-32-NEXT:    lwz 3, L..C3(2) # %const.0
+; CHECK-32-NEXT:    lxv 0, 0(3)
+; CHECK-32-NEXT:    xxperm 34, 34, 0
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 4>
   ret <8 x i16> %vecins
 }
 
 ; The following testcases take one byte element from the second vector and
 ; inserts it at various locations in the first vector
 define <16 x i8> @shuffle_vector_byte_0_16(<16 x i8> %a, <16 x i8> %b) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsldoi 3, 3, 3, 8
-; CHECK-NEXT:    vinsertb 2, 3, 15
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_0_16:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 9
-; CHECK-BE-NEXT:    vinsertb 2, 3, 0
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_0_16:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    vsldoi 3, 3, 3, 9
 ; CHECK-64-NEXT:    vinsertb 2, 3, 0
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_0_16:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    vsldoi 3, 3, 3, 9
 ; CHECK-32-NEXT:    vinsertb 2, 3, 0
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_1_25(<16 x i8> %a, <16 x i8> %b) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsldoi 3, 3, 3, 15
-; CHECK-NEXT:    vinsertb 2, 3, 14
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_1_25:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 2
-; CHECK-BE-NEXT:    vinsertb 2, 3, 1
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_1_25:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    vsldoi 3, 3, 3, 2
 ; CHECK-64-NEXT:    vinsertb 2, 3, 1
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_1_25:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    vsldoi 3, 3, 3, 2
 ; CHECK-32-NEXT:    vinsertb 2, 3, 1
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 25, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_2_18(<16 x i8> %a, <16 x i8> %b) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsldoi 3, 3, 3, 6
-; CHECK-NEXT:    vinsertb 2, 3, 13
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_2_18:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 11
-; CHECK-BE-NEXT:    vinsertb 2, 3, 2
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_2_18:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    vsldoi 3, 3, 3, 11
 ; CHECK-64-NEXT:    vinsertb 2, 3, 2
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_2_18:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    vsldoi 3, 3, 3, 11
 ; CHECK-32-NEXT:    vinsertb 2, 3, 2
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 18, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_3_27(<16 x i8> %a, <16 x i8> %b) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsldoi 3, 3, 3, 13
-; CHECK-NEXT:    vinsertb 2, 3, 12
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_3_27:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 4
-; CHECK-BE-NEXT:    vinsertb 2, 3, 3
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_3_27:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    vsldoi 3, 3, 3, 4
 ; CHECK-64-NEXT:    vinsertb 2, 3, 3
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_3_27:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    vsldoi 3, 3, 3, 4
 ; CHECK-32-NEXT:    vinsertb 2, 3, 3
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 27, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_4_20(<16 x i8> %a, <16 x i8> %b) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsldoi 3, 3, 3, 4
-; CHECK-NEXT:    vinsertb 2, 3, 11
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_4_20:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 13
-; CHECK-BE-NEXT:    vinsertb 2, 3, 4
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_4_20:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    vsldoi 3, 3, 3, 13
 ; CHECK-64-NEXT:    vinsertb 2, 3, 4
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_4_20:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    vsldoi 3, 3, 3, 13
 ; CHECK-32-NEXT:    vinsertb 2, 3, 4
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 20, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_5_29(<16 x i8> %a, <16 x i8> %b) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsldoi 3, 3, 3, 11
-; CHECK-NEXT:    vinsertb 2, 3, 10
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_5_29:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 6
-; CHECK-BE-NEXT:    vinsertb 2, 3, 5
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_5_29:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    vsldoi 3, 3, 3, 6
 ; CHECK-64-NEXT:    vinsertb 2, 3, 5
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_5_29:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    vsldoi 3, 3, 3, 6
 ; CHECK-32-NEXT:    vinsertb 2, 3, 5
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 29, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_6_22(<16 x i8> %a, <16 x i8> %b) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsldoi 3, 3, 3, 2
-; CHECK-NEXT:    vinsertb 2, 3, 9
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_6_22:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 15
-; CHECK-BE-NEXT:    vinsertb 2, 3, 6
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_6_22:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    vsldoi 3, 3, 3, 15
 ; CHECK-64-NEXT:    vinsertb 2, 3, 6
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_6_22:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    vsldoi 3, 3, 3, 15
 ; CHECK-32-NEXT:    vinsertb 2, 3, 6
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 22, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_7_31(<16 x i8> %a, <16 x i8> %b) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsldoi 3, 3, 3, 9
-; CHECK-NEXT:    vinsertb 2, 3, 8
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_7_31:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 8
-; CHECK-BE-NEXT:    vinsertb 2, 3, 7
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_7_31:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    vsldoi 3, 3, 3, 8
 ; CHECK-64-NEXT:    vinsertb 2, 3, 7
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_7_31:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    vsldoi 3, 3, 3, 8
 ; CHECK-32-NEXT:    vinsertb 2, 3, 7
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 31, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_8_24(<16 x i8> %a, <16 x i8> %b) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vinsertb 2, 3, 7
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_8_24:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 1
-; CHECK-BE-NEXT:    vinsertb 2, 3, 8
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_8_24:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    vsldoi 3, 3, 3, 1
 ; CHECK-64-NEXT:    vinsertb 2, 3, 8
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_8_24:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    vsldoi 3, 3, 3, 1
 ; CHECK-32-NEXT:    vinsertb 2, 3, 8
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 24, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_9_17(<16 x i8> %a, <16 x i8> %b) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsldoi 3, 3, 3, 7
-; CHECK-NEXT:    vinsertb 2, 3, 6
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_9_17:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 10
-; CHECK-BE-NEXT:    vinsertb 2, 3, 9
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_9_17:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    vsldoi 3, 3, 3, 10
 ; CHECK-64-NEXT:    vinsertb 2, 3, 9
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_9_17:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    vsldoi 3, 3, 3, 10
 ; CHECK-32-NEXT:    vinsertb 2, 3, 9
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 17, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_10_26(<16 x i8> %a, <16 x i8> %b) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsldoi 3, 3, 3, 14
-; CHECK-NEXT:    vinsertb 2, 3, 5
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_10_26:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 3
-; CHECK-BE-NEXT:    vinsertb 2, 3, 10
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_10_26:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    vsldoi 3, 3, 3, 3
 ; CHECK-64-NEXT:    vinsertb 2, 3, 10
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_10_26:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    vsldoi 3, 3, 3, 3
 ; CHECK-32-NEXT:    vinsertb 2, 3, 10
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 26, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_11_19(<16 x i8> %a, <16 x i8> %b) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsldoi 3, 3, 3, 5
-; CHECK-NEXT:    vinsertb 2, 3, 4
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_11_19:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 12
-; CHECK-BE-NEXT:    vinsertb 2, 3, 11
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_11_19:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    vsldoi 3, 3, 3, 12
 ; CHECK-64-NEXT:    vinsertb 2, 3, 11
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_11_19:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    vsldoi 3, 3, 3, 12
 ; CHECK-32-NEXT:    vinsertb 2, 3, 11
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 19, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_12_28(<16 x i8> %a, <16 x i8> %b) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsldoi 3, 3, 3, 12
-; CHECK-NEXT:    vinsertb 2, 3, 3
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_12_28:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 5
-; CHECK-BE-NEXT:    vinsertb 2, 3, 12
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_12_28:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    vsldoi 3, 3, 3, 5
 ; CHECK-64-NEXT:    vinsertb 2, 3, 12
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_12_28:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    vsldoi 3, 3, 3, 5
 ; CHECK-32-NEXT:    vinsertb 2, 3, 12
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 28, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_13_21(<16 x i8> %a, <16 x i8> %b) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsldoi 3, 3, 3, 3
-; CHECK-NEXT:    vinsertb 2, 3, 2
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_13_21:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 14
-; CHECK-BE-NEXT:    vinsertb 2, 3, 13
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_13_21:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    vsldoi 3, 3, 3, 14
 ; CHECK-64-NEXT:    vinsertb 2, 3, 13
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_13_21:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    vsldoi 3, 3, 3, 14
 ; CHECK-32-NEXT:    vinsertb 2, 3, 13
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 21, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_14_30(<16 x i8> %a, <16 x i8> %b) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsldoi 3, 3, 3, 10
-; CHECK-NEXT:    vinsertb 2, 3, 1
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_14_30:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vsldoi 3, 3, 3, 7
-; CHECK-BE-NEXT:    vinsertb 2, 3, 14
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_14_30:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    vsldoi 3, 3, 3, 7
 ; CHECK-64-NEXT:    vinsertb 2, 3, 14
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_14_30:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    vsldoi 3, 3, 3, 7
 ; CHECK-32-NEXT:    vinsertb 2, 3, 14
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 30, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_15_23(<16 x i8> %a, <16 x i8> %b) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsldoi 3, 3, 3, 1
-; CHECK-NEXT:    vinsertb 2, 3, 0
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_15_23:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vinsertb 2, 3, 15
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_15_23:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    vinsertb 2, 3, 15
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_15_23:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    vinsertb 2, 3, 15
entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 15>
   ret <16 x i8> %vecins
 }
 
 ; The following testcases use the same vector in both arguments of the
 ; shufflevector.  If byte element 7 in BE mode(or 8 in LE mode) is the one
 ; we're attempting to insert, then we can use the vector insert instruction
 define <16 x i8> @shuffle_vector_byte_0_7(<16 x i8> %a) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addis 3, 2, .LCPI56_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI56_0@toc@l
-; CHECK-NEXT:    lxvx 35, 0, 3
-; CHECK-NEXT:    vperm 2, 2, 2, 3
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_0_7:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vinsertb 2, 2, 0
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_0_7:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    vinsertb 2, 2, 0
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_0_7:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    vinsertb 2, 2, 0
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 7, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_1_8(<16 x i8> %a) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vinsertb 2, 2, 14
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_1_8:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis 3, 2, .LCPI57_0@toc@ha
-; CHECK-BE-NEXT:    addi 3, 3, .LCPI57_0@toc@l
-; CHECK-BE-NEXT:    lxvx 35, 0, 3
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_1_8:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    ld 3, L..C4(2)
-; CHECK-64-NEXT:    lxv 35, 0(3)
-; CHECK-64-NEXT:    vperm 2, 2, 2, 3
+; CHECK-64-NEXT:    ld 3, L..C4(2) # %const.0
+; CHECK-64-NEXT:    lxv 0, 0(3)
+; CHECK-64-NEXT:    xxperm 34, 34, 0
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_1_8:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    lwz 3, L..C4(2)
-; CHECK-32-NEXT:    lxv 35, 0(3)
-; CHECK-32-NEXT:    vperm 2, 2, 2, 3
+; CHECK-32-NEXT:    lwz 3, L..C4(2) # %const.0
+; CHECK-32-NEXT:    lxv 0, 0(3)
+; CHECK-32-NEXT:    xxperm 34, 34, 0
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 8, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_2_8(<16 x i8> %a) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vinsertb 2, 2, 13
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_2_8:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis 3, 2, .LCPI58_0@toc@ha
-; CHECK-BE-NEXT:    addi 3, 3, .LCPI58_0@toc@l
-; CHECK-BE-NEXT:    lxvx 35, 0, 3
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_2_8:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    ld 3, L..C5(2)
-; CHECK-64-NEXT:    lxv 35, 0(3)
-; CHECK-64-NEXT:    vperm 2, 2, 2, 3
+; CHECK-64-NEXT:    ld 3, L..C5(2) # %const.0
+; CHECK-64-NEXT:    lxv 0, 0(3)
+; CHECK-64-NEXT:    xxperm 34, 34, 0
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_2_8:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    lwz 3, L..C5(2)
-; CHECK-32-NEXT:    lxv 35, 0(3)
-; CHECK-32-NEXT:    vperm 2, 2, 2, 3
+; CHECK-32-NEXT:    lwz 3, L..C5(2) # %const.0
+; CHECK-32-NEXT:    lxv 0, 0(3)
+; CHECK-32-NEXT:    xxperm 34, 34, 0
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 8, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_3_7(<16 x i8> %a) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addis 3, 2, .LCPI59_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI59_0@toc@l
-; CHECK-NEXT:    lxvx 35, 0, 3
-; CHECK-NEXT:    vperm 2, 2, 2, 3
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_3_7:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vinsertb 2, 2, 3
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_3_7:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    vinsertb 2, 2, 3
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_3_7:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    vinsertb 2, 2, 3
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 7, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_4_7(<16 x i8> %a) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addis 3, 2, .LCPI60_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI60_0@toc@l
-; CHECK-NEXT:    lxvx 35, 0, 3
-; CHECK-NEXT:    vperm 2, 2, 2, 3
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_4_7:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vinsertb 2, 2, 4
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_4_7:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    vinsertb 2, 2, 4
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_4_7:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    vinsertb 2, 2, 4
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 7, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_5_8(<16 x i8> %a) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vinsertb 2, 2, 10
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_5_8:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis 3, 2, .LCPI61_0@toc@ha
-; CHECK-BE-NEXT:    addi 3, 3, .LCPI61_0@toc@l
-; CHECK-BE-NEXT:    lxvx 35, 0, 3
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_5_8:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    ld 3, L..C6(2)
-; CHECK-64-NEXT:    lxv 35, 0(3)
-; CHECK-64-NEXT:    vperm 2, 2, 2, 3
+; CHECK-64-NEXT:    ld 3, L..C6(2) # %const.0
+; CHECK-64-NEXT:    lxv 0, 0(3)
+; CHECK-64-NEXT:    xxperm 34, 34, 0
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_5_8:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    lwz 3, L..C6(2)
-; CHECK-32-NEXT:    lxv 35, 0(3)
-; CHECK-32-NEXT:    vperm 2, 2, 2, 3
+; CHECK-32-NEXT:    lwz 3, L..C6(2) # %const.0
+; CHECK-32-NEXT:    lxv 0, 0(3)
+; CHECK-32-NEXT:    xxperm 34, 34, 0
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 8, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_6_8(<16 x i8> %a) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vinsertb 2, 2, 9
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_6_8:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis 3, 2, .LCPI62_0@toc@ha
-; CHECK-BE-NEXT:    addi 3, 3, .LCPI62_0@toc@l
-; CHECK-BE-NEXT:    lxvx 35, 0, 3
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_6_8:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    ld 3, L..C7(2)
-; CHECK-64-NEXT:    lxv 35, 0(3)
-; CHECK-64-NEXT:    vperm 2, 2, 2, 3
+; CHECK-64-NEXT:    ld 3, L..C7(2) # %const.0
+; CHECK-64-NEXT:    lxv 0, 0(3)
+; CHECK-64-NEXT:    xxperm 34, 34, 0
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_6_8:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    lwz 3, L..C7(2)
-; CHECK-32-NEXT:    lxv 35, 0(3)
-; CHECK-32-NEXT:    vperm 2, 2, 2, 3
+; CHECK-32-NEXT:    lwz 3, L..C7(2) # %const.0
+; CHECK-32-NEXT:    lxv 0, 0(3)
+; CHECK-32-NEXT:    xxperm 34, 34, 0
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 8, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_7_8(<16 x i8> %a) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vinsertb 2, 2, 8
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_7_8:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis 3, 2, .LCPI63_0@toc@ha
-; CHECK-BE-NEXT:    addi 3, 3, .LCPI63_0@toc@l
-; CHECK-BE-NEXT:    lxvx 35, 0, 3
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_7_8:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    ld 3, L..C8(2)
-; CHECK-64-NEXT:    lxv 35, 0(3)
-; CHECK-64-NEXT:    vperm 2, 2, 2, 3
+; CHECK-64-NEXT:    ld 3, L..C8(2) # %const.0
+; CHECK-64-NEXT:    lxv 0, 0(3)
+; CHECK-64-NEXT:    xxperm 34, 34, 0
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_7_8:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    lwz 3, L..C8(2)
-; CHECK-32-NEXT:    lxv 35, 0(3)
-; CHECK-32-NEXT:    vperm 2, 2, 2, 3
+; CHECK-32-NEXT:    lwz 3, L..C8(2) # %const.0
+; CHECK-32-NEXT:    lxv 0, 0(3)
+; CHECK-32-NEXT:    xxperm 34, 34, 0
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 8, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_8_7(<16 x i8> %a) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addis 3, 2, .LCPI64_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI64_0@toc@l
-; CHECK-NEXT:    lxvx 35, 0, 3
-; CHECK-NEXT:    vperm 2, 2, 2, 3
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_8_7:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vinsertb 2, 2, 8
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_8_7:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    vinsertb 2, 2, 8
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_8_7:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    vinsertb 2, 2, 8
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 7, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_9_7(<16 x i8> %a) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addis 3, 2, .LCPI65_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI65_0@toc@l
-; CHECK-NEXT:    lxvx 35, 0, 3
-; CHECK-NEXT:    vperm 2, 2, 2, 3
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_9_7:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vinsertb 2, 2, 9
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_9_7:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    vinsertb 2, 2, 9
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_9_7:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    vinsertb 2, 2, 9
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 7, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_10_7(<16 x i8> %a) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addis 3, 2, .LCPI66_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI66_0@toc@l
-; CHECK-NEXT:    lxvx 35, 0, 3
-; CHECK-NEXT:    vperm 2, 2, 2, 3
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_10_7:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vinsertb 2, 2, 10
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_10_7:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    vinsertb 2, 2, 10
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_10_7:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    vinsertb 2, 2, 10
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 7, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_11_8(<16 x i8> %a) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vinsertb 2, 2, 4
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_11_8:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis 3, 2, .LCPI67_0@toc@ha
-; CHECK-BE-NEXT:    addi 3, 3, .LCPI67_0@toc@l
-; CHECK-BE-NEXT:    lxvx 35, 0, 3
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_11_8:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    ld 3, L..C9(2)
-; CHECK-64-NEXT:    lxv 35, 0(3)
-; CHECK-64-NEXT:    vperm 2, 2, 2, 3
+; CHECK-64-NEXT:    ld 3, L..C9(2) # %const.0
+; CHECK-64-NEXT:    lxv 0, 0(3)
+; CHECK-64-NEXT:    xxperm 34, 34, 0
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_11_8:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    lwz 3, L..C9(2)
-; CHECK-32-NEXT:    lxv 35, 0(3)
-; CHECK-32-NEXT:    vperm 2, 2, 2, 3
+; CHECK-32-NEXT:    lwz 3, L..C9(2) # %const.0
+; CHECK-32-NEXT:    lxv 0, 0(3)
+; CHECK-32-NEXT:    xxperm 34, 34, 0
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 8, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_12_8(<16 x i8> %a) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vinsertb 2, 2, 3
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_12_8:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis 3, 2, .LCPI68_0@toc@ha
-; CHECK-BE-NEXT:    addi 3, 3, .LCPI68_0@toc@l
-; CHECK-BE-NEXT:    lxvx 35, 0, 3
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_12_8:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    ld 3, L..C10(2)
-; CHECK-64-NEXT:    lxv 35, 0(3)
-; CHECK-64-NEXT:    vperm 2, 2, 2, 3
+; CHECK-64-NEXT:    ld 3, L..C10(2) # %const.0
+; CHECK-64-NEXT:    lxv 0, 0(3)
+; CHECK-64-NEXT:    xxperm 34, 34, 0
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_12_8:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    lwz 3, L..C10(2)
-; CHECK-32-NEXT:    lxv 35, 0(3)
-; CHECK-32-NEXT:    vperm 2, 2, 2, 3
+; CHECK-32-NEXT:    lwz 3, L..C10(2) # %const.0
+; CHECK-32-NEXT:    lxv 0, 0(3)
+; CHECK-32-NEXT:    xxperm 34, 34, 0
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 8, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_13_7(<16 x i8> %a) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addis 3, 2, .LCPI69_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI69_0@toc@l
-; CHECK-NEXT:    lxvx 35, 0, 3
-; CHECK-NEXT:    vperm 2, 2, 2, 3
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_13_7:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vinsertb 2, 2, 13
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_13_7:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    vinsertb 2, 2, 13
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_13_7:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    vinsertb 2, 2, 13
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 7, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_14_7(<16 x i8> %a) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addis 3, 2, .LCPI70_0@toc@ha
-; CHECK-NEXT:    addi 3, 3, .LCPI70_0@toc@l
-; CHECK-NEXT:    lxvx 35, 0, 3
-; CHECK-NEXT:    vperm 2, 2, 2, 3
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_14_7:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vinsertb 2, 2, 14
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_14_7:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    vinsertb 2, 2, 14
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_14_7:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    vinsertb 2, 2, 14
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 7, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_15_8(<16 x i8> %a) {
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vinsertb 2, 2, 0
-; CHECK-NEXT:    blr
-; CHECK-BE-LABEL: shuffle_vector_byte_15_8:
-; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    addis 3, 2, .LCPI71_0@toc@ha
-; CHECK-BE-NEXT:    addi 3, 3, .LCPI71_0@toc@l
-; CHECK-BE-NEXT:    lxvx 35, 0, 3
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
-; CHECK-BE-NEXT:    blr
 ; CHECK-64-LABEL: shuffle_vector_byte_15_8:
 ; CHECK-64:       # %bb.0: # %entry
-; CHECK-64-NEXT:    ld 3, L..C11(2)
-; CHECK-64-NEXT:    lxv 35, 0(3)
-; CHECK-64-NEXT:    vperm 2, 2, 2, 3
+; CHECK-64-NEXT:    ld 3, L..C11(2) # %const.0
+; CHECK-64-NEXT:    lxv 0, 0(3)
+; CHECK-64-NEXT:    xxperm 34, 34, 0
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: shuffle_vector_byte_15_8:
 ; CHECK-32:       # %bb.0: # %entry
-; CHECK-32-NEXT:    lwz 3, L..C11(2)
-; CHECK-32-NEXT:    lxv 35, 0(3)
-; CHECK-32-NEXT:    vperm 2, 2, 2, 3
+; CHECK-32-NEXT:    lwz 3, L..C11(2) # %const.0
+; CHECK-32-NEXT:    lxv 0, 0(3)
+; CHECK-32-NEXT:    xxperm 34, 34, 0
 ; CHECK-32-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 8>
   ret <16 x i8> %vecins
 }
 
 ; The following tests try to insert one halfword element into the vector.  We
 ; should always be using the 'vinserth' instruction.

llvm/test/CodeGen/PowerPC/build-vector-tests.ll

 }
 
 define <4 x i32> @fromDiffMemConsDi(i32* nocapture readonly %arr) {
 ; P9BE-LABEL: fromDiffMemConsDi:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    lxv v2, 0(r3)
 ; P9BE-NEXT:    addis r3, r2, .LCPI7_0@toc@ha
 ; P9BE-NEXT:    addi r3, r3, .LCPI7_0@toc@l
-; P9BE-NEXT:    lxv v3, 0(r3)
-; P9BE-NEXT:    vperm v2, v2, v2, v3
+; P9BE-NEXT:    lxv vs0, 0(r3)
+; P9BE-NEXT:    xxperm v2, v2, vs0
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: fromDiffMemConsDi:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    lxvw4x v2, 0, r3
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: fromDiffMemConsDi:

 ; P9BE-LABEL: fromDiffMemVarDi:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    sldi r4, r4, 2
 ; P9BE-NEXT:    add r3, r3, r4
 ; P9BE-NEXT:    li r4, -12
 ; P9BE-NEXT:    lxvx v2, r3, r4
 ; P9BE-NEXT:    addis r3, r2, .LCPI9_0@toc@ha
 ; P9BE-NEXT:    addi r3, r3, .LCPI9_0@toc@l
-; P9BE-NEXT:    lxv v3, 0(r3)
-; P9BE-NEXT:    vperm v2, v2, v2, v3
+; P9BE-NEXT:    lxv vs0, 0(r3)
+; P9BE-NEXT:    xxperm v2, v2, vs0
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: fromDiffMemVarDi:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    sldi r4, r4, 2
 ; P9LE-NEXT:    add r3, r3, r4
 ; P9LE-NEXT:    li r4, -12
 ; P9LE-NEXT:    lxvx v2, r3, r4
 ; P9LE-NEXT:    addis r3, r2, .LCPI9_0@toc@ha
 ; P9LE-NEXT:    addi r3, r3, .LCPI9_0@toc@l
-; P9LE-NEXT:    lxv v3, 0(r3)
-; P9LE-NEXT:    vperm v2, v2, v2, v3
+; P9LE-NEXT:    lxv vs0, 0(r3)
+; P9LE-NEXT:    xxperm v2, v2, vs0
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: fromDiffMemVarDi:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    sldi r4, r4, 2
 ; P8BE-NEXT:    addis r5, r2, .LCPI9_0@toc@ha
 ; P8BE-NEXT:    add r3, r3, r4
 ; P8BE-NEXT:    addi r4, r5, .LCPI9_0@toc@l
entry:
   %1 = load <4 x float>, <4 x float>* %0, align 4
   %2 = fptosi <4 x float> %1 to <4 x i32>
   ret <4 x i32> %2
 }
 
 define <4 x i32> @fromDiffMemConsDConvftoi(float* nocapture readonly %ptr) {
 ; P9BE-LABEL: fromDiffMemConsDConvftoi:
 ; P9BE:       # %bb.0: # %entry
-; P9BE-NEXT:    lxv v2, 0(r3)
+; P9BE-NEXT:    lxv vs0, 0(r3)
 ; P9BE-NEXT:    addis r3, r2, .LCPI18_0@toc@ha
 ; P9BE-NEXT:    addi r3, r3, .LCPI18_0@toc@l
-; P9BE-NEXT:    lxv v3, 0(r3)
-; P9BE-NEXT:    vperm v2, v2, v2, v3
-; P9BE-NEXT:    xvcvspsxws v2, v2
+; P9BE-NEXT:    lxv vs1, 0(r3)
+; P9BE-NEXT:    xxperm vs0, vs0, vs1
+; P9BE-NEXT:    xvcvspsxws v2, vs0
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: fromDiffMemConsDConvftoi:
 ; P9LE:       # %bb.0: # %entry
-; P9LE-NEXT:    lxv v2, 0(r3)
+; P9LE-NEXT:    lxv vs0, 0(r3)
 ; P9LE-NEXT:    addis r3, r2, .LCPI18_0@toc@ha
 ; P9LE-NEXT:    addi r3, r3, .LCPI18_0@toc@l
-; P9LE-NEXT:    lxv v3, 0(r3)
-; P9LE-NEXT:    vperm v2, v2, v2, v3
-; P9LE-NEXT:    xvcvspsxws v2, v2
+; P9LE-NEXT:    lxv vs1, 0(r3)
+; P9LE-NEXT:    xxperm vs0, vs0, vs1
+; P9LE-NEXT:    xvcvspsxws v2, vs0
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: fromDiffMemConsDConvftoi:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    addis r4, r2, .LCPI18_0@toc@ha
 ; P8BE-NEXT:    lxvw4x v2, 0, r3
 ; P8BE-NEXT:    addi r4, r4, .LCPI18_0@toc@l
 ; P8BE-NEXT:    lxvw4x v3, 0, r4

 }
 
 define <4 x i32> @fromDiffMemConsDui(i32* nocapture readonly %arr) {
 ; P9BE-LABEL: fromDiffMemConsDui:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    lxv v2, 0(r3)
 ; P9BE-NEXT:    addis r3, r2, .LCPI39_0@toc@ha
 ; P9BE-NEXT:    addi r3, r3, .LCPI39_0@toc@l
-; P9BE-NEXT:    lxv v3, 0(r3)
-; P9BE-NEXT:    vperm v2, v2, v2, v3
+; P9BE-NEXT:    lxv vs0, 0(r3)
+; P9BE-NEXT:    xxperm v2, v2, vs0
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: fromDiffMemConsDui:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    lxvw4x v2, 0, r3
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: fromDiffMemConsDui:

 ; P9BE-LABEL: fromDiffMemVarDui:
 ; P9BE:       # %bb.0: # %entry
 ; P9BE-NEXT:    sldi r4, r4, 2
 ; P9BE-NEXT:    add r3, r3, r4
 ; P9BE-NEXT:    li r4, -12
 ; P9BE-NEXT:    lxvx v2, r3, r4
 ; P9BE-NEXT:    addis r3, r2, .LCPI41_0@toc@ha
 ; P9BE-NEXT:    addi r3, r3, .LCPI41_0@toc@l
-; P9BE-NEXT:    lxv v3, 0(r3)
-; P9BE-NEXT:    vperm v2, v2, v2, v3
+; P9BE-NEXT:    lxv vs0, 0(r3)
+; P9BE-NEXT:    xxperm v2, v2, vs0
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: fromDiffMemVarDui:
 ; P9LE:       # %bb.0: # %entry
 ; P9LE-NEXT:    sldi r4, r4, 2
 ; P9LE-NEXT:    add r3, r3, r4
 ; P9LE-NEXT:    li r4, -12
 ; P9LE-NEXT:    lxvx v2, r3, r4
 ; P9LE-NEXT:    addis r3, r2, .LCPI41_0@toc@ha
 ; P9LE-NEXT:    addi r3, r3, .LCPI41_0@toc@l
-; P9LE-NEXT:    lxv v3, 0(r3)
-; P9LE-NEXT:    vperm v2, v2, v2, v3
+; P9LE-NEXT:    lxv vs0, 0(r3)
+; P9LE-NEXT:    xxperm v2, v2, vs0
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: fromDiffMemVarDui:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    sldi r4, r4, 2
 ; P8BE-NEXT:    addis r5, r2, .LCPI41_0@toc@ha
 ; P8BE-NEXT:    add r3, r3, r4
 ; P8BE-NEXT:    addi r4, r5, .LCPI41_0@toc@l
entry:
   %1 = load <4 x float>, <4 x float>* %0, align 4
   %2 = fptoui <4 x float> %1 to <4 x i32>
   ret <4 x i32> %2
 }
 
 define <4 x i32> @fromDiffMemConsDConvftoui(float* nocapture readonly %ptr) {
 ; P9BE-LABEL: fromDiffMemConsDConvftoui:
 ; P9BE:       # %bb.0: # %entry
-; P9BE-NEXT:    lxv v2, 0(r3)
+; P9BE-NEXT:    lxv vs0, 0(r3)
 ; P9BE-NEXT:    addis r3, r2, .LCPI50_0@toc@ha
 ; P9BE-NEXT:    addi r3, r3, .LCPI50_0@toc@l
-; P9BE-NEXT:    lxv v3, 0(r3)
-; P9BE-NEXT:    vperm v2, v2, v2, v3
-; P9BE-NEXT:    xvcvspuxws v2, v2
+; P9BE-NEXT:    lxv vs1, 0(r3)
+; P9BE-NEXT:    xxperm vs0, vs0, vs1
+; P9BE-NEXT:    xvcvspuxws v2, vs0
 ; P9BE-NEXT:    blr
 ;
 ; P9LE-LABEL: fromDiffMemConsDConvftoui:
 ; P9LE:       # %bb.0: # %entry
-; P9LE-NEXT:    lxv v2, 0(r3)
+; P9LE-NEXT:    lxv vs0, 0(r3)
 ; P9LE-NEXT:    addis r3, r2, .LCPI50_0@toc@ha
 ; P9LE-NEXT:    addi r3, r3, .LCPI50_0@toc@l
-; P9LE-NEXT:    lxv v3, 0(r3)
-; P9LE-NEXT:    vperm v2, v2, v2, v3
-; P9LE-NEXT:    xvcvspuxws v2, v2
+; P9LE-NEXT:    lxv vs1, 0(r3)
+; P9LE-NEXT:    xxperm vs0, vs0, vs1
+; P9LE-NEXT:    xvcvspuxws v2, vs0
 ; P9LE-NEXT:    blr
 ;
 ; P8BE-LABEL: fromDiffMemConsDConvftoui:
 ; P8BE:       # %bb.0: # %entry
 ; P8BE-NEXT:    addis r4, r2, .LCPI50_0@toc@ha
 ; P8BE-NEXT:    lxvw4x v2, 0, r3
 ; P8BE-NEXT:    addi r4, r4, .LCPI50_0@toc@l
 ; P8BE-NEXT:    lxvw4x v3, 0, r4

llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll

 ; CHECK-P9-NEXT:    xxlxor v3, v3, v3
 ; CHECK-P9-NEXT:    vmrghb v2, v3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P9-BE-LABEL: testmrglb3:
 ; CHECK-P9-BE:       # %bb.0: # %entry
 ; CHECK-P9-BE-NEXT:    lxsd v2, 0(r3)
 ; CHECK-P9-BE-NEXT:    addis r3, r2, .LCPI12_0@toc@ha
-; CHECK-P9-BE-NEXT:    xxlxor v4, v4, v4
+; CHECK-P9-BE-NEXT:    xxlxor vs0, vs0, vs0
 ; CHECK-P9-BE-NEXT:    addi r3, r3, .LCPI12_0@toc@l
-; CHECK-P9-BE-NEXT:    lxv v3, 0(r3)
-; CHECK-P9-BE-NEXT:    vperm v2, v4, v2, v3
+; CHECK-P9-BE-NEXT:    lxv vs1, 0(r3)
+; CHECK-P9-BE-NEXT:    xxperm v2, vs0, vs1
 ; CHECK-P9-BE-NEXT:    blr
 ;
 ; CHECK-NOVSX-LABEL: testmrglb3:
 ; CHECK-NOVSX:       # %bb.0: # %entry
 ; CHECK-NOVSX-NEXT:    vxor v2, v2, v2
 ; CHECK-NOVSX-NEXT:    ld r3, 0(r3)
 ; CHECK-NOVSX-NEXT:    addis r4, r2, .LCPI12_0@toc@ha
 ; CHECK-NOVSX-NEXT:    addi r4, r4, .LCPI12_0@toc@l

 ; CHECK-P9-NEXT:    lxv v3, 0(r3)
 ; CHECK-P9-NEXT:    vmrgow v2, v3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P9-BE-LABEL: replace_undefs_in_splat:
 ; CHECK-P9-BE:       # %bb.0: # %entry
 ; CHECK-P9-BE-NEXT:    addis r3, r2, .LCPI15_0@toc@ha
 ; CHECK-P9-BE-NEXT:    addi r3, r3, .LCPI15_0@toc@l
-; CHECK-P9-BE-NEXT:    lxv v3, 0(r3)
+; CHECK-P9-BE-NEXT:    lxv vs1, 0(r3)
 ; CHECK-P9-BE-NEXT:    addis r3, r2, .LCPI15_1@toc@ha
 ; CHECK-P9-BE-NEXT:    addi r3, r3, .LCPI15_1@toc@l
-; CHECK-P9-BE-NEXT:    lxv v4, 0(r3)
-; CHECK-P9-BE-NEXT:    vperm v2, v2, v4, v3
+; CHECK-P9-BE-NEXT:    lxv vs0, 0(r3)
+; CHECK-P9-BE-NEXT:    xxperm vs0, v2, vs1
+; CHECK-P9-BE-NEXT:    xxlor v2, vs0, vs0
 ; CHECK-P9-BE-NEXT:    blr
 ;
 ; CHECK-NOVSX-LABEL: replace_undefs_in_splat:
 ; CHECK-NOVSX:       # %bb.0: # %entry
 ; CHECK-NOVSX-NEXT:    addis r3, r2, .LCPI15_0@toc@ha
 ; CHECK-NOVSX-NEXT:    addis r4, r2, .LCPI15_1@toc@ha
 ; CHECK-NOVSX-NEXT:    addi r3, r3, .LCPI15_0@toc@l
 ; CHECK-NOVSX-NEXT:    lvx v3, 0, r3

llvm/test/CodeGen/PowerPC/extract-and-store.ll

 ; CHECK-BE-NEXT:    xxsldwi vs0, vs34, vs0, 2
 ; CHECK-BE-NEXT:    stfiwx f1, r5, r4
 ; CHECK-BE-NEXT:    stxvw4x vs0, 0, r5
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test_stores_exceed_vec_size:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    addis r3, r2, .LCPI16_0@toc@ha
-; CHECK-P9-NEXT:    xxsldwi vs0, vs34, vs34, 1
+; CHECK-P9-NEXT:    xxlor vs1, vs34, vs34
 ; CHECK-P9-NEXT:    addi r3, r3, .LCPI16_0@toc@l
-; CHECK-P9-NEXT:    lxv vs35, 0(r3)
+; CHECK-P9-NEXT:    lxv vs0, 0(r3)
 ; CHECK-P9-NEXT:    li r3, 16
+; CHECK-P9-NEXT:    xxperm vs1, vs34, vs0
+; CHECK-P9-NEXT:    xxsldwi vs0, vs34, vs34, 1
 ; CHECK-P9-NEXT:    stfiwx f0, r5, r3
 ; CHECK-P9-NEXT:    li r3, 20
+; CHECK-P9-NEXT:    stxv vs1, 0(r5)
 ; CHECK-P9-NEXT:    stxsiwx vs34, r5, r3
-; CHECK-P9-NEXT:    vperm v3, v2, v2, v3
-; CHECK-P9-NEXT:    stxv vs35, 0(r5)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P9-BE-LABEL: test_stores_exceed_vec_size:
 ; CHECK-P9-BE:       # %bb.0: # %entry
 ; CHECK-P9-BE-NEXT:    xxspltw vs0, vs34, 0
 ; CHECK-P9-BE-NEXT:    li r3, 16
 ; CHECK-P9-BE-NEXT:    stxsiwx vs34, r5, r3
 ; CHECK-P9-BE-NEXT:    li r3, 20

llvm/test/CodeGen/PowerPC/load-shuffle-and-shuffle-store.ll

 ; CHECK-P8-BE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P8-BE-NEXT:    blr
 ;
 ; CHECK-P9-BE-LABEL: load_swap10:
 ; CHECK-P9-BE:       # %bb.0:
 ; CHECK-P9-BE-NEXT:    lxv v2, 0(r3)
 ; CHECK-P9-BE-NEXT:    addis r3, r2, .LCPI2_0@toc@ha
 ; CHECK-P9-BE-NEXT:    addi r3, r3, .LCPI2_0@toc@l
-; CHECK-P9-BE-NEXT:    lxv v3, 0(r3)
-; CHECK-P9-BE-NEXT:    vperm v2, v2, v2, v3
+; CHECK-P9-BE-NEXT:    lxv vs0, 0(r3)
+; CHECK-P9-BE-NEXT:    xxperm v2, v2, vs0
 ; CHECK-P9-BE-NEXT:    blr
   %v1 = load <4 x i32>, <4 x i32>* %vp1
   %v2 = load <4 x i32>, <4 x i32>* %vp2
   %v3 = shufflevector <4 x i32> %v1, <4 x i32> %v2, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
   ret <4 x i32> %v3
 }
 
 define <4 x i32> @load_swap11(<4 x i32>* %vp1, <4 x i32>* %vp2) {

 ; CHECK-P8-BE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P8-BE-NEXT:    blr
 ;
 ; CHECK-P9-BE-LABEL: load_swap11:
 ; CHECK-P9-BE:       # %bb.0:
 ; CHECK-P9-BE-NEXT:    addis r3, r2, .LCPI3_0@toc@ha
 ; CHECK-P9-BE-NEXT:    lxv v2, 0(r4)
 ; CHECK-P9-BE-NEXT:    addi r3, r3, .LCPI3_0@toc@l
-; CHECK-P9-BE-NEXT:    lxv v3, 0(r3)
-; CHECK-P9-BE-NEXT:    vperm v2, v2, v2, v3
+; CHECK-P9-BE-NEXT:    lxv vs0, 0(r3)
+; CHECK-P9-BE-NEXT:    xxperm v2, v2, vs0
 ; CHECK-P9-BE-NEXT:    blr
   %v1 = load <4 x i32>, <4 x i32>* %vp1
   %v2 = load <4 x i32>, <4 x i32>* %vp2
   %v3 = shufflevector <4 x i32> %v1, <4 x i32> %v2, <4 x i32> <i32 7, i32 6, i32 5, i32 4>
   ret <4 x i32> %v3
 }
 
 define <8 x i16> @load_swap20(<8 x i16>* %vp1, <8 x i16>* %vp2){

 ; CHECK-P8-BE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P8-BE-NEXT:    blr
 ;
 ; CHECK-P9-BE-LABEL: load_swap20:
 ; CHECK-P9-BE:       # %bb.0:
 ; CHECK-P9-BE-NEXT:    lxv v2, 0(r3)
 ; CHECK-P9-BE-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
 ; CHECK-P9-BE-NEXT:    addi r3, r3, .LCPI4_0@toc@l
-; CHECK-P9-BE-NEXT:    lxv v3, 0(r3)
-; CHECK-P9-BE-NEXT:    vperm v2, v2, v2, v3
+; CHECK-P9-BE-NEXT:    lxv vs0, 0(r3)
+; CHECK-P9-BE-NEXT:    xxperm v2, v2, vs0
 ; CHECK-P9-BE-NEXT:    blr
   %v1 = load <8 x i16>, <8 x i16>* %vp1
   %v2 = load <8 x i16>, <8 x i16>* %vp2
   %v3 = shufflevector <8 x i16> %v1, <8 x i16> %v2, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
   ret <8 x i16> %v3
 }
 
 define <8 x i16> @load_swap21(<8 x i16>* %vp1, <8 x i16>* %vp2){

 ; CHECK-P8-BE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P8-BE-NEXT:    blr
 ;
 ; CHECK-P9-BE-LABEL: load_swap21:
 ; CHECK-P9-BE:       # %bb.0:
 ; CHECK-P9-BE-NEXT:    addis r3, r2, .LCPI5_0@toc@ha
 ; CHECK-P9-BE-NEXT:    lxv v2, 0(r4)
 ; CHECK-P9-BE-NEXT:    addi r3, r3, .LCPI5_0@toc@l
-; CHECK-P9-BE-NEXT:    lxv v3, 0(r3)
-; CHECK-P9-BE-NEXT:    vperm v2, v2, v2, v3
+; CHECK-P9-BE-NEXT:    lxv vs0, 0(r3)
+; CHECK-P9-BE-NEXT:    xxperm v2, v2, vs0
 ; CHECK-P9-BE-NEXT:    blr
   %v1 = load <8 x i16>, <8 x i16>* %vp1
   %v2 = load <8 x i16>, <8 x i16>* %vp2
   %v3 = shufflevector <8 x i16> %v1, <8 x i16> %v2, <8 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>
   ret <8 x i16> %v3
 }
 
 define <16 x i8> @load_swap30(<16 x i8>* %vp1, <16 x i8>* %vp2){

 ; CHECK-P8-BE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P8-BE-NEXT:    blr
 ;
 ; CHECK-P9-BE-LABEL: load_swap50:
 ; CHECK-P9-BE:       # %bb.0:
 ; CHECK-P9-BE-NEXT:    lxv v2, 0(r3)
 ; CHECK-P9-BE-NEXT:    addis r3, r2, .LCPI9_0@toc@ha
 ; CHECK-P9-BE-NEXT:    addi r3, r3, .LCPI9_0@toc@l
-; CHECK-P9-BE-NEXT:    lxv v3, 0(r3)
-; CHECK-P9-BE-NEXT:    vperm v2, v2, v2, v3
+; CHECK-P9-BE-NEXT:    lxv vs0, 0(r3)
+; CHECK-P9-BE-NEXT:    xxperm v2, v2, vs0
 ; CHECK-P9-BE-NEXT:    blr
   %v1 = load <4 x float>, <4 x float>* %vp1
   %v2 = load <4 x float>, <4 x float>* %vp2
   %v3 = shufflevector <4 x float> %v1, <4 x float> %v2, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
   ret <4 x float> %v3
 }
 
 define <4 x float> @load_swap51(<4 x float>* %vp1, <4 x float>* %vp2) {

 ; CHECK-P8-BE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P8-BE-NEXT:    blr
 ;
 ; CHECK-P9-BE-LABEL: load_swap51:
 ; CHECK-P9-BE:       # %bb.0:
 ; CHECK-P9-BE-NEXT:    addis r3, r2, .LCPI10_0@toc@ha
 ; CHECK-P9-BE-NEXT:    lxv v2, 0(r4)
 ; CHECK-P9-BE-NEXT:    addi r3, r3, .LCPI10_0@toc@l
-; CHECK-P9-BE-NEXT:    lxv v3, 0(r3)
-; CHECK-P9-BE-NEXT:    vperm v2, v2, v2, v3
+; CHECK-P9-BE-NEXT:    lxv vs0, 0(r3)
+; CHECK-P9-BE-NEXT:    xxperm v2, v2, vs0
 ; CHECK-P9-BE-NEXT:    blr
   %v1 = load <4 x float>, <4 x float>* %vp1
   %v2 = load <4 x float>, <4 x float>* %vp2
   %v3 = shufflevector <4 x float> %v1, <4 x float> %v2, <4 x i32> <i32 7, i32 6, i32 5, i32 4>
   ret <4 x float> %v3
 }
 
 define void @swap_store00(<2 x i64> %v1, <2 x i64> %v2, <2 x i64>* %vp) {

 ; CHECK-P8-BE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P8-BE-NEXT:    stxvw4x v2, 0, r7
 ; CHECK-P8-BE-NEXT:    blr
 ;
 ; CHECK-P9-BE-LABEL: swap_store10:
 ; CHECK-P9-BE:       # %bb.0:
 ; CHECK-P9-BE-NEXT:    addis r3, r2, .LCPI13_0@toc@ha
 ; CHECK-P9-BE-NEXT:    addi r3, r3, .LCPI13_0@toc@l
-; CHECK-P9-BE-NEXT:    lxv v3, 0(r3)
-; CHECK-P9-BE-NEXT:    vperm v2, v2, v2, v3
+; CHECK-P9-BE-NEXT:    lxv vs0, 0(r3)
+; CHECK-P9-BE-NEXT:    xxperm v2, v2, vs0
 ; CHECK-P9-BE-NEXT:    stxv v2, 0(r7)
 ; CHECK-P9-BE-NEXT:    blr
   %v3 = shufflevector <4 x i32> %v1, <4 x i32> %v2, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
   store <4 x i32> %v3, <4 x i32>* %vp
   ret void
 }
 
 define void @swap_store11(<4 x i32> %v1, <4 x i32> %v2, <4 x i32>* %vp) {

 ; CHECK-P8-BE-NEXT:    vperm v2, v3, v3, v2
 ; CHECK-P8-BE-NEXT:    stxvw4x v2, 0, r7
 ; CHECK-P8-BE-NEXT:    blr
 ;
 ; CHECK-P9-BE-LABEL: swap_store11:
 ; CHECK-P9-BE:       # %bb.0:
 ; CHECK-P9-BE-NEXT:    addis r3, r2, .LCPI14_0@toc@ha
 ; CHECK-P9-BE-NEXT:    addi r3, r3, .LCPI14_0@toc@l
-; CHECK-P9-BE-NEXT:    lxv v2, 0(r3)
-; CHECK-P9-BE-NEXT:    vperm v2, v3, v3, v2
-; CHECK-P9-BE-NEXT:    stxv v2, 0(r7)
+; CHECK-P9-BE-NEXT:    lxv vs0, 0(r3)
+; CHECK-P9-BE-NEXT:    xxperm v3, v3, vs0
+; CHECK-P9-BE-NEXT:    stxv v3, 0(r7)
 ; CHECK-P9-BE-NEXT:    blr
   %v3 = shufflevector <4 x i32> %v1, <4 x i32> %v2, <4 x i32> <i32 7, i32 6, i32 5, i32 4>
   store <4 x i32> %v3, <4 x i32>* %vp
   ret void
 }
 
 define void @swap_store20(<8 x i16> %v1, <8 x i16> %v2, <8 x i16>* %vp) {
 ; CHECK-P8-LABEL: swap_store20:

 ; CHECK-P8-BE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P8-BE-NEXT:    stxvw4x v2, 0, r7
 ; CHECK-P8-BE-NEXT:    blr
 ;
 ; CHECK-P9-BE-LABEL: swap_store20:
 ; CHECK-P9-BE:       # %bb.0:
 ; CHECK-P9-BE-NEXT:    addis r3, r2, .LCPI15_0@toc@ha
 ; CHECK-P9-BE-NEXT:    addi r3, r3, .LCPI15_0@toc@l
-; CHECK-P9-BE-NEXT:    lxv v3, 0(r3)
-; CHECK-P9-BE-NEXT:    vperm v2, v2, v2, v3
+; CHECK-P9-BE-NEXT:    lxv vs0, 0(r3)
+; CHECK-P9-BE-NEXT:    xxperm v2, v2, vs0
 ; CHECK-P9-BE-NEXT:    stxv v2, 0(r7)
 ; CHECK-P9-BE-NEXT:    blr
   %v3 = shufflevector <8 x i16> %v1, <8 x i16> %v2, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
   store <8 x i16> %v3, <8 x i16>* %vp
   ret void
 }
 
 define void @swap_store21(<8 x i16> %v1, <8 x i16> %v2, <8 x i16>* %vp) {

 ; CHECK-P8-BE-NEXT:    vperm v2, v3, v3, v2
 ; CHECK-P8-BE-NEXT:    stxvw4x v2, 0, r7
 ; CHECK-P8-BE-NEXT:    blr
 ;
 ; CHECK-P9-BE-LABEL: swap_store21:
 ; CHECK-P9-BE:       # %bb.0:
 ; CHECK-P9-BE-NEXT:    addis r3, r2, .LCPI16_0@toc@ha
 ; CHECK-P9-BE-NEXT:    addi r3, r3, .LCPI16_0@toc@l
-; CHECK-P9-BE-NEXT:    lxv v2, 0(r3)
-; CHECK-P9-BE-NEXT:    vperm v2, v3, v3, v2
-; CHECK-P9-BE-NEXT:    stxv v2, 0(r7)
+; CHECK-P9-BE-NEXT:    lxv vs0, 0(r3)
+; CHECK-P9-BE-NEXT:    xxperm v3, v3, vs0
+; CHECK-P9-BE-NEXT:    stxv v3, 0(r7)
 ; CHECK-P9-BE-NEXT:    blr
   %v3 = shufflevector <8 x i16> %v1, <8 x i16> %v2, <8 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>
   store <8 x i16> %v3, <8 x i16>* %vp
   ret void
 }
 
 define void @swap_store30(<16 x i8> %v1, <16 x i8> %v2, <16 x i8>* %vp) {
 ; CHECK-P8-LABEL: swap_store30:

 ; CHECK-P8-BE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P8-BE-NEXT:    stxvw4x v2, 0, r7
 ; CHECK-P8-BE-NEXT:    blr
 ;
 ; CHECK-P9-BE-LABEL: swap_store50:
 ; CHECK-P9-BE:       # %bb.0:
 ; CHECK-P9-BE-NEXT:    addis r3, r2, .LCPI21_0@toc@ha
 ; CHECK-P9-BE-NEXT:    addi r3, r3, .LCPI21_0@toc@l
-; CHECK-P9-BE-NEXT:    lxv v3, 0(r3)
-; CHECK-P9-BE-NEXT:    vperm v2, v2, v2, v3
+; CHECK-P9-BE-NEXT:    lxv vs0, 0(r3)
+; CHECK-P9-BE-NEXT:    xxperm v2, v2, vs0
 ; CHECK-P9-BE-NEXT:    stxv v2, 0(r7)
 ; CHECK-P9-BE-NEXT:    blr
   %v3 = shufflevector <4 x float> %v1, <4 x float> %v2, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
   store <4 x float> %v3, <4 x float>* %vp
   ret void
 }
 
 define void @swap_store51(<4 x float> %v1, <4 x float> %v2, <4 x float>* %vp) {

 ; CHECK-P8-BE-NEXT:    vperm v2, v3, v3, v2
 ; CHECK-P8-BE-NEXT:    stxvw4x v2, 0, r7
 ; CHECK-P8-BE-NEXT:    blr
 ;
 ; CHECK-P9-BE-LABEL: swap_store51:
 ; CHECK-P9-BE:       # %bb.0:
 ; CHECK-P9-BE-NEXT:    addis r3, r2, .LCPI22_0@toc@ha
 ; CHECK-P9-BE-NEXT:    addi r3, r3, .LCPI22_0@toc@l
-; CHECK-P9-BE-NEXT:    lxv v2, 0(r3)
-; CHECK-P9-BE-NEXT:    vperm v2, v3, v3, v2
-; CHECK-P9-BE-NEXT:    stxv v2, 0(r7)
+; CHECK-P9-BE-NEXT:    lxv vs0, 0(r3)
+; CHECK-P9-BE-NEXT:    xxperm v3, v3, vs0
+; CHECK-P9-BE-NEXT:    stxv v3, 0(r7)
 ; CHECK-P9-BE-NEXT:    blr
   %v3 = shufflevector <4 x float> %v1, <4 x float> %v2, <4 x i32> <i32 7, i32 6, i32 5, i32 4>
   store <4 x float> %v3, <4 x float>* %vp
   ret void
 }

llvm/test/CodeGen/PowerPC/p10-vector-rotate.ll

entry:
   %tmp = tail call <1 x i128> @llvm.ppc.altivec.vrlqmi(<1 x i128> %a, <1 x i128> %c, <1 x i128> %b)
   ret <1 x i128> %tmp
 }
 
 ; Function Attrs: nounwind readnone
 define <1 x i128> @test_vrlqnm(<1 x i128> %a, <1 x i128> %b, <1 x i128> %c) {
 ; CHECK-LE-LABEL: test_vrlqnm:
 ; CHECK-LE:       # %bb.0: # %entry
-; CHECK-LE-NEXT:    plxv v5, .LCPI4_0@PCREL(0), 1
-; CHECK-LE-NEXT:    vperm v3, v4, v3, v5
+; CHECK-LE-NEXT:    plxv vs0, .LCPI4_0@PCREL(0), 1
+; CHECK-LE-NEXT:    xxperm v3, v4, vs0
 ; CHECK-LE-NEXT:    vrlqnm v2, v2, v3
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test_vrlqnm:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI4_0@toc@l
-; CHECK-BE-NEXT:    lxv v5, 0(r3)
-; CHECK-BE-NEXT:    vperm v3, v3, v4, v5
-; CHECK-BE-NEXT:    vrlqnm v2, v2, v3
+; CHECK-BE-NEXT:    lxv vs0, 0(r3)
+; CHECK-BE-NEXT:    xxperm v4, v3, vs0
+; CHECK-BE-NEXT:    vrlqnm v2, v2, v4
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast <1 x i128> %b to <16 x i8>
   %1 = bitcast <1 x i128> %c to <16 x i8>
   %shuffle.i = shufflevector <16 x i8> %0, <16 x i8> %1, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 16, i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
   %d = bitcast <16 x i8> %shuffle.i to <1 x i128>
   %tmp = tail call <1 x i128> @llvm.ppc.altivec.vrlqnm(<1 x i128> %a, <1 x i128> %d)
   ret <1 x i128> %tmp
 }
 
 ; Function Attrs: nounwind readnone
 declare <1 x i128> @llvm.ppc.altivec.vrlqmi(<1 x i128>, <1 x i128>, <1 x i128>)
 
 ; Function Attrs: nounwind readnone
 declare <1 x i128> @llvm.ppc.altivec.vrlqnm(<1 x i128>, <1 x i128>)

llvm/test/CodeGen/PowerPC/p9-vinsert-vextract.ll

 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vinserth 2, 2, 14
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_halfword_0_4:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    addis 3, 2, .LCPI16_0@toc@ha
 ; CHECK-BE-NEXT:    addi 3, 3, .LCPI16_0@toc@l
-; CHECK-BE-NEXT:    lxv 35, 0(3)
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
+; CHECK-BE-NEXT:    lxv 0, 0(3)
+; CHECK-BE-NEXT:    xxperm 34, 34, 0
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 4, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_1_3(<8 x i16> %a) {
 ; CHECK-LABEL: shuffle_vector_halfword_1_3:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis 3, 2, .LCPI17_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI17_0@toc@l
-; CHECK-NEXT:    lxv 35, 0(3)
-; CHECK-NEXT:    vperm 2, 2, 2, 3
+; CHECK-NEXT:    lxv 0, 0(3)
+; CHECK-NEXT:    xxperm 34, 34, 0
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_halfword_1_3:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    vinserth 2, 2, 2
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 3, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_2_3(<8 x i16> %a) {
 ; CHECK-LABEL: shuffle_vector_halfword_2_3:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis 3, 2, .LCPI18_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI18_0@toc@l
-; CHECK-NEXT:    lxv 35, 0(3)
-; CHECK-NEXT:    vperm 2, 2, 2, 3
+; CHECK-NEXT:    lxv 0, 0(3)
+; CHECK-NEXT:    xxperm 34, 34, 0
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_halfword_2_3:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    vinserth 2, 2, 4
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 3, i32 3, i32 4, i32 5, i32 6, i32 7>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_3_4(<8 x i16> %a) {
 ; CHECK-LABEL: shuffle_vector_halfword_3_4:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vinserth 2, 2, 8
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_halfword_3_4:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    addis 3, 2, .LCPI19_0@toc@ha
 ; CHECK-BE-NEXT:    addi 3, 3, .LCPI19_0@toc@l
-; CHECK-BE-NEXT:    lxv 35, 0(3)
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
+; CHECK-BE-NEXT:    lxv 0, 0(3)
+; CHECK-BE-NEXT:    xxperm 34, 34, 0
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 4, i32 4, i32 5, i32 6, i32 7>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_4_3(<8 x i16> %a) {
 ; CHECK-LABEL: shuffle_vector_halfword_4_3:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis 3, 2, .LCPI20_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI20_0@toc@l
-; CHECK-NEXT:    lxv 35, 0(3)
-; CHECK-NEXT:    vperm 2, 2, 2, 3
+; CHECK-NEXT:    lxv 0, 0(3)
+; CHECK-NEXT:    xxperm 34, 34, 0
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_halfword_4_3:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    vinserth 2, 2, 8
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 3, i32 5, i32 6, i32 7>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_5_3(<8 x i16> %a) {
 ; CHECK-LABEL: shuffle_vector_halfword_5_3:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis 3, 2, .LCPI21_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI21_0@toc@l
-; CHECK-NEXT:    lxv 35, 0(3)
-; CHECK-NEXT:    vperm 2, 2, 2, 3
+; CHECK-NEXT:    lxv 0, 0(3)
+; CHECK-NEXT:    xxperm 34, 34, 0
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_halfword_5_3:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    vinserth 2, 2, 10
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 3, i32 6, i32 7>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_6_4(<8 x i16> %a) {
 ; CHECK-LABEL: shuffle_vector_halfword_6_4:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vinserth 2, 2, 2
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_halfword_6_4:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    addis 3, 2, .LCPI22_0@toc@ha
 ; CHECK-BE-NEXT:    addi 3, 3, .LCPI22_0@toc@l
-; CHECK-BE-NEXT:    lxv 35, 0(3)
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
+; CHECK-BE-NEXT:    lxv 0, 0(3)
+; CHECK-BE-NEXT:    xxperm 34, 34, 0
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 4, i32 7>
   ret <8 x i16> %vecins
 }
 
 define <8 x i16> @shuffle_vector_halfword_7_4(<8 x i16> %a) {
 ; CHECK-LABEL: shuffle_vector_halfword_7_4:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vinserth 2, 2, 0
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_halfword_7_4:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    addis 3, 2, .LCPI23_0@toc@ha
 ; CHECK-BE-NEXT:    addi 3, 3, .LCPI23_0@toc@l
-; CHECK-BE-NEXT:    lxv 35, 0(3)
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
+; CHECK-BE-NEXT:    lxv 0, 0(3)
+; CHECK-BE-NEXT:    xxperm 34, 34, 0
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 4>
   ret <8 x i16> %vecins
 }
 
 ; The following testcases take one byte element from the second vector and
 ; inserts it at various locations in the first vector

 ; The following testcases use the same vector in both arguments of the
 ; shufflevector.  If byte element 7 in BE mode(or 8 in LE mode) is the one
 ; we're attempting to insert, then we can use the vector insert instruction
 define <16 x i8> @shuffle_vector_byte_0_7(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_0_7:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis 3, 2, .LCPI56_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI56_0@toc@l
-; CHECK-NEXT:    lxv 35, 0(3)
-; CHECK-NEXT:    vperm 2, 2, 2, 3
+; CHECK-NEXT:    lxv 0, 0(3)
+; CHECK-NEXT:    xxperm 34, 34, 0
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_0_7:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    vinsertb 2, 2, 0
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 7, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_1_8(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_1_8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vinsertb 2, 2, 14
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_1_8:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    addis 3, 2, .LCPI57_0@toc@ha
 ; CHECK-BE-NEXT:    addi 3, 3, .LCPI57_0@toc@l
-; CHECK-BE-NEXT:    lxv 35, 0(3)
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
+; CHECK-BE-NEXT:    lxv 0, 0(3)
+; CHECK-BE-NEXT:    xxperm 34, 34, 0
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 8, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_2_8(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_2_8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vinsertb 2, 2, 13
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_2_8:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    addis 3, 2, .LCPI58_0@toc@ha
 ; CHECK-BE-NEXT:    addi 3, 3, .LCPI58_0@toc@l
-; CHECK-BE-NEXT:    lxv 35, 0(3)
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
+; CHECK-BE-NEXT:    lxv 0, 0(3)
+; CHECK-BE-NEXT:    xxperm 34, 34, 0
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 8, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_3_7(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_3_7:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis 3, 2, .LCPI59_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI59_0@toc@l
-; CHECK-NEXT:    lxv 35, 0(3)
-; CHECK-NEXT:    vperm 2, 2, 2, 3
+; CHECK-NEXT:    lxv 0, 0(3)
+; CHECK-NEXT:    xxperm 34, 34, 0
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_3_7:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    vinsertb 2, 2, 3
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 7, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_4_7(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_4_7:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis 3, 2, .LCPI60_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI60_0@toc@l
-; CHECK-NEXT:    lxv 35, 0(3)
-; CHECK-NEXT:    vperm 2, 2, 2, 3
+; CHECK-NEXT:    lxv 0, 0(3)
+; CHECK-NEXT:    xxperm 34, 34, 0
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_4_7:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    vinsertb 2, 2, 4
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 7, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_5_8(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_5_8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vinsertb 2, 2, 10
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_5_8:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    addis 3, 2, .LCPI61_0@toc@ha
 ; CHECK-BE-NEXT:    addi 3, 3, .LCPI61_0@toc@l
-; CHECK-BE-NEXT:    lxv 35, 0(3)
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
+; CHECK-BE-NEXT:    lxv 0, 0(3)
+; CHECK-BE-NEXT:    xxperm 34, 34, 0
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 8, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_6_8(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_6_8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vinsertb 2, 2, 9
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_6_8:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    addis 3, 2, .LCPI62_0@toc@ha
 ; CHECK-BE-NEXT:    addi 3, 3, .LCPI62_0@toc@l
-; CHECK-BE-NEXT:    lxv 35, 0(3)
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
+; CHECK-BE-NEXT:    lxv 0, 0(3)
+; CHECK-BE-NEXT:    xxperm 34, 34, 0
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 8, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_7_8(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_7_8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vinsertb 2, 2, 8
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_7_8:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    addis 3, 2, .LCPI63_0@toc@ha
 ; CHECK-BE-NEXT:    addi 3, 3, .LCPI63_0@toc@l
-; CHECK-BE-NEXT:    lxv 35, 0(3)
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
+; CHECK-BE-NEXT:    lxv 0, 0(3)
+; CHECK-BE-NEXT:    xxperm 34, 34, 0
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 8, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_8_7(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_8_7:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis 3, 2, .LCPI64_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI64_0@toc@l
-; CHECK-NEXT:    lxv 35, 0(3)
-; CHECK-NEXT:    vperm 2, 2, 2, 3
+; CHECK-NEXT:    lxv 0, 0(3)
+; CHECK-NEXT:    xxperm 34, 34, 0
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_8_7:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    vinsertb 2, 2, 8
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 7, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_9_7(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_9_7:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis 3, 2, .LCPI65_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI65_0@toc@l
-; CHECK-NEXT:    lxv 35, 0(3)
-; CHECK-NEXT:    vperm 2, 2, 2, 3
+; CHECK-NEXT:    lxv 0, 0(3)
+; CHECK-NEXT:    xxperm 34, 34, 0
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_9_7:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    vinsertb 2, 2, 9
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 7, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_10_7(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_10_7:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis 3, 2, .LCPI66_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI66_0@toc@l
-; CHECK-NEXT:    lxv 35, 0(3)
-; CHECK-NEXT:    vperm 2, 2, 2, 3
+; CHECK-NEXT:    lxv 0, 0(3)
+; CHECK-NEXT:    xxperm 34, 34, 0
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_10_7:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    vinsertb 2, 2, 10
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 7, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_11_8(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_11_8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vinsertb 2, 2, 4
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_11_8:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    addis 3, 2, .LCPI67_0@toc@ha
 ; CHECK-BE-NEXT:    addi 3, 3, .LCPI67_0@toc@l
-; CHECK-BE-NEXT:    lxv 35, 0(3)
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
+; CHECK-BE-NEXT:    lxv 0, 0(3)
+; CHECK-BE-NEXT:    xxperm 34, 34, 0
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 8, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_12_8(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_12_8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vinsertb 2, 2, 3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_12_8:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    addis 3, 2, .LCPI68_0@toc@ha
 ; CHECK-BE-NEXT:    addi 3, 3, .LCPI68_0@toc@l
-; CHECK-BE-NEXT:    lxv 35, 0(3)
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
+; CHECK-BE-NEXT:    lxv 0, 0(3)
+; CHECK-BE-NEXT:    xxperm 34, 34, 0
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 8, i32 13, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_13_7(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_13_7:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis 3, 2, .LCPI69_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI69_0@toc@l
-; CHECK-NEXT:    lxv 35, 0(3)
-; CHECK-NEXT:    vperm 2, 2, 2, 3
+; CHECK-NEXT:    lxv 0, 0(3)
+; CHECK-NEXT:    xxperm 34, 34, 0
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_13_7:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    vinsertb 2, 2, 13
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 7, i32 14, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_14_7(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_14_7:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis 3, 2, .LCPI70_0@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .LCPI70_0@toc@l
-; CHECK-NEXT:    lxv 35, 0(3)
-; CHECK-NEXT:    vperm 2, 2, 2, 3
+; CHECK-NEXT:    lxv 0, 0(3)
+; CHECK-NEXT:    xxperm 34, 34, 0
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_14_7:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    vinsertb 2, 2, 14
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 7, i32 15>
   ret <16 x i8> %vecins
 }
 
 define <16 x i8> @shuffle_vector_byte_15_8(<16 x i8> %a) {
 ; CHECK-LABEL: shuffle_vector_byte_15_8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vinsertb 2, 2, 0
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: shuffle_vector_byte_15_8:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    addis 3, 2, .LCPI71_0@toc@ha
 ; CHECK-BE-NEXT:    addi 3, 3, .LCPI71_0@toc@l
-; CHECK-BE-NEXT:    lxv 35, 0(3)
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
+; CHECK-BE-NEXT:    lxv 0, 0(3)
+; CHECK-BE-NEXT:    xxperm 34, 34, 0
 ; CHECK-BE-NEXT:    blr
 entry:
   %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 8>
   ret <16 x i8> %vecins
 }
 
 ; The following tests try to insert one halfword element into the vector.  We
 ; should always be using the 'vinserth' instruction.

llvm/test/CodeGen/PowerPC/pre-inc-disable.ll

 ; RUN: llc -mcpu=pwr9 -O3 -verify-machineinstrs -ppc-vsr-nums-as-vr \
 ; RUN:     -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:     < %s | FileCheck %s
 
 ; RUN: llc -mcpu=pwr9 -O3 -verify-machineinstrs -ppc-vsr-nums-as-vr \
 ; RUN:     -mtriple=powerpc64-unknown-linux-gnu \
 ; RUN:     < %s | FileCheck %s --check-prefix=P9BE
 
 ; RUN: llc -mcpu=pwr9 -O3 -verify-machineinstrs -ppc-vsr-nums-as-vr \
 ; RUN:     -mtriple=powerpc64-ibm-aix-xcoff -vec-extabi \
 ; RUN:     < %s | FileCheck %s --check-prefix=P9BE
 
 define void @test64(i8* nocapture readonly %pix2, i32 signext %i_pix2) {
 ; CHECK-LABEL: test64:
 ; CHECK-NOT: ldux
 ; CHECK-NOT: mtvsrd
-; CHECK: lxsdx [[REG:[0-9]+]]
-; CHECK: vperm {{[0-9]+}}, [[REG]]
+; CHECK: lxsd [[REG:[0-9]+]]
+; CHECK: xxperm {{[0-9]+}}, [[REG]]
 ; P9BE-LABEL: test64:
 ; P9BE-NOT: ldux
 ; P9BE-NOT: mtvsrd
 ; P9BE: lxsdx [[REG:[0-9]+]]
-; P9BE: vperm {{[0-9]+}}, {{[0-9]+}}, [[REG]]
+; P9BE: xxperm [[REG]], {{[0-9]+}}, {{[0-9]+}}
 entry:
   %idx.ext63 = sext i32 %i_pix2 to i64
   %add.ptr64 = getelementptr inbounds i8, i8* %pix2, i64 %idx.ext63
   %arrayidx5.1 = getelementptr inbounds i8, i8* %add.ptr64, i64 4
   %0 = bitcast i8* %add.ptr64 to <4 x i16>*
   %1 = load <4 x i16>, <4 x i16>* %0, align 1
   %reorder_shuffle117 = shufflevector <4 x i16> %1, <4 x i16> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
   %2 = zext <4 x i16> %reorder_shuffle117 to <4 x i32>
entry:
   store <4 x i32> %13, <4 x i32>* undef, align 16
   ret void
 }
 
 define void @test32(i8* nocapture readonly %pix2, i32 signext %i_pix2) {
 ; CHECK-LABEL: test32:
 ; CHECK-NOT: lwzux
 ; CHECK-NOT: mtvsrwz
-; CHECK: lxsiwzx [[REG:[0-9]+]]
-; CHECK: vperm {{[0-9]+}}, [[REG]]
+; CHECK: lfiwzx [[REG:[0-9]+]]
+; CHECK: xxperm {{[0-9]+}}, [[REG]]
 ; P9BE-LABEL: test32:
 ; P9BE-NOT: lwzux
 ; P9BE-NOT: mtvsrwz
 ; P9BE: lxsiwzx [[REG:[0-9]+]]
 ; P9BE: vperm {{[0-9]+}}, {{[0-9]+}}, [[REG]]
 entry:
   %idx.ext63 = sext i32 %i_pix2 to i64
   %add.ptr64 = getelementptr inbounds i8, i8* %pix2, i64 %idx.ext63

llvm/test/CodeGen/PowerPC/srem-vector-lkk.ll

 ; P9BE-NEXT:    mulhw r4, r3, r4
 ; P9BE-NEXT:    add r4, r4, r3
 ; P9BE-NEXT:    srwi r5, r4, 31
 ; P9BE-NEXT:    srawi r4, r4, 6
 ; P9BE-NEXT:    add r4, r4, r5
 ; P9BE-NEXT:    mulli r4, r4, 95
 ; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    lis r4, -16728
-; P9BE-NEXT:    mtvsrwz v4, r3
+; P9BE-NEXT:    mtfprwz f0, r3
 ; P9BE-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
 ; P9BE-NEXT:    ori r4, r4, 63249
 ; P9BE-NEXT:    addi r3, r3, .LCPI0_0@toc@l
-; P9BE-NEXT:    lxv v5, 0(r3)
+; P9BE-NEXT:    lxv vs1, 0(r3)
 ; P9BE-NEXT:    li r3, 6
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r3, r3
-; P9BE-NEXT:    vperm v3, v4, v3, v5
+; P9BE-NEXT:    xxperm v3, vs0, vs1
 ; P9BE-NEXT:    mulhw r4, r3, r4
 ; P9BE-NEXT:    srwi r5, r4, 31
 ; P9BE-NEXT:    srawi r4, r4, 8
 ; P9BE-NEXT:    add r4, r4, r5
 ; P9BE-NEXT:    mulli r4, r4, -1003
 ; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    lis r4, 21399
 ; P9BE-NEXT:    mtvsrwz v4, r3
 ; P9BE-NEXT:    li r3, 4
 ; P9BE-NEXT:    ori r4, r4, 33437
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r3, r3
 ; P9BE-NEXT:    mulhw r4, r3, r4
 ; P9BE-NEXT:    srwi r5, r4, 31
 ; P9BE-NEXT:    srawi r4, r4, 5
 ; P9BE-NEXT:    add r4, r4, r5
 ; P9BE-NEXT:    mulli r4, r4, 98
 ; P9BE-NEXT:    sub r3, r3, r4
-; P9BE-NEXT:    mtvsrwz v2, r3
-; P9BE-NEXT:    vperm v2, v2, v4, v5
-; P9BE-NEXT:    vmrghw v2, v3, v2
+; P9BE-NEXT:    mtfprwz f0, r3
+; P9BE-NEXT:    xxperm v4, vs0, vs1
+; P9BE-NEXT:    vmrghw v2, v3, v4
 ; P9BE-NEXT:    blr
 ;
 ; P8LE-LABEL: fold_srem_vec_1:
 ; P8LE:       # %bb.0:
 ; P8LE-NEXT:    xxswapd vs0, v2
 ; P8LE-NEXT:    lis r3, 21399
 ; P8LE-NEXT:    lis r8, -16728
 ; P8LE-NEXT:    lis r9, -21386

 ; P9BE-NEXT:    extsh r3, r3
 ; P9BE-NEXT:    mulhw r5, r3, r4
 ; P9BE-NEXT:    add r5, r5, r3
 ; P9BE-NEXT:    srwi r6, r5, 31
 ; P9BE-NEXT:    srawi r5, r5, 6
 ; P9BE-NEXT:    add r5, r5, r6
 ; P9BE-NEXT:    mulli r5, r5, 95
 ; P9BE-NEXT:    sub r3, r3, r5
-; P9BE-NEXT:    mtvsrwz v4, r3
+; P9BE-NEXT:    mtfprwz f0, r3
 ; P9BE-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
 ; P9BE-NEXT:    addi r3, r3, .LCPI1_0@toc@l
-; P9BE-NEXT:    lxv v5, 0(r3)
+; P9BE-NEXT:    lxv vs1, 0(r3)
 ; P9BE-NEXT:    li r3, 2
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r3, r3
-; P9BE-NEXT:    vperm v3, v4, v3, v5
+; P9BE-NEXT:    xxperm v3, vs0, vs1
 ; P9BE-NEXT:    mulhw r5, r3, r4
 ; P9BE-NEXT:    add r5, r5, r3
 ; P9BE-NEXT:    srwi r6, r5, 31
 ; P9BE-NEXT:    srawi r5, r5, 6
 ; P9BE-NEXT:    add r5, r5, r6
 ; P9BE-NEXT:    mulli r5, r5, 95
 ; P9BE-NEXT:    sub r3, r3, r5
 ; P9BE-NEXT:    mtvsrwz v4, r3
 ; P9BE-NEXT:    li r3, 0
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r3, r3
 ; P9BE-NEXT:    mulhw r4, r3, r4
 ; P9BE-NEXT:    add r4, r4, r3
 ; P9BE-NEXT:    srwi r5, r4, 31
 ; P9BE-NEXT:    srawi r4, r4, 6
 ; P9BE-NEXT:    add r4, r4, r5
 ; P9BE-NEXT:    mulli r4, r4, 95
 ; P9BE-NEXT:    sub r3, r3, r4
-; P9BE-NEXT:    mtvsrwz v2, r3
-; P9BE-NEXT:    vperm v2, v2, v4, v5
-; P9BE-NEXT:    vmrghw v2, v2, v3
+; P9BE-NEXT:    mtfprwz f0, r3
+; P9BE-NEXT:    xxperm v4, vs0, vs1
+; P9BE-NEXT:    vmrghw v2, v4, v3
 ; P9BE-NEXT:    blr
 ;
 ; P8LE-LABEL: fold_srem_vec_2:
 ; P8LE:       # %bb.0:
 ; P8LE-NEXT:    xxswapd vs0, v2
 ; P8LE-NEXT:    lis r3, -21386
 ; P8LE-NEXT:    ori r3, r3, 37253
 ; P8LE-NEXT:    mffprd r4, f0

 ; P9BE-NEXT:    extsh r6, r3
 ; P9BE-NEXT:    mulhw r7, r6, r5
 ; P9BE-NEXT:    add r6, r7, r6
 ; P9BE-NEXT:    srwi r7, r6, 31
 ; P9BE-NEXT:    srawi r6, r6, 6
 ; P9BE-NEXT:    add r6, r6, r7
 ; P9BE-NEXT:    mulli r7, r6, 95
 ; P9BE-NEXT:    sub r3, r3, r7
-; P9BE-NEXT:    mtvsrwz v4, r3
+; P9BE-NEXT:    mtfprwz f0, r3
 ; P9BE-NEXT:    addis r3, r2, .LCPI2_0@toc@ha
 ; P9BE-NEXT:    addi r3, r3, .LCPI2_0@toc@l
-; P9BE-NEXT:    lxv v5, 0(r3)
+; P9BE-NEXT:    lxv vs1, 0(r3)
 ; P9BE-NEXT:    li r3, 2
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r7, r3
-; P9BE-NEXT:    vperm v3, v4, v3, v5
+; P9BE-NEXT:    xxperm v3, vs0, vs1
 ; P9BE-NEXT:    mulhw r8, r7, r5
 ; P9BE-NEXT:    add r7, r8, r7
 ; P9BE-NEXT:    srwi r8, r7, 31
 ; P9BE-NEXT:    srawi r7, r7, 6
 ; P9BE-NEXT:    add r7, r7, r8
 ; P9BE-NEXT:    mulli r8, r7, 95
 ; P9BE-NEXT:    sub r3, r3, r8
 ; P9BE-NEXT:    mtvsrwz v4, r3
 ; P9BE-NEXT:    li r3, 0
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r3, r3
 ; P9BE-NEXT:    mulhw r5, r3, r5
 ; P9BE-NEXT:    add r5, r5, r3
 ; P9BE-NEXT:    srwi r8, r5, 31
 ; P9BE-NEXT:    srawi r5, r5, 6
 ; P9BE-NEXT:    add r5, r5, r8
 ; P9BE-NEXT:    mulli r8, r5, 95
-; P9BE-NEXT:    mtvsrwz v0, r5
 ; P9BE-NEXT:    sub r3, r3, r8
-; P9BE-NEXT:    mtvsrwz v2, r3
-; P9BE-NEXT:    vperm v2, v2, v4, v5
-; P9BE-NEXT:    mtvsrwz v4, r6
-; P9BE-NEXT:    vmrghw v2, v2, v3
+; P9BE-NEXT:    mtfprwz f0, r3
+; P9BE-NEXT:    xxperm v4, vs0, vs1
+; P9BE-NEXT:    mtfprwz f0, r6
+; P9BE-NEXT:    vmrghw v2, v4, v3
 ; P9BE-NEXT:    mtvsrwz v3, r4
-; P9BE-NEXT:    vperm v3, v4, v3, v5
 ; P9BE-NEXT:    mtvsrwz v4, r7
-; P9BE-NEXT:    vperm v4, v0, v4, v5
+; P9BE-NEXT:    xxperm v3, vs0, vs1
+; P9BE-NEXT:    mtfprwz f0, r5
+; P9BE-NEXT:    xxperm v4, vs0, vs1
 ; P9BE-NEXT:    vmrghw v3, v4, v3
 ; P9BE-NEXT:    vadduhm v2, v2, v3
 ; P9BE-NEXT:    blr
 ;
 ; P8LE-LABEL: combine_srem_sdiv:
 ; P8LE:       # %bb.0:
 ; P8LE-NEXT:    xxswapd vs0, v2
 ; P8LE-NEXT:    lis r3, -21386

 ; P9BE-NEXT:    li r3, 0
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r3, r3
 ; P9BE-NEXT:    srawi r4, r3, 6
 ; P9BE-NEXT:    addze r4, r4
 ; P9BE-NEXT:    slwi r4, r4, 6
 ; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    lis r4, -21386
-; P9BE-NEXT:    mtvsrwz v4, r3
+; P9BE-NEXT:    mtfprwz f0, r3
 ; P9BE-NEXT:    addis r3, r2, .LCPI3_0@toc@ha
 ; P9BE-NEXT:    ori r4, r4, 37253
 ; P9BE-NEXT:    addi r3, r3, .LCPI3_0@toc@l
-; P9BE-NEXT:    lxv v5, 0(r3)
+; P9BE-NEXT:    lxv vs1, 0(r3)
 ; P9BE-NEXT:    li r3, 6
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r3, r3
-; P9BE-NEXT:    vperm v3, v4, v3, v5
+; P9BE-NEXT:    xxperm v3, vs0, vs1
 ; P9BE-NEXT:    mulhw r4, r3, r4
 ; P9BE-NEXT:    add r4, r4, r3
 ; P9BE-NEXT:    srwi r5, r4, 31
 ; P9BE-NEXT:    srawi r4, r4, 6
 ; P9BE-NEXT:    add r4, r4, r5
 ; P9BE-NEXT:    mulli r4, r4, 95
 ; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    mtvsrwz v4, r3
 ; P9BE-NEXT:    li r3, 4
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r3, r3
 ; P9BE-NEXT:    srawi r4, r3, 3
 ; P9BE-NEXT:    addze r4, r4
 ; P9BE-NEXT:    slwi r4, r4, 3
 ; P9BE-NEXT:    sub r3, r3, r4
-; P9BE-NEXT:    mtvsrwz v2, r3
-; P9BE-NEXT:    vperm v2, v2, v4, v5
-; P9BE-NEXT:    vmrghw v2, v3, v2
+; P9BE-NEXT:    mtfprwz f0, r3
+; P9BE-NEXT:    xxperm v4, vs0, vs1
+; P9BE-NEXT:    vmrghw v2, v3, v4
 ; P9BE-NEXT:    blr
 ;
 ; P8LE-LABEL: dont_fold_srem_power_of_two:
 ; P8LE:       # %bb.0:
 ; P8LE-NEXT:    xxswapd vs0, v2
 ; P8LE-NEXT:    lis r3, -21386
 ; P8LE-NEXT:    ori r3, r3, 37253
 ; P8LE-NEXT:    mffprd r4, f0

 ; P9BE-NEXT:    mulhw r4, r3, r4
 ; P9BE-NEXT:    add r4, r4, r3
 ; P9BE-NEXT:    srwi r5, r4, 31
 ; P9BE-NEXT:    srawi r4, r4, 4
 ; P9BE-NEXT:    add r4, r4, r5
 ; P9BE-NEXT:    mulli r4, r4, 23
 ; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    lis r4, 24749
-; P9BE-NEXT:    mtvsrwz v3, r3
+; P9BE-NEXT:    mtfprwz f0, r3
 ; P9BE-NEXT:    li r3, 6
 ; P9BE-NEXT:    ori r4, r4, 47143
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r3, r3
 ; P9BE-NEXT:    mulhw r4, r3, r4
 ; P9BE-NEXT:    srwi r5, r4, 31
 ; P9BE-NEXT:    srawi r4, r4, 11
 ; P9BE-NEXT:    add r4, r4, r5
 ; P9BE-NEXT:    mulli r4, r4, 5423
 ; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    lis r4, -14230
-; P9BE-NEXT:    mtvsrwz v4, r3
+; P9BE-NEXT:    mtvsrwz v3, r3
 ; P9BE-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
 ; P9BE-NEXT:    ori r4, r4, 30865
 ; P9BE-NEXT:    addi r3, r3, .LCPI4_0@toc@l
-; P9BE-NEXT:    lxv v5, 0(r3)
+; P9BE-NEXT:    lxv vs1, 0(r3)
 ; P9BE-NEXT:    li r3, 2
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r3, r3
-; P9BE-NEXT:    vperm v3, v3, v4, v5
+; P9BE-NEXT:    xxperm v3, vs0, vs1
 ; P9BE-NEXT:    mulhw r4, r3, r4
 ; P9BE-NEXT:    add r4, r4, r3
 ; P9BE-NEXT:    srwi r5, r4, 31
 ; P9BE-NEXT:    srawi r4, r4, 9
 ; P9BE-NEXT:    add r4, r4, r5
 ; P9BE-NEXT:    mulli r4, r4, 654
 ; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    mtvsrwz v2, r3
 ; P9BE-NEXT:    li r3, 0
-; P9BE-NEXT:    mtvsrwz v4, r3
-; P9BE-NEXT:    vperm v2, v4, v2, v5
+; P9BE-NEXT:    mtfprwz f0, r3
+; P9BE-NEXT:    xxperm v2, vs0, vs1
 ; P9BE-NEXT:    vmrghw v2, v2, v3
 ; P9BE-NEXT:    blr
 ;
 ; P8LE-LABEL: dont_fold_srem_one:
 ; P8LE:       # %bb.0:
 ; P8LE-NEXT:    xxswapd vs0, v2
 ; P8LE-NEXT:    lis r5, 24749
 ; P8LE-NEXT:    lis r6, -19946

 ; P9BE-NEXT:    mulhw r4, r3, r4
 ; P9BE-NEXT:    add r4, r4, r3
 ; P9BE-NEXT:    srwi r5, r4, 31
 ; P9BE-NEXT:    srawi r4, r4, 4
 ; P9BE-NEXT:    add r4, r4, r5
 ; P9BE-NEXT:    mulli r4, r4, 23
 ; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    lis r4, 24749
-; P9BE-NEXT:    mtvsrwz v3, r3
+; P9BE-NEXT:    mtfprwz f0, r3
 ; P9BE-NEXT:    li r3, 6
 ; P9BE-NEXT:    ori r4, r4, 47143
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r3, r3
 ; P9BE-NEXT:    mulhw r4, r3, r4
 ; P9BE-NEXT:    srwi r5, r4, 31
 ; P9BE-NEXT:    srawi r4, r4, 11
 ; P9BE-NEXT:    add r4, r4, r5
 ; P9BE-NEXT:    mulli r4, r4, 5423
 ; P9BE-NEXT:    sub r3, r3, r4
-; P9BE-NEXT:    mtvsrwz v4, r3
+; P9BE-NEXT:    mtvsrwz v3, r3
 ; P9BE-NEXT:    addis r3, r2, .LCPI5_0@toc@ha
 ; P9BE-NEXT:    addi r3, r3, .LCPI5_0@toc@l
-; P9BE-NEXT:    lxv v5, 0(r3)
+; P9BE-NEXT:    lxv vs1, 0(r3)
 ; P9BE-NEXT:    li r3, 2
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r3, r3
-; P9BE-NEXT:    vperm v3, v3, v4, v5
+; P9BE-NEXT:    xxperm v3, vs0, vs1
 ; P9BE-NEXT:    srawi r4, r3, 15
 ; P9BE-NEXT:    addze r4, r4
 ; P9BE-NEXT:    slwi r4, r4, 15
 ; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    mtvsrwz v2, r3
 ; P9BE-NEXT:    li r3, 0
-; P9BE-NEXT:    mtvsrwz v4, r3
-; P9BE-NEXT:    vperm v2, v4, v2, v5
+; P9BE-NEXT:    mtfprwz f0, r3
+; P9BE-NEXT:    xxperm v2, vs0, vs1
 ; P9BE-NEXT:    vmrghw v2, v2, v3
 ; P9BE-NEXT:    blr
 ;
 ; P8LE-LABEL: dont_fold_urem_i16_smax:
 ; P8LE:       # %bb.0:
 ; P8LE-NEXT:    xxswapd vs0, v2
 ; P8LE-NEXT:    lis r4, 24749
 ; P8LE-NEXT:    lis r5, -19946

llvm/test/CodeGen/PowerPC/urem-vector-lkk.ll

 ; P9BE-NEXT:    li r3, 4
 ; P9BE-NEXT:    ori r4, r4, 33437
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    clrlwi r3, r3, 16
 ; P9BE-NEXT:    mulhwu r4, r3, r4
 ; P9BE-NEXT:    srwi r4, r4, 5
 ; P9BE-NEXT:    mulli r4, r4, 98
 ; P9BE-NEXT:    sub r3, r3, r4
-; P9BE-NEXT:    mtvsrwz v4, r3
+; P9BE-NEXT:    mtfprwz f0, r3
 ; P9BE-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
 ; P9BE-NEXT:    addi r3, r3, .LCPI0_0@toc@l
-; P9BE-NEXT:    lxv v5, 0(r3)
+; P9BE-NEXT:    lxv vs1, 0(r3)
 ; P9BE-NEXT:    li r3, 2
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    clrlwi r4, r3, 16
 ; P9BE-NEXT:    rlwinm r3, r3, 30, 18, 31
-; P9BE-NEXT:    vperm v3, v4, v3, v5
+; P9BE-NEXT:    xxperm v3, vs0, vs1
 ; P9BE-NEXT:    mulhwu r3, r3, r5
 ; P9BE-NEXT:    srwi r3, r3, 2
 ; P9BE-NEXT:    mulli r3, r3, 124
 ; P9BE-NEXT:    sub r3, r4, r3
 ; P9BE-NEXT:    lis r4, 22765
 ; P9BE-NEXT:    mtvsrwz v4, r3
 ; P9BE-NEXT:    li r3, 0
 ; P9BE-NEXT:    ori r4, r4, 8969
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    clrlwi r3, r3, 16
 ; P9BE-NEXT:    mulhwu r4, r3, r4
 ; P9BE-NEXT:    sub r5, r3, r4
 ; P9BE-NEXT:    srwi r5, r5, 1
 ; P9BE-NEXT:    add r4, r5, r4
 ; P9BE-NEXT:    srwi r4, r4, 6
 ; P9BE-NEXT:    mulli r4, r4, 95
 ; P9BE-NEXT:    sub r3, r3, r4
-; P9BE-NEXT:    mtvsrwz v2, r3
-; P9BE-NEXT:    vperm v2, v2, v4, v5
-; P9BE-NEXT:    vmrghw v2, v2, v3
+; P9BE-NEXT:    mtfprwz f0, r3
+; P9BE-NEXT:    xxperm v4, vs0, vs1
+; P9BE-NEXT:    vmrghw v2, v4, v3
 ; P9BE-NEXT:    blr
 ;
 ; P8LE-LABEL: fold_urem_vec_1:
 ; P8LE:       # %bb.0:
 ; P8LE-NEXT:    xxswapd vs0, v2
 ; P8LE-NEXT:    lis r3, 22765
 ; P8LE-NEXT:    lis r7, 21399
 ; P8LE-NEXT:    lis r9, 16727

 ; P9BE-NEXT:    clrlwi r3, r3, 16
 ; P9BE-NEXT:    mulhwu r5, r3, r4
 ; P9BE-NEXT:    sub r6, r3, r5
 ; P9BE-NEXT:    srwi r6, r6, 1
 ; P9BE-NEXT:    add r5, r6, r5
 ; P9BE-NEXT:    srwi r5, r5, 6
 ; P9BE-NEXT:    mulli r5, r5, 95
 ; P9BE-NEXT:    sub r3, r3, r5
-; P9BE-NEXT:    mtvsrwz v4, r3
+; P9BE-NEXT:    mtfprwz f0, r3
 ; P9BE-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
 ; P9BE-NEXT:    addi r3, r3, .LCPI1_0@toc@l
-; P9BE-NEXT:    lxv v5, 0(r3)
+; P9BE-NEXT:    lxv vs1, 0(r3)
 ; P9BE-NEXT:    li r3, 2
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    clrlwi r3, r3, 16
-; P9BE-NEXT:    vperm v3, v4, v3, v5
+; P9BE-NEXT:    xxperm v3, vs0, vs1
 ; P9BE-NEXT:    mulhwu r5, r3, r4
 ; P9BE-NEXT:    sub r6, r3, r5
 ; P9BE-NEXT:    srwi r6, r6, 1
 ; P9BE-NEXT:    add r5, r6, r5
 ; P9BE-NEXT:    srwi r5, r5, 6
 ; P9BE-NEXT:    mulli r5, r5, 95
 ; P9BE-NEXT:    sub r3, r3, r5
 ; P9BE-NEXT:    mtvsrwz v4, r3
 ; P9BE-NEXT:    li r3, 0
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    clrlwi r3, r3, 16
 ; P9BE-NEXT:    mulhwu r4, r3, r4
 ; P9BE-NEXT:    sub r5, r3, r4
 ; P9BE-NEXT:    srwi r5, r5, 1
 ; P9BE-NEXT:    add r4, r5, r4
 ; P9BE-NEXT:    srwi r4, r4, 6
 ; P9BE-NEXT:    mulli r4, r4, 95
 ; P9BE-NEXT:    sub r3, r3, r4
-; P9BE-NEXT:    mtvsrwz v2, r3
-; P9BE-NEXT:    vperm v2, v2, v4, v5
-; P9BE-NEXT:    vmrghw v2, v2, v3
+; P9BE-NEXT:    mtfprwz f0, r3
+; P9BE-NEXT:    xxperm v4, vs0, vs1
+; P9BE-NEXT:    vmrghw v2, v4, v3
 ; P9BE-NEXT:    blr
 ;
 ; P8LE-LABEL: fold_urem_vec_2:
 ; P8LE:       # %bb.0:
 ; P8LE-NEXT:    xxswapd vs0, v2
 ; P8LE-NEXT:    lis r3, 22765
 ; P8LE-NEXT:    ori r3, r3, 8969
 ; P8LE-NEXT:    mffprd r4, f0

 ; P9BE-NEXT:    clrlwi r6, r3, 16
 ; P9BE-NEXT:    mulhwu r7, r6, r5
 ; P9BE-NEXT:    sub r6, r6, r7
 ; P9BE-NEXT:    srwi r6, r6, 1
 ; P9BE-NEXT:    add r6, r6, r7
 ; P9BE-NEXT:    srwi r6, r6, 6
 ; P9BE-NEXT:    mulli r7, r6, 95
 ; P9BE-NEXT:    sub r3, r3, r7
-; P9BE-NEXT:    mtvsrwz v4, r3
+; P9BE-NEXT:    mtfprwz f0, r3
 ; P9BE-NEXT:    addis r3, r2, .LCPI2_0@toc@ha
 ; P9BE-NEXT:    addi r3, r3, .LCPI2_0@toc@l
-; P9BE-NEXT:    lxv v5, 0(r3)
+; P9BE-NEXT:    lxv vs1, 0(r3)
 ; P9BE-NEXT:    li r3, 2
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    clrlwi r7, r3, 16
-; P9BE-NEXT:    vperm v3, v4, v3, v5
+; P9BE-NEXT:    xxperm v3, vs0, vs1
 ; P9BE-NEXT:    mulhwu r8, r7, r5
 ; P9BE-NEXT:    sub r7, r7, r8
 ; P9BE-NEXT:    srwi r7, r7, 1
 ; P9BE-NEXT:    add r7, r7, r8
 ; P9BE-NEXT:    srwi r7, r7, 6
 ; P9BE-NEXT:    mulli r8, r7, 95
 ; P9BE-NEXT:    sub r3, r3, r8
 ; P9BE-NEXT:    mtvsrwz v4, r3
 ; P9BE-NEXT:    li r3, 0
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    clrlwi r3, r3, 16
 ; P9BE-NEXT:    mulhwu r5, r3, r5
 ; P9BE-NEXT:    sub r8, r3, r5
 ; P9BE-NEXT:    srwi r8, r8, 1
 ; P9BE-NEXT:    add r5, r8, r5
 ; P9BE-NEXT:    srwi r5, r5, 6
 ; P9BE-NEXT:    mulli r8, r5, 95
-; P9BE-NEXT:    mtvsrwz v0, r5
 ; P9BE-NEXT:    sub r3, r3, r8
-; P9BE-NEXT:    mtvsrwz v2, r3
-; P9BE-NEXT:    vperm v2, v2, v4, v5
-; P9BE-NEXT:    mtvsrwz v4, r6
-; P9BE-NEXT:    vmrghw v2, v2, v3
+; P9BE-NEXT:    mtfprwz f0, r3
+; P9BE-NEXT:    xxperm v4, vs0, vs1
+; P9BE-NEXT:    mtfprwz f0, r6
+; P9BE-NEXT:    vmrghw v2, v4, v3
 ; P9BE-NEXT:    mtvsrwz v3, r4
-; P9BE-NEXT:    vperm v3, v4, v3, v5
 ; P9BE-NEXT:    mtvsrwz v4, r7
-; P9BE-NEXT:    vperm v4, v0, v4, v5
+; P9BE-NEXT:    xxperm v3, vs0, vs1
+; P9BE-NEXT:    mtfprwz f0, r5
+; P9BE-NEXT:    xxperm v4, vs0, vs1
 ; P9BE-NEXT:    vmrghw v3, v4, v3
 ; P9BE-NEXT:    vadduhm v2, v2, v3
 ; P9BE-NEXT:    blr
 ;
 ; P8LE-LABEL: combine_urem_udiv:
 ; P8LE:       # %bb.0:
 ; P8LE-NEXT:    xxswapd vs0, v2
 ; P8LE-NEXT:    lis r3, 22765

 ; P9BE-NEXT:    lis r4, 22765
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    ori r4, r4, 8969
 ; P9BE-NEXT:    clrlwi r3, r3, 27
 ; P9BE-NEXT:    mtvsrwz v3, r3
 ; P9BE-NEXT:    li r3, 0
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    clrlwi r3, r3, 26
-; P9BE-NEXT:    mtvsrwz v4, r3
+; P9BE-NEXT:    mtfprwz f0, r3
 ; P9BE-NEXT:    addis r3, r2, .LCPI3_0@toc@ha
 ; P9BE-NEXT:    addi r3, r3, .LCPI3_0@toc@l
-; P9BE-NEXT:    lxv v5, 0(r3)
+; P9BE-NEXT:    lxv vs1, 0(r3)
 ; P9BE-NEXT:    li r3, 6
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    clrlwi r3, r3, 16
-; P9BE-NEXT:    vperm v3, v4, v3, v5
+; P9BE-NEXT:    xxperm v3, vs0, vs1
 ; P9BE-NEXT:    mulhwu r4, r3, r4
 ; P9BE-NEXT:    sub r5, r3, r4
 ; P9BE-NEXT:    srwi r5, r5, 1
 ; P9BE-NEXT:    add r4, r5, r4
 ; P9BE-NEXT:    srwi r4, r4, 6
 ; P9BE-NEXT:    mulli r4, r4, 95
 ; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    mtvsrwz v4, r3
 ; P9BE-NEXT:    li r3, 4
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    clrlwi r3, r3, 29
-; P9BE-NEXT:    mtvsrwz v2, r3
-; P9BE-NEXT:    vperm v2, v2, v4, v5
-; P9BE-NEXT:    vmrghw v2, v3, v2
+; P9BE-NEXT:    mtfprwz f0, r3
+; P9BE-NEXT:    xxperm v4, vs0, vs1
+; P9BE-NEXT:    vmrghw v2, v3, v4
 ; P9BE-NEXT:    blr
 ;
 ; P8LE-LABEL: dont_fold_urem_power_of_two:
 ; P8LE:       # %bb.0:
 ; P8LE-NEXT:    xxswapd vs0, v2
 ; P8LE-NEXT:    lis r3, 22765
 ; P8LE-NEXT:    ori r3, r3, 8969
 ; P8LE-NEXT:    mffprd r4, f0

 ; P9BE-NEXT:    li r3, 4
 ; P9BE-NEXT:    ori r4, r4, 17097
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    clrlwi r3, r3, 16
 ; P9BE-NEXT:    mulhwu r4, r3, r4
 ; P9BE-NEXT:    srwi r4, r4, 4
 ; P9BE-NEXT:    mulli r4, r4, 23
 ; P9BE-NEXT:    sub r3, r3, r4
-; P9BE-NEXT:    mtvsrwz v4, r3
+; P9BE-NEXT:    mtfprwz f0, r3
 ; P9BE-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
 ; P9BE-NEXT:    addi r3, r3, .LCPI4_0@toc@l
-; P9BE-NEXT:    lxv v5, 0(r3)
+; P9BE-NEXT:    lxv vs1, 0(r3)
 ; P9BE-NEXT:    li r3, 2
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    clrlwi r4, r3, 16
 ; P9BE-NEXT:    rlwinm r3, r3, 31, 17, 31
-; P9BE-NEXT:    vperm v3, v4, v3, v5
+; P9BE-NEXT:    xxperm v3, vs0, vs1
 ; P9BE-NEXT:    mulhwu r3, r3, r5
 ; P9BE-NEXT:    srwi r3, r3, 8
 ; P9BE-NEXT:    mulli r3, r3, 654
 ; P9BE-NEXT:    sub r3, r4, r3
 ; P9BE-NEXT:    mtvsrwz v2, r3
 ; P9BE-NEXT:    li r3, 0
-; P9BE-NEXT:    mtvsrwz v4, r3
-; P9BE-NEXT:    vperm v2, v4, v2, v5
+; P9BE-NEXT:    mtfprwz f0, r3
+; P9BE-NEXT:    xxperm v2, vs0, vs1
 ; P9BE-NEXT:    vmrghw v2, v2, v3
 ; P9BE-NEXT:    blr
 ;
 ; P8LE-LABEL: dont_fold_urem_one:
 ; P8LE:       # %bb.0:
 ; P8LE-NEXT:    xxswapd vs0, v2
 ; P8LE-NEXT:    lis r3, -14230
 ; P8LE-NEXT:    lis r7, -19946

llvm/test/CodeGen/PowerPC/vec-itofp.ll

 ; CHECK-P8-NEXT:    vperm v2, v4, v3, v2
 ; CHECK-P8-NEXT:    xvcvuxddp vs0, v2
 ; CHECK-P8-NEXT:    xxswapd vs0, vs0
 ; CHECK-P8-NEXT:    stxvd2x vs0, 0, r3
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test2:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    lxv v2, 0(r4)
+; CHECK-P9-NEXT:    lxv vs1, 0(r4)
 ; CHECK-P9-NEXT:    addis r4, r2, .LCPI2_0@toc@ha
-; CHECK-P9-NEXT:    xxlxor v4, v4, v4
+; CHECK-P9-NEXT:    xxlxor vs0, vs0, vs0
 ; CHECK-P9-NEXT:    addi r4, r4, .LCPI2_0@toc@l
-; CHECK-P9-NEXT:    lxv v3, 0(r4)
-; CHECK-P9-NEXT:    vperm v2, v4, v2, v3
-; CHECK-P9-NEXT:    xvcvuxddp vs0, v2
+; CHECK-P9-NEXT:    lxv vs2, 0(r4)
+; CHECK-P9-NEXT:    xxperm vs1, vs0, vs2
+; CHECK-P9-NEXT:    xvcvuxddp vs0, vs1
 ; CHECK-P9-NEXT:    stxv vs0, 0(r3)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv v2, 0(r4)
 ; CHECK-BE-NEXT:    addis r4, r2, .LCPI2_0@toc@ha
 ; CHECK-BE-NEXT:    xxlxor v4, v4, v4

 ; CHECK-P9-NEXT:    xvcvsxddp vs1, v2
 ; CHECK-P9-NEXT:    stxv vs1, 16(r3)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: stest4:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv v2, 0(r4)
 ; CHECK-BE-NEXT:    addis r4, r2, .LCPI4_0@toc@ha
-; CHECK-BE-NEXT:    xxlxor v3, v3, v3
+; CHECK-BE-NEXT:    xxlxor vs0, vs0, vs0
 ; CHECK-BE-NEXT:    addi r4, r4, .LCPI4_0@toc@l
-; CHECK-BE-NEXT:    lxv v4, 0(r4)
+; CHECK-BE-NEXT:    lxv vs1, 0(r4)
 ; CHECK-BE-NEXT:    addis r4, r2, .LCPI4_1@toc@ha
 ; CHECK-BE-NEXT:    addi r4, r4, .LCPI4_1@toc@l
-; CHECK-BE-NEXT:    vperm v3, v3, v2, v4
+; CHECK-BE-NEXT:    vmr v3, v2
+; CHECK-BE-NEXT:    xxperm v3, vs0, vs1
+; CHECK-BE-NEXT:    lxv vs1, 0(r4)
 ; CHECK-BE-NEXT:    vextsh2d v3, v3
+; CHECK-BE-NEXT:    xxperm v2, v2, vs1
 ; CHECK-BE-NEXT:    xvcvsxddp vs0, v3
-; CHECK-BE-NEXT:    lxv v3, 0(r4)
-; CHECK-BE-NEXT:    vperm v2, v2, v2, v3
-; CHECK-BE-NEXT:    stxv vs0, 16(r3)
 ; CHECK-BE-NEXT:    vextsh2d v2, v2
 ; CHECK-BE-NEXT:    xvcvsxddp vs1, v2
+; CHECK-BE-NEXT:    stxv vs0, 16(r3)
 ; CHECK-BE-NEXT:    stxv vs1, 0(r3)
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = load <4 x i16>, <4 x i16>* %SrcPtr, align 16
   %1 = sitofp <4 x i16> %0 to <4 x double>
   store <4 x double> %1, <4 x double>* %Sink, align 16
   ret void
 }

 ; CHECK-P8-NEXT:    stxvd2x vs0, 0, r3
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: stest2:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    lxv v2, 0(r4)
 ; CHECK-P9-NEXT:    addis r4, r2, .LCPI5_0@toc@ha
 ; CHECK-P9-NEXT:    addi r4, r4, .LCPI5_0@toc@l
-; CHECK-P9-NEXT:    lxv v3, 0(r4)
-; CHECK-P9-NEXT:    vperm v2, v2, v2, v3
+; CHECK-P9-NEXT:    lxv vs0, 0(r4)
+; CHECK-P9-NEXT:    xxperm v2, v2, vs0
 ; CHECK-P9-NEXT:    vextsh2d v2, v2
 ; CHECK-P9-NEXT:    xvcvsxddp vs0, v2
 ; CHECK-P9-NEXT:    stxv vs0, 0(r3)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: stest2:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv v2, 0(r4)
 ; CHECK-BE-NEXT:    addis r4, r2, .LCPI5_0@toc@ha
 ; CHECK-BE-NEXT:    addi r4, r4, .LCPI5_0@toc@l
-; CHECK-BE-NEXT:    lxv v3, 0(r4)
-; CHECK-BE-NEXT:    vperm v2, v2, v2, v3
+; CHECK-BE-NEXT:    lxv vs0, 0(r4)
+; CHECK-BE-NEXT:    xxperm v2, v2, vs0
 ; CHECK-BE-NEXT:    vextsh2d v2, v2
 ; CHECK-BE-NEXT:    xvcvsxddp vs0, v2
 ; CHECK-BE-NEXT:    stxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = load <2 x i16>, <2 x i16>* %SrcPtr, align 16
   %1 = sitofp <2 x i16> %0 to <2 x double>
   store <2 x double> %1, <2 x double>* %Sink, align 16
   ret void
 }

llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i16_elts.ll

 ; CHECK-P9-NEXT:    vmrghh v2, v3, v2
 ; CHECK-P9-NEXT:    vextuwrx r3, r3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtfprd f0, r3
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
-; CHECK-BE-NEXT:    xscvspdpn f1, vs0
+; CHECK-BE-NEXT:    xscvspdpn f2, vs0
 ; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI0_0@toc@l
-; CHECK-BE-NEXT:    lxv v2, 0(r3)
+; CHECK-BE-NEXT:    lxv vs1, 0(r3)
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    xscvdpsxws f1, f1
+; CHECK-BE-NEXT:    xscvdpsxws f2, f2
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    mtvsrwz v3, r3
+; CHECK-BE-NEXT:    mffprwz r3, f2
+; CHECK-BE-NEXT:    mtfprwz f2, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mtvsrwz v2, r3
 ; CHECK-BE-NEXT:    li r3, 0
-; CHECK-BE-NEXT:    vperm v2, v3, v4, v2
+; CHECK-BE-NEXT:    xxperm v2, vs2, vs1
 ; CHECK-BE-NEXT:    vextuwlx r3, r3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i64 %a.coerce to <2 x float>
   %1 = fptoui <2 x float> %0 to <2 x i16>
   %2 = bitcast <2 x i16> %1 to i32
   ret i32 %2
 }

 ; CHECK-P9-NEXT:    mtvsrd v2, r3
 ; CHECK-P9-NEXT:    vmrghh v2, v4, v2
 ; CHECK-P9-NEXT:    vmrglw v2, v2, v3
 ; CHECK-P9-NEXT:    mfvsrld r3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test4elt:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    xxsldwi vs0, v2, v2, 3
+; CHECK-BE-NEXT:    xxsldwi vs1, v2, v2, 3
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
+; CHECK-BE-NEXT:    xxsldwi vs2, v2, v2, 1
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI1_0@toc@l
-; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    lxv v3, 0(r3)
-; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    xxswapd vs0, v2
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
-; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    xscvspdpn f0, v2
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
-; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    vperm v4, v5, v4, v3
-; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    xxsldwi vs0, v2, v2, 1
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
-; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mffprwz r3, f0
+; CHECK-BE-NEXT:    xscvspdpn f1, vs1
+; CHECK-BE-NEXT:    xscvspdpn f2, vs2
+; CHECK-BE-NEXT:    lxv vs0, 0(r3)
+; CHECK-BE-NEXT:    xscvdpsxws f1, f1
+; CHECK-BE-NEXT:    xscvdpsxws f2, f2
+; CHECK-BE-NEXT:    mffprwz r3, f1
+; CHECK-BE-NEXT:    xxswapd vs1, v2
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
+; CHECK-BE-NEXT:    xscvspdpn f1, vs1
+; CHECK-BE-NEXT:    xscvdpsxws f1, f1
+; CHECK-BE-NEXT:    mffprwz r3, f1
+; CHECK-BE-NEXT:    mtfprwz f1, r3
+; CHECK-BE-NEXT:    xxperm v3, vs1, vs0
+; CHECK-BE-NEXT:    xscvspdpn f1, v2
+; CHECK-BE-NEXT:    xscvdpsxws f1, f1
+; CHECK-BE-NEXT:    mffprwz r3, f1
+; CHECK-BE-NEXT:    mtfprwz f1, r3
+; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    mtvsrwz v2, r3
-; CHECK-BE-NEXT:    vperm v2, v5, v2, v3
-; CHECK-BE-NEXT:    vmrghw v2, v2, v4
+; CHECK-BE-NEXT:    xxperm v2, vs1, vs0
+; CHECK-BE-NEXT:    vmrghw v2, v2, v3
 ; CHECK-BE-NEXT:    mfvsrd r3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = fptoui <4 x float> %a to <4 x i16>
   %1 = bitcast <4 x i16> %0 to i64
   ret i64 %1
 }
 

 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test8elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI2_0@toc@ha
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI2_0@toc@l
-; CHECK-BE-NEXT:    lxv v2, 0(r3)
-; CHECK-BE-NEXT:    xxsldwi vs2, vs1, vs1, 3
-; CHECK-BE-NEXT:    xscvspdpn f2, vs2
-; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    xxswapd vs2, vs1
-; CHECK-BE-NEXT:    mtvsrwz v3, r3
-; CHECK-BE-NEXT:    xscvspdpn f2, vs2
-; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    xscvspdpn f2, vs1
+; CHECK-BE-NEXT:    lxv vs2, 0(r3)
+; CHECK-BE-NEXT:    xxsldwi vs3, vs1, vs1, 3
+; CHECK-BE-NEXT:    xscvspdpn f3, vs3
+; CHECK-BE-NEXT:    xscvdpsxws f3, f3
+; CHECK-BE-NEXT:    mffprwz r3, f3
+; CHECK-BE-NEXT:    xxswapd vs3, vs1
+; CHECK-BE-NEXT:    mtvsrwz v2, r3
+; CHECK-BE-NEXT:    xscvspdpn f3, vs3
+; CHECK-BE-NEXT:    xscvdpsxws f3, f3
+; CHECK-BE-NEXT:    mffprwz r3, f3
+; CHECK-BE-NEXT:    mtfprwz f3, r3
+; CHECK-BE-NEXT:    xxperm v2, vs3, vs2
+; CHECK-BE-NEXT:    xscvspdpn f3, vs1
 ; CHECK-BE-NEXT:    xxsldwi vs1, vs1, vs1, 1
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
-; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    vperm v3, v4, v3, v2
+; CHECK-BE-NEXT:    xscvdpsxws f3, f3
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mffprwz r3, f3
+; CHECK-BE-NEXT:    mtfprwz f3, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xxsldwi vs1, vs0, vs0, 3
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
-; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
+; CHECK-BE-NEXT:    xxperm v3, vs3, vs2
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    vmrghw v3, v4, v3
+; CHECK-BE-NEXT:    vmrghw v2, v3, v2
 ; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs0
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
 ; CHECK-BE-NEXT:    mffprwz r3, f1
+; CHECK-BE-NEXT:    mtfprwz f1, r3
+; CHECK-BE-NEXT:    xxperm v3, vs1, vs2
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs0
 ; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    vperm v4, v5, v4, v2
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    mtfprwz f1, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    mtvsrwz v0, r3
-; CHECK-BE-NEXT:    vperm v2, v5, v0, v2
-; CHECK-BE-NEXT:    vmrghw v2, v2, v4
-; CHECK-BE-NEXT:    xxmrghd v2, v2, v3
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    xxperm v4, vs1, vs2
+; CHECK-BE-NEXT:    vmrghw v3, v4, v3
+; CHECK-BE-NEXT:    xxmrghd v2, v3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <8 x float>, <8 x float>* %0, align 32
   %1 = fptoui <8 x float> %a to <8 x i16>
   ret <8 x i16> %1
 }
 
 define void @test16elt(<16 x i16>* noalias nocapture sret(<16 x i16>) %agg.result, <16 x float>* nocapture readonly) local_unnamed_addr #3 {

 ; CHECK-P9-NEXT:    vmrglw v3, v4, v3
 ; CHECK-P9-NEXT:    xxmrgld vs0, v3, v2
 ; CHECK-P9-NEXT:    stxv vs0, 16(r3)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test16elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs2, 16(r4)
-; CHECK-BE-NEXT:    addis r5, r2, .LCPI3_0@toc@ha
-; CHECK-BE-NEXT:    lxv vs1, 0(r4)
-; CHECK-BE-NEXT:    lxv vs0, 48(r4)
-; CHECK-BE-NEXT:    addi r5, r5, .LCPI3_0@toc@l
-; CHECK-BE-NEXT:    lxv v2, 0(r5)
+; CHECK-BE-NEXT:    lxv vs0, 32(r4)
+; CHECK-BE-NEXT:    lxv vs1, 48(r4)
+; CHECK-BE-NEXT:    lxv vs4, 0(r4)
+; CHECK-BE-NEXT:    addis r4, r2, .LCPI3_0@toc@ha
+; CHECK-BE-NEXT:    addi r4, r4, .LCPI3_0@toc@l
+; CHECK-BE-NEXT:    lxv vs5, 0(r4)
 ; CHECK-BE-NEXT:    xxsldwi vs3, vs2, vs2, 3
-; CHECK-BE-NEXT:    xxswapd vs4, vs2
-; CHECK-BE-NEXT:    xscvspdpn f5, vs2
+; CHECK-BE-NEXT:    xxswapd vs6, vs2
+; CHECK-BE-NEXT:    xscvspdpn f7, vs2
 ; CHECK-BE-NEXT:    xxsldwi vs2, vs2, vs2, 1
-; CHECK-BE-NEXT:    xxsldwi vs6, vs1, vs1, 3
 ; CHECK-BE-NEXT:    xscvspdpn f3, vs3
-; CHECK-BE-NEXT:    xscvspdpn f4, vs4
+; CHECK-BE-NEXT:    xscvspdpn f6, vs6
 ; CHECK-BE-NEXT:    xscvspdpn f2, vs2
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    xscvdpsxws f4, f4
+; CHECK-BE-NEXT:    xscvdpsxws f6, f6
+; CHECK-BE-NEXT:    xscvdpsxws f2, f2
+; CHECK-BE-NEXT:    mffprwz r4, f3
+; CHECK-BE-NEXT:    mtvsrwz v2, r4
+; CHECK-BE-NEXT:    mffprwz r4, f6
+; CHECK-BE-NEXT:    xscvdpsxws f6, f7
+; CHECK-BE-NEXT:    mtfprwz f3, r4
+; CHECK-BE-NEXT:    xxperm v2, vs3, vs5
+; CHECK-BE-NEXT:    xxsldwi vs3, vs4, vs4, 3
+; CHECK-BE-NEXT:    mffprwz r4, f6
+; CHECK-BE-NEXT:    xscvspdpn f3, vs3
+; CHECK-BE-NEXT:    mtfprwz f6, r4
+; CHECK-BE-NEXT:    mffprwz r4, f2
+; CHECK-BE-NEXT:    xxswapd vs2, vs4
+; CHECK-BE-NEXT:    xscvdpsxws f3, f3
+; CHECK-BE-NEXT:    mtvsrwz v3, r4
+; CHECK-BE-NEXT:    xscvspdpn f2, vs2
+; CHECK-BE-NEXT:    xxperm v3, vs6, vs5
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    mffprwz r5, f3
+; CHECK-BE-NEXT:    vmrghw v2, v3, v2
+; CHECK-BE-NEXT:    mffprwz r4, f3
+; CHECK-BE-NEXT:    xxsldwi vs3, vs4, vs4, 1
+; CHECK-BE-NEXT:    mtvsrwz v4, r4
+; CHECK-BE-NEXT:    xscvspdpn f3, vs3
+; CHECK-BE-NEXT:    mffprwz r4, f2
+; CHECK-BE-NEXT:    xscvdpsxws f3, f3
+; CHECK-BE-NEXT:    mtfprwz f2, r4
+; CHECK-BE-NEXT:    xxperm v4, vs2, vs5
+; CHECK-BE-NEXT:    xscvspdpn f2, vs4
+; CHECK-BE-NEXT:    xscvdpsxws f2, f2
+; CHECK-BE-NEXT:    mffprwz r4, f2
+; CHECK-BE-NEXT:    mtfprwz f2, r4
+; CHECK-BE-NEXT:    mffprwz r4, f3
 ; CHECK-BE-NEXT:    xxswapd vs3, vs1
-; CHECK-BE-NEXT:    mtvsrwz v3, r5
-; CHECK-BE-NEXT:    mffprwz r5, f4
-; CHECK-BE-NEXT:    xscvdpsxws f4, f5
+; CHECK-BE-NEXT:    mtvsrwz v3, r4
 ; CHECK-BE-NEXT:    xscvspdpn f3, vs3
-; CHECK-BE-NEXT:    mtvsrwz v4, r5
-; CHECK-BE-NEXT:    vperm v3, v4, v3, v2
+; CHECK-BE-NEXT:    xxperm v3, vs2, vs5
+; CHECK-BE-NEXT:    xxsldwi vs2, vs1, vs1, 3
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    mffprwz r5, f4
-; CHECK-BE-NEXT:    xscvspdpn f4, vs6
-; CHECK-BE-NEXT:    mtvsrwz v4, r5
-; CHECK-BE-NEXT:    mffprwz r5, f2
+; CHECK-BE-NEXT:    xscvspdpn f2, vs2
+; CHECK-BE-NEXT:    vmrghw v3, v3, v4
+; CHECK-BE-NEXT:    xscvdpsxws f2, f2
+; CHECK-BE-NEXT:    mffprwz r4, f2
+; CHECK-BE-NEXT:    mtvsrwz v4, r4
+; CHECK-BE-NEXT:    mffprwz r4, f3
+; CHECK-BE-NEXT:    xxmrghd vs3, v3, v2
+; CHECK-BE-NEXT:    mtfprwz f2, r4
+; CHECK-BE-NEXT:    xxperm v4, vs2, vs5
 ; CHECK-BE-NEXT:    xscvspdpn f2, vs1
 ; CHECK-BE-NEXT:    xxsldwi vs1, vs1, vs1, 1
-; CHECK-BE-NEXT:    xscvdpsxws f4, f4
-; CHECK-BE-NEXT:    mtvsrwz v5, r5
+; CHECK-BE-NEXT:    xscvspdpn f1, vs1
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
+; CHECK-BE-NEXT:    xscvdpsxws f1, f1
+; CHECK-BE-NEXT:    mffprwz r4, f2
+; CHECK-BE-NEXT:    mtfprwz f2, r4
+; CHECK-BE-NEXT:    mffprwz r4, f1
+; CHECK-BE-NEXT:    xxsldwi vs1, vs0, vs0, 3
+; CHECK-BE-NEXT:    mtvsrwz v2, r4
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
-; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
+; CHECK-BE-NEXT:    xxperm v2, vs2, vs5
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    vmrghw v3, v4, v3
-; CHECK-BE-NEXT:    mffprwz r5, f4
-; CHECK-BE-NEXT:    mtvsrwz v5, r5
-; CHECK-BE-NEXT:    mffprwz r5, f3
-; CHECK-BE-NEXT:    xxsldwi vs3, vs0, vs0, 3
-; CHECK-BE-NEXT:    mtvsrwz v0, r5
-; CHECK-BE-NEXT:    mffprwz r5, f2
-; CHECK-BE-NEXT:    xscvspdpn f2, vs3
-; CHECK-BE-NEXT:    vperm v5, v0, v5, v2
-; CHECK-BE-NEXT:    mtvsrwz v0, r5
-; CHECK-BE-NEXT:    mffprwz r5, f1
+; CHECK-BE-NEXT:    vmrghw v2, v2, v4
+; CHECK-BE-NEXT:    mffprwz r4, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs0
-; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    mtvsrwz v1, r5
+; CHECK-BE-NEXT:    mtvsrwz v3, r4
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
-; CHECK-BE-NEXT:    vperm v0, v0, v1, v2
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    vmrghw v4, v0, v5
-; CHECK-BE-NEXT:    mffprwz r5, f2
-; CHECK-BE-NEXT:    xscvspdpn f2, vs0
+; CHECK-BE-NEXT:    mffprwz r4, f1
+; CHECK-BE-NEXT:    mtfprwz f1, r4
+; CHECK-BE-NEXT:    xxperm v3, vs1, vs5
+; CHECK-BE-NEXT:    xscvspdpn f1, vs0
 ; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1
-; CHECK-BE-NEXT:    mtvsrwz v1, r5
-; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    mffprwz r5, f1
-; CHECK-BE-NEXT:    lxv vs1, 32(r4)
-; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mtvsrwz v6, r5
-; CHECK-BE-NEXT:    vperm v1, v6, v1, v2
-; CHECK-BE-NEXT:    mffprwz r4, f2
-; CHECK-BE-NEXT:    xxmrghd vs2, v4, v3
-; CHECK-BE-NEXT:    mtvsrwz v5, r4
-; CHECK-BE-NEXT:    mffprwz r4, f0
-; CHECK-BE-NEXT:    xxsldwi vs0, vs1, vs1, 3
-; CHECK-BE-NEXT:    stxv vs2, 0(r3)
-; CHECK-BE-NEXT:    mtvsrwz v3, r4
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    vperm v3, v5, v3, v2
+; CHECK-BE-NEXT:    xscvdpsxws f1, f1
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    vmrghw v3, v3, v1
+; CHECK-BE-NEXT:    mffprwz r4, f1
+; CHECK-BE-NEXT:    mtfprwz f1, r4
 ; CHECK-BE-NEXT:    mffprwz r4, f0
-; CHECK-BE-NEXT:    xxswapd vs0, vs1
 ; CHECK-BE-NEXT:    mtvsrwz v4, r4
-; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mffprwz r4, f0
-; CHECK-BE-NEXT:    xscvspdpn f0, vs1
-; CHECK-BE-NEXT:    mtvsrwz v5, r4
-; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    vperm v4, v5, v4, v2
-; CHECK-BE-NEXT:    mffprwz r4, f0
-; CHECK-BE-NEXT:    xxsldwi vs0, vs1, vs1, 1
-; CHECK-BE-NEXT:    mtvsrwz v5, r4
-; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mffprwz r4, f0
-; CHECK-BE-NEXT:    mtvsrwz v0, r4
-; CHECK-BE-NEXT:    vperm v2, v5, v0, v2
-; CHECK-BE-NEXT:    vmrghw v2, v2, v4
-; CHECK-BE-NEXT:    xxmrghd vs0, v2, v3
+; CHECK-BE-NEXT:    xxperm v4, vs1, vs5
+; CHECK-BE-NEXT:    stxv vs3, 0(r3)
+; CHECK-BE-NEXT:    vmrghw v3, v4, v3
+; CHECK-BE-NEXT:    xxmrghd vs0, v3, v2
 ; CHECK-BE-NEXT:    stxv vs0, 16(r3)
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <16 x float>, <16 x float>* %0, align 64
   %1 = fptoui <16 x float> %a to <16 x i16>
   store <16 x i16> %1, <16 x i16>* %agg.result, align 32
   ret void
 }

 ; CHECK-P9-NEXT:    vmrghh v2, v3, v2
 ; CHECK-P9-NEXT:    vextuwrx r3, r3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtfprd f0, r3
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
-; CHECK-BE-NEXT:    xscvspdpn f1, vs0
+; CHECK-BE-NEXT:    xscvspdpn f2, vs0
 ; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI4_0@toc@l
-; CHECK-BE-NEXT:    lxv v2, 0(r3)
+; CHECK-BE-NEXT:    lxv vs1, 0(r3)
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    xscvdpsxws f1, f1
+; CHECK-BE-NEXT:    xscvdpsxws f2, f2
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    mtvsrwz v3, r3
+; CHECK-BE-NEXT:    mffprwz r3, f2
+; CHECK-BE-NEXT:    mtfprwz f2, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mtvsrwz v2, r3
 ; CHECK-BE-NEXT:    li r3, 0
-; CHECK-BE-NEXT:    vperm v2, v3, v4, v2
+; CHECK-BE-NEXT:    xxperm v2, vs2, vs1
 ; CHECK-BE-NEXT:    vextuwlx r3, r3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i64 %a.coerce to <2 x float>
   %1 = fptosi <2 x float> %0 to <2 x i16>
   %2 = bitcast <2 x i16> %1 to i32
   ret i32 %2
 }

 ; CHECK-P9-NEXT:    mtvsrd v2, r3
 ; CHECK-P9-NEXT:    vmrghh v2, v4, v2
 ; CHECK-P9-NEXT:    vmrglw v2, v2, v3
 ; CHECK-P9-NEXT:    mfvsrld r3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test4elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    xxsldwi vs0, v2, v2, 3
+; CHECK-BE-NEXT:    xxsldwi vs1, v2, v2, 3
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI5_0@toc@ha
+; CHECK-BE-NEXT:    xxsldwi vs2, v2, v2, 1
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI5_0@toc@l
-; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    lxv v3, 0(r3)
-; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    xxswapd vs0, v2
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
-; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    xscvspdpn f0, v2
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
-; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    vperm v4, v5, v4, v3
-; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    xxsldwi vs0, v2, v2, 1
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
-; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mffprwz r3, f0
+; CHECK-BE-NEXT:    xscvspdpn f1, vs1
+; CHECK-BE-NEXT:    xscvspdpn f2, vs2
+; CHECK-BE-NEXT:    lxv vs0, 0(r3)
+; CHECK-BE-NEXT:    xscvdpsxws f1, f1
+; CHECK-BE-NEXT:    xscvdpsxws f2, f2
+; CHECK-BE-NEXT:    mffprwz r3, f1
+; CHECK-BE-NEXT:    xxswapd vs1, v2
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
+; CHECK-BE-NEXT:    xscvspdpn f1, vs1
+; CHECK-BE-NEXT:    xscvdpsxws f1, f1
+; CHECK-BE-NEXT:    mffprwz r3, f1
+; CHECK-BE-NEXT:    mtfprwz f1, r3
+; CHECK-BE-NEXT:    xxperm v3, vs1, vs0
+; CHECK-BE-NEXT:    xscvspdpn f1, v2
+; CHECK-BE-NEXT:    xscvdpsxws f1, f1
+; CHECK-BE-NEXT:    mffprwz r3, f1
+; CHECK-BE-NEXT:    mtfprwz f1, r3
+; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    mtvsrwz v2, r3
-; CHECK-BE-NEXT:    vperm v2, v5, v2, v3
-; CHECK-BE-NEXT:    vmrghw v2, v2, v4
+; CHECK-BE-NEXT:    xxperm v2, vs1, vs0
+; CHECK-BE-NEXT:    vmrghw v2, v2, v3
 ; CHECK-BE-NEXT:    mfvsrd r3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = fptosi <4 x float> %a to <4 x i16>
   %1 = bitcast <4 x i16> %0 to i64
   ret i64 %1
 }
 

 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test8elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI6_0@toc@ha
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI6_0@toc@l
-; CHECK-BE-NEXT:    lxv v2, 0(r3)
-; CHECK-BE-NEXT:    xxsldwi vs2, vs1, vs1, 3
-; CHECK-BE-NEXT:    xscvspdpn f2, vs2
-; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    xxswapd vs2, vs1
-; CHECK-BE-NEXT:    mtvsrwz v3, r3
-; CHECK-BE-NEXT:    xscvspdpn f2, vs2
-; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    xscvspdpn f2, vs1
+; CHECK-BE-NEXT:    lxv vs2, 0(r3)
+; CHECK-BE-NEXT:    xxsldwi vs3, vs1, vs1, 3
+; CHECK-BE-NEXT:    xscvspdpn f3, vs3
+; CHECK-BE-NEXT:    xscvdpsxws f3, f3
+; CHECK-BE-NEXT:    mffprwz r3, f3
+; CHECK-BE-NEXT:    xxswapd vs3, vs1
+; CHECK-BE-NEXT:    mtvsrwz v2, r3
+; CHECK-BE-NEXT:    xscvspdpn f3, vs3
+; CHECK-BE-NEXT:    xscvdpsxws f3, f3
+; CHECK-BE-NEXT:    mffprwz r3, f3
+; CHECK-BE-NEXT:    mtfprwz f3, r3
+; CHECK-BE-NEXT:    xxperm v2, vs3, vs2
+; CHECK-BE-NEXT:    xscvspdpn f3, vs1
 ; CHECK-BE-NEXT:    xxsldwi vs1, vs1, vs1, 1
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
-; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    vperm v3, v4, v3, v2
+; CHECK-BE-NEXT:    xscvdpsxws f3, f3
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mffprwz r3, f3
+; CHECK-BE-NEXT:    mtfprwz f3, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xxsldwi vs1, vs0, vs0, 3
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
-; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
+; CHECK-BE-NEXT:    xxperm v3, vs3, vs2
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    vmrghw v3, v4, v3
+; CHECK-BE-NEXT:    vmrghw v2, v3, v2
 ; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs0
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
 ; CHECK-BE-NEXT:    mffprwz r3, f1
+; CHECK-BE-NEXT:    mtfprwz f1, r3
+; CHECK-BE-NEXT:    xxperm v3, vs1, vs2
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs0
 ; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    vperm v4, v5, v4, v2
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    mtfprwz f1, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    mtvsrwz v0, r3
-; CHECK-BE-NEXT:    vperm v2, v5, v0, v2
-; CHECK-BE-NEXT:    vmrghw v2, v2, v4
-; CHECK-BE-NEXT:    xxmrghd v2, v2, v3
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    xxperm v4, vs1, vs2
+; CHECK-BE-NEXT:    vmrghw v3, v4, v3
+; CHECK-BE-NEXT:    xxmrghd v2, v3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <8 x float>, <8 x float>* %0, align 32
   %1 = fptosi <8 x float> %a to <8 x i16>
   ret <8 x i16> %1
 }
 
 define void @test16elt_signed(<16 x i16>* noalias nocapture sret(<16 x i16>) %agg.result, <16 x float>* nocapture readonly) local_unnamed_addr #3 {

 ; CHECK-P9-NEXT:    vmrglw v3, v4, v3
 ; CHECK-P9-NEXT:    xxmrgld vs0, v3, v2
 ; CHECK-P9-NEXT:    stxv vs0, 16(r3)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test16elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs2, 16(r4)
-; CHECK-BE-NEXT:    addis r5, r2, .LCPI7_0@toc@ha
-; CHECK-BE-NEXT:    lxv vs1, 0(r4)
-; CHECK-BE-NEXT:    lxv vs0, 48(r4)
-; CHECK-BE-NEXT:    addi r5, r5, .LCPI7_0@toc@l
-; CHECK-BE-NEXT:    lxv v2, 0(r5)
+; CHECK-BE-NEXT:    lxv vs0, 32(r4)
+; CHECK-BE-NEXT:    lxv vs1, 48(r4)
+; CHECK-BE-NEXT:    lxv vs4, 0(r4)
+; CHECK-BE-NEXT:    addis r4, r2, .LCPI7_0@toc@ha
+; CHECK-BE-NEXT:    addi r4, r4, .LCPI7_0@toc@l
+; CHECK-BE-NEXT:    lxv vs5, 0(r4)
 ; CHECK-BE-NEXT:    xxsldwi vs3, vs2, vs2, 3
-; CHECK-BE-NEXT:    xxswapd vs4, vs2
-; CHECK-BE-NEXT:    xscvspdpn f5, vs2
+; CHECK-BE-NEXT:    xxswapd vs6, vs2
+; CHECK-BE-NEXT:    xscvspdpn f7, vs2
 ; CHECK-BE-NEXT:    xxsldwi vs2, vs2, vs2, 1
-; CHECK-BE-NEXT:    xxsldwi vs6, vs1, vs1, 3
 ; CHECK-BE-NEXT:    xscvspdpn f3, vs3
-; CHECK-BE-NEXT:    xscvspdpn f4, vs4
+; CHECK-BE-NEXT:    xscvspdpn f6, vs6
 ; CHECK-BE-NEXT:    xscvspdpn f2, vs2
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    xscvdpsxws f4, f4
+; CHECK-BE-NEXT:    xscvdpsxws f6, f6
+; CHECK-BE-NEXT:    xscvdpsxws f2, f2
+; CHECK-BE-NEXT:    mffprwz r4, f3
+; CHECK-BE-NEXT:    mtvsrwz v2, r4
+; CHECK-BE-NEXT:    mffprwz r4, f6
+; CHECK-BE-NEXT:    xscvdpsxws f6, f7
+; CHECK-BE-NEXT:    mtfprwz f3, r4
+; CHECK-BE-NEXT:    xxperm v2, vs3, vs5
+; CHECK-BE-NEXT:    xxsldwi vs3, vs4, vs4, 3
+; CHECK-BE-NEXT:    mffprwz r4, f6
+; CHECK-BE-NEXT:    xscvspdpn f3, vs3
+; CHECK-BE-NEXT:    mtfprwz f6, r4
+; CHECK-BE-NEXT:    mffprwz r4, f2
+; CHECK-BE-NEXT:    xxswapd vs2, vs4
+; CHECK-BE-NEXT:    xscvdpsxws f3, f3
+; CHECK-BE-NEXT:    mtvsrwz v3, r4
+; CHECK-BE-NEXT:    xscvspdpn f2, vs2
+; CHECK-BE-NEXT:    xxperm v3, vs6, vs5
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    mffprwz r5, f3
+; CHECK-BE-NEXT:    vmrghw v2, v3, v2
+; CHECK-BE-NEXT:    mffprwz r4, f3
+; CHECK-BE-NEXT:    xxsldwi vs3, vs4, vs4, 1
+; CHECK-BE-NEXT:    mtvsrwz v4, r4
+; CHECK-BE-NEXT:    xscvspdpn f3, vs3
+; CHECK-BE-NEXT:    mffprwz r4, f2
+; CHECK-BE-NEXT:    xscvdpsxws f3, f3
+; CHECK-BE-NEXT:    mtfprwz f2, r4
+; CHECK-BE-NEXT:    xxperm v4, vs2, vs5
+; CHECK-BE-NEXT:    xscvspdpn f2, vs4
+; CHECK-BE-NEXT:    xscvdpsxws f2, f2
+; CHECK-BE-NEXT:    mffprwz r4, f2
+; CHECK-BE-NEXT:    mtfprwz f2, r4
+; CHECK-BE-NEXT:    mffprwz r4, f3
 ; CHECK-BE-NEXT:    xxswapd vs3, vs1
-; CHECK-BE-NEXT:    mtvsrwz v3, r5
-; CHECK-BE-NEXT:    mffprwz r5, f4
-; CHECK-BE-NEXT:    xscvdpsxws f4, f5
+; CHECK-BE-NEXT:    mtvsrwz v3, r4
 ; CHECK-BE-NEXT:    xscvspdpn f3, vs3
-; CHECK-BE-NEXT:    mtvsrwz v4, r5
-; CHECK-BE-NEXT:    vperm v3, v4, v3, v2
+; CHECK-BE-NEXT:    xxperm v3, vs2, vs5
+; CHECK-BE-NEXT:    xxsldwi vs2, vs1, vs1, 3
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    mffprwz r5, f4
-; CHECK-BE-NEXT:    xscvspdpn f4, vs6
-; CHECK-BE-NEXT:    mtvsrwz v4, r5
-; CHECK-BE-NEXT:    mffprwz r5, f2
+; CHECK-BE-NEXT:    xscvspdpn f2, vs2
+; CHECK-BE-NEXT:    vmrghw v3, v3, v4
+; CHECK-BE-NEXT:    xscvdpsxws f2, f2
+; CHECK-BE-NEXT:    mffprwz r4, f2
+; CHECK-BE-NEXT:    mtvsrwz v4, r4
+; CHECK-BE-NEXT:    mffprwz r4, f3
+; CHECK-BE-NEXT:    xxmrghd vs3, v3, v2
+; CHECK-BE-NEXT:    mtfprwz f2, r4
+; CHECK-BE-NEXT:    xxperm v4, vs2, vs5
 ; CHECK-BE-NEXT:    xscvspdpn f2, vs1
 ; CHECK-BE-NEXT:    xxsldwi vs1, vs1, vs1, 1
-; CHECK-BE-NEXT:    xscvdpsxws f4, f4
-; CHECK-BE-NEXT:    mtvsrwz v5, r5
+; CHECK-BE-NEXT:    xscvspdpn f1, vs1
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
+; CHECK-BE-NEXT:    xscvdpsxws f1, f1
+; CHECK-BE-NEXT:    mffprwz r4, f2
+; CHECK-BE-NEXT:    mtfprwz f2, r4
+; CHECK-BE-NEXT:    mffprwz r4, f1
+; CHECK-BE-NEXT:    xxsldwi vs1, vs0, vs0, 3
+; CHECK-BE-NEXT:    mtvsrwz v2, r4
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
-; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
+; CHECK-BE-NEXT:    xxperm v2, vs2, vs5
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    vmrghw v3, v4, v3
-; CHECK-BE-NEXT:    mffprwz r5, f4
-; CHECK-BE-NEXT:    mtvsrwz v5, r5
-; CHECK-BE-NEXT:    mffprwz r5, f3
-; CHECK-BE-NEXT:    xxsldwi vs3, vs0, vs0, 3
-; CHECK-BE-NEXT:    mtvsrwz v0, r5
-; CHECK-BE-NEXT:    mffprwz r5, f2
-; CHECK-BE-NEXT:    xscvspdpn f2, vs3
-; CHECK-BE-NEXT:    vperm v5, v0, v5, v2
-; CHECK-BE-NEXT:    mtvsrwz v0, r5
-; CHECK-BE-NEXT:    mffprwz r5, f1
+; CHECK-BE-NEXT:    vmrghw v2, v2, v4
+; CHECK-BE-NEXT:    mffprwz r4, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs0
-; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    mtvsrwz v1, r5
+; CHECK-BE-NEXT:    mtvsrwz v3, r4
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
-; CHECK-BE-NEXT:    vperm v0, v0, v1, v2
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    vmrghw v4, v0, v5
-; CHECK-BE-NEXT:    mffprwz r5, f2
-; CHECK-BE-NEXT:    xscvspdpn f2, vs0
+; CHECK-BE-NEXT:    mffprwz r4, f1
+; CHECK-BE-NEXT:    mtfprwz f1, r4
+; CHECK-BE-NEXT:    xxperm v3, vs1, vs5
+; CHECK-BE-NEXT:    xscvspdpn f1, vs0
 ; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1
-; CHECK-BE-NEXT:    mtvsrwz v1, r5
-; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    mffprwz r5, f1
-; CHECK-BE-NEXT:    lxv vs1, 32(r4)
-; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mtvsrwz v6, r5
-; CHECK-BE-NEXT:    vperm v1, v6, v1, v2
-; CHECK-BE-NEXT:    mffprwz r4, f2
-; CHECK-BE-NEXT:    xxmrghd vs2, v4, v3
-; CHECK-BE-NEXT:    mtvsrwz v5, r4
-; CHECK-BE-NEXT:    mffprwz r4, f0
-; CHECK-BE-NEXT:    xxsldwi vs0, vs1, vs1, 3
-; CHECK-BE-NEXT:    stxv vs2, 0(r3)
-; CHECK-BE-NEXT:    mtvsrwz v3, r4
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    vperm v3, v5, v3, v2
+; CHECK-BE-NEXT:    xscvdpsxws f1, f1
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    vmrghw v3, v3, v1
+; CHECK-BE-NEXT:    mffprwz r4, f1
+; CHECK-BE-NEXT:    mtfprwz f1, r4
 ; CHECK-BE-NEXT:    mffprwz r4, f0
-; CHECK-BE-NEXT:    xxswapd vs0, vs1
 ; CHECK-BE-NEXT:    mtvsrwz v4, r4
-; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mffprwz r4, f0
-; CHECK-BE-NEXT:    xscvspdpn f0, vs1
-; CHECK-BE-NEXT:    mtvsrwz v5, r4
-; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    vperm v4, v5, v4, v2
-; CHECK-BE-NEXT:    mffprwz r4, f0
-; CHECK-BE-NEXT:    xxsldwi vs0, vs1, vs1, 1
-; CHECK-BE-NEXT:    mtvsrwz v5, r4
-; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mffprwz r4, f0
-; CHECK-BE-NEXT:    mtvsrwz v0, r4
-; CHECK-BE-NEXT:    vperm v2, v5, v0, v2
-; CHECK-BE-NEXT:    vmrghw v2, v2, v4
-; CHECK-BE-NEXT:    xxmrghd vs0, v2, v3
+; CHECK-BE-NEXT:    xxperm v4, vs1, vs5
+; CHECK-BE-NEXT:    stxv vs3, 0(r3)
+; CHECK-BE-NEXT:    vmrghw v3, v4, v3
+; CHECK-BE-NEXT:    xxmrghd vs0, v3, v2
 ; CHECK-BE-NEXT:    stxv vs0, 16(r3)
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <16 x float>, <16 x float>* %0, align 64
   %1 = fptosi <16 x float> %a to <16 x i16>
   store <16 x i16> %1, <16 x i16>* %agg.result, align 32
   ret void
 }

llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i8_elts.ll

 ; CHECK-P9-NEXT:    stxsihx v2, 0, r3
 ; CHECK-P9-NEXT:    lhz r3, -2(r1)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtfprd f0, r3
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
-; CHECK-BE-NEXT:    xscvspdpn f1, vs0
+; CHECK-BE-NEXT:    xscvspdpn f2, vs0
 ; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI0_0@toc@l
-; CHECK-BE-NEXT:    lxv v2, 0(r3)
+; CHECK-BE-NEXT:    lxv vs1, 0(r3)
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    xscvdpsxws f1, f1
+; CHECK-BE-NEXT:    xscvdpsxws f2, f2
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    mtvsrwz v3, r3
+; CHECK-BE-NEXT:    mffprwz r3, f2
+; CHECK-BE-NEXT:    mtfprwz f2, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mtvsrwz v2, r3
 ; CHECK-BE-NEXT:    addi r3, r1, -2
-; CHECK-BE-NEXT:    vperm v2, v3, v4, v2
+; CHECK-BE-NEXT:    xxperm v2, vs2, vs1
 ; CHECK-BE-NEXT:    vsldoi v2, v2, v2, 10
 ; CHECK-BE-NEXT:    stxsihx v2, 0, r3
 ; CHECK-BE-NEXT:    lhz r3, -2(r1)
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i64 %a.coerce to <2 x float>
   %1 = fptoui <2 x float> %0 to <2 x i8>
   %2 = bitcast <2 x i8> %1 to i16

 ; CHECK-P9-NEXT:    li r3, 0
 ; CHECK-P9-NEXT:    vmrghb v2, v4, v2
 ; CHECK-P9-NEXT:    vmrglh v2, v2, v3
 ; CHECK-P9-NEXT:    vextuwrx r3, r3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test4elt:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    xxsldwi vs0, v2, v2, 3
+; CHECK-BE-NEXT:    xxsldwi vs1, v2, v2, 3
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
+; CHECK-BE-NEXT:    xxsldwi vs2, v2, v2, 1
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI1_0@toc@l
-; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    lxv v3, 0(r3)
-; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    xxswapd vs0, v2
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
-; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    xscvspdpn f0, v2
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
-; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    vperm v4, v5, v4, v3
-; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    xxsldwi vs0, v2, v2, 1
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
-; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mffprwz r3, f0
+; CHECK-BE-NEXT:    xscvspdpn f1, vs1
+; CHECK-BE-NEXT:    xscvspdpn f2, vs2
+; CHECK-BE-NEXT:    lxv vs0, 0(r3)
+; CHECK-BE-NEXT:    xscvdpsxws f1, f1
+; CHECK-BE-NEXT:    xscvdpsxws f2, f2
+; CHECK-BE-NEXT:    mffprwz r3, f1
+; CHECK-BE-NEXT:    xxswapd vs1, v2
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
+; CHECK-BE-NEXT:    xscvspdpn f1, vs1
+; CHECK-BE-NEXT:    xscvdpsxws f1, f1
+; CHECK-BE-NEXT:    mffprwz r3, f1
+; CHECK-BE-NEXT:    mtfprwz f1, r3
+; CHECK-BE-NEXT:    xxperm v3, vs1, vs0
+; CHECK-BE-NEXT:    xscvspdpn f1, v2
+; CHECK-BE-NEXT:    xscvdpsxws f1, f1
+; CHECK-BE-NEXT:    mffprwz r3, f1
+; CHECK-BE-NEXT:    mtfprwz f1, r3
+; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    mtvsrwz v2, r3
 ; CHECK-BE-NEXT:    li r3, 0
-; CHECK-BE-NEXT:    vperm v2, v5, v2, v3
-; CHECK-BE-NEXT:    vmrghh v2, v2, v4
+; CHECK-BE-NEXT:    xxperm v2, vs1, vs0
+; CHECK-BE-NEXT:    vmrghh v2, v2, v3
 ; CHECK-BE-NEXT:    vextuwlx r3, r3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = fptoui <4 x float> %a to <4 x i8>
   %1 = bitcast <4 x i8> %0 to i32
   ret i32 %1
 }
 

 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test8elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI2_0@toc@ha
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI2_0@toc@l
-; CHECK-BE-NEXT:    lxv v2, 0(r3)
-; CHECK-BE-NEXT:    xxsldwi vs2, vs1, vs1, 3
-; CHECK-BE-NEXT:    xscvspdpn f2, vs2
-; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    xxswapd vs2, vs1
-; CHECK-BE-NEXT:    mtvsrwz v3, r3
-; CHECK-BE-NEXT:    xscvspdpn f2, vs2
-; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    xscvspdpn f2, vs1
+; CHECK-BE-NEXT:    lxv vs2, 0(r3)
+; CHECK-BE-NEXT:    xxsldwi vs3, vs1, vs1, 3
+; CHECK-BE-NEXT:    xscvspdpn f3, vs3
+; CHECK-BE-NEXT:    xscvdpsxws f3, f3
+; CHECK-BE-NEXT:    mffprwz r3, f3
+; CHECK-BE-NEXT:    xxswapd vs3, vs1
+; CHECK-BE-NEXT:    mtvsrwz v2, r3
+; CHECK-BE-NEXT:    xscvspdpn f3, vs3
+; CHECK-BE-NEXT:    xscvdpsxws f3, f3
+; CHECK-BE-NEXT:    mffprwz r3, f3
+; CHECK-BE-NEXT:    mtfprwz f3, r3
+; CHECK-BE-NEXT:    xxperm v2, vs3, vs2
+; CHECK-BE-NEXT:    xscvspdpn f3, vs1
 ; CHECK-BE-NEXT:    xxsldwi vs1, vs1, vs1, 1
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
-; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    vperm v3, v4, v3, v2
+; CHECK-BE-NEXT:    xscvdpsxws f3, f3
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mffprwz r3, f3
+; CHECK-BE-NEXT:    mtfprwz f3, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xxsldwi vs1, vs0, vs0, 3
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
-; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
+; CHECK-BE-NEXT:    xxperm v3, vs3, vs2
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    vmrghh v3, v4, v3
+; CHECK-BE-NEXT:    vmrghh v2, v3, v2
 ; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs0
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
 ; CHECK-BE-NEXT:    mffprwz r3, f1
+; CHECK-BE-NEXT:    mtfprwz f1, r3
+; CHECK-BE-NEXT:    xxperm v3, vs1, vs2
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs0
 ; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    vperm v4, v5, v4, v2
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    mtfprwz f1, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    mtvsrwz v0, r3
-; CHECK-BE-NEXT:    vperm v2, v5, v0, v2
-; CHECK-BE-NEXT:    vmrghh v2, v2, v4
-; CHECK-BE-NEXT:    vmrghw v2, v2, v3
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    xxperm v4, vs1, vs2
+; CHECK-BE-NEXT:    vmrghh v3, v4, v3
+; CHECK-BE-NEXT:    vmrghw v2, v3, v2
 ; CHECK-BE-NEXT:    mfvsrd r3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <8 x float>, <8 x float>* %0, align 32
   %1 = fptoui <8 x float> %a to <8 x i8>
   %2 = bitcast <8 x i8> %1 to i64
   ret i64 %2
 }

 ; CHECK-BE-LABEL: test16elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs3, 48(r3)
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    lxv vs2, 32(r3)
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI3_0@toc@ha
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI3_0@toc@l
-; CHECK-BE-NEXT:    lxv v2, 0(r3)
-; CHECK-BE-NEXT:    xxsldwi vs4, vs3, vs3, 3
-; CHECK-BE-NEXT:    xscvspdpn f4, vs4
-; CHECK-BE-NEXT:    xscvdpsxws f4, f4
-; CHECK-BE-NEXT:    mffprwz r3, f4
-; CHECK-BE-NEXT:    xxswapd vs4, vs3
-; CHECK-BE-NEXT:    mtvsrwz v3, r3
-; CHECK-BE-NEXT:    xscvspdpn f4, vs4
-; CHECK-BE-NEXT:    xscvdpsxws f4, f4
-; CHECK-BE-NEXT:    mffprwz r3, f4
-; CHECK-BE-NEXT:    xscvspdpn f4, vs3
+; CHECK-BE-NEXT:    lxv vs4, 0(r3)
+; CHECK-BE-NEXT:    xxsldwi vs5, vs3, vs3, 3
+; CHECK-BE-NEXT:    xscvspdpn f5, vs5
+; CHECK-BE-NEXT:    xscvdpsxws f5, f5
+; CHECK-BE-NEXT:    mffprwz r3, f5
+; CHECK-BE-NEXT:    xxswapd vs5, vs3
+; CHECK-BE-NEXT:    mtvsrwz v2, r3
+; CHECK-BE-NEXT:    xscvspdpn f5, vs5
+; CHECK-BE-NEXT:    xscvdpsxws f5, f5
+; CHECK-BE-NEXT:    mffprwz r3, f5
+; CHECK-BE-NEXT:    mtfprwz f5, r3
+; CHECK-BE-NEXT:    xxperm v2, vs5, vs4
+; CHECK-BE-NEXT:    xscvspdpn f5, vs3
 ; CHECK-BE-NEXT:    xxsldwi vs3, vs3, vs3, 1
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    xscvspdpn f3, vs3
-; CHECK-BE-NEXT:    xscvdpsxws f4, f4
-; CHECK-BE-NEXT:    vperm v3, v4, v3, v2
+; CHECK-BE-NEXT:    xscvdpsxws f5, f5
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    mffprwz r3, f4
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mffprwz r3, f5
+; CHECK-BE-NEXT:    mtfprwz f5, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f3
 ; CHECK-BE-NEXT:    xxsldwi vs3, vs2, vs2, 3
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    xscvspdpn f3, vs3
-; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
+; CHECK-BE-NEXT:    xxperm v3, vs5, vs4
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    vmrghh v3, v4, v3
+; CHECK-BE-NEXT:    vmrghh v2, v3, v2
 ; CHECK-BE-NEXT:    mffprwz r3, f3
 ; CHECK-BE-NEXT:    xxswapd vs3, vs2
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    xscvspdpn f3, vs3
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f3
 ; CHECK-BE-NEXT:    mffprwz r3, f3
+; CHECK-BE-NEXT:    mtfprwz f3, r3
+; CHECK-BE-NEXT:    xxperm v3, vs3, vs4
 ; CHECK-BE-NEXT:    xscvspdpn f3, vs2
 ; CHECK-BE-NEXT:    xxsldwi vs2, vs2, vs2, 1
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    xscvspdpn f2, vs2
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    vperm v4, v5, v4, v2
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
 ; CHECK-BE-NEXT:    mffprwz r3, f3
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    mtfprwz f3, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    xxsldwi vs2, vs1, vs1, 3
-; CHECK-BE-NEXT:    mtvsrwz v0, r3
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    xscvspdpn f2, vs2
-; CHECK-BE-NEXT:    vperm v5, v5, v0, v2
+; CHECK-BE-NEXT:    xxperm v4, vs3, vs4
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    vmrghh v4, v5, v4
-; CHECK-BE-NEXT:    vmrghw v3, v4, v3
+; CHECK-BE-NEXT:    vmrghh v3, v4, v3
+; CHECK-BE-NEXT:    vmrghw v2, v3, v2
 ; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    xxswapd vs2, vs1
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    xscvspdpn f2, vs2
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
 ; CHECK-BE-NEXT:    mffprwz r3, f2
+; CHECK-BE-NEXT:    mtfprwz f2, r3
+; CHECK-BE-NEXT:    xxperm v3, vs2, vs4
 ; CHECK-BE-NEXT:    xscvspdpn f2, vs1
 ; CHECK-BE-NEXT:    xxsldwi vs1, vs1, vs1, 1
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    vperm v4, v5, v4, v2
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
 ; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    mtfprwz f2, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xxsldwi vs1, vs0, vs0, 3
-; CHECK-BE-NEXT:    mtvsrwz v0, r3
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
-; CHECK-BE-NEXT:    vperm v5, v5, v0, v2
+; CHECK-BE-NEXT:    xxperm v4, vs2, vs4
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    vmrghh v4, v5, v4
+; CHECK-BE-NEXT:    vmrghh v3, v4, v3
 ; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs0
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
 ; CHECK-BE-NEXT:    mffprwz r3, f1
+; CHECK-BE-NEXT:    mtfprwz f1, r3
+; CHECK-BE-NEXT:    xxperm v4, vs1, vs4
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs0
 ; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1
-; CHECK-BE-NEXT:    mtvsrwz v0, r3
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    vperm v5, v0, v5, v2
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    mtvsrwz v0, r3
+; CHECK-BE-NEXT:    mtfprwz f1, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    mtvsrwz v1, r3
-; CHECK-BE-NEXT:    vperm v2, v0, v1, v2
-; CHECK-BE-NEXT:    vmrghh v2, v2, v5
-; CHECK-BE-NEXT:    vmrghw v2, v2, v4
-; CHECK-BE-NEXT:    xxmrghd v2, v2, v3
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    xxperm v5, vs1, vs4
+; CHECK-BE-NEXT:    vmrghh v4, v5, v4
+; CHECK-BE-NEXT:    vmrghw v3, v4, v3
+; CHECK-BE-NEXT:    xxmrghd v2, v3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <16 x float>, <16 x float>* %0, align 64
   %1 = fptoui <16 x float> %a to <16 x i8>
   ret <16 x i8> %1
 }
 
 define i16 @test2elt_signed(i64 %a.coerce) local_unnamed_addr #0 {

 ; CHECK-P9-NEXT:    stxsihx v2, 0, r3
 ; CHECK-P9-NEXT:    lhz r3, -2(r1)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtfprd f0, r3
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
-; CHECK-BE-NEXT:    xscvspdpn f1, vs0
+; CHECK-BE-NEXT:    xscvspdpn f2, vs0
 ; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI4_0@toc@l
-; CHECK-BE-NEXT:    lxv v2, 0(r3)
+; CHECK-BE-NEXT:    lxv vs1, 0(r3)
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    xscvdpsxws f1, f1
+; CHECK-BE-NEXT:    xscvdpsxws f2, f2
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    mtvsrwz v3, r3
+; CHECK-BE-NEXT:    mffprwz r3, f2
+; CHECK-BE-NEXT:    mtfprwz f2, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mtvsrwz v2, r3
 ; CHECK-BE-NEXT:    addi r3, r1, -2
-; CHECK-BE-NEXT:    vperm v2, v3, v4, v2
+; CHECK-BE-NEXT:    xxperm v2, vs2, vs1
 ; CHECK-BE-NEXT:    vsldoi v2, v2, v2, 10
 ; CHECK-BE-NEXT:    stxsihx v2, 0, r3
 ; CHECK-BE-NEXT:    lhz r3, -2(r1)
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i64 %a.coerce to <2 x float>
   %1 = fptosi <2 x float> %0 to <2 x i8>
   %2 = bitcast <2 x i8> %1 to i16

 ; CHECK-P9-NEXT:    li r3, 0
 ; CHECK-P9-NEXT:    vmrghb v2, v4, v2
 ; CHECK-P9-NEXT:    vmrglh v2, v2, v3
 ; CHECK-P9-NEXT:    vextuwrx r3, r3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test4elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    xxsldwi vs0, v2, v2, 3
+; CHECK-BE-NEXT:    xxsldwi vs1, v2, v2, 3
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI5_0@toc@ha
+; CHECK-BE-NEXT:    xxsldwi vs2, v2, v2, 1
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI5_0@toc@l
-; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    lxv v3, 0(r3)
-; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    xxswapd vs0, v2
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
-; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    xscvspdpn f0, v2
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
-; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    vperm v4, v5, v4, v3
-; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    xxsldwi vs0, v2, v2, 1
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
-; CHECK-BE-NEXT:    xscvspdpn f0, vs0
-; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mffprwz r3, f0
+; CHECK-BE-NEXT:    xscvspdpn f1, vs1
+; CHECK-BE-NEXT:    xscvspdpn f2, vs2
+; CHECK-BE-NEXT:    lxv vs0, 0(r3)
+; CHECK-BE-NEXT:    xscvdpsxws f1, f1
+; CHECK-BE-NEXT:    xscvdpsxws f2, f2
+; CHECK-BE-NEXT:    mffprwz r3, f1
+; CHECK-BE-NEXT:    xxswapd vs1, v2
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
+; CHECK-BE-NEXT:    xscvspdpn f1, vs1
+; CHECK-BE-NEXT:    xscvdpsxws f1, f1
+; CHECK-BE-NEXT:    mffprwz r3, f1
+; CHECK-BE-NEXT:    mtfprwz f1, r3
+; CHECK-BE-NEXT:    xxperm v3, vs1, vs0
+; CHECK-BE-NEXT:    xscvspdpn f1, v2
+; CHECK-BE-NEXT:    xscvdpsxws f1, f1
+; CHECK-BE-NEXT:    mffprwz r3, f1
+; CHECK-BE-NEXT:    mtfprwz f1, r3
+; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    mtvsrwz v2, r3
 ; CHECK-BE-NEXT:    li r3, 0
-; CHECK-BE-NEXT:    vperm v2, v5, v2, v3
-; CHECK-BE-NEXT:    vmrghh v2, v2, v4
+; CHECK-BE-NEXT:    xxperm v2, vs1, vs0
+; CHECK-BE-NEXT:    vmrghh v2, v2, v3
 ; CHECK-BE-NEXT:    vextuwlx r3, r3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = fptosi <4 x float> %a to <4 x i8>
   %1 = bitcast <4 x i8> %0 to i32
   ret i32 %1
 }
 

 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test8elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI6_0@toc@ha
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI6_0@toc@l
-; CHECK-BE-NEXT:    lxv v2, 0(r3)
-; CHECK-BE-NEXT:    xxsldwi vs2, vs1, vs1, 3
-; CHECK-BE-NEXT:    xscvspdpn f2, vs2
-; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    xxswapd vs2, vs1
-; CHECK-BE-NEXT:    mtvsrwz v3, r3
-; CHECK-BE-NEXT:    xscvspdpn f2, vs2
-; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    xscvspdpn f2, vs1
+; CHECK-BE-NEXT:    lxv vs2, 0(r3)
+; CHECK-BE-NEXT:    xxsldwi vs3, vs1, vs1, 3
+; CHECK-BE-NEXT:    xscvspdpn f3, vs3
+; CHECK-BE-NEXT:    xscvdpsxws f3, f3
+; CHECK-BE-NEXT:    mffprwz r3, f3
+; CHECK-BE-NEXT:    xxswapd vs3, vs1
+; CHECK-BE-NEXT:    mtvsrwz v2, r3
+; CHECK-BE-NEXT:    xscvspdpn f3, vs3
+; CHECK-BE-NEXT:    xscvdpsxws f3, f3
+; CHECK-BE-NEXT:    mffprwz r3, f3
+; CHECK-BE-NEXT:    mtfprwz f3, r3
+; CHECK-BE-NEXT:    xxperm v2, vs3, vs2
+; CHECK-BE-NEXT:    xscvspdpn f3, vs1
 ; CHECK-BE-NEXT:    xxsldwi vs1, vs1, vs1, 1
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
-; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    vperm v3, v4, v3, v2
+; CHECK-BE-NEXT:    xscvdpsxws f3, f3
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mffprwz r3, f3
+; CHECK-BE-NEXT:    mtfprwz f3, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xxsldwi vs1, vs0, vs0, 3
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
-; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
+; CHECK-BE-NEXT:    xxperm v3, vs3, vs2
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    vmrghh v3, v4, v3
+; CHECK-BE-NEXT:    vmrghh v2, v3, v2
 ; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs0
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
 ; CHECK-BE-NEXT:    mffprwz r3, f1
+; CHECK-BE-NEXT:    mtfprwz f1, r3
+; CHECK-BE-NEXT:    xxperm v3, vs1, vs2
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs0
 ; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    vperm v4, v5, v4, v2
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    mtfprwz f1, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    mtvsrwz v0, r3
-; CHECK-BE-NEXT:    vperm v2, v5, v0, v2
-; CHECK-BE-NEXT:    vmrghh v2, v2, v4
-; CHECK-BE-NEXT:    vmrghw v2, v2, v3
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    xxperm v4, vs1, vs2
+; CHECK-BE-NEXT:    vmrghh v3, v4, v3
+; CHECK-BE-NEXT:    vmrghw v2, v3, v2
 ; CHECK-BE-NEXT:    mfvsrd r3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <8 x float>, <8 x float>* %0, align 32
   %1 = fptosi <8 x float> %a to <8 x i8>
   %2 = bitcast <8 x i8> %1 to i64
   ret i64 %2
 }

 ; CHECK-BE-LABEL: test16elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs3, 48(r3)
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    lxv vs2, 32(r3)
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI7_0@toc@ha
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI7_0@toc@l
-; CHECK-BE-NEXT:    lxv v2, 0(r3)
-; CHECK-BE-NEXT:    xxsldwi vs4, vs3, vs3, 3
-; CHECK-BE-NEXT:    xscvspdpn f4, vs4
-; CHECK-BE-NEXT:    xscvdpsxws f4, f4
-; CHECK-BE-NEXT:    mffprwz r3, f4
-; CHECK-BE-NEXT:    xxswapd vs4, vs3
-; CHECK-BE-NEXT:    mtvsrwz v3, r3
-; CHECK-BE-NEXT:    xscvspdpn f4, vs4
-; CHECK-BE-NEXT:    xscvdpsxws f4, f4
-; CHECK-BE-NEXT:    mffprwz r3, f4
-; CHECK-BE-NEXT:    xscvspdpn f4, vs3
+; CHECK-BE-NEXT:    lxv vs4, 0(r3)
+; CHECK-BE-NEXT:    xxsldwi vs5, vs3, vs3, 3
+; CHECK-BE-NEXT:    xscvspdpn f5, vs5
+; CHECK-BE-NEXT:    xscvdpsxws f5, f5
+; CHECK-BE-NEXT:    mffprwz r3, f5
+; CHECK-BE-NEXT:    xxswapd vs5, vs3
+; CHECK-BE-NEXT:    mtvsrwz v2, r3
+; CHECK-BE-NEXT:    xscvspdpn f5, vs5
+; CHECK-BE-NEXT:    xscvdpsxws f5, f5
+; CHECK-BE-NEXT:    mffprwz r3, f5
+; CHECK-BE-NEXT:    mtfprwz f5, r3
+; CHECK-BE-NEXT:    xxperm v2, vs5, vs4
+; CHECK-BE-NEXT:    xscvspdpn f5, vs3
 ; CHECK-BE-NEXT:    xxsldwi vs3, vs3, vs3, 1
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    xscvspdpn f3, vs3
-; CHECK-BE-NEXT:    xscvdpsxws f4, f4
-; CHECK-BE-NEXT:    vperm v3, v4, v3, v2
+; CHECK-BE-NEXT:    xscvdpsxws f5, f5
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    mffprwz r3, f4
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mffprwz r3, f5
+; CHECK-BE-NEXT:    mtfprwz f5, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f3
 ; CHECK-BE-NEXT:    xxsldwi vs3, vs2, vs2, 3
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    xscvspdpn f3, vs3
-; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
+; CHECK-BE-NEXT:    xxperm v3, vs5, vs4
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    vmrghh v3, v4, v3
+; CHECK-BE-NEXT:    vmrghh v2, v3, v2
 ; CHECK-BE-NEXT:    mffprwz r3, f3
 ; CHECK-BE-NEXT:    xxswapd vs3, vs2
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    xscvspdpn f3, vs3
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f3
 ; CHECK-BE-NEXT:    mffprwz r3, f3
+; CHECK-BE-NEXT:    mtfprwz f3, r3
+; CHECK-BE-NEXT:    xxperm v3, vs3, vs4
 ; CHECK-BE-NEXT:    xscvspdpn f3, vs2
 ; CHECK-BE-NEXT:    xxsldwi vs2, vs2, vs2, 1
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    xscvspdpn f2, vs2
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    vperm v4, v5, v4, v2
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
 ; CHECK-BE-NEXT:    mffprwz r3, f3
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    mtfprwz f3, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    xxsldwi vs2, vs1, vs1, 3
-; CHECK-BE-NEXT:    mtvsrwz v0, r3
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    xscvspdpn f2, vs2
-; CHECK-BE-NEXT:    vperm v5, v5, v0, v2
+; CHECK-BE-NEXT:    xxperm v4, vs3, vs4
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    vmrghh v4, v5, v4
-; CHECK-BE-NEXT:    vmrghw v3, v4, v3
+; CHECK-BE-NEXT:    vmrghh v3, v4, v3
+; CHECK-BE-NEXT:    vmrghw v2, v3, v2
 ; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    xxswapd vs2, vs1
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    xscvspdpn f2, vs2
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
 ; CHECK-BE-NEXT:    mffprwz r3, f2
+; CHECK-BE-NEXT:    mtfprwz f2, r3
+; CHECK-BE-NEXT:    xxperm v3, vs2, vs4
 ; CHECK-BE-NEXT:    xscvspdpn f2, vs1
 ; CHECK-BE-NEXT:    xxsldwi vs1, vs1, vs1, 1
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    vperm v4, v5, v4, v2
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
 ; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    mtfprwz f2, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xxsldwi vs1, vs0, vs0, 3
-; CHECK-BE-NEXT:    mtvsrwz v0, r3
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
-; CHECK-BE-NEXT:    vperm v5, v5, v0, v2
+; CHECK-BE-NEXT:    xxperm v4, vs2, vs4
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    vmrghh v4, v5, v4
+; CHECK-BE-NEXT:    vmrghh v3, v4, v3
 ; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs0
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
 ; CHECK-BE-NEXT:    mffprwz r3, f1
+; CHECK-BE-NEXT:    mtfprwz f1, r3
+; CHECK-BE-NEXT:    xxperm v4, vs1, vs4
 ; CHECK-BE-NEXT:    xscvspdpn f1, vs0
 ; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1
-; CHECK-BE-NEXT:    mtvsrwz v0, r3
 ; CHECK-BE-NEXT:    xscvspdpn f0, vs0
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    vperm v5, v0, v5, v2
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
 ; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    mtvsrwz v0, r3
+; CHECK-BE-NEXT:    mtfprwz f1, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    mtvsrwz v1, r3
-; CHECK-BE-NEXT:    vperm v2, v0, v1, v2
-; CHECK-BE-NEXT:    vmrghh v2, v2, v5
-; CHECK-BE-NEXT:    vmrghw v2, v2, v4
-; CHECK-BE-NEXT:    xxmrghd v2, v2, v3
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    xxperm v5, vs1, vs4
+; CHECK-BE-NEXT:    vmrghh v4, v5, v4
+; CHECK-BE-NEXT:    vmrghw v3, v4, v3
+; CHECK-BE-NEXT:    xxmrghd v2, v3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <16 x float>, <16 x float>* %0, align 64
   %1 = fptosi <16 x float> %a to <16 x i8>
   ret <16 x i8> %1
 }

llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i16_elts.ll

 ; CHECK-P9-NEXT:    mtvsrd v2, r3
 ; CHECK-P9-NEXT:    li r3, 0
 ; CHECK-P9-NEXT:    vmrghh v2, v3, v2
 ; CHECK-P9-NEXT:    vextuwrx r3, r3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2elt:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    xscvdpsxws f0, v2
+; CHECK-BE-NEXT:    xxswapd vs2, v2
+; CHECK-BE-NEXT:    xscvdpsxws f1, v2
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI0_0@toc@l
-; CHECK-BE-NEXT:    lxv v3, 0(r3)
-; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    xxswapd vs0, v2
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
-; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mffprwz r3, f0
+; CHECK-BE-NEXT:    xscvdpsxws f2, f2
+; CHECK-BE-NEXT:    lxv vs0, 0(r3)
+; CHECK-BE-NEXT:    mffprwz r3, f1
+; CHECK-BE-NEXT:    mtfprwz f1, r3
+; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    mtvsrwz v2, r3
 ; CHECK-BE-NEXT:    li r3, 0
-; CHECK-BE-NEXT:    vperm v2, v4, v2, v3
+; CHECK-BE-NEXT:    xxperm v2, vs1, vs0
 ; CHECK-BE-NEXT:    vextuwlx r3, r3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = fptoui <2 x double> %a to <2 x i16>
   %1 = bitcast <2 x i16> %0 to i32
   ret i32 %1
 }
 

 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test4elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI1_0@toc@l
-; CHECK-BE-NEXT:    lxv v2, 0(r3)
-; CHECK-BE-NEXT:    xscvdpsxws f2, f1
+; CHECK-BE-NEXT:    lxv vs2, 0(r3)
+; CHECK-BE-NEXT:    xscvdpsxws f3, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    mtvsrwz v3, r3
+; CHECK-BE-NEXT:    mffprwz r3, f3
+; CHECK-BE-NEXT:    mtfprwz f3, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, vs0
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mtvsrwz v2, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    vperm v3, v3, v4, v2
+; CHECK-BE-NEXT:    xxperm v2, vs3, vs2
 ; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mtfprwz f1, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
-; CHECK-BE-NEXT:    vperm v2, v4, v5, v2
-; CHECK-BE-NEXT:    vmrghw v2, v2, v3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
+; CHECK-BE-NEXT:    xxperm v3, vs1, vs2
+; CHECK-BE-NEXT:    vmrghw v2, v3, v2
 ; CHECK-BE-NEXT:    mfvsrd r3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <4 x double>, <4 x double>* %0, align 32
   %1 = fptoui <4 x double> %a to <4 x i16>
   %2 = bitcast <4 x i16> %1 to i64
   ret i64 %2
 }

 ; CHECK-BE-LABEL: test8elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs3, 48(r3)
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    lxv vs2, 32(r3)
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI2_0@toc@ha
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI2_0@toc@l
-; CHECK-BE-NEXT:    lxv v2, 0(r3)
-; CHECK-BE-NEXT:    xscvdpsxws f4, f3
+; CHECK-BE-NEXT:    lxv vs4, 0(r3)
+; CHECK-BE-NEXT:    xscvdpsxws f5, f3
 ; CHECK-BE-NEXT:    xxswapd vs3, vs3
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    mffprwz r3, f4
-; CHECK-BE-NEXT:    mtvsrwz v3, r3
+; CHECK-BE-NEXT:    mffprwz r3, f5
+; CHECK-BE-NEXT:    mtfprwz f5, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f3
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f2
 ; CHECK-BE-NEXT:    xxswapd vs2, vs2
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mtvsrwz v2, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    vperm v3, v3, v4, v2
+; CHECK-BE-NEXT:    xxperm v2, vs5, vs4
 ; CHECK-BE-NEXT:    mffprwz r3, f3
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mtfprwz f3, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs1
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
+; CHECK-BE-NEXT:    xxperm v3, vs3, vs4
 ; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    vmrghw v3, v4, v3
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    vmrghw v2, v3, v2
+; CHECK-BE-NEXT:    mtfprwz f2, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, vs0
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
+; CHECK-BE-NEXT:    xxperm v3, vs2, vs4
 ; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    mtfprwz f1, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    mtvsrwz v0, r3
-; CHECK-BE-NEXT:    vperm v2, v5, v0, v2
-; CHECK-BE-NEXT:    vmrghw v2, v2, v4
-; CHECK-BE-NEXT:    xxmrghd v2, v2, v3
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    xxperm v4, vs1, vs4
+; CHECK-BE-NEXT:    vmrghw v3, v4, v3
+; CHECK-BE-NEXT:    xxmrghd v2, v3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <8 x double>, <8 x double>* %0, align 64
   %1 = fptoui <8 x double> %a to <8 x i16>
   ret <8 x i16> %1
 }
 
 define void @test16elt(<16 x i16>* noalias nocapture sret(<16 x i16>) %agg.result, <16 x double>* nocapture readonly) local_unnamed_addr #3 {

 ; CHECK-P9-NEXT:    vmrghh v4, v4, v5
 ; CHECK-P9-NEXT:    vmrglw v3, v4, v3
 ; CHECK-P9-NEXT:    xxmrgld vs0, v3, v2
 ; CHECK-P9-NEXT:    stxv vs0, 16(r3)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test16elt:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    lxv vs3, 48(r4)
-; CHECK-BE-NEXT:    lxv vs2, 32(r4)
-; CHECK-BE-NEXT:    lxv vs1, 16(r4)
-; CHECK-BE-NEXT:    lxv vs0, 0(r4)
-; CHECK-BE-NEXT:    addis r5, r2, .LCPI3_0@toc@ha
-; CHECK-BE-NEXT:    addi r5, r5, .LCPI3_0@toc@l
-; CHECK-BE-NEXT:    lxv v2, 0(r5)
-; CHECK-BE-NEXT:    xscvdpsxws f4, f3
-; CHECK-BE-NEXT:    xscvdpsxws f5, f2
-; CHECK-BE-NEXT:    xscvdpsxws f6, f1
-; CHECK-BE-NEXT:    xxswapd vs3, vs3
-; CHECK-BE-NEXT:    xscvdpsxws f7, f0
-; CHECK-BE-NEXT:    xxswapd vs2, vs2
-; CHECK-BE-NEXT:    xxswapd vs1, vs1
-; CHECK-BE-NEXT:    xxswapd vs0, vs0
-; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mffprwz r5, f4
-; CHECK-BE-NEXT:    mtvsrwz v3, r5
-; CHECK-BE-NEXT:    mffprwz r5, f5
-; CHECK-BE-NEXT:    mtvsrwz v4, r5
-; CHECK-BE-NEXT:    mffprwz r5, f6
-; CHECK-BE-NEXT:    mtvsrwz v5, r5
-; CHECK-BE-NEXT:    mffprwz r5, f7
-; CHECK-BE-NEXT:    mtvsrwz v0, r5
-; CHECK-BE-NEXT:    mffprwz r5, f3
-; CHECK-BE-NEXT:    lxv vs3, 112(r4)
-; CHECK-BE-NEXT:    mtvsrwz v1, r5
-; CHECK-BE-NEXT:    mffprwz r5, f2
-; CHECK-BE-NEXT:    lxv vs2, 96(r4)
-; CHECK-BE-NEXT:    vperm v3, v3, v1, v2
-; CHECK-BE-NEXT:    mtvsrwz v1, r5
-; CHECK-BE-NEXT:    mffprwz r5, f1
+; CHECK-BE-NEXT:    lxv vs7, 48(r4)
+; CHECK-BE-NEXT:    lxv vs0, 64(r4)
 ; CHECK-BE-NEXT:    lxv vs1, 80(r4)
-; CHECK-BE-NEXT:    xscvdpsxws f4, f3
+; CHECK-BE-NEXT:    lxv vs2, 96(r4)
+; CHECK-BE-NEXT:    xscvdpsxws f9, f7
+; CHECK-BE-NEXT:    xxswapd vs7, vs7
+; CHECK-BE-NEXT:    lxv vs3, 112(r4)
+; CHECK-BE-NEXT:    lxv vs4, 0(r4)
+; CHECK-BE-NEXT:    lxv vs5, 16(r4)
+; CHECK-BE-NEXT:    lxv vs6, 32(r4)
+; CHECK-BE-NEXT:    addis r4, r2, .LCPI3_0@toc@ha
+; CHECK-BE-NEXT:    addi r4, r4, .LCPI3_0@toc@l
+; CHECK-BE-NEXT:    lxv vs8, 0(r4)
+; CHECK-BE-NEXT:    xscvdpsxws f7, f7
+; CHECK-BE-NEXT:    mffprwz r4, f9
+; CHECK-BE-NEXT:    mtfprwz f9, r4
+; CHECK-BE-NEXT:    mffprwz r4, f7
+; CHECK-BE-NEXT:    xscvdpsxws f7, f6
+; CHECK-BE-NEXT:    xxswapd vs6, vs6
+; CHECK-BE-NEXT:    mtvsrwz v2, r4
+; CHECK-BE-NEXT:    xscvdpsxws f6, f6
+; CHECK-BE-NEXT:    xxperm v2, vs9, vs8
+; CHECK-BE-NEXT:    mffprwz r4, f7
+; CHECK-BE-NEXT:    mtfprwz f7, r4
+; CHECK-BE-NEXT:    mffprwz r4, f6
+; CHECK-BE-NEXT:    xscvdpsxws f6, f5
+; CHECK-BE-NEXT:    xxswapd vs5, vs5
+; CHECK-BE-NEXT:    mtvsrwz v3, r4
+; CHECK-BE-NEXT:    xscvdpsxws f5, f5
+; CHECK-BE-NEXT:    xxperm v3, vs7, vs8
+; CHECK-BE-NEXT:    mffprwz r4, f6
+; CHECK-BE-NEXT:    vmrghw v2, v3, v2
+; CHECK-BE-NEXT:    mtfprwz f6, r4
+; CHECK-BE-NEXT:    mffprwz r4, f5
+; CHECK-BE-NEXT:    xscvdpsxws f5, f4
+; CHECK-BE-NEXT:    xxswapd vs4, vs4
+; CHECK-BE-NEXT:    mtvsrwz v4, r4
+; CHECK-BE-NEXT:    xscvdpsxws f4, f4
+; CHECK-BE-NEXT:    xxperm v4, vs6, vs8
+; CHECK-BE-NEXT:    xscvdpsxws f6, f3
 ; CHECK-BE-NEXT:    xxswapd vs3, vs3
-; CHECK-BE-NEXT:    vperm v4, v4, v1, v2
-; CHECK-BE-NEXT:    mtvsrwz v1, r5
-; CHECK-BE-NEXT:    mffprwz r5, f0
-; CHECK-BE-NEXT:    lxv vs0, 64(r4)
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    vperm v5, v5, v1, v2
-; CHECK-BE-NEXT:    mtvsrwz v1, r5
-; CHECK-BE-NEXT:    vmrghw v3, v4, v3
-; CHECK-BE-NEXT:    vperm v0, v0, v1, v2
+; CHECK-BE-NEXT:    mffprwz r4, f5
+; CHECK-BE-NEXT:    mtfprwz f5, r4
+; CHECK-BE-NEXT:    mffprwz r4, f6
+; CHECK-BE-NEXT:    mtfprwz f6, r4
 ; CHECK-BE-NEXT:    mffprwz r4, f4
-; CHECK-BE-NEXT:    vmrghw v5, v0, v5
-; CHECK-BE-NEXT:    mtvsrwz v4, r4
+; CHECK-BE-NEXT:    mtvsrwz v3, r4
 ; CHECK-BE-NEXT:    mffprwz r4, f3
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f2
 ; CHECK-BE-NEXT:    xxswapd vs2, vs2
-; CHECK-BE-NEXT:    xxmrghd vs4, v5, v3
-; CHECK-BE-NEXT:    mtvsrwz v3, r4
+; CHECK-BE-NEXT:    xxperm v3, vs5, vs8
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    vperm v3, v4, v3, v2
-; CHECK-BE-NEXT:    stxv vs4, 0(r3)
+; CHECK-BE-NEXT:    vmrghw v3, v3, v4
+; CHECK-BE-NEXT:    xxmrghd vs4, v3, v2
+; CHECK-BE-NEXT:    mtvsrwz v2, r4
 ; CHECK-BE-NEXT:    mffprwz r4, f3
-; CHECK-BE-NEXT:    mtvsrwz v4, r4
+; CHECK-BE-NEXT:    mtfprwz f3, r4
 ; CHECK-BE-NEXT:    mffprwz r4, f2
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs1
-; CHECK-BE-NEXT:    mtvsrwz v5, r4
+; CHECK-BE-NEXT:    xxperm v2, vs6, vs8
+; CHECK-BE-NEXT:    mtvsrwz v3, r4
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
+; CHECK-BE-NEXT:    xxperm v3, vs3, vs8
 ; CHECK-BE-NEXT:    mffprwz r4, f2
-; CHECK-BE-NEXT:    vmrghw v3, v4, v3
-; CHECK-BE-NEXT:    mtvsrwz v4, r4
+; CHECK-BE-NEXT:    vmrghw v2, v3, v2
+; CHECK-BE-NEXT:    mtfprwz f2, r4
 ; CHECK-BE-NEXT:    mffprwz r4, f1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, vs0
-; CHECK-BE-NEXT:    mtvsrwz v5, r4
+; CHECK-BE-NEXT:    mtvsrwz v3, r4
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
+; CHECK-BE-NEXT:    xxperm v3, vs2, vs8
 ; CHECK-BE-NEXT:    mffprwz r4, f1
-; CHECK-BE-NEXT:    mtvsrwz v5, r4
+; CHECK-BE-NEXT:    mtfprwz f1, r4
 ; CHECK-BE-NEXT:    mffprwz r4, f0
-; CHECK-BE-NEXT:    mtvsrwz v0, r4
-; CHECK-BE-NEXT:    vperm v2, v5, v0, v2
-; CHECK-BE-NEXT:    vmrghw v2, v2, v4
-; CHECK-BE-NEXT:    xxmrghd vs0, v2, v3
+; CHECK-BE-NEXT:    mtvsrwz v4, r4
+; CHECK-BE-NEXT:    xxperm v4, vs1, vs8
+; CHECK-BE-NEXT:    stxv vs4, 0(r3)
+; CHECK-BE-NEXT:    vmrghw v3, v4, v3
+; CHECK-BE-NEXT:    xxmrghd vs0, v3, v2
 ; CHECK-BE-NEXT:    stxv vs0, 16(r3)
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <16 x double>, <16 x double>* %0, align 128
   %1 = fptoui <16 x double> %a to <16 x i16>
   store <16 x i16> %1, <16 x i16>* %agg.result, align 32
   ret void
 }

 ; CHECK-P9-NEXT:    mtvsrd v2, r3
 ; CHECK-P9-NEXT:    li r3, 0
 ; CHECK-P9-NEXT:    vmrghh v2, v3, v2
 ; CHECK-P9-NEXT:    vextuwrx r3, r3, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    xscvdpsxws f0, v2
+; CHECK-BE-NEXT:    xxswapd vs2, v2
+; CHECK-BE-NEXT:    xscvdpsxws f1, v2
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI4_0@toc@l
-; CHECK-BE-NEXT:    lxv v3, 0(r3)
-; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    xxswapd vs0, v2
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
-; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mffprwz r3, f0
+; CHECK-BE-NEXT:    xscvdpsxws f2, f2
+; CHECK-BE-NEXT:    lxv vs0, 0(r3)
+; CHECK-BE-NEXT:    mffprwz r3, f1
+; CHECK-BE-NEXT:    mtfprwz f1, r3
+; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    mtvsrwz v2, r3
 ; CHECK-BE-NEXT:    li r3, 0
-; CHECK-BE-NEXT:    vperm v2, v4, v2, v3
+; CHECK-BE-NEXT:    xxperm v2, vs1, vs0
 ; CHECK-BE-NEXT:    vextuwlx r3, r3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = fptosi <2 x double> %a to <2 x i16>
   %1 = bitcast <2 x i16> %0 to i32
   ret i32 %1
 }
 

 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test4elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI5_0@toc@ha
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI5_0@toc@l
-; CHECK-BE-NEXT:    lxv v2, 0(r3)
-; CHECK-BE-NEXT:    xscvdpsxws f2, f1
+; CHECK-BE-NEXT:    lxv vs2, 0(r3)
+; CHECK-BE-NEXT:    xscvdpsxws f3, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    mtvsrwz v3, r3
+; CHECK-BE-NEXT:    mffprwz r3, f3
+; CHECK-BE-NEXT:    mtfprwz f3, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, vs0
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mtvsrwz v2, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    vperm v3, v3, v4, v2
+; CHECK-BE-NEXT:    xxperm v2, vs3, vs2
 ; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mtfprwz f1, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
-; CHECK-BE-NEXT:    vperm v2, v4, v5, v2
-; CHECK-BE-NEXT:    vmrghw v2, v2, v3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
+; CHECK-BE-NEXT:    xxperm v3, vs1, vs2
+; CHECK-BE-NEXT:    vmrghw v2, v3, v2
 ; CHECK-BE-NEXT:    mfvsrd r3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <4 x double>, <4 x double>* %0, align 32
   %1 = fptosi <4 x double> %a to <4 x i16>
   %2 = bitcast <4 x i16> %1 to i64
   ret i64 %2
 }

 ; CHECK-BE-LABEL: test8elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs3, 48(r3)
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    lxv vs2, 32(r3)
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI6_0@toc@ha
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI6_0@toc@l
-; CHECK-BE-NEXT:    lxv v2, 0(r3)
-; CHECK-BE-NEXT:    xscvdpsxws f4, f3
+; CHECK-BE-NEXT:    lxv vs4, 0(r3)
+; CHECK-BE-NEXT:    xscvdpsxws f5, f3
 ; CHECK-BE-NEXT:    xxswapd vs3, vs3
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    mffprwz r3, f4
-; CHECK-BE-NEXT:    mtvsrwz v3, r3
+; CHECK-BE-NEXT:    mffprwz r3, f5
+; CHECK-BE-NEXT:    mtfprwz f5, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f3
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f2
 ; CHECK-BE-NEXT:    xxswapd vs2, vs2
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mtvsrwz v2, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    vperm v3, v3, v4, v2
+; CHECK-BE-NEXT:    xxperm v2, vs5, vs4
 ; CHECK-BE-NEXT:    mffprwz r3, f3
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mtfprwz f3, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs1
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
+; CHECK-BE-NEXT:    xxperm v3, vs3, vs4
 ; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    vmrghw v3, v4, v3
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    vmrghw v2, v3, v2
+; CHECK-BE-NEXT:    mtfprwz f2, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, vs0
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
+; CHECK-BE-NEXT:    xxperm v3, vs2, vs4
 ; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    mtfprwz f1, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    mtvsrwz v0, r3
-; CHECK-BE-NEXT:    vperm v2, v5, v0, v2
-; CHECK-BE-NEXT:    vmrghw v2, v2, v4
-; CHECK-BE-NEXT:    xxmrghd v2, v2, v3
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    xxperm v4, vs1, vs4
+; CHECK-BE-NEXT:    vmrghw v3, v4, v3
+; CHECK-BE-NEXT:    xxmrghd v2, v3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <8 x double>, <8 x double>* %0, align 64
   %1 = fptosi <8 x double> %a to <8 x i16>
   ret <8 x i16> %1
 }
 
 define void @test16elt_signed(<16 x i16>* noalias nocapture sret(<16 x i16>) %agg.result, <16 x double>* nocapture readonly) local_unnamed_addr #3 {

 ; CHECK-P9-NEXT:    vmrghh v4, v4, v5
 ; CHECK-P9-NEXT:    vmrglw v3, v4, v3
 ; CHECK-P9-NEXT:    xxmrgld vs0, v3, v2
 ; CHECK-P9-NEXT:    stxv vs0, 16(r3)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test16elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    lxv vs3, 48(r4)
-; CHECK-BE-NEXT:    lxv vs2, 32(r4)
-; CHECK-BE-NEXT:    lxv vs1, 16(r4)
-; CHECK-BE-NEXT:    lxv vs0, 0(r4)
-; CHECK-BE-NEXT:    addis r5, r2, .LCPI7_0@toc@ha
-; CHECK-BE-NEXT:    addi r5, r5, .LCPI7_0@toc@l
-; CHECK-BE-NEXT:    lxv v2, 0(r5)
-; CHECK-BE-NEXT:    xscvdpsxws f4, f3
-; CHECK-BE-NEXT:    xscvdpsxws f5, f2
-; CHECK-BE-NEXT:    xscvdpsxws f6, f1
-; CHECK-BE-NEXT:    xxswapd vs3, vs3
-; CHECK-BE-NEXT:    xscvdpsxws f7, f0
-; CHECK-BE-NEXT:    xxswapd vs2, vs2
-; CHECK-BE-NEXT:    xxswapd vs1, vs1
-; CHECK-BE-NEXT:    xxswapd vs0, vs0
-; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mffprwz r5, f4
-; CHECK-BE-NEXT:    mtvsrwz v3, r5
-; CHECK-BE-NEXT:    mffprwz r5, f5
-; CHECK-BE-NEXT:    mtvsrwz v4, r5
-; CHECK-BE-NEXT:    mffprwz r5, f6
-; CHECK-BE-NEXT:    mtvsrwz v5, r5
-; CHECK-BE-NEXT:    mffprwz r5, f7
-; CHECK-BE-NEXT:    mtvsrwz v0, r5
-; CHECK-BE-NEXT:    mffprwz r5, f3
-; CHECK-BE-NEXT:    lxv vs3, 112(r4)
-; CHECK-BE-NEXT:    mtvsrwz v1, r5
-; CHECK-BE-NEXT:    mffprwz r5, f2
-; CHECK-BE-NEXT:    lxv vs2, 96(r4)
-; CHECK-BE-NEXT:    vperm v3, v3, v1, v2
-; CHECK-BE-NEXT:    mtvsrwz v1, r5
-; CHECK-BE-NEXT:    mffprwz r5, f1
+; CHECK-BE-NEXT:    lxv vs7, 48(r4)
+; CHECK-BE-NEXT:    lxv vs0, 64(r4)
 ; CHECK-BE-NEXT:    lxv vs1, 80(r4)
-; CHECK-BE-NEXT:    xscvdpsxws f4, f3
+; CHECK-BE-NEXT:    lxv vs2, 96(r4)
+; CHECK-BE-NEXT:    xscvdpsxws f9, f7
+; CHECK-BE-NEXT:    xxswapd vs7, vs7
+; CHECK-BE-NEXT:    lxv vs3, 112(r4)
+; CHECK-BE-NEXT:    lxv vs4, 0(r4)
+; CHECK-BE-NEXT:    lxv vs5, 16(r4)
+; CHECK-BE-NEXT:    lxv vs6, 32(r4)
+; CHECK-BE-NEXT:    addis r4, r2, .LCPI7_0@toc@ha
+; CHECK-BE-NEXT:    addi r4, r4, .LCPI7_0@toc@l
+; CHECK-BE-NEXT:    lxv vs8, 0(r4)
+; CHECK-BE-NEXT:    xscvdpsxws f7, f7
+; CHECK-BE-NEXT:    mffprwz r4, f9
+; CHECK-BE-NEXT:    mtfprwz f9, r4
+; CHECK-BE-NEXT:    mffprwz r4, f7
+; CHECK-BE-NEXT:    xscvdpsxws f7, f6
+; CHECK-BE-NEXT:    xxswapd vs6, vs6
+; CHECK-BE-NEXT:    mtvsrwz v2, r4
+; CHECK-BE-NEXT:    xscvdpsxws f6, f6
+; CHECK-BE-NEXT:    xxperm v2, vs9, vs8
+; CHECK-BE-NEXT:    mffprwz r4, f7
+; CHECK-BE-NEXT:    mtfprwz f7, r4
+; CHECK-BE-NEXT:    mffprwz r4, f6
+; CHECK-BE-NEXT:    xscvdpsxws f6, f5
+; CHECK-BE-NEXT:    xxswapd vs5, vs5
+; CHECK-BE-NEXT:    mtvsrwz v3, r4
+; CHECK-BE-NEXT:    xscvdpsxws f5, f5
+; CHECK-BE-NEXT:    xxperm v3, vs7, vs8
+; CHECK-BE-NEXT:    mffprwz r4, f6
+; CHECK-BE-NEXT:    vmrghw v2, v3, v2
+; CHECK-BE-NEXT:    mtfprwz f6, r4
+; CHECK-BE-NEXT:    mffprwz r4, f5
+; CHECK-BE-NEXT:    xscvdpsxws f5, f4
+; CHECK-BE-NEXT:    xxswapd vs4, vs4
+; CHECK-BE-NEXT:    mtvsrwz v4, r4
+; CHECK-BE-NEXT:    xscvdpsxws f4, f4
+; CHECK-BE-NEXT:    xxperm v4, vs6, vs8
+; CHECK-BE-NEXT:    xscvdpsxws f6, f3
 ; CHECK-BE-NEXT:    xxswapd vs3, vs3
-; CHECK-BE-NEXT:    vperm v4, v4, v1, v2
-; CHECK-BE-NEXT:    mtvsrwz v1, r5
-; CHECK-BE-NEXT:    mffprwz r5, f0
-; CHECK-BE-NEXT:    lxv vs0, 64(r4)
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    vperm v5, v5, v1, v2
-; CHECK-BE-NEXT:    mtvsrwz v1, r5
-; CHECK-BE-NEXT:    vmrghw v3, v4, v3
-; CHECK-BE-NEXT:    vperm v0, v0, v1, v2
+; CHECK-BE-NEXT:    mffprwz r4, f5
+; CHECK-BE-NEXT:    mtfprwz f5, r4
+; CHECK-BE-NEXT:    mffprwz r4, f6
+; CHECK-BE-NEXT:    mtfprwz f6, r4
 ; CHECK-BE-NEXT:    mffprwz r4, f4
-; CHECK-BE-NEXT:    vmrghw v5, v0, v5
-; CHECK-BE-NEXT:    mtvsrwz v4, r4
+; CHECK-BE-NEXT:    mtvsrwz v3, r4
 ; CHECK-BE-NEXT:    mffprwz r4, f3
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f2
 ; CHECK-BE-NEXT:    xxswapd vs2, vs2
-; CHECK-BE-NEXT:    xxmrghd vs4, v5, v3
-; CHECK-BE-NEXT:    mtvsrwz v3, r4
+; CHECK-BE-NEXT:    xxperm v3, vs5, vs8
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    vperm v3, v4, v3, v2
-; CHECK-BE-NEXT:    stxv vs4, 0(r3)
+; CHECK-BE-NEXT:    vmrghw v3, v3, v4
+; CHECK-BE-NEXT:    xxmrghd vs4, v3, v2
+; CHECK-BE-NEXT:    mtvsrwz v2, r4
 ; CHECK-BE-NEXT:    mffprwz r4, f3
-; CHECK-BE-NEXT:    mtvsrwz v4, r4
+; CHECK-BE-NEXT:    mtfprwz f3, r4
 ; CHECK-BE-NEXT:    mffprwz r4, f2
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs1
-; CHECK-BE-NEXT:    mtvsrwz v5, r4
+; CHECK-BE-NEXT:    xxperm v2, vs6, vs8
+; CHECK-BE-NEXT:    mtvsrwz v3, r4
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
+; CHECK-BE-NEXT:    xxperm v3, vs3, vs8
 ; CHECK-BE-NEXT:    mffprwz r4, f2
-; CHECK-BE-NEXT:    vmrghw v3, v4, v3
-; CHECK-BE-NEXT:    mtvsrwz v4, r4
+; CHECK-BE-NEXT:    vmrghw v2, v3, v2
+; CHECK-BE-NEXT:    mtfprwz f2, r4
 ; CHECK-BE-NEXT:    mffprwz r4, f1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, vs0
-; CHECK-BE-NEXT:    mtvsrwz v5, r4
+; CHECK-BE-NEXT:    mtvsrwz v3, r4
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
+; CHECK-BE-NEXT:    xxperm v3, vs2, vs8
 ; CHECK-BE-NEXT:    mffprwz r4, f1
-; CHECK-BE-NEXT:    mtvsrwz v5, r4
+; CHECK-BE-NEXT:    mtfprwz f1, r4
 ; CHECK-BE-NEXT:    mffprwz r4, f0
-; CHECK-BE-NEXT:    mtvsrwz v0, r4
-; CHECK-BE-NEXT:    vperm v2, v5, v0, v2
-; CHECK-BE-NEXT:    vmrghw v2, v2, v4
-; CHECK-BE-NEXT:    xxmrghd vs0, v2, v3
+; CHECK-BE-NEXT:    mtvsrwz v4, r4
+; CHECK-BE-NEXT:    xxperm v4, vs1, vs8
+; CHECK-BE-NEXT:    stxv vs4, 0(r3)
+; CHECK-BE-NEXT:    vmrghw v3, v4, v3
+; CHECK-BE-NEXT:    xxmrghd vs0, v3, v2
 ; CHECK-BE-NEXT:    stxv vs0, 16(r3)
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <16 x double>, <16 x double>* %0, align 128
   %1 = fptosi <16 x double> %a to <16 x i16>
   store <16 x i16> %1, <16 x i16>* %agg.result, align 32
   ret void
 }

llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i8_elts.ll

 ; CHECK-P9-NEXT:    vmrghb v2, v3, v2
 ; CHECK-P9-NEXT:    vsldoi v2, v2, v2, 8
 ; CHECK-P9-NEXT:    stxsihx v2, 0, r3
 ; CHECK-P9-NEXT:    lhz r3, -2(r1)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2elt:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    xscvdpsxws f0, v2
+; CHECK-BE-NEXT:    xxswapd vs2, v2
+; CHECK-BE-NEXT:    xscvdpsxws f1, v2
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI0_0@toc@l
-; CHECK-BE-NEXT:    lxv v3, 0(r3)
-; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    xxswapd vs0, v2
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
-; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mffprwz r3, f0
+; CHECK-BE-NEXT:    xscvdpsxws f2, f2
+; CHECK-BE-NEXT:    lxv vs0, 0(r3)
+; CHECK-BE-NEXT:    mffprwz r3, f1
+; CHECK-BE-NEXT:    mtfprwz f1, r3
+; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    mtvsrwz v2, r3
 ; CHECK-BE-NEXT:    addi r3, r1, -2
-; CHECK-BE-NEXT:    vperm v2, v4, v2, v3
+; CHECK-BE-NEXT:    xxperm v2, vs1, vs0
 ; CHECK-BE-NEXT:    vsldoi v2, v2, v2, 10
 ; CHECK-BE-NEXT:    stxsihx v2, 0, r3
 ; CHECK-BE-NEXT:    lhz r3, -2(r1)
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = fptoui <2 x double> %a to <2 x i8>
   %1 = bitcast <2 x i8> %0 to i16
   ret i16 %1

 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test4elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI1_0@toc@l
-; CHECK-BE-NEXT:    lxv v2, 0(r3)
-; CHECK-BE-NEXT:    xscvdpsxws f2, f1
+; CHECK-BE-NEXT:    lxv vs2, 0(r3)
+; CHECK-BE-NEXT:    xscvdpsxws f3, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    mtvsrwz v3, r3
+; CHECK-BE-NEXT:    mffprwz r3, f3
+; CHECK-BE-NEXT:    mtfprwz f3, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, vs0
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mtvsrwz v2, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    vperm v3, v3, v4, v2
+; CHECK-BE-NEXT:    xxperm v2, vs3, vs2
 ; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mtfprwz f1, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    li r3, 0
-; CHECK-BE-NEXT:    vperm v2, v4, v5, v2
-; CHECK-BE-NEXT:    vmrghh v2, v2, v3
+; CHECK-BE-NEXT:    xxperm v3, vs1, vs2
+; CHECK-BE-NEXT:    vmrghh v2, v3, v2
 ; CHECK-BE-NEXT:    vextuwlx r3, r3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <4 x double>, <4 x double>* %0, align 32
   %1 = fptoui <4 x double> %a to <4 x i8>
   %2 = bitcast <4 x i8> %1 to i32
   ret i32 %2
 }

 ; CHECK-BE-LABEL: test8elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs3, 48(r3)
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    lxv vs2, 32(r3)
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI2_0@toc@ha
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI2_0@toc@l
-; CHECK-BE-NEXT:    lxv v2, 0(r3)
-; CHECK-BE-NEXT:    xscvdpsxws f4, f3
+; CHECK-BE-NEXT:    lxv vs4, 0(r3)
+; CHECK-BE-NEXT:    xscvdpsxws f5, f3
 ; CHECK-BE-NEXT:    xxswapd vs3, vs3
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    mffprwz r3, f4
-; CHECK-BE-NEXT:    mtvsrwz v3, r3
+; CHECK-BE-NEXT:    mffprwz r3, f5
+; CHECK-BE-NEXT:    mtfprwz f5, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f3
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f2
 ; CHECK-BE-NEXT:    xxswapd vs2, vs2
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mtvsrwz v2, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    vperm v3, v3, v4, v2
+; CHECK-BE-NEXT:    xxperm v2, vs5, vs4
 ; CHECK-BE-NEXT:    mffprwz r3, f3
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mtfprwz f3, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs1
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
+; CHECK-BE-NEXT:    xxperm v3, vs3, vs4
 ; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    vmrghh v3, v4, v3
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    vmrghh v2, v3, v2
+; CHECK-BE-NEXT:    mtfprwz f2, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, vs0
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
+; CHECK-BE-NEXT:    xxperm v3, vs2, vs4
 ; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    mtfprwz f1, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    mtvsrwz v0, r3
-; CHECK-BE-NEXT:    vperm v2, v5, v0, v2
-; CHECK-BE-NEXT:    vmrghh v2, v2, v4
-; CHECK-BE-NEXT:    vmrghw v2, v2, v3
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    xxperm v4, vs1, vs4
+; CHECK-BE-NEXT:    vmrghh v3, v4, v3
+; CHECK-BE-NEXT:    vmrghw v2, v3, v2
 ; CHECK-BE-NEXT:    mfvsrd r3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <8 x double>, <8 x double>* %0, align 64
   %1 = fptoui <8 x double> %a to <8 x i8>
   %2 = bitcast <8 x i8> %1 to i64
   ret i64 %2
 }

 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test16elt:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs7, 112(r3)
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    lxv vs2, 32(r3)
-; CHECK-BE-NEXT:    xscvdpsxws f8, f7
+; CHECK-BE-NEXT:    xscvdpsxws f9, f7
 ; CHECK-BE-NEXT:    xxswapd vs7, vs7
 ; CHECK-BE-NEXT:    lxv vs3, 48(r3)
 ; CHECK-BE-NEXT:    lxv vs4, 64(r3)
 ; CHECK-BE-NEXT:    lxv vs5, 80(r3)
 ; CHECK-BE-NEXT:    lxv vs6, 96(r3)
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI3_0@toc@ha
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI3_0@toc@l
-; CHECK-BE-NEXT:    lxv v2, 0(r3)
+; CHECK-BE-NEXT:    lxv vs8, 0(r3)
 ; CHECK-BE-NEXT:    xscvdpsxws f7, f7
-; CHECK-BE-NEXT:    mffprwz r3, f8
-; CHECK-BE-NEXT:    mtvsrwz v3, r3
+; CHECK-BE-NEXT:    mffprwz r3, f9
+; CHECK-BE-NEXT:    mtfprwz f9, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f7
 ; CHECK-BE-NEXT:    xscvdpsxws f7, f6
 ; CHECK-BE-NEXT:    xxswapd vs6, vs6
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mtvsrwz v2, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f6, f6
-; CHECK-BE-NEXT:    vperm v3, v3, v4, v2
+; CHECK-BE-NEXT:    xxperm v2, vs9, vs8
 ; CHECK-BE-NEXT:    mffprwz r3, f7
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mtfprwz f7, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f6
 ; CHECK-BE-NEXT:    xscvdpsxws f6, f5
 ; CHECK-BE-NEXT:    xxswapd vs5, vs5
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f5, f5
-; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
+; CHECK-BE-NEXT:    xxperm v3, vs7, vs8
 ; CHECK-BE-NEXT:    mffprwz r3, f6
-; CHECK-BE-NEXT:    vmrghh v3, v4, v3
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    vmrghh v2, v3, v2
+; CHECK-BE-NEXT:    mtfprwz f6, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f5
 ; CHECK-BE-NEXT:    xscvdpsxws f5, f4
 ; CHECK-BE-NEXT:    xxswapd vs4, vs4
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f4, f4
-; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
+; CHECK-BE-NEXT:    xxperm v3, vs6, vs8
 ; CHECK-BE-NEXT:    mffprwz r3, f5
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    mtfprwz f5, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f4
 ; CHECK-BE-NEXT:    xscvdpsxws f4, f3
 ; CHECK-BE-NEXT:    xxswapd vs3, vs3
-; CHECK-BE-NEXT:    mtvsrwz v0, r3
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    vperm v5, v5, v0, v2
-; CHECK-BE-NEXT:    vmrghh v4, v5, v4
+; CHECK-BE-NEXT:    xxperm v4, vs5, vs8
 ; CHECK-BE-NEXT:    mffprwz r3, f4
-; CHECK-BE-NEXT:    vmrghw v3, v4, v3
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    vmrghh v3, v4, v3
+; CHECK-BE-NEXT:    mtfprwz f4, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f3
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f2
 ; CHECK-BE-NEXT:    xxswapd vs2, vs2
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    vmrghw v2, v3, v2
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
+; CHECK-BE-NEXT:    xxperm v3, vs4, vs8
 ; CHECK-BE-NEXT:    mffprwz r3, f3
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    mtfprwz f3, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs1
-; CHECK-BE-NEXT:    mtvsrwz v0, r3
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    vperm v5, v5, v0, v2
+; CHECK-BE-NEXT:    xxperm v4, vs3, vs8
 ; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    vmrghh v4, v5, v4
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    vmrghh v3, v4, v3
+; CHECK-BE-NEXT:    mtfprwz f2, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, vs0
-; CHECK-BE-NEXT:    mtvsrwz v0, r3
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    vperm v5, v5, v0, v2
+; CHECK-BE-NEXT:    xxperm v4, vs2, vs8
 ; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    mtvsrwz v0, r3
+; CHECK-BE-NEXT:    mtfprwz f1, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    mtvsrwz v1, r3
-; CHECK-BE-NEXT:    vperm v2, v0, v1, v2
-; CHECK-BE-NEXT:    vmrghh v2, v2, v5
-; CHECK-BE-NEXT:    vmrghw v2, v2, v4
-; CHECK-BE-NEXT:    xxmrghd v2, v2, v3
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    xxperm v5, vs1, vs8
+; CHECK-BE-NEXT:    vmrghh v4, v5, v4
+; CHECK-BE-NEXT:    vmrghw v3, v4, v3
+; CHECK-BE-NEXT:    xxmrghd v2, v3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <16 x double>, <16 x double>* %0, align 128
   %1 = fptoui <16 x double> %a to <16 x i8>
   ret <16 x i8> %1
 }
 
 define i16 @test2elt_signed(<2 x double> %a) local_unnamed_addr #0 {

 ; CHECK-P9-NEXT:    vmrghb v2, v3, v2
 ; CHECK-P9-NEXT:    vsldoi v2, v2, v2, 8
 ; CHECK-P9-NEXT:    stxsihx v2, 0, r3
 ; CHECK-P9-NEXT:    lhz r3, -2(r1)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    xscvdpsxws f0, v2
+; CHECK-BE-NEXT:    xxswapd vs2, v2
+; CHECK-BE-NEXT:    xscvdpsxws f1, v2
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI4_0@toc@l
-; CHECK-BE-NEXT:    lxv v3, 0(r3)
-; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    xxswapd vs0, v2
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
-; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    mffprwz r3, f0
+; CHECK-BE-NEXT:    xscvdpsxws f2, f2
+; CHECK-BE-NEXT:    lxv vs0, 0(r3)
+; CHECK-BE-NEXT:    mffprwz r3, f1
+; CHECK-BE-NEXT:    mtfprwz f1, r3
+; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    mtvsrwz v2, r3
 ; CHECK-BE-NEXT:    addi r3, r1, -2
-; CHECK-BE-NEXT:    vperm v2, v4, v2, v3
+; CHECK-BE-NEXT:    xxperm v2, vs1, vs0
 ; CHECK-BE-NEXT:    vsldoi v2, v2, v2, 10
 ; CHECK-BE-NEXT:    stxsihx v2, 0, r3
 ; CHECK-BE-NEXT:    lhz r3, -2(r1)
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = fptosi <2 x double> %a to <2 x i8>
   %1 = bitcast <2 x i8> %0 to i16
   ret i16 %1

 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test4elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI5_0@toc@ha
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI5_0@toc@l
-; CHECK-BE-NEXT:    lxv v2, 0(r3)
-; CHECK-BE-NEXT:    xscvdpsxws f2, f1
+; CHECK-BE-NEXT:    lxv vs2, 0(r3)
+; CHECK-BE-NEXT:    xscvdpsxws f3, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    mtvsrwz v3, r3
+; CHECK-BE-NEXT:    mffprwz r3, f3
+; CHECK-BE-NEXT:    mtfprwz f3, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, vs0
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mtvsrwz v2, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    vperm v3, v3, v4, v2
+; CHECK-BE-NEXT:    xxperm v2, vs3, vs2
 ; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mtfprwz f1, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    li r3, 0
-; CHECK-BE-NEXT:    vperm v2, v4, v5, v2
-; CHECK-BE-NEXT:    vmrghh v2, v2, v3
+; CHECK-BE-NEXT:    xxperm v3, vs1, vs2
+; CHECK-BE-NEXT:    vmrghh v2, v3, v2
 ; CHECK-BE-NEXT:    vextuwlx r3, r3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <4 x double>, <4 x double>* %0, align 32
   %1 = fptosi <4 x double> %a to <4 x i8>
   %2 = bitcast <4 x i8> %1 to i32
   ret i32 %2
 }

 ; CHECK-BE-LABEL: test8elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs3, 48(r3)
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    lxv vs2, 32(r3)
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI6_0@toc@ha
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI6_0@toc@l
-; CHECK-BE-NEXT:    lxv v2, 0(r3)
-; CHECK-BE-NEXT:    xscvdpsxws f4, f3
+; CHECK-BE-NEXT:    lxv vs4, 0(r3)
+; CHECK-BE-NEXT:    xscvdpsxws f5, f3
 ; CHECK-BE-NEXT:    xxswapd vs3, vs3
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    mffprwz r3, f4
-; CHECK-BE-NEXT:    mtvsrwz v3, r3
+; CHECK-BE-NEXT:    mffprwz r3, f5
+; CHECK-BE-NEXT:    mtfprwz f5, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f3
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f2
 ; CHECK-BE-NEXT:    xxswapd vs2, vs2
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mtvsrwz v2, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    vperm v3, v3, v4, v2
+; CHECK-BE-NEXT:    xxperm v2, vs5, vs4
 ; CHECK-BE-NEXT:    mffprwz r3, f3
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mtfprwz f3, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs1
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
+; CHECK-BE-NEXT:    xxperm v3, vs3, vs4
 ; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    vmrghh v3, v4, v3
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    vmrghh v2, v3, v2
+; CHECK-BE-NEXT:    mtfprwz f2, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, vs0
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
+; CHECK-BE-NEXT:    xxperm v3, vs2, vs4
 ; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    mtfprwz f1, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    mtvsrwz v0, r3
-; CHECK-BE-NEXT:    vperm v2, v5, v0, v2
-; CHECK-BE-NEXT:    vmrghh v2, v2, v4
-; CHECK-BE-NEXT:    vmrghw v2, v2, v3
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    xxperm v4, vs1, vs4
+; CHECK-BE-NEXT:    vmrghh v3, v4, v3
+; CHECK-BE-NEXT:    vmrghw v2, v3, v2
 ; CHECK-BE-NEXT:    mfvsrd r3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <8 x double>, <8 x double>* %0, align 64
   %1 = fptosi <8 x double> %a to <8 x i8>
   %2 = bitcast <8 x i8> %1 to i64
   ret i64 %2
 }

 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test16elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    lxv vs7, 112(r3)
 ; CHECK-BE-NEXT:    lxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    lxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    lxv vs2, 32(r3)
-; CHECK-BE-NEXT:    xscvdpsxws f8, f7
+; CHECK-BE-NEXT:    xscvdpsxws f9, f7
 ; CHECK-BE-NEXT:    xxswapd vs7, vs7
 ; CHECK-BE-NEXT:    lxv vs3, 48(r3)
 ; CHECK-BE-NEXT:    lxv vs4, 64(r3)
 ; CHECK-BE-NEXT:    lxv vs5, 80(r3)
 ; CHECK-BE-NEXT:    lxv vs6, 96(r3)
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI7_0@toc@ha
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI7_0@toc@l
-; CHECK-BE-NEXT:    lxv v2, 0(r3)
+; CHECK-BE-NEXT:    lxv vs8, 0(r3)
 ; CHECK-BE-NEXT:    xscvdpsxws f7, f7
-; CHECK-BE-NEXT:    mffprwz r3, f8
-; CHECK-BE-NEXT:    mtvsrwz v3, r3
+; CHECK-BE-NEXT:    mffprwz r3, f9
+; CHECK-BE-NEXT:    mtfprwz f9, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f7
 ; CHECK-BE-NEXT:    xscvdpsxws f7, f6
 ; CHECK-BE-NEXT:    xxswapd vs6, vs6
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mtvsrwz v2, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f6, f6
-; CHECK-BE-NEXT:    vperm v3, v3, v4, v2
+; CHECK-BE-NEXT:    xxperm v2, vs9, vs8
 ; CHECK-BE-NEXT:    mffprwz r3, f7
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    mtfprwz f7, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f6
 ; CHECK-BE-NEXT:    xscvdpsxws f6, f5
 ; CHECK-BE-NEXT:    xxswapd vs5, vs5
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f5, f5
-; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
+; CHECK-BE-NEXT:    xxperm v3, vs7, vs8
 ; CHECK-BE-NEXT:    mffprwz r3, f6
-; CHECK-BE-NEXT:    vmrghh v3, v4, v3
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    vmrghh v2, v3, v2
+; CHECK-BE-NEXT:    mtfprwz f6, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f5
 ; CHECK-BE-NEXT:    xscvdpsxws f5, f4
 ; CHECK-BE-NEXT:    xxswapd vs4, vs4
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f4, f4
-; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
+; CHECK-BE-NEXT:    xxperm v3, vs6, vs8
 ; CHECK-BE-NEXT:    mffprwz r3, f5
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    mtfprwz f5, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f4
 ; CHECK-BE-NEXT:    xscvdpsxws f4, f3
 ; CHECK-BE-NEXT:    xxswapd vs3, vs3
-; CHECK-BE-NEXT:    mtvsrwz v0, r3
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f3
-; CHECK-BE-NEXT:    vperm v5, v5, v0, v2
-; CHECK-BE-NEXT:    vmrghh v4, v5, v4
+; CHECK-BE-NEXT:    xxperm v4, vs5, vs8
 ; CHECK-BE-NEXT:    mffprwz r3, f4
-; CHECK-BE-NEXT:    vmrghw v3, v4, v3
-; CHECK-BE-NEXT:    mtvsrwz v4, r3
+; CHECK-BE-NEXT:    vmrghh v3, v4, v3
+; CHECK-BE-NEXT:    mtfprwz f4, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f3
 ; CHECK-BE-NEXT:    xscvdpsxws f3, f2
 ; CHECK-BE-NEXT:    xxswapd vs2, vs2
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    vmrghw v2, v3, v2
+; CHECK-BE-NEXT:    mtvsrwz v3, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f2
-; CHECK-BE-NEXT:    vperm v4, v4, v5, v2
+; CHECK-BE-NEXT:    xxperm v3, vs4, vs8
 ; CHECK-BE-NEXT:    mffprwz r3, f3
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    mtfprwz f3, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f2
 ; CHECK-BE-NEXT:    xscvdpsxws f2, f1
 ; CHECK-BE-NEXT:    xxswapd vs1, vs1
-; CHECK-BE-NEXT:    mtvsrwz v0, r3
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f1
-; CHECK-BE-NEXT:    vperm v5, v5, v0, v2
+; CHECK-BE-NEXT:    xxperm v4, vs3, vs8
 ; CHECK-BE-NEXT:    mffprwz r3, f2
-; CHECK-BE-NEXT:    vmrghh v4, v5, v4
-; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    vmrghh v3, v4, v3
+; CHECK-BE-NEXT:    mtfprwz f2, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f1
 ; CHECK-BE-NEXT:    xscvdpsxws f1, f0
 ; CHECK-BE-NEXT:    xxswapd vs0, vs0
-; CHECK-BE-NEXT:    mtvsrwz v0, r3
+; CHECK-BE-NEXT:    mtvsrwz v4, r3
 ; CHECK-BE-NEXT:    xscvdpsxws f0, f0
-; CHECK-BE-NEXT:    vperm v5, v5, v0, v2
+; CHECK-BE-NEXT:    xxperm v4, vs2, vs8
 ; CHECK-BE-NEXT:    mffprwz r3, f1
-; CHECK-BE-NEXT:    mtvsrwz v0, r3
+; CHECK-BE-NEXT:    mtfprwz f1, r3
 ; CHECK-BE-NEXT:    mffprwz r3, f0
-; CHECK-BE-NEXT:    mtvsrwz v1, r3
-; CHECK-BE-NEXT:    vperm v2, v0, v1, v2
-; CHECK-BE-NEXT:    vmrghh v2, v2, v5
-; CHECK-BE-NEXT:    vmrghw v2, v2, v4
-; CHECK-BE-NEXT:    xxmrghd v2, v2, v3
+; CHECK-BE-NEXT:    mtvsrwz v5, r3
+; CHECK-BE-NEXT:    xxperm v5, vs1, vs8
+; CHECK-BE-NEXT:    vmrghh v4, v5, v4
+; CHECK-BE-NEXT:    vmrghw v3, v4, v3
+; CHECK-BE-NEXT:    xxmrghd v2, v3, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %a = load <16 x double>, <16 x double>* %0, align 128
   %1 = fptosi <16 x double> %a to <16 x i8>
   ret <16 x i8> %1
 }

llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll

 ; CHECK-P9-NEXT:    mtvsrd v2, r3
 ; CHECK-P9-NEXT:    xxlxor v3, v3, v3
 ; CHECK-P9-NEXT:    vmrghh v2, v3, v2
 ; CHECK-P9-NEXT:    xvcvuxwsp v2, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test4elt:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    mtvsrd v2, r3
+; CHECK-BE-NEXT:    mtfprd f1, r3
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
-; CHECK-BE-NEXT:    xxlxor v4, v4, v4
+; CHECK-BE-NEXT:    xxlxor vs0, vs0, vs0
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI1_0@toc@l
-; CHECK-BE-NEXT:    lxv v3, 0(r3)
-; CHECK-BE-NEXT:    vperm v2, v4, v2, v3
-; CHECK-BE-NEXT:    xvcvuxwsp v2, v2
+; CHECK-BE-NEXT:    lxv vs2, 0(r3)
+; CHECK-BE-NEXT:    xxperm vs1, vs0, vs2
+; CHECK-BE-NEXT:    xvcvuxwsp v2, vs1
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i64 %a.coerce to <4 x i16>
   %1 = uitofp <4 x i16> %0 to <4 x float>
   ret <4 x float> %1
 }
 
 define void @test8elt(<8 x float>* noalias nocapture sret(<8 x float>) %agg.result, <8 x i16> %a) local_unnamed_addr #2 {

llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp64_elts.ll

 ; CHECK-P8-NEXT:    xxlxor v4, v4, v4
 ; CHECK-P8-NEXT:    lvx v3, 0, r4
 ; CHECK-P8-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-P8-NEXT:    xvcvuxddp v2, v2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test2elt:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    mtvsrwz v2, r3
+; CHECK-P9-NEXT:    mtfprwz f1, r3
 ; CHECK-P9-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
-; CHECK-P9-NEXT:    xxlxor v4, v4, v4
+; CHECK-P9-NEXT:    xxlxor vs0, vs0, vs0
 ; CHECK-P9-NEXT:    addi r3, r3, .LCPI0_0@toc@l
-; CHECK-P9-NEXT:    lxv v3, 0(r3)
-; CHECK-P9-NEXT:    vperm v2, v4, v2, v3
-; CHECK-P9-NEXT:    xvcvuxddp v2, v2
+; CHECK-P9-NEXT:    lxv vs2, 0(r3)
+; CHECK-P9-NEXT:    xxperm vs1, vs0, vs2
+; CHECK-P9-NEXT:    xvcvuxddp v2, vs1
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2elt:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    mtvsrwz v2, r3
+; CHECK-BE-NEXT:    mtfprwz f1, r3
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
-; CHECK-BE-NEXT:    xxlxor v4, v4, v4
+; CHECK-BE-NEXT:    xxlxor vs0, vs0, vs0
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI0_0@toc@l
-; CHECK-BE-NEXT:    lxv v3, 0(r3)
-; CHECK-BE-NEXT:    vperm v2, v4, v2, v3
-; CHECK-BE-NEXT:    xvcvuxddp v2, v2
+; CHECK-BE-NEXT:    lxv vs2, 0(r3)
+; CHECK-BE-NEXT:    xxperm vs1, vs0, vs2
+; CHECK-BE-NEXT:    xvcvuxddp v2, vs1
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i32 %a.coerce to <2 x i16>
   %1 = uitofp <2 x i16> %0 to <2 x double>
   ret <2 x double> %1
 }
 
 define void @test4elt(<4 x double>* noalias nocapture sret(<4 x double>) %agg.result, i64 %a.coerce) local_unnamed_addr #1 {

 ; CHECK-P8-NEXT:    xvcvsxddp v2, v2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test2elt_signed:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    mtvsrwz v2, r3
 ; CHECK-P9-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
 ; CHECK-P9-NEXT:    addi r3, r3, .LCPI4_0@toc@l
-; CHECK-P9-NEXT:    lxv v3, 0(r3)
-; CHECK-P9-NEXT:    vperm v2, v2, v2, v3
+; CHECK-P9-NEXT:    lxv vs0, 0(r3)
+; CHECK-P9-NEXT:    xxperm v2, v2, vs0
 ; CHECK-P9-NEXT:    vextsh2d v2, v2
 ; CHECK-P9-NEXT:    xvcvsxddp v2, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtvsrwz v2, r3
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI4_0@toc@l
-; CHECK-BE-NEXT:    lxv v3, 0(r3)
-; CHECK-BE-NEXT:    vperm v2, v2, v2, v3
+; CHECK-BE-NEXT:    lxv vs0, 0(r3)
+; CHECK-BE-NEXT:    xxperm v2, v2, vs0
 ; CHECK-BE-NEXT:    vextsh2d v2, v2
 ; CHECK-BE-NEXT:    xvcvsxddp v2, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i32 %a.coerce to <2 x i16>
   %1 = sitofp <2 x i16> %0 to <2 x double>
   ret <2 x double> %1
 }

 ; CHECK-P9-NEXT:    xvcvsxddp vs1, v2
 ; CHECK-P9-NEXT:    stxv vs1, 16(r3)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test4elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtvsrd v2, r4
 ; CHECK-BE-NEXT:    addis r4, r2, .LCPI5_0@toc@ha
-; CHECK-BE-NEXT:    xxlxor v3, v3, v3
+; CHECK-BE-NEXT:    xxlxor vs0, vs0, vs0
 ; CHECK-BE-NEXT:    addi r4, r4, .LCPI5_0@toc@l
-; CHECK-BE-NEXT:    lxv v4, 0(r4)
+; CHECK-BE-NEXT:    vmr v3, v2
+; CHECK-BE-NEXT:    lxv vs1, 0(r4)
 ; CHECK-BE-NEXT:    addis r4, r2, .LCPI5_1@toc@ha
 ; CHECK-BE-NEXT:    addi r4, r4, .LCPI5_1@toc@l
-; CHECK-BE-NEXT:    vperm v3, v3, v2, v4
+; CHECK-BE-NEXT:    xxperm v3, vs0, vs1
+; CHECK-BE-NEXT:    lxv vs1, 0(r4)
 ; CHECK-BE-NEXT:    vextsh2d v3, v3
+; CHECK-BE-NEXT:    xxperm v2, v2, vs1
 ; CHECK-BE-NEXT:    xvcvsxddp vs0, v3
-; CHECK-BE-NEXT:    lxv v3, 0(r4)
-; CHECK-BE-NEXT:    vperm v2, v2, v2, v3
-; CHECK-BE-NEXT:    stxv vs0, 16(r3)
 ; CHECK-BE-NEXT:    vextsh2d v2, v2
 ; CHECK-BE-NEXT:    xvcvsxddp vs1, v2
+; CHECK-BE-NEXT:    stxv vs0, 16(r3)
 ; CHECK-BE-NEXT:    stxv vs1, 0(r3)
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i64 %a.coerce to <4 x i16>
   %1 = sitofp <4 x i16> %0 to <4 x double>
   store <4 x double> %1, <4 x double>* %agg.result, align 32
   ret void
 }

llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll

 ; CHECK-P8-NEXT:    xxlxor v4, v4, v4
 ; CHECK-P8-NEXT:    lvx v3, 0, r4
 ; CHECK-P8-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-P8-NEXT:    xvcvuxwsp v2, v2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test4elt:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    mtvsrwz v2, r3
+; CHECK-P9-NEXT:    mtfprwz f1, r3
 ; CHECK-P9-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
-; CHECK-P9-NEXT:    xxlxor v4, v4, v4
+; CHECK-P9-NEXT:    xxlxor vs0, vs0, vs0
 ; CHECK-P9-NEXT:    addi r3, r3, .LCPI1_0@toc@l
-; CHECK-P9-NEXT:    lxv v3, 0(r3)
-; CHECK-P9-NEXT:    vperm v2, v4, v2, v3
-; CHECK-P9-NEXT:    xvcvuxwsp v2, v2
+; CHECK-P9-NEXT:    lxv vs2, 0(r3)
+; CHECK-P9-NEXT:    xxperm vs1, vs0, vs2
+; CHECK-P9-NEXT:    xvcvuxwsp v2, vs1
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test4elt:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    mtvsrwz v2, r3
+; CHECK-BE-NEXT:    mtfprwz f1, r3
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
-; CHECK-BE-NEXT:    xxlxor v4, v4, v4
+; CHECK-BE-NEXT:    xxlxor vs0, vs0, vs0
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI1_0@toc@l
-; CHECK-BE-NEXT:    lxv v3, 0(r3)
-; CHECK-BE-NEXT:    vperm v2, v4, v2, v3
-; CHECK-BE-NEXT:    xvcvuxwsp v2, v2
+; CHECK-BE-NEXT:    lxv vs2, 0(r3)
+; CHECK-BE-NEXT:    xxperm vs1, vs0, vs2
+; CHECK-BE-NEXT:    xvcvuxwsp v2, vs1
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i32 %a.coerce to <4 x i8>
   %1 = uitofp <4 x i8> %0 to <4 x float>
   ret <4 x float> %1
 }
 
 define void @test8elt(<8 x float>* noalias nocapture sret(<8 x float>) %agg.result, i64 %a.coerce) local_unnamed_addr #2 {

 ; CHECK-P8-NEXT:    xvcvsxwsp v2, v2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test4elt_signed:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    mtvsrwz v2, r3
 ; CHECK-P9-NEXT:    addis r3, r2, .LCPI5_0@toc@ha
 ; CHECK-P9-NEXT:    addi r3, r3, .LCPI5_0@toc@l
-; CHECK-P9-NEXT:    lxv v3, 0(r3)
-; CHECK-P9-NEXT:    vperm v2, v2, v2, v3
+; CHECK-P9-NEXT:    lxv vs0, 0(r3)
+; CHECK-P9-NEXT:    xxperm v2, v2, vs0
 ; CHECK-P9-NEXT:    vextsb2w v2, v2
 ; CHECK-P9-NEXT:    xvcvsxwsp v2, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test4elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtvsrwz v2, r3
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI5_0@toc@ha
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI5_0@toc@l
-; CHECK-BE-NEXT:    lxv v3, 0(r3)
-; CHECK-BE-NEXT:    vperm v2, v2, v2, v3
+; CHECK-BE-NEXT:    lxv vs0, 0(r3)
+; CHECK-BE-NEXT:    xxperm v2, v2, vs0
 ; CHECK-BE-NEXT:    vextsb2w v2, v2
 ; CHECK-BE-NEXT:    xvcvsxwsp v2, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i32 %a.coerce to <4 x i8>
   %1 = sitofp <4 x i8> %0 to <4 x float>
   ret <4 x float> %1
 }

 ; CHECK-P9-NEXT:    xvcvsxwsp vs1, v2
 ; CHECK-P9-NEXT:    stxv vs1, 16(r3)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test8elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtvsrd v2, r4
 ; CHECK-BE-NEXT:    addis r4, r2, .LCPI6_0@toc@ha
-; CHECK-BE-NEXT:    xxlxor v3, v3, v3
+; CHECK-BE-NEXT:    xxlxor vs0, vs0, vs0
 ; CHECK-BE-NEXT:    addi r4, r4, .LCPI6_0@toc@l
-; CHECK-BE-NEXT:    lxv v4, 0(r4)
+; CHECK-BE-NEXT:    lxv vs1, 0(r4)
 ; CHECK-BE-NEXT:    addis r4, r2, .LCPI6_1@toc@ha
 ; CHECK-BE-NEXT:    addi r4, r4, .LCPI6_1@toc@l
-; CHECK-BE-NEXT:    vperm v3, v3, v2, v4
-; CHECK-BE-NEXT:    vextsb2w v3, v3
-; CHECK-BE-NEXT:    xvcvsxwsp vs0, v3
 ; CHECK-BE-NEXT:    lxv v3, 0(r4)
-; CHECK-BE-NEXT:    vperm v2, v2, v2, v3
-; CHECK-BE-NEXT:    stxv vs0, 16(r3)
+; CHECK-BE-NEXT:    vperm v3, v2, v2, v3
+; CHECK-BE-NEXT:    xxperm v2, vs0, vs1
 ; CHECK-BE-NEXT:    vextsb2w v2, v2
+; CHECK-BE-NEXT:    xvcvsxwsp vs0, v2
+; CHECK-BE-NEXT:    stxv vs0, 16(r3)
+; CHECK-BE-NEXT:    vextsb2w v2, v3
 ; CHECK-BE-NEXT:    xvcvsxwsp vs1, v2
 ; CHECK-BE-NEXT:    stxv vs1, 0(r3)
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i64 %a.coerce to <8 x i8>
   %1 = sitofp <8 x i8> %0 to <8 x float>
   store <8 x float> %1, <8 x float>* %agg.result, align 32
   ret void

llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp64_elts.ll

 ; CHECK-P8-NEXT:    xxlxor v4, v4, v4
 ; CHECK-P8-NEXT:    lvx v3, 0, r4
 ; CHECK-P8-NEXT:    vperm v2, v4, v2, v3
 ; CHECK-P8-NEXT:    xvcvuxddp v2, v2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test2elt:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    mtvsrwz v2, r3
+; CHECK-P9-NEXT:    mtfprwz f1, r3
 ; CHECK-P9-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
-; CHECK-P9-NEXT:    xxlxor v4, v4, v4
+; CHECK-P9-NEXT:    xxlxor vs0, vs0, vs0
 ; CHECK-P9-NEXT:    addi r3, r3, .LCPI0_0@toc@l
-; CHECK-P9-NEXT:    lxv v3, 0(r3)
-; CHECK-P9-NEXT:    vperm v2, v4, v2, v3
-; CHECK-P9-NEXT:    xvcvuxddp v2, v2
+; CHECK-P9-NEXT:    lxv vs2, 0(r3)
+; CHECK-P9-NEXT:    xxperm vs1, vs0, vs2
+; CHECK-P9-NEXT:    xvcvuxddp v2, vs1
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2elt:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    mtvsrwz v2, r3
+; CHECK-BE-NEXT:    mtfprwz f1, r3
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
-; CHECK-BE-NEXT:    xxlxor v4, v4, v4
+; CHECK-BE-NEXT:    xxlxor vs0, vs0, vs0
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI0_0@toc@l
-; CHECK-BE-NEXT:    lxv v3, 0(r3)
-; CHECK-BE-NEXT:    vperm v2, v4, v2, v3
-; CHECK-BE-NEXT:    xvcvuxddp v2, v2
+; CHECK-BE-NEXT:    lxv vs2, 0(r3)
+; CHECK-BE-NEXT:    xxperm vs1, vs0, vs2
+; CHECK-BE-NEXT:    xvcvuxddp v2, vs1
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i16 %a.coerce to <2 x i8>
   %1 = uitofp <2 x i8> %0 to <2 x double>
   ret <2 x double> %1
 }
 
 define void @test4elt(<4 x double>* noalias nocapture sret(<4 x double>) %agg.result, i32 %a.coerce) local_unnamed_addr #1 {

 ; CHECK-P8-NEXT:    xvcvsxddp v2, v2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: test2elt_signed:
 ; CHECK-P9:       # %bb.0: # %entry
 ; CHECK-P9-NEXT:    mtvsrwz v2, r3
 ; CHECK-P9-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
 ; CHECK-P9-NEXT:    addi r3, r3, .LCPI4_0@toc@l
-; CHECK-P9-NEXT:    lxv v3, 0(r3)
-; CHECK-P9-NEXT:    vperm v2, v2, v2, v3
+; CHECK-P9-NEXT:    lxv vs0, 0(r3)
+; CHECK-P9-NEXT:    xxperm v2, v2, vs0
 ; CHECK-P9-NEXT:    vextsb2d v2, v2
 ; CHECK-P9-NEXT:    xvcvsxddp v2, v2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtvsrwz v2, r3
 ; CHECK-BE-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
 ; CHECK-BE-NEXT:    addi r3, r3, .LCPI4_0@toc@l
-; CHECK-BE-NEXT:    lxv v3, 0(r3)
-; CHECK-BE-NEXT:    vperm v2, v2, v2, v3
+; CHECK-BE-NEXT:    lxv vs0, 0(r3)
+; CHECK-BE-NEXT:    xxperm v2, v2, vs0
 ; CHECK-BE-NEXT:    vextsb2d v2, v2
 ; CHECK-BE-NEXT:    xvcvsxddp v2, v2
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i16 %a.coerce to <2 x i8>
   %1 = sitofp <2 x i8> %0 to <2 x double>
   ret <2 x double> %1
 }

 ; CHECK-P9-NEXT:    xvcvsxddp vs1, v2
 ; CHECK-P9-NEXT:    stxv vs1, 16(r3)
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test4elt_signed:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    mtvsrwz v2, r4
 ; CHECK-BE-NEXT:    addis r4, r2, .LCPI5_0@toc@ha
-; CHECK-BE-NEXT:    xxlxor v3, v3, v3
+; CHECK-BE-NEXT:    xxlxor vs0, vs0, vs0
 ; CHECK-BE-NEXT:    addi r4, r4, .LCPI5_0@toc@l
-; CHECK-BE-NEXT:    lxv v4, 0(r4)
+; CHECK-BE-NEXT:    lxv vs1, 0(r4)
 ; CHECK-BE-NEXT:    addis r4, r2, .LCPI5_1@toc@ha
 ; CHECK-BE-NEXT:    addi r4, r4, .LCPI5_1@toc@l
-; CHECK-BE-NEXT:    vperm v3, v3, v2, v4
-; CHECK-BE-NEXT:    vextsb2d v3, v3
-; CHECK-BE-NEXT:    xvcvsxddp vs0, v3
 ; CHECK-BE-NEXT:    lxv v3, 0(r4)
-; CHECK-BE-NEXT:    vperm v2, v2, v2, v3
-; CHECK-BE-NEXT:    stxv vs0, 16(r3)
+; CHECK-BE-NEXT:    vperm v3, v2, v2, v3
+; CHECK-BE-NEXT:    xxperm v2, vs0, vs1
 ; CHECK-BE-NEXT:    vextsb2d v2, v2
+; CHECK-BE-NEXT:    xvcvsxddp vs0, v2
+; CHECK-BE-NEXT:    stxv vs0, 16(r3)
+; CHECK-BE-NEXT:    vextsb2d v2, v3
 ; CHECK-BE-NEXT:    xvcvsxddp vs1, v2
 ; CHECK-BE-NEXT:    stxv vs1, 0(r3)
 ; CHECK-BE-NEXT:    blr
 entry:
   %0 = bitcast i32 %a.coerce to <4 x i8>
   %1 = sitofp <4 x i8> %0 to <4 x double>
   store <4 x double> %1, <4 x double>* %agg.result, align 32
   ret void

llvm/test/CodeGen/PowerPC/vec_extract_p9.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-gnu-linux -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-LE
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-gnu-linux -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-BE
 
 define zeroext i8 @test1(<16 x i8> %a, i32 signext %index) {
 ; CHECK-LE-LABEL: test1:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    vextubrx 3, 5, 2
 ; CHECK-LE-NEXT:    clrldi 3, 3, 56
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test1:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    vextublx 3, 5, 2
 ; CHECK-BE-NEXT:    clrldi 3, 3, 56
 ; CHECK-BE-NEXT:    blr
-
 entry:
   %vecext = extractelement <16 x i8> %a, i32 %index
   ret i8 %vecext
 }
 
 define signext i8 @test2(<16 x i8> %a, i32 signext %index) {
 ; CHECK-LE-LABEL: test2:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    vextubrx 3, 5, 2
 ; CHECK-LE-NEXT:    extsb 3, 3
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test2:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    vextublx 3, 5, 2
 ; CHECK-BE-NEXT:    extsb 3, 3
 ; CHECK-BE-NEXT:    blr
-
 entry:
   %vecext = extractelement <16 x i8> %a, i32 %index
   ret i8 %vecext
 }
 
 define zeroext i16 @test3(<8 x i16> %a, i32 signext %index) {
 ; CHECK-LE-LABEL: test3:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    rlwinm 3, 5, 1, 28, 30
 ; CHECK-LE-NEXT:    vextuhrx 3, 3, 2
 ; CHECK-LE-NEXT:    clrldi 3, 3, 48
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test3:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    rlwinm 3, 5, 1, 28, 30
 ; CHECK-BE-NEXT:    vextuhlx 3, 3, 2
 ; CHECK-BE-NEXT:    clrldi 3, 3, 48
 ; CHECK-BE-NEXT:    blr
-
 entry:
   %vecext = extractelement <8 x i16> %a, i32 %index
   ret i16 %vecext
 }
 
 define signext i16 @test4(<8 x i16> %a, i32 signext %index) {
 ; CHECK-LE-LABEL: test4:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    rlwinm 3, 5, 1, 28, 30
 ; CHECK-LE-NEXT:    vextuhrx 3, 3, 2
 ; CHECK-LE-NEXT:    extsh 3, 3
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test4:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    rlwinm 3, 5, 1, 28, 30
 ; CHECK-BE-NEXT:    vextuhlx 3, 3, 2
 ; CHECK-BE-NEXT:    extsh 3, 3
 ; CHECK-BE-NEXT:    blr
-
 entry:
   %vecext = extractelement <8 x i16> %a, i32 %index
   ret i16 %vecext
 }
 
 define zeroext i32 @test5(<4 x i32> %a, i32 signext %index) {
 ; CHECK-LE-LABEL: test5:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    rlwinm 3, 5, 2, 28, 29
 ; CHECK-LE-NEXT:    vextuwrx 3, 3, 2
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test5:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    rlwinm 3, 5, 2, 28, 29
 ; CHECK-BE-NEXT:    vextuwlx 3, 3, 2
 ; CHECK-BE-NEXT:    blr
-
 entry:
   %vecext = extractelement <4 x i32> %a, i32 %index
   ret i32 %vecext
 }
 
 define signext i32 @test6(<4 x i32> %a, i32 signext %index) {
 ; CHECK-LE-LABEL: test6:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    rlwinm 3, 5, 2, 28, 29
 ; CHECK-LE-NEXT:    vextuwrx 3, 3, 2
 ; CHECK-LE-NEXT:    extsw 3, 3
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test6:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    rlwinm 3, 5, 2, 28, 29
 ; CHECK-BE-NEXT:    vextuwlx 3, 3, 2
 ; CHECK-BE-NEXT:    extsw 3, 3
 ; CHECK-BE-NEXT:    blr
-
 entry:
   %vecext = extractelement <4 x i32> %a, i32 %index
   ret i32 %vecext
 }
 
 ; Test with immediate index
 define zeroext i8 @test7(<16 x i8> %a) {
 ; CHECK-LE-LABEL: test7:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    li 3, 1
 ; CHECK-LE-NEXT:    vextubrx 3, 3, 2
 ; CHECK-LE-NEXT:    clrldi 3, 3, 56
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test7:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    li 3, 1
 ; CHECK-BE-NEXT:    vextublx 3, 3, 2
 ; CHECK-BE-NEXT:    clrldi 3, 3, 56
 ; CHECK-BE-NEXT:    blr
-
 entry:
   %vecext = extractelement <16 x i8> %a, i32 1
   ret i8 %vecext
 }
 
 define zeroext i16 @test8(<8 x i16> %a) {
 ; CHECK-LE-LABEL: test8:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    li 3, 2
 ; CHECK-LE-NEXT:    vextuhrx 3, 3, 2
 ; CHECK-LE-NEXT:    clrldi 3, 3, 48
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test8:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    li 3, 2
 ; CHECK-BE-NEXT:    vextuhlx 3, 3, 2
 ; CHECK-BE-NEXT:    clrldi 3, 3, 48
 ; CHECK-BE-NEXT:    blr
-
 entry:
   %vecext = extractelement <8 x i16> %a, i32 1
   ret i16 %vecext
 }
 
 define zeroext i32 @test9(<4 x i32> %a) {
 ; CHECK-LE-LABEL: test9:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    li 3, 12
 ; CHECK-LE-NEXT:    vextuwrx 3, 3, 2
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test9:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    li 3, 12
 ; CHECK-BE-NEXT:    vextuwlx 3, 3, 2
 ; CHECK-BE-NEXT:    blr
-
 entry:
   %vecext = extractelement <4 x i32> %a, i32 3
   ret i32 %vecext
 }
 
 define double @test10(<4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LE-LABEL: test10:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    addis 3, 2, .LCPI9_0@toc@ha
 ; CHECK-LE-NEXT:    addi 3, 3, .LCPI9_0@toc@l
-; CHECK-LE-NEXT:    lxv 36, 0(3)
+; CHECK-LE-NEXT:    lxv 0, 0(3)
 ; CHECK-LE-NEXT:    addis 3, 2, .LCPI9_1@toc@ha
-; CHECK-LE-NEXT:    lfs 0, .LCPI9_1@toc@l(3)
-; CHECK-LE-NEXT:    vperm 2, 3, 2, 4
-; CHECK-LE-NEXT:    xsadddp 1, 34, 0
+; CHECK-LE-NEXT:    lfs 1, .LCPI9_1@toc@l(3)
+; CHECK-LE-NEXT:    xxperm 35, 34, 0
+; CHECK-LE-NEXT:    xxswapd 0, 35
+; CHECK-LE-NEXT:    xsadddp 1, 0, 1
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: test10:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    addis 3, 2, .LCPI9_0@toc@ha
 ; CHECK-BE-NEXT:    vmrghw 3, 3, 2
 ; CHECK-BE-NEXT:    lfs 0, .LCPI9_0@toc@l(3)
 ; CHECK-BE-NEXT:    vmrglw 2, 3, 2

llvm/test/CodeGen/PowerPC/vec_int_ext.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-gnu-linux -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-LE
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-gnu-linux -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-BE
 
 define <4 x i32> @vextsb2wLE(<16 x i8> %a) {
 ; CHECK-LE-LABEL: vextsb2wLE:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    vextsb2w 2, 2
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: vextsb2wLE:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
 ; CHECK-BE-NEXT:    addi 3, 3, .LCPI0_0@toc@l
-; CHECK-BE-NEXT:    lxv 35, 0(3)
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
+; CHECK-BE-NEXT:    lxv 0, 0(3)
+; CHECK-BE-NEXT:    xxperm 34, 34, 0
 ; CHECK-BE-NEXT:    vextsb2w 2, 2
 ; CHECK-BE-NEXT:    blr
-
 entry:
   %vecext = extractelement <16 x i8> %a, i32 0
   %conv = sext i8 %vecext to i32
   %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
   %vecext1 = extractelement <16 x i8> %a, i32 4
   %conv2 = sext i8 %vecext1 to i32
   %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1
   %vecext4 = extractelement <16 x i8> %a, i32 8

 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    vextsb2d 2, 2
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: vextsb2dLE:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    addis 3, 2, .LCPI1_0@toc@ha
 ; CHECK-BE-NEXT:    addi 3, 3, .LCPI1_0@toc@l
-; CHECK-BE-NEXT:    lxv 35, 0(3)
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
+; CHECK-BE-NEXT:    lxv 0, 0(3)
+; CHECK-BE-NEXT:    xxperm 34, 34, 0
 ; CHECK-BE-NEXT:    vextsb2d 2, 2
 ; CHECK-BE-NEXT:    blr
-
 entry:
   %vecext = extractelement <16 x i8> %a, i32 0
   %conv = sext i8 %vecext to i64
   %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
   %vecext1 = extractelement <16 x i8> %a, i32 8
   %conv2 = sext i8 %vecext1 to i64
   %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1
   ret <2 x i64> %vecinit3
 }
 
 define <4 x i32> @vextsh2wLE(<8 x i16> %a) {
 ; CHECK-LE-LABEL: vextsh2wLE:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    vextsh2w 2, 2
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: vextsh2wLE:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    addis 3, 2, .LCPI2_0@toc@ha
 ; CHECK-BE-NEXT:    addi 3, 3, .LCPI2_0@toc@l
-; CHECK-BE-NEXT:    lxv 35, 0(3)
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
+; CHECK-BE-NEXT:    lxv 0, 0(3)
+; CHECK-BE-NEXT:    xxperm 34, 34, 0
 ; CHECK-BE-NEXT:    vextsh2w 2, 2
 ; CHECK-BE-NEXT:    blr
-
 entry:
   %vecext = extractelement <8 x i16> %a, i32 0
   %conv = sext i16 %vecext to i32
   %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
   %vecext1 = extractelement <8 x i16> %a, i32 2
   %conv2 = sext i16 %vecext1 to i32
   %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1
   %vecext4 = extractelement <8 x i16> %a, i32 4

 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    vextsh2d 2, 2
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: vextsh2dLE:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    addis 3, 2, .LCPI3_0@toc@ha
 ; CHECK-BE-NEXT:    addi 3, 3, .LCPI3_0@toc@l
-; CHECK-BE-NEXT:    lxv 35, 0(3)
-; CHECK-BE-NEXT:    vperm 2, 2, 2, 3
+; CHECK-BE-NEXT:    lxv 0, 0(3)
+; CHECK-BE-NEXT:    xxperm 34, 34, 0
 ; CHECK-BE-NEXT:    vextsh2d 2, 2
 ; CHECK-BE-NEXT:    blr
-
 entry:
   %vecext = extractelement <8 x i16> %a, i32 0
   %conv = sext i16 %vecext to i64
   %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
   %vecext1 = extractelement <8 x i16> %a, i32 4
   %conv2 = sext i16 %vecext1 to i64
   %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1
   ret <2 x i64> %vecinit3
 }
 
 define <2 x i64> @vextsw2dLE(<4 x i32> %a) {
 ; CHECK-LE-LABEL: vextsw2dLE:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    vextsw2d 2, 2
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: vextsw2dLE:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    vmrgew 2, 2, 2
 ; CHECK-BE-NEXT:    vextsw2d 2, 2
 ; CHECK-BE-NEXT:    blr
-
 entry:
   %vecext = extractelement <4 x i32> %a, i32 0
   %conv = sext i32 %vecext to i64
   %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
   %vecext1 = extractelement <4 x i32> %a, i32 2
   %conv2 = sext i32 %vecext1 to i64
   %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1
   ret <2 x i64> %vecinit3

 ; CHECK-BE-NEXT:    li 3, 0
 ; CHECK-BE-NEXT:    li 4, 8
 ; CHECK-BE-NEXT:    vextuwlx 3, 3, 2
 ; CHECK-BE-NEXT:    vextuwlx 4, 4, 3
 ; CHECK-BE-NEXT:    extsw 3, 3
 ; CHECK-BE-NEXT:    extsw 4, 4
 ; CHECK-BE-NEXT:    mtvsrdd 34, 3, 4
 ; CHECK-BE-NEXT:    blr
-
 entry:
   %vecext = extractelement <4 x i32> %a, i32 0
   %conv = sext i32 %vecext to i64
   %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
   %vecext1 = extractelement <4 x i32> %b, i32 2
   %conv2 = sext i32 %vecext1 to i64
   %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1
   ret <2 x i64> %vecinit3

 ; CHECK-BE-NEXT:    vextublx 3, 3, 2
 ; CHECK-BE-NEXT:    vextublx 4, 4, 2
 ; CHECK-BE-NEXT:    vextublx 5, 5, 2
 ; CHECK-BE-NEXT:    extsb 7, 7
 ; CHECK-BE-NEXT:    extsb 8, 8
 ; CHECK-BE-NEXT:    extsb 5, 5
 ; CHECK-BE-NEXT:    extsb 3, 3
 ; CHECK-BE-NEXT:    extsb 4, 4
-; CHECK-BE-NEXT:    mtvsrwz 35, 9
+; CHECK-BE-NEXT:    mtfprwz 0, 9
 ; CHECK-BE-NEXT:    addis 9, 2, .LCPI11_0@toc@ha
 ; CHECK-BE-NEXT:    vextublx 6, 6, 2
 ; CHECK-BE-NEXT:    mtvsrwz 34, 10
-; CHECK-BE-NEXT:    mtvsrwz 37, 7
+; CHECK-BE-NEXT:    mtvsrwz 35, 8
 ; CHECK-BE-NEXT:    extsb 6, 6
-; CHECK-BE-NEXT:    mtvsrwz 32, 3
+; CHECK-BE-NEXT:    mtvsrwz 36, 4
 ; CHECK-BE-NEXT:    addi 9, 9, .LCPI11_0@toc@l
-; CHECK-BE-NEXT:    lxv 36, 0(9)
-; CHECK-BE-NEXT:    vperm 2, 3, 2, 4
-; CHECK-BE-NEXT:    mtvsrwz 35, 8
-; CHECK-BE-NEXT:    vperm 3, 5, 3, 4
-; CHECK-BE-NEXT:    mtvsrwz 37, 5
+; CHECK-BE-NEXT:    lxv 1, 0(9)
+; CHECK-BE-NEXT:    xxperm 34, 0, 1
+; CHECK-BE-NEXT:    mtfprwz 0, 7
+; CHECK-BE-NEXT:    xxperm 35, 0, 1
+; CHECK-BE-NEXT:    mtfprwz 0, 5
 ; CHECK-BE-NEXT:    vmrghw 2, 3, 2
 ; CHECK-BE-NEXT:    mtvsrwz 35, 6
-; CHECK-BE-NEXT:    vperm 3, 5, 3, 4
-; CHECK-BE-NEXT:    mtvsrwz 37, 4
-; CHECK-BE-NEXT:    vperm 4, 0, 5, 4
+; CHECK-BE-NEXT:    xxperm 35, 0, 1
+; CHECK-BE-NEXT:    mtfprwz 0, 3
+; CHECK-BE-NEXT:    xxperm 36, 0, 1
 ; CHECK-BE-NEXT:    vmrghw 3, 4, 3
 ; CHECK-BE-NEXT:    xxmrghd 34, 35, 34
 ; CHECK-BE-NEXT:    blr
 entry:
 
 
   %vecext = extractelement <16 x i8> %a, i32 0
   %conv = sext i8 %vecext to i16

llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll

 ; PC64LE9-NEXT:    addis 3, 2, .LCPI2_0@toc@ha
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI2_0@toc@l
 ; PC64LE9-NEXT:    xxswapd 2, 34
 ; PC64LE9-NEXT:    xxsldwi 3, 34, 34, 3
 ; PC64LE9-NEXT:    xscvspdpn 0, 0
 ; PC64LE9-NEXT:    xscvspdpn 1, 1
 ; PC64LE9-NEXT:    xscvspdpn 2, 2
 ; PC64LE9-NEXT:    xscvspdpn 3, 3
-; PC64LE9-NEXT:    lxv 36, 0(3)
 ; PC64LE9-NEXT:    xsdivsp 0, 1, 0
 ; PC64LE9-NEXT:    xxswapd 1, 35
 ; PC64LE9-NEXT:    xscvspdpn 1, 1
 ; PC64LE9-NEXT:    xsdivsp 1, 2, 1
 ; PC64LE9-NEXT:    xxsldwi 2, 35, 35, 3
 ; PC64LE9-NEXT:    xscvspdpn 2, 2
 ; PC64LE9-NEXT:    xsdivsp 2, 3, 2
+; PC64LE9-NEXT:    xscvdpspn 0, 0
 ; PC64LE9-NEXT:    xscvdpspn 35, 1
+; PC64LE9-NEXT:    lxv 1, 0(3)
 ; PC64LE9-NEXT:    xscvdpspn 34, 2
 ; PC64LE9-NEXT:    vmrghw 2, 3, 2
-; PC64LE9-NEXT:    xscvdpspn 35, 0
-; PC64LE9-NEXT:    vperm 2, 3, 2, 4
+; PC64LE9-NEXT:    xxperm 34, 0, 1
 ; PC64LE9-NEXT:    blr
 entry:
   %div = call <3 x float> @llvm.experimental.constrained.fdiv.v3f32(
            <3 x float> %x,
            <3 x float> %y,
            metadata !"round.dynamic",
            metadata !"fpexcept.strict") #1
   ret <3 x float> %div

 ; PC64LE9-NEXT:    xscvspdpn 1, 0
 ; PC64LE9-NEXT:    xxsldwi 0, 63, 63, 3
 ; PC64LE9-NEXT:    xscvspdpn 2, 0
 ; PC64LE9-NEXT:    bl fmodf
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    xscvdpspn 34, 1
 ; PC64LE9-NEXT:    xscvdpspn 35, 30
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI7_0@toc@ha
-; PC64LE9-NEXT:    lxv 63, 48(1) # 16-byte Folded Reload
-; PC64LE9-NEXT:    lxv 62, 32(1) # 16-byte Folded Reload
-; PC64LE9-NEXT:    lfd 30, 64(1) # 8-byte Folded Reload
+; PC64LE9-NEXT:    xscvdpspn 0, 31
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI7_0@toc@l
-; PC64LE9-NEXT:    lxv 36, 0(3)
+; PC64LE9-NEXT:    lxv 1, 0(3)
 ; PC64LE9-NEXT:    vmrghw 2, 3, 2
-; PC64LE9-NEXT:    xscvdpspn 35, 31
+; PC64LE9-NEXT:    xxperm 34, 0, 1
+; PC64LE9-NEXT:    lxv 63, 48(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    lxv 62, 32(1) # 16-byte Folded Reload
 ; PC64LE9-NEXT:    lfd 31, 72(1) # 8-byte Folded Reload
-; PC64LE9-NEXT:    vperm 2, 3, 2, 4
+; PC64LE9-NEXT:    lfd 30, 64(1) # 8-byte Folded Reload
 ; PC64LE9-NEXT:    addi 1, 1, 80
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %rem = call <3 x float> @llvm.experimental.constrained.frem.v3f32(
            <3 x float> %x,
            <3 x float> %y,

 ; PC64LE9-NEXT:    addis 3, 2, .LCPI12_0@toc@ha
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI12_0@toc@l
 ; PC64LE9-NEXT:    xxswapd 2, 34
 ; PC64LE9-NEXT:    xxsldwi 3, 34, 34, 3
 ; PC64LE9-NEXT:    xscvspdpn 0, 0
 ; PC64LE9-NEXT:    xscvspdpn 1, 1
 ; PC64LE9-NEXT:    xscvspdpn 2, 2
 ; PC64LE9-NEXT:    xscvspdpn 3, 3
-; PC64LE9-NEXT:    lxv 36, 0(3)
 ; PC64LE9-NEXT:    xsmulsp 0, 1, 0
 ; PC64LE9-NEXT:    xxswapd 1, 35
 ; PC64LE9-NEXT:    xscvspdpn 1, 1
 ; PC64LE9-NEXT:    xsmulsp 1, 2, 1
 ; PC64LE9-NEXT:    xxsldwi 2, 35, 35, 3
+; PC64LE9-NEXT:    xscvdpspn 0, 0
 ; PC64LE9-NEXT:    xscvspdpn 2, 2
 ; PC64LE9-NEXT:    xsmulsp 2, 3, 2
 ; PC64LE9-NEXT:    xscvdpspn 35, 1
+; PC64LE9-NEXT:    lxv 1, 0(3)
 ; PC64LE9-NEXT:    xscvdpspn 34, 2
 ; PC64LE9-NEXT:    vmrghw 2, 3, 2
-; PC64LE9-NEXT:    xscvdpspn 35, 0
-; PC64LE9-NEXT:    vperm 2, 3, 2, 4
+; PC64LE9-NEXT:    xxperm 34, 0, 1
 ; PC64LE9-NEXT:    blr
 entry:
   %mul = call <3 x float> @llvm.experimental.constrained.fmul.v3f32(
            <3 x float> %x,
            <3 x float> %y,
            metadata !"round.dynamic",
            metadata !"fpexcept.strict") #1
   ret <3 x float> %mul

 ; PC64LE9-NEXT:    addis 3, 2, .LCPI17_0@toc@ha
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI17_0@toc@l
 ; PC64LE9-NEXT:    xxswapd 2, 34
 ; PC64LE9-NEXT:    xxsldwi 3, 34, 34, 3
 ; PC64LE9-NEXT:    xscvspdpn 0, 0
 ; PC64LE9-NEXT:    xscvspdpn 1, 1
 ; PC64LE9-NEXT:    xscvspdpn 2, 2
 ; PC64LE9-NEXT:    xscvspdpn 3, 3
-; PC64LE9-NEXT:    lxv 36, 0(3)
 ; PC64LE9-NEXT:    xsaddsp 0, 1, 0
 ; PC64LE9-NEXT:    xxswapd 1, 35
 ; PC64LE9-NEXT:    xscvspdpn 1, 1
 ; PC64LE9-NEXT:    xsaddsp 1, 2, 1
 ; PC64LE9-NEXT:    xxsldwi 2, 35, 35, 3
+; PC64LE9-NEXT:    xscvdpspn 0, 0
 ; PC64LE9-NEXT:    xscvspdpn 2, 2
 ; PC64LE9-NEXT:    xsaddsp 2, 3, 2
 ; PC64LE9-NEXT:    xscvdpspn 35, 1
+; PC64LE9-NEXT:    lxv 1, 0(3)
 ; PC64LE9-NEXT:    xscvdpspn 34, 2
 ; PC64LE9-NEXT:    vmrghw 2, 3, 2
-; PC64LE9-NEXT:    xscvdpspn 35, 0
-; PC64LE9-NEXT:    vperm 2, 3, 2, 4
+; PC64LE9-NEXT:    xxperm 34, 0, 1
 ; PC64LE9-NEXT:    blr
 entry:
   %add = call <3 x float> @llvm.experimental.constrained.fadd.v3f32(
            <3 x float> %x,
            <3 x float> %y,
            metadata !"round.dynamic",
            metadata !"fpexcept.strict") #1
   ret <3 x float> %add

 ; PC64LE9-NEXT:    addis 3, 2, .LCPI22_0@toc@ha
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI22_0@toc@l
 ; PC64LE9-NEXT:    xxswapd 2, 34
 ; PC64LE9-NEXT:    xxsldwi 3, 34, 34, 3
 ; PC64LE9-NEXT:    xscvspdpn 0, 0
 ; PC64LE9-NEXT:    xscvspdpn 1, 1
 ; PC64LE9-NEXT:    xscvspdpn 2, 2
 ; PC64LE9-NEXT:    xscvspdpn 3, 3
-; PC64LE9-NEXT:    lxv 36, 0(3)
 ; PC64LE9-NEXT:    xssubsp 0, 1, 0
 ; PC64LE9-NEXT:    xxswapd 1, 35
 ; PC64LE9-NEXT:    xscvspdpn 1, 1
 ; PC64LE9-NEXT:    xssubsp 1, 2, 1
 ; PC64LE9-NEXT:    xxsldwi 2, 35, 35, 3
+; PC64LE9-NEXT:    xscvdpspn 0, 0
 ; PC64LE9-NEXT:    xscvspdpn 2, 2
 ; PC64LE9-NEXT:    xssubsp 2, 3, 2
 ; PC64LE9-NEXT:    xscvdpspn 35, 1
+; PC64LE9-NEXT:    lxv 1, 0(3)
 ; PC64LE9-NEXT:    xscvdpspn 34, 2
 ; PC64LE9-NEXT:    vmrghw 2, 3, 2
-; PC64LE9-NEXT:    xscvdpspn 35, 0
-; PC64LE9-NEXT:    vperm 2, 3, 2, 4
+; PC64LE9-NEXT:    xxperm 34, 0, 1
 ; PC64LE9-NEXT:    blr
 entry:
   %sub = call <3 x float> @llvm.experimental.constrained.fsub.v3f32(
            <3 x float> %x,
            <3 x float> %y,
            metadata !"round.dynamic",
            metadata !"fpexcept.strict") #1
   ret <3 x float> %sub

 ; PC64LE9-NEXT:    xscvspdpn 1, 1
 ; PC64LE9-NEXT:    xscvspdpn 2, 2
 ; PC64LE9-NEXT:    xscvspdpn 0, 0
 ; PC64LE9-NEXT:    xssqrtsp 1, 1
 ; PC64LE9-NEXT:    xssqrtsp 2, 2
 ; PC64LE9-NEXT:    xssqrtsp 0, 0
 ; PC64LE9-NEXT:    xscvdpspn 34, 2
 ; PC64LE9-NEXT:    xscvdpspn 35, 1
-; PC64LE9-NEXT:    xscvdpspn 36, 0
+; PC64LE9-NEXT:    xscvdpspn 0, 0
+; PC64LE9-NEXT:    lxv 1, 0(3)
 ; PC64LE9-NEXT:    vmrghw 2, 3, 2
-; PC64LE9-NEXT:    lxv 35, 0(3)
-; PC64LE9-NEXT:    vperm 2, 4, 2, 3
+; PC64LE9-NEXT:    xxperm 34, 0, 1
 ; PC64LE9-NEXT:    blr
 entry:
   %sqrt = call <3 x float> @llvm.experimental.constrained.sqrt.v3f32(
                               <3 x float> %x,
                               metadata !"round.dynamic",
                               metadata !"fpexcept.strict") #1
   ret <3 x float> %sqrt
 }

 ; PC64LE9-NEXT:    xscvspdpn 1, 0
 ; PC64LE9-NEXT:    xxsldwi 0, 63, 63, 3
 ; PC64LE9-NEXT:    xscvspdpn 2, 0
 ; PC64LE9-NEXT:    bl powf
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    xscvdpspn 34, 1
 ; PC64LE9-NEXT:    xscvdpspn 35, 30
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI32_0@toc@ha
-; PC64LE9-NEXT:    lxv 63, 48(1) # 16-byte Folded Reload
-; PC64LE9-NEXT:    lxv 62, 32(1) # 16-byte Folded Reload
-; PC64LE9-NEXT:    lfd 30, 64(1) # 8-byte Folded Reload
+; PC64LE9-NEXT:    xscvdpspn 0, 31
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI32_0@toc@l
-; PC64LE9-NEXT:    lxv 36, 0(3)
+; PC64LE9-NEXT:    lxv 1, 0(3)
 ; PC64LE9-NEXT:    vmrghw 2, 3, 2
-; PC64LE9-NEXT:    xscvdpspn 35, 31
+; PC64LE9-NEXT:    xxperm 34, 0, 1
+; PC64LE9-NEXT:    lxv 63, 48(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    lxv 62, 32(1) # 16-byte Folded Reload
 ; PC64LE9-NEXT:    lfd 31, 72(1) # 8-byte Folded Reload
-; PC64LE9-NEXT:    vperm 2, 3, 2, 4
+; PC64LE9-NEXT:    lfd 30, 64(1) # 8-byte Folded Reload
 ; PC64LE9-NEXT:    addi 1, 1, 80
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %pow = call <3 x float> @llvm.experimental.constrained.pow.v3f32(
                              <3 x float> %x,
                              <3 x float> %y,
%powi = call <2 x double> @llvm.experimental.constrained.powi.v2f64(
                               <2 x double> %x,
                               i32 %y,
                               metadata !"round.dynamic",
                               metadata !"fpexcept.strict") #1
   ret <2 x double> %powi
 }
 
 define <3 x float> @constrained_vector_powi_v3f32(<3 x float> %x, i32 %y) #0 {
-;
-;
 ; PC64LE-LABEL: constrained_vector_powi_v3f32:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    mflr 0
 ; PC64LE-NEXT:    std 0, 16(1)
 ; PC64LE-NEXT:    stdu 1, -96(1)
 ; PC64LE-NEXT:    xxsldwi 0, 34, 34, 1
 ; PC64LE-NEXT:    std 30, 64(1) # 8-byte Folded Spill
 ; PC64LE-NEXT:    clrldi 30, 5, 32

 ; PC64LE9-NEXT:    fmr 30, 1
 ; PC64LE9-NEXT:    mr 4, 30
 ; PC64LE9-NEXT:    xscvspdpn 1, 0
 ; PC64LE9-NEXT:    bl __powisf2
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    xscvdpspn 34, 1
 ; PC64LE9-NEXT:    xscvdpspn 35, 30
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI37_0@toc@ha
-; PC64LE9-NEXT:    lxv 63, 32(1) # 16-byte Folded Reload
-; PC64LE9-NEXT:    lfd 30, 64(1) # 8-byte Folded Reload
-; PC64LE9-NEXT:    ld 30, 48(1) # 8-byte Folded Reload
+; PC64LE9-NEXT:    xscvdpspn 0, 31
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI37_0@toc@l
-; PC64LE9-NEXT:    lxv 36, 0(3)
+; PC64LE9-NEXT:    lxv 1, 0(3)
 ; PC64LE9-NEXT:    vmrghw 2, 3, 2
-; PC64LE9-NEXT:    xscvdpspn 35, 31
+; PC64LE9-NEXT:    xxperm 34, 0, 1
+; PC64LE9-NEXT:    lxv 63, 32(1) # 16-byte Folded Reload
 ; PC64LE9-NEXT:    lfd 31, 72(1) # 8-byte Folded Reload
-; PC64LE9-NEXT:    vperm 2, 3, 2, 4
+; PC64LE9-NEXT:    lfd 30, 64(1) # 8-byte Folded Reload
+; PC64LE9-NEXT:    ld 30, 48(1) # 8-byte Folded Reload
 ; PC64LE9-NEXT:    addi 1, 1, 80
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %powi = call <3 x float> @llvm.experimental.constrained.powi.v3f32(
                               <3 x float> %x,
                               i32 %y,

 ; PC64LE9-NEXT:    xxsldwi 0, 63, 63, 3
 ; PC64LE9-NEXT:    fmr 30, 1
 ; PC64LE9-NEXT:    xscvspdpn 1, 0
 ; PC64LE9-NEXT:    bl sinf
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    xscvdpspn 34, 1
 ; PC64LE9-NEXT:    xscvdpspn 35, 30
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI42_0@toc@ha
-; PC64LE9-NEXT:    xscvdpspn 36, 31
+; PC64LE9-NEXT:    xscvdpspn 1, 31
+; PC64LE9-NEXT:    addi 3, 3, .LCPI42_0@toc@l
+; PC64LE9-NEXT:    lxv 0, 0(3)
+; PC64LE9-NEXT:    vmrghw 2, 3, 2
+; PC64LE9-NEXT:    xxperm 34, 1, 0
 ; PC64LE9-NEXT:    lxv 63, 32(1) # 16-byte Folded Reload
 ; PC64LE9-NEXT:    lfd 31, 56(1) # 8-byte Folded Reload
-; PC64LE9-NEXT:    addi 3, 3, .LCPI42_0@toc@l
 ; PC64LE9-NEXT:    lfd 30, 48(1) # 8-byte Folded Reload
-; PC64LE9-NEXT:    vmrghw 2, 3, 2
-; PC64LE9-NEXT:    lxv 35, 0(3)
-; PC64LE9-NEXT:    vperm 2, 4, 2, 3
 ; PC64LE9-NEXT:    addi 1, 1, 64
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %sin = call <3 x float> @llvm.experimental.constrained.sin.v3f32(
                               <3 x float> %x,
                               metadata !"round.dynamic",

 ; PC64LE9-NEXT:    xxsldwi 0, 63, 63, 3
 ; PC64LE9-NEXT:    fmr 30, 1
 ; PC64LE9-NEXT:    xscvspdpn 1, 0
 ; PC64LE9-NEXT:    bl cosf
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    xscvdpspn 34, 1
 ; PC64LE9-NEXT:    xscvdpspn 35, 30
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI47_0@toc@ha
-; PC64LE9-NEXT:    xscvdpspn 36, 31
+; PC64LE9-NEXT:    xscvdpspn 1, 31
+; PC64LE9-NEXT:    addi 3, 3, .LCPI47_0@toc@l
+; PC64LE9-NEXT:    lxv 0, 0(3)
+; PC64LE9-NEXT:    vmrghw 2, 3, 2
+; PC64LE9-NEXT:    xxperm 34, 1, 0
 ; PC64LE9-NEXT:    lxv 63, 32(1) # 16-byte Folded Reload
 ; PC64LE9-NEXT:    lfd 31, 56(1) # 8-byte Folded Reload
-; PC64LE9-NEXT:    addi 3, 3, .LCPI47_0@toc@l
 ; PC64LE9-NEXT:    lfd 30, 48(1) # 8-byte Folded Reload
-; PC64LE9-NEXT:    vmrghw 2, 3, 2
-; PC64LE9-NEXT:    lxv 35, 0(3)
-; PC64LE9-NEXT:    vperm 2, 4, 2, 3
 ; PC64LE9-NEXT:    addi 1, 1, 64
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %cos = call <3 x float> @llvm.experimental.constrained.cos.v3f32(
                               <3 x float> %x,
                               metadata !"round.dynamic",

 ; PC64LE9-NEXT:    xxsldwi 0, 63, 63, 3
 ; PC64LE9-NEXT:    fmr 30, 1
 ; PC64LE9-NEXT:    xscvspdpn 1, 0
 ; PC64LE9-NEXT:    bl expf
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    xscvdpspn 34, 1
 ; PC64LE9-NEXT:    xscvdpspn 35, 30
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI52_0@toc@ha
-; PC64LE9-NEXT:    xscvdpspn 36, 31
+; PC64LE9-NEXT:    xscvdpspn 1, 31
+; PC64LE9-NEXT:    addi 3, 3, .LCPI52_0@toc@l
+; PC64LE9-NEXT:    lxv 0, 0(3)
+; PC64LE9-NEXT:    vmrghw 2, 3, 2
+; PC64LE9-NEXT:    xxperm 34, 1, 0
 ; PC64LE9-NEXT:    lxv 63, 32(1) # 16-byte Folded Reload
 ; PC64LE9-NEXT:    lfd 31, 56(1) # 8-byte Folded Reload
-; PC64LE9-NEXT:    addi 3, 3, .LCPI52_0@toc@l
 ; PC64LE9-NEXT:    lfd 30, 48(1) # 8-byte Folded Reload
-; PC64LE9-NEXT:    vmrghw 2, 3, 2
-; PC64LE9-NEXT:    lxv 35, 0(3)
-; PC64LE9-NEXT:    vperm 2, 4, 2, 3
 ; PC64LE9-NEXT:    addi 1, 1, 64
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %exp = call <3 x float> @llvm.experimental.constrained.exp.v3f32(
                               <3 x float> %x,
                               metadata !"round.dynamic",

 ; PC64LE9-NEXT:    xxsldwi 0, 63, 63, 3
 ; PC64LE9-NEXT:    fmr 30, 1
 ; PC64LE9-NEXT:    xscvspdpn 1, 0
 ; PC64LE9-NEXT:    bl exp2f
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    xscvdpspn 34, 1
 ; PC64LE9-NEXT:    xscvdpspn 35, 30
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI57_0@toc@ha
-; PC64LE9-NEXT:    xscvdpspn 36, 31
+; PC64LE9-NEXT:    xscvdpspn 1, 31
+; PC64LE9-NEXT:    addi 3, 3, .LCPI57_0@toc@l
+; PC64LE9-NEXT:    lxv 0, 0(3)
+; PC64LE9-NEXT:    vmrghw 2, 3, 2
+; PC64LE9-NEXT:    xxperm 34, 1, 0
 ; PC64LE9-NEXT:    lxv 63, 32(1) # 16-byte Folded Reload
 ; PC64LE9-NEXT:    lfd 31, 56(1) # 8-byte Folded Reload
-; PC64LE9-NEXT:    addi 3, 3, .LCPI57_0@toc@l
 ; PC64LE9-NEXT:    lfd 30, 48(1) # 8-byte Folded Reload
-; PC64LE9-NEXT:    vmrghw 2, 3, 2
-; PC64LE9-NEXT:    lxv 35, 0(3)
-; PC64LE9-NEXT:    vperm 2, 4, 2, 3
 ; PC64LE9-NEXT:    addi 1, 1, 64
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %exp2 = call <3 x float> @llvm.experimental.constrained.exp2.v3f32(
                               <3 x float> %x,
                               metadata !"round.dynamic",

 ; PC64LE9-NEXT:    xxsldwi 0, 63, 63, 3
 ; PC64LE9-NEXT:    fmr 30, 1
 ; PC64LE9-NEXT:    xscvspdpn 1, 0
 ; PC64LE9-NEXT:    bl logf
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    xscvdpspn 34, 1
 ; PC64LE9-NEXT:    xscvdpspn 35, 30
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI62_0@toc@ha
-; PC64LE9-NEXT:    xscvdpspn 36, 31
+; PC64LE9-NEXT:    xscvdpspn 1, 31
+; PC64LE9-NEXT:    addi 3, 3, .LCPI62_0@toc@l
+; PC64LE9-NEXT:    lxv 0, 0(3)
+; PC64LE9-NEXT:    vmrghw 2, 3, 2
+; PC64LE9-NEXT:    xxperm 34, 1, 0
 ; PC64LE9-NEXT:    lxv 63, 32(1) # 16-byte Folded Reload
 ; PC64LE9-NEXT:    lfd 31, 56(1) # 8-byte Folded Reload
-; PC64LE9-NEXT:    addi 3, 3, .LCPI62_0@toc@l
 ; PC64LE9-NEXT:    lfd 30, 48(1) # 8-byte Folded Reload
-; PC64LE9-NEXT:    vmrghw 2, 3, 2
-; PC64LE9-NEXT:    lxv 35, 0(3)
-; PC64LE9-NEXT:    vperm 2, 4, 2, 3
 ; PC64LE9-NEXT:    addi 1, 1, 64
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %log = call <3 x float> @llvm.experimental.constrained.log.v3f32(
                               <3 x float> %x,
                               metadata !"round.dynamic",

 ; PC64LE9-NEXT:    xxsldwi 0, 63, 63, 3
 ; PC64LE9-NEXT:    fmr 30, 1
 ; PC64LE9-NEXT:    xscvspdpn 1, 0
 ; PC64LE9-NEXT:    bl log10f
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    xscvdpspn 34, 1
 ; PC64LE9-NEXT:    xscvdpspn 35, 30
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI67_0@toc@ha
-; PC64LE9-NEXT:    xscvdpspn 36, 31
+; PC64LE9-NEXT:    xscvdpspn 1, 31
+; PC64LE9-NEXT:    addi 3, 3, .LCPI67_0@toc@l
+; PC64LE9-NEXT:    lxv 0, 0(3)
+; PC64LE9-NEXT:    vmrghw 2, 3, 2
+; PC64LE9-NEXT:    xxperm 34, 1, 0
 ; PC64LE9-NEXT:    lxv 63, 32(1) # 16-byte Folded Reload
 ; PC64LE9-NEXT:    lfd 31, 56(1) # 8-byte Folded Reload
-; PC64LE9-NEXT:    addi 3, 3, .LCPI67_0@toc@l
 ; PC64LE9-NEXT:    lfd 30, 48(1) # 8-byte Folded Reload
-; PC64LE9-NEXT:    vmrghw 2, 3, 2
-; PC64LE9-NEXT:    lxv 35, 0(3)
-; PC64LE9-NEXT:    vperm 2, 4, 2, 3
 ; PC64LE9-NEXT:    addi 1, 1, 64
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %log10 = call <3 x float> @llvm.experimental.constrained.log10.v3f32(
                               <3 x float> %x,
                               metadata !"round.dynamic",

 ; PC64LE9-NEXT:    xxsldwi 0, 63, 63, 3
 ; PC64LE9-NEXT:    fmr 30, 1
 ; PC64LE9-NEXT:    xscvspdpn 1, 0
 ; PC64LE9-NEXT:    bl log2f
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    xscvdpspn 34, 1
 ; PC64LE9-NEXT:    xscvdpspn 35, 30
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI72_0@toc@ha
-; PC64LE9-NEXT:    xscvdpspn 36, 31
+; PC64LE9-NEXT:    xscvdpspn 1, 31
+; PC64LE9-NEXT:    addi 3, 3, .LCPI72_0@toc@l
+; PC64LE9-NEXT:    lxv 0, 0(3)
+; PC64LE9-NEXT:    vmrghw 2, 3, 2
+; PC64LE9-NEXT:    xxperm 34, 1, 0
 ; PC64LE9-NEXT:    lxv 63, 32(1) # 16-byte Folded Reload
 ; PC64LE9-NEXT:    lfd 31, 56(1) # 8-byte Folded Reload
-; PC64LE9-NEXT:    addi 3, 3, .LCPI72_0@toc@l
 ; PC64LE9-NEXT:    lfd 30, 48(1) # 8-byte Folded Reload
-; PC64LE9-NEXT:    vmrghw 2, 3, 2
-; PC64LE9-NEXT:    lxv 35, 0(3)
-; PC64LE9-NEXT:    vperm 2, 4, 2, 3
 ; PC64LE9-NEXT:    addi 1, 1, 64
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %log2 = call <3 x float> @llvm.experimental.constrained.log2.v3f32(
                               <3 x float> %x,
                               metadata !"round.dynamic",

 ; PC64LE9-NEXT:    xscvspdpn 1, 1
 ; PC64LE9-NEXT:    xscvspdpn 2, 2
 ; PC64LE9-NEXT:    xscvspdpn 0, 0
 ; PC64LE9-NEXT:    xsrdpic 1, 1
 ; PC64LE9-NEXT:    xsrdpic 2, 2
 ; PC64LE9-NEXT:    xsrdpic 0, 0
 ; PC64LE9-NEXT:    xscvdpspn 34, 2
 ; PC64LE9-NEXT:    xscvdpspn 35, 1
-; PC64LE9-NEXT:    xscvdpspn 36, 0
+; PC64LE9-NEXT:    xscvdpspn 0, 0
+; PC64LE9-NEXT:    lxv 1, 0(3)
 ; PC64LE9-NEXT:    vmrghw 2, 3, 2
-; PC64LE9-NEXT:    lxv 35, 0(3)
-; PC64LE9-NEXT:    vperm 2, 4, 2, 3
+; PC64LE9-NEXT:    xxperm 34, 0, 1
 ; PC64LE9-NEXT:    blr
  entry:
   %rint = call <3 x float> @llvm.experimental.constrained.rint.v3f32(
                               <3 x float> %x,
                               metadata !"round.dynamic",
                               metadata !"fpexcept.strict") #1
   ret <3 x float> %rint
 }

 ; PC64LE9-NEXT:    xxsldwi 0, 63, 63, 3
 ; PC64LE9-NEXT:    fmr 30, 1
 ; PC64LE9-NEXT:    xscvspdpn 1, 0
 ; PC64LE9-NEXT:    bl nearbyintf
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    xscvdpspn 34, 1
 ; PC64LE9-NEXT:    xscvdpspn 35, 30
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI82_0@toc@ha
-; PC64LE9-NEXT:    xscvdpspn 36, 31
+; PC64LE9-NEXT:    xscvdpspn 1, 31
+; PC64LE9-NEXT:    addi 3, 3, .LCPI82_0@toc@l
+; PC64LE9-NEXT:    lxv 0, 0(3)
+; PC64LE9-NEXT:    vmrghw 2, 3, 2
+; PC64LE9-NEXT:    xxperm 34, 1, 0
 ; PC64LE9-NEXT:    lxv 63, 32(1) # 16-byte Folded Reload
 ; PC64LE9-NEXT:    lfd 31, 56(1) # 8-byte Folded Reload
-; PC64LE9-NEXT:    addi 3, 3, .LCPI82_0@toc@l
 ; PC64LE9-NEXT:    lfd 30, 48(1) # 8-byte Folded Reload
-; PC64LE9-NEXT:    vmrghw 2, 3, 2
-; PC64LE9-NEXT:    lxv 35, 0(3)
-; PC64LE9-NEXT:    vperm 2, 4, 2, 3
 ; PC64LE9-NEXT:    addi 1, 1, 64
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %nearby = call <3 x float> @llvm.experimental.constrained.nearbyint.v3f32(
                               <3 x float> %x,
                               metadata !"round.dynamic",

 ; PC64LE9-NEXT:    xscvspdpn 1, 0
 ; PC64LE9-NEXT:    xxsldwi 0, 63, 63, 3
 ; PC64LE9-NEXT:    xscvspdpn 2, 0
 ; PC64LE9-NEXT:    bl fmaxf
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    xscvdpspn 34, 1
 ; PC64LE9-NEXT:    xscvdpspn 35, 30
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI87_0@toc@ha
-; PC64LE9-NEXT:    lxv 63, 48(1) # 16-byte Folded Reload
-; PC64LE9-NEXT:    lxv 62, 32(1) # 16-byte Folded Reload
-; PC64LE9-NEXT:    lfd 30, 64(1) # 8-byte Folded Reload
+; PC64LE9-NEXT:    xscvdpspn 0, 31
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI87_0@toc@l
-; PC64LE9-NEXT:    lxv 36, 0(3)
+; PC64LE9-NEXT:    lxv 1, 0(3)
 ; PC64LE9-NEXT:    vmrghw 2, 3, 2
-; PC64LE9-NEXT:    xscvdpspn 35, 31
+; PC64LE9-NEXT:    xxperm 34, 0, 1
+; PC64LE9-NEXT:    lxv 63, 48(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    lxv 62, 32(1) # 16-byte Folded Reload
 ; PC64LE9-NEXT:    lfd 31, 72(1) # 8-byte Folded Reload
-; PC64LE9-NEXT:    vperm 2, 3, 2, 4
+; PC64LE9-NEXT:    lfd 30, 64(1) # 8-byte Folded Reload
 ; PC64LE9-NEXT:    addi 1, 1, 80
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %max = call <3 x float> @llvm.experimental.constrained.maxnum.v3f32(
                               <3 x float> %x,
                               <3 x float> %y,

 ; PC64LE9-NEXT:    xscvspdpn 1, 0
 ; PC64LE9-NEXT:    xxsldwi 0, 63, 63, 3
 ; PC64LE9-NEXT:    xscvspdpn 2, 0
 ; PC64LE9-NEXT:    bl fminf
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    xscvdpspn 34, 1
 ; PC64LE9-NEXT:    xscvdpspn 35, 30
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI92_0@toc@ha
-; PC64LE9-NEXT:    lxv 63, 48(1) # 16-byte Folded Reload
-; PC64LE9-NEXT:    lxv 62, 32(1) # 16-byte Folded Reload
-; PC64LE9-NEXT:    lfd 30, 64(1) # 8-byte Folded Reload
+; PC64LE9-NEXT:    xscvdpspn 0, 31
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI92_0@toc@l
-; PC64LE9-NEXT:    lxv 36, 0(3)
+; PC64LE9-NEXT:    lxv 1, 0(3)
 ; PC64LE9-NEXT:    vmrghw 2, 3, 2
-; PC64LE9-NEXT:    xscvdpspn 35, 31
+; PC64LE9-NEXT:    xxperm 34, 0, 1
+; PC64LE9-NEXT:    lxv 63, 48(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    lxv 62, 32(1) # 16-byte Folded Reload
 ; PC64LE9-NEXT:    lfd 31, 72(1) # 8-byte Folded Reload
-; PC64LE9-NEXT:    vperm 2, 3, 2, 4
+; PC64LE9-NEXT:    lfd 30, 64(1) # 8-byte Folded Reload
 ; PC64LE9-NEXT:    addi 1, 1, 80
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %min = call <3 x float> @llvm.experimental.constrained.minnum.v3f32(
                               <3 x float> %x,
                               <3 x float> %y,

 ; PC64LE-NEXT:    lvx 3, 0, 3
 ; PC64LE-NEXT:    mtvsrwz 36, 4
 ; PC64LE-NEXT:    vperm 2, 4, 2, 3
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fptosi_v3i32_v3f32:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 3
+; PC64LE9-NEXT:    xxsldwi 1, 34, 34, 1
 ; PC64LE9-NEXT:    xscvspdpn 0, 0
+; PC64LE9-NEXT:    xscvspdpn 1, 1
 ; PC64LE9-NEXT:    xscvdpsxws 0, 0
+; PC64LE9-NEXT:    xscvdpsxws 1, 1
 ; PC64LE9-NEXT:    mffprwz 3, 0
 ; PC64LE9-NEXT:    xxswapd 0, 34
 ; PC64LE9-NEXT:    mtvsrwz 35, 3
 ; PC64LE9-NEXT:    xscvspdpn 0, 0
 ; PC64LE9-NEXT:    xscvdpsxws 0, 0
 ; PC64LE9-NEXT:    mffprwz 3, 0
-; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 1
 ; PC64LE9-NEXT:    mtvsrwz 36, 3
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI97_0@toc@ha
-; PC64LE9-NEXT:    xscvspdpn 0, 0
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI97_0@toc@l
 ; PC64LE9-NEXT:    vmrghw 3, 4, 3
-; PC64LE9-NEXT:    xscvdpsxws 0, 0
-; PC64LE9-NEXT:    lxv 36, 0(3)
-; PC64LE9-NEXT:    mffprwz 3, 0
-; PC64LE9-NEXT:    mtvsrwz 34, 3
-; PC64LE9-NEXT:    vperm 2, 2, 3, 4
+; PC64LE9-NEXT:    lxv 0, 0(3)
+; PC64LE9-NEXT:    mffprwz 3, 1
+; PC64LE9-NEXT:    mtfprwz 1, 3
+; PC64LE9-NEXT:    xxperm 35, 1, 0
+; PC64LE9-NEXT:    vmr 2, 3
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <3 x i32> @llvm.experimental.constrained.fptosi.v3i32.v3f32(
                                 <3 x float> %x,
                                 metadata !"fpexcept.strict") #0
   ret <3 x i32> %result
 }
 

 ; PC64LE-NEXT:    lvx 3, 0, 3
 ; PC64LE-NEXT:    mtvsrwz 36, 4
 ; PC64LE-NEXT:    vperm 2, 4, 2, 3
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fptosi_v3i32_v3f64:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    xscvdpsxws 0, 1
+; PC64LE9-NEXT:    xscvdpsxws 1, 3
 ; PC64LE9-NEXT:    mffprwz 3, 0
 ; PC64LE9-NEXT:    xscvdpsxws 0, 2
 ; PC64LE9-NEXT:    mtvsrwz 34, 3
 ; PC64LE9-NEXT:    mffprwz 3, 0
-; PC64LE9-NEXT:    xscvdpsxws 0, 3
 ; PC64LE9-NEXT:    mtvsrwz 35, 3
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI105_0@toc@ha
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI105_0@toc@l
 ; PC64LE9-NEXT:    vmrghw 2, 3, 2
-; PC64LE9-NEXT:    lxv 35, 0(3)
-; PC64LE9-NEXT:    mffprwz 3, 0
-; PC64LE9-NEXT:    mtvsrwz 36, 3
-; PC64LE9-NEXT:    vperm 2, 4, 2, 3
+; PC64LE9-NEXT:    lxv 0, 0(3)
+; PC64LE9-NEXT:    mffprwz 3, 1
+; PC64LE9-NEXT:    mtfprwz 1, 3
+; PC64LE9-NEXT:    xxperm 34, 1, 0
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <3 x i32> @llvm.experimental.constrained.fptosi.v3i32.v3f64(
                                 <3 x double> %x,
                                 metadata !"fpexcept.strict") #0
   ret <3 x i32> %result
 }
 

 ; PC64LE-NEXT:    lvx 3, 0, 3
 ; PC64LE-NEXT:    mtvsrwz 36, 4
 ; PC64LE-NEXT:    vperm 2, 4, 2, 3
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fptoui_v3i32_v3f32:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 3
+; PC64LE9-NEXT:    xxsldwi 1, 34, 34, 1
 ; PC64LE9-NEXT:    xscvspdpn 0, 0
+; PC64LE9-NEXT:    xscvspdpn 1, 1
 ; PC64LE9-NEXT:    xscvdpuxws 0, 0
+; PC64LE9-NEXT:    xscvdpuxws 1, 1
 ; PC64LE9-NEXT:    mffprwz 3, 0
 ; PC64LE9-NEXT:    xxswapd 0, 34
 ; PC64LE9-NEXT:    mtvsrwz 35, 3
 ; PC64LE9-NEXT:    xscvspdpn 0, 0
 ; PC64LE9-NEXT:    xscvdpuxws 0, 0
 ; PC64LE9-NEXT:    mffprwz 3, 0
-; PC64LE9-NEXT:    xxsldwi 0, 34, 34, 1
 ; PC64LE9-NEXT:    mtvsrwz 36, 3
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI113_0@toc@ha
-; PC64LE9-NEXT:    xscvspdpn 0, 0
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI113_0@toc@l
 ; PC64LE9-NEXT:    vmrghw 3, 4, 3
-; PC64LE9-NEXT:    xscvdpuxws 0, 0
-; PC64LE9-NEXT:    lxv 36, 0(3)
-; PC64LE9-NEXT:    mffprwz 3, 0
-; PC64LE9-NEXT:    mtvsrwz 34, 3
-; PC64LE9-NEXT:    vperm 2, 2, 3, 4
+; PC64LE9-NEXT:    lxv 0, 0(3)
+; PC64LE9-NEXT:    mffprwz 3, 1
+; PC64LE9-NEXT:    mtfprwz 1, 3
+; PC64LE9-NEXT:    xxperm 35, 1, 0
+; PC64LE9-NEXT:    vmr 2, 3
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <3 x i32> @llvm.experimental.constrained.fptoui.v3i32.v3f32(
                                 <3 x float> %x,
                                 metadata !"fpexcept.strict") #0
   ret <3 x i32> %result
 }
 

 ; PC64LE-NEXT:    lvx 3, 0, 3
 ; PC64LE-NEXT:    mtvsrwz 36, 4
 ; PC64LE-NEXT:    vperm 2, 4, 2, 3
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fptoui_v3i32_v3f64:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    xscvdpuxws 0, 1
+; PC64LE9-NEXT:    xscvdpuxws 1, 3
 ; PC64LE9-NEXT:    mffprwz 3, 0
 ; PC64LE9-NEXT:    xscvdpuxws 0, 2
 ; PC64LE9-NEXT:    mtvsrwz 34, 3
 ; PC64LE9-NEXT:    mffprwz 3, 0
-; PC64LE9-NEXT:    xscvdpuxws 0, 3
 ; PC64LE9-NEXT:    mtvsrwz 35, 3
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI121_0@toc@ha
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI121_0@toc@l
 ; PC64LE9-NEXT:    vmrghw 2, 3, 2
-; PC64LE9-NEXT:    lxv 35, 0(3)
-; PC64LE9-NEXT:    mffprwz 3, 0
-; PC64LE9-NEXT:    mtvsrwz 36, 3
-; PC64LE9-NEXT:    vperm 2, 4, 2, 3
+; PC64LE9-NEXT:    lxv 0, 0(3)
+; PC64LE9-NEXT:    mffprwz 3, 1
+; PC64LE9-NEXT:    mtfprwz 1, 3
+; PC64LE9-NEXT:    xxperm 34, 1, 0
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <3 x i32> @llvm.experimental.constrained.fptoui.v3i32.v3f64(
                                 <3 x double> %x,
                                 metadata !"fpexcept.strict") #0
   ret <3 x i32> %result
 }
 

 ;
 ; PC64LE9-LABEL: constrained_vector_fptrunc_v3f64:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    xsrsp 0, 1
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI129_0@toc@ha
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI129_0@toc@l
 ; PC64LE9-NEXT:    xscvdpspn 34, 0
 ; PC64LE9-NEXT:    xsrsp 0, 2
+; PC64LE9-NEXT:    xsrsp 1, 3
 ; PC64LE9-NEXT:    xscvdpspn 35, 0
-; PC64LE9-NEXT:    xsrsp 0, 3
-; PC64LE9-NEXT:    xscvdpspn 36, 0
+; PC64LE9-NEXT:    xscvdpspn 1, 1
+; PC64LE9-NEXT:    lxv 0, 0(3)
 ; PC64LE9-NEXT:    vmrghw 2, 3, 2
-; PC64LE9-NEXT:    lxv 35, 0(3)
-; PC64LE9-NEXT:    vperm 2, 4, 2, 3
+; PC64LE9-NEXT:    xxperm 34, 1, 0
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <3 x float> @llvm.experimental.constrained.fptrunc.v3f32.v3f64(
                                 <3 x double> %x,
                                 metadata !"round.dynamic",
                                 metadata !"fpexcept.strict") #1
   ret <3 x float> %result
 }

 ; PC64LE9-NEXT:    xscvspdpn 1, 1
 ; PC64LE9-NEXT:    xscvspdpn 2, 2
 ; PC64LE9-NEXT:    xscvspdpn 0, 0
 ; PC64LE9-NEXT:    xsrdpip 1, 1
 ; PC64LE9-NEXT:    xsrdpip 2, 2
 ; PC64LE9-NEXT:    xsrdpip 0, 0
 ; PC64LE9-NEXT:    xscvdpspn 34, 2
 ; PC64LE9-NEXT:    xscvdpspn 35, 1
-; PC64LE9-NEXT:    xscvdpspn 36, 0
+; PC64LE9-NEXT:    xscvdpspn 0, 0
+; PC64LE9-NEXT:    lxv 1, 0(3)
 ; PC64LE9-NEXT:    vmrghw 2, 3, 2
-; PC64LE9-NEXT:    lxv 35, 0(3)
-; PC64LE9-NEXT:    vperm 2, 4, 2, 3
+; PC64LE9-NEXT:    xxperm 34, 0, 1
 ; PC64LE9-NEXT:    blr
 entry:
   %ceil = call <3 x float> @llvm.experimental.constrained.ceil.v3f32(
                               <3 x float> %x,
                               metadata !"fpexcept.strict") #1
   ret <3 x float> %ceil
 }
 

 ; PC64LE9-NEXT:    xscvspdpn 1, 1
 ; PC64LE9-NEXT:    xscvspdpn 2, 2
 ; PC64LE9-NEXT:    xscvspdpn 0, 0
 ; PC64LE9-NEXT:    xsrdpim 1, 1
 ; PC64LE9-NEXT:    xsrdpim 2, 2
 ; PC64LE9-NEXT:    xsrdpim 0, 0
 ; PC64LE9-NEXT:    xscvdpspn 34, 2
 ; PC64LE9-NEXT:    xscvdpspn 35, 1
-; PC64LE9-NEXT:    xscvdpspn 36, 0
+; PC64LE9-NEXT:    xscvdpspn 0, 0
+; PC64LE9-NEXT:    lxv 1, 0(3)
 ; PC64LE9-NEXT:    vmrghw 2, 3, 2
-; PC64LE9-NEXT:    lxv 35, 0(3)
-; PC64LE9-NEXT:    vperm 2, 4, 2, 3
+; PC64LE9-NEXT:    xxperm 34, 0, 1
 ; PC64LE9-NEXT:    blr
 entry:
   %floor = call <3 x float> @llvm.experimental.constrained.floor.v3f32(
                               <3 x float> %x,
                               metadata !"fpexcept.strict") #1
   ret <3 x float> %floor
 }
 

 ; PC64LE9-NEXT:    xscvspdpn 1, 1
 ; PC64LE9-NEXT:    xscvspdpn 2, 2
 ; PC64LE9-NEXT:    xscvspdpn 0, 0
 ; PC64LE9-NEXT:    xsrdpi 1, 1
 ; PC64LE9-NEXT:    xsrdpi 2, 2
 ; PC64LE9-NEXT:    xsrdpi 0, 0
 ; PC64LE9-NEXT:    xscvdpspn 34, 2
 ; PC64LE9-NEXT:    xscvdpspn 35, 1
-; PC64LE9-NEXT:    xscvdpspn 36, 0
+; PC64LE9-NEXT:    xscvdpspn 0, 0
+; PC64LE9-NEXT:    lxv 1, 0(3)
 ; PC64LE9-NEXT:    vmrghw 2, 3, 2
-; PC64LE9-NEXT:    lxv 35, 0(3)
-; PC64LE9-NEXT:    vperm 2, 4, 2, 3
+; PC64LE9-NEXT:    xxperm 34, 0, 1
 ; PC64LE9-NEXT:    blr
 entry:
   %round = call <3 x float> @llvm.experimental.constrained.round.v3f32(
                               <3 x float> %x,
                               metadata !"fpexcept.strict") #1
   ret <3 x float> %round
 }
 

 ; PC64LE9-NEXT:    xscvspdpn 1, 1
 ; PC64LE9-NEXT:    xscvspdpn 2, 2
 ; PC64LE9-NEXT:    xscvspdpn 0, 0
 ; PC64LE9-NEXT:    xsrdpiz 1, 1
 ; PC64LE9-NEXT:    xsrdpiz 2, 2
 ; PC64LE9-NEXT:    xsrdpiz 0, 0
 ; PC64LE9-NEXT:    xscvdpspn 34, 2
 ; PC64LE9-NEXT:    xscvdpspn 35, 1
-; PC64LE9-NEXT:    xscvdpspn 36, 0
+; PC64LE9-NEXT:    xscvdpspn 0, 0
+; PC64LE9-NEXT:    lxv 1, 0(3)
 ; PC64LE9-NEXT:    vmrghw 2, 3, 2
-; PC64LE9-NEXT:    lxv 35, 0(3)
-; PC64LE9-NEXT:    vperm 2, 4, 2, 3
+; PC64LE9-NEXT:    xxperm 34, 0, 1
 ; PC64LE9-NEXT:    blr
 entry:
   %trunc = call <3 x float> @llvm.experimental.constrained.trunc.v3f32(
                               <3 x float> %x,
                               metadata !"fpexcept.strict") #1
   ret <3 x float> %trunc
 }
 

 ; PC64LE-NEXT:    vsrad 2, 2, 3
 ; PC64LE-NEXT:    xvcvsxddp 34, 34
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_sitofp_v2f64_v2i16:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI155_0@toc@ha
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI155_0@toc@l
-; PC64LE9-NEXT:    lxv 35, 0(3)
-; PC64LE9-NEXT:    vperm 2, 2, 2, 3
+; PC64LE9-NEXT:    lxv 0, 0(3)
+; PC64LE9-NEXT:    xxperm 34, 34, 0
 ; PC64LE9-NEXT:    vextsh2d 2, 2
 ; PC64LE9-NEXT:    xvcvsxddp 34, 34
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <2 x double>
            @llvm.experimental.constrained.sitofp.v2f64.v2i16(<2 x i16> %x,
                                                 metadata !"round.dynamic",
                                                 metadata !"fpexcept.strict") #0

 ; PC64LE9-NEXT:    xscvsxdsp 0, 0
 ; PC64LE9-NEXT:    vextuwrx 3, 3, 2
 ; PC64LE9-NEXT:    xscvdpspn 35, 0
 ; PC64LE9-NEXT:    mtfprwa 0, 3
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI161_0@toc@ha
 ; PC64LE9-NEXT:    xscvsxdsp 0, 0
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI161_0@toc@l
 ; PC64LE9-NEXT:    xscvdpspn 36, 0
-; PC64LE9-NEXT:    vmrghw 3, 4, 3
-; PC64LE9-NEXT:    lxv 36, 0(3)
+; PC64LE9-NEXT:    lxv 0, 0(3)
 ; PC64LE9-NEXT:    mfvsrwz 3, 34
-; PC64LE9-NEXT:    mtfprwa 0, 3
-; PC64LE9-NEXT:    xscvsxdsp 0, 0
-; PC64LE9-NEXT:    xscvdpspn 34, 0
-; PC64LE9-NEXT:    vperm 2, 2, 3, 4
+; PC64LE9-NEXT:    mtfprwa 1, 3
+; PC64LE9-NEXT:    xscvsxdsp 1, 1
+; PC64LE9-NEXT:    vmrghw 3, 4, 3
+; PC64LE9-NEXT:    xscvdpspn 1, 1
+; PC64LE9-NEXT:    xxperm 35, 1, 0
+; PC64LE9-NEXT:    vmr 2, 3
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <3 x float>
            @llvm.experimental.constrained.sitofp.v3f32.v3i32(<3 x i32> %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret <3 x float> %result
 }

 ; PC64LE-NEXT:    vmrghw 2, 3, 2
 ; PC64LE-NEXT:    xscvdpspn 35, 0
 ; PC64LE-NEXT:    vperm 2, 3, 2, 4
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_sitofp_v3f32_v3i64:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    mtfprd 0, 3
+; PC64LE9-NEXT:    mtfprd 1, 5
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI163_0@toc@ha
 ; PC64LE9-NEXT:    xscvsxdsp 0, 0
+; PC64LE9-NEXT:    xscvsxdsp 1, 1
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI163_0@toc@l
 ; PC64LE9-NEXT:    xscvdpspn 34, 0
 ; PC64LE9-NEXT:    mtfprd 0, 4
+; PC64LE9-NEXT:    xscvdpspn 1, 1
 ; PC64LE9-NEXT:    xscvsxdsp 0, 0
 ; PC64LE9-NEXT:    xscvdpspn 35, 0
-; PC64LE9-NEXT:    mtfprd 0, 5
-; PC64LE9-NEXT:    xscvsxdsp 0, 0
+; PC64LE9-NEXT:    lxv 0, 0(3)
 ; PC64LE9-NEXT:    vmrghw 2, 3, 2
-; PC64LE9-NEXT:    lxv 35, 0(3)
-; PC64LE9-NEXT:    xscvdpspn 36, 0
-; PC64LE9-NEXT:    vperm 2, 4, 2, 3
+; PC64LE9-NEXT:    xxperm 34, 1, 0
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <3 x float>
            @llvm.experimental.constrained.sitofp.v3f32.v3i64(<3 x i64> %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret <3 x float> %result
 }

 ; PC64LE-NEXT:    lvx 3, 0, 3
 ; PC64LE-NEXT:    vperm 2, 4, 2, 3
 ; PC64LE-NEXT:    xvcvuxddp 34, 34
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_uitofp_v2f64_v2i16:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI173_0@toc@ha
-; PC64LE9-NEXT:    xxlxor 36, 36, 36
+; PC64LE9-NEXT:    xxlxor 0, 0, 0
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI173_0@toc@l
-; PC64LE9-NEXT:    lxv 35, 0(3)
-; PC64LE9-NEXT:    vperm 2, 4, 2, 3
+; PC64LE9-NEXT:    lxv 1, 0(3)
+; PC64LE9-NEXT:    xxperm 34, 0, 1
 ; PC64LE9-NEXT:    xvcvuxddp 34, 34
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <2 x double>
            @llvm.experimental.constrained.uitofp.v2f64.v2i16(<2 x i16> %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret <2 x double> %result

 ; PC64LE9-NEXT:    xscvuxdsp 0, 0
 ; PC64LE9-NEXT:    vextuwrx 3, 3, 2
 ; PC64LE9-NEXT:    xscvdpspn 35, 0
 ; PC64LE9-NEXT:    mtfprwz 0, 3
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI179_0@toc@ha
 ; PC64LE9-NEXT:    xscvuxdsp 0, 0
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI179_0@toc@l
 ; PC64LE9-NEXT:    xscvdpspn 36, 0
-; PC64LE9-NEXT:    vmrghw 3, 4, 3
-; PC64LE9-NEXT:    lxv 36, 0(3)
+; PC64LE9-NEXT:    lxv 0, 0(3)
 ; PC64LE9-NEXT:    mfvsrwz 3, 34
-; PC64LE9-NEXT:    mtfprwz 0, 3
-; PC64LE9-NEXT:    xscvuxdsp 0, 0
-; PC64LE9-NEXT:    xscvdpspn 34, 0
-; PC64LE9-NEXT:    vperm 2, 2, 3, 4
+; PC64LE9-NEXT:    mtfprwz 1, 3
+; PC64LE9-NEXT:    xscvuxdsp 1, 1
+; PC64LE9-NEXT:    vmrghw 3, 4, 3
+; PC64LE9-NEXT:    xscvdpspn 1, 1
+; PC64LE9-NEXT:    xxperm 35, 1, 0
+; PC64LE9-NEXT:    vmr 2, 3
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <3 x float>
            @llvm.experimental.constrained.uitofp.v3f32.v3i32(<3 x i32> %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret <3 x float> %result
 }

 ; PC64LE-NEXT:    vmrghw 2, 3, 2
 ; PC64LE-NEXT:    xscvdpspn 35, 0
 ; PC64LE-NEXT:    vperm 2, 3, 2, 4
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_uitofp_v3f32_v3i64:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    mtfprd 0, 3
+; PC64LE9-NEXT:    mtfprd 1, 5
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI181_0@toc@ha
 ; PC64LE9-NEXT:    xscvuxdsp 0, 0
+; PC64LE9-NEXT:    xscvuxdsp 1, 1
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI181_0@toc@l
 ; PC64LE9-NEXT:    xscvdpspn 34, 0
 ; PC64LE9-NEXT:    mtfprd 0, 4
+; PC64LE9-NEXT:    xscvdpspn 1, 1
 ; PC64LE9-NEXT:    xscvuxdsp 0, 0
 ; PC64LE9-NEXT:    xscvdpspn 35, 0
-; PC64LE9-NEXT:    mtfprd 0, 5
-; PC64LE9-NEXT:    xscvuxdsp 0, 0
+; PC64LE9-NEXT:    lxv 0, 0(3)
 ; PC64LE9-NEXT:    vmrghw 2, 3, 2
-; PC64LE9-NEXT:    lxv 35, 0(3)
-; PC64LE9-NEXT:    xscvdpspn 36, 0
-; PC64LE9-NEXT:    vperm 2, 4, 2, 3
+; PC64LE9-NEXT:    xxperm 34, 1, 0
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <3 x float>
            @llvm.experimental.constrained.uitofp.v3f32.v3i64(<3 x i64> %x,
                                                metadata !"round.dynamic",
                                                metadata !"fpexcept.strict") #0
   ret <3 x float> %result
 }

llvm/test/CodeGen/PowerPC/xxperm-tests.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN:   -mtriple=powerpc64le-unknown-unknown < %s | FileCheck  %s \
+; RUN:   -check-prefix=P9LE
+; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN:   -mtriple=powerpc64-unknown-unknown < %s | FileCheck  %s \
+; RUN:   -check-prefix=P9BE
+; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN:   -mtriple=powerpc64-unknown-unknown < %s | FileCheck  %s \
+; RUN:   -check-prefix=P8
+
+define <4 x i32> @fromDiffMemConsDConvftoi(float* nocapture readonly %ptr) {
+; P9LE-LABEL: fromDiffMemConsDConvftoi:
+; P9LE:       # %bb.0: # %entry
+; P9LE-NEXT:    lxv vs0, 0(r3)
+; P9LE-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
+; P9LE-NEXT:    addi r3, r3, .LCPI0_0@toc@l
+; P9LE-NEXT:    lxv vs1, 0(r3)
+; P9LE-NEXT:    xxperm vs0, vs0, vs1
+; P9LE-NEXT:    xvcvspsxws v2, vs0
+; P9LE-NEXT:    blr
+;
+; P9BE-LABEL: fromDiffMemConsDConvftoi:
+; P9BE:       # %bb.0: # %entry
+; P9BE-NEXT:    lxv vs0, 0(r3)
+; P9BE-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
+; P9BE-NEXT:    addi r3, r3, .LCPI0_0@toc@l
+; P9BE-NEXT:    lxv vs1, 0(r3)
+; P9BE-NEXT:    xxperm vs0, vs0, vs1
+; P9BE-NEXT:    xvcvspsxws v2, vs0
+; P9BE-NEXT:    blr
+;
+; P8-LABEL: fromDiffMemConsDConvftoi:
+; P8:       # %bb.0: # %entry
+; P8-NEXT:    addis r4, r2, .LCPI0_0@toc@ha
+; P8-NEXT:    lxvw4x v2, 0, r3
+; P8-NEXT:    addi r4, r4, .LCPI0_0@toc@l
+; P8-NEXT:    lxvw4x v3, 0, r4
+; P8-NEXT:    vperm v2, v2, v2, v3
+; P8-NEXT:    xvcvspsxws v2, v2
+; P8-NEXT:    blr
+entry:
+  %arrayidx = getelementptr inbounds float, float* %ptr, i64 3
+  %0 = load float, float* %arrayidx, align 4
+  %conv = fptosi float %0 to i32
+  %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
+  %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 2
+  %1 = load float, float* %arrayidx1, align 4
+  %conv2 = fptosi float %1 to i32
+  %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1
+  %arrayidx4 = getelementptr inbounds float, float* %ptr, i64 1
+  %2 = load float, float* %arrayidx4, align 4
+  %conv5 = fptosi float %2 to i32
+  %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2
+  %3 = load float, float* %ptr, align 4
+  %conv8 = fptosi float %3 to i32
+  %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3
+  ret <4 x i32> %vecinit9
+}
+
+define dso_local <16 x i8> @no_RAUW_in_combine_during_legalize(i32* nocapture readonly %ptr, i32 signext %offset) local_unnamed_addr #0 {
+; P9LE-LABEL: no_RAUW_in_combine_during_legalize:
+; P9LE:       # %bb.0: # %entry
+; P9LE-NEXT:    sldi r4, r4, 2
+; P9LE-NEXT:    xxlxor v3, v3, v3
+; P9LE-NEXT:    lfiwzx f0, r3, r4
+; P9LE-NEXT:    xxspltd v2, f0, 0
+; P9LE-NEXT:    vmrglb v2, v3, v2
+; P9LE-NEXT:    blr
+;
+; P9BE-LABEL: no_RAUW_in_combine_during_legalize:
+; P9BE:       # %bb.0: # %entry
+; P9BE-NEXT:    sldi r4, r4, 2
+; P9BE-NEXT:    xxlxor v3, v3, v3
+; P9BE-NEXT:    lxsiwzx v2, r3, r4
+; P9BE-NEXT:    vmrghb v2, v2, v3
+; P9BE-NEXT:    blr
+;
+; P8-LABEL: no_RAUW_in_combine_during_legalize:
+; P8:       # %bb.0: # %entry
+; P8-NEXT:    sldi r4, r4, 2
+; P8-NEXT:    xxlxor v3, v3, v3
+; P8-NEXT:    lxsiwzx v2, r3, r4
+; P8-NEXT:    vmrghb v2, v2, v3
+; P8-NEXT:    blr
+entry:
+  %idx.ext = sext i32 %offset to i64
+  %add.ptr = getelementptr inbounds i32, i32* %ptr, i64 %idx.ext
+  %0 = load i32, i32* %add.ptr, align 4
+  %conv = zext i32 %0 to i64
+  %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0
+  %1 = bitcast <2 x i64> %splat.splatinsert to <16 x i8>
+  %shuffle = shufflevector <16 x i8> %1, <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
+  ret <16 x i8> %shuffle
+}
+
+define <16 x i8> @test_vrlqnm(<1 x i128> %a, <1 x i128> %b, <1 x i128> %c) {
+; P9LE-LABEL: test_vrlqnm:
+; P9LE:       # %bb.0: # %entry
+; P9LE-NEXT:    addis r3, r2, .LCPI2_0@toc@ha
+; P9LE-NEXT:    vmr v2, v3
+; P9LE-NEXT:    addi r3, r3, .LCPI2_0@toc@l
+; P9LE-NEXT:    lxv vs0, 0(r3)
+; P9LE-NEXT:    xxperm v2, v4, vs0
+; P9LE-NEXT:    blr
+;
+; P9BE-LABEL: test_vrlqnm:
+; P9BE:       # %bb.0: # %entry
+; P9BE-NEXT:    addis r3, r2, .LCPI2_0@toc@ha
+; P9BE-NEXT:    vmr v2, v4
+; P9BE-NEXT:    addi r3, r3, .LCPI2_0@toc@l
+; P9BE-NEXT:    lxv vs0, 0(r3)
+; P9BE-NEXT:    xxperm v2, v3, vs0
+; P9BE-NEXT:    blr
+;
+; P8-LABEL: test_vrlqnm:
+; P8:       # %bb.0: # %entry
+; P8-NEXT:    addis r3, r2, .LCPI2_0@toc@ha
+; P8-NEXT:    addi r3, r3, .LCPI2_0@toc@l
+; P8-NEXT:    lxvw4x v2, 0, r3
+; P8-NEXT:    vperm v2, v3, v4, v2
+; P8-NEXT:    blr
+entry:
+  %0 = bitcast <1 x i128> %b to <16 x i8>
+  %1 = bitcast <1 x i128> %c to <16 x i8>
+  %shuffle.i = shufflevector <16 x i8> %0, <16 x i8> %1, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 16, i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  ret <16 x i8> %shuffle.i
+}