[MSP430] Add assembler and MC support for MSP430X shift instructions

[jozefl]

Summary

There are two forms of MSP430X extended shift instructions:

• "RxxM": RRAM, RRUM, RLAM, RRCM e.g. rram #3, r12
• "RxxX": RRAX, RRUX, RLAX, RRCX e.g. rrax r12

RxxM shifts can only shift by up to 4 bit positions, but are cheaper
than RxxX shifts.

RxxX shifts do not specify the shift count in the instruction. The shift
count is set separately by setting the repetition count in the extension
word that precedes the instruction. This support will be added in a
separate patch.

[asl]

llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp

98

Do we need these changes here?

llvm/lib/Target/MSP430/MSP430ISelLowering.cpp

46

Ditto

llvm/lib/Target/MSP430/MSP430ISelLowering.h

74

Ditto

[jozefl]

llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp

98

Yes, we need access to Subtarget so that the HasMSP430X predicate in MSP430InstrInfoExtended.td can check Subtarget->hasMSP430X() before enabling all the MSP430X instructions.

[jozefl]

Rebase onto new base revision to fix pre-merge tests.

[jozefl]

Ping.

Thanks,
Jozef

[jozefl]

Ping.

Thanks,
Jozef

[jozefl]

Ping.

Thanks,
Jozef

llvm/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp

public:
   bool isReg()   const override { return Kind == k_Reg; }
   bool isImm()   const override { return Kind == k_Imm; }
   bool isToken() const override { return Kind == k_Tok; }
   bool isMem()   const override { return Kind == k_Mem; }
   bool isIndReg()         const { return Kind == k_IndReg; }
   bool isPostIndReg()     const { return Kind == k_PostIndReg; }
 
   bool isCGImm() const {
-    if (Kind != k_Imm)
-      return false;
+    int64_t Val;
+    if (!isImm() || !Imm->evaluateAsAbsolute(Val))
+      return false;
+    
+    if (Val == 0 || Val == 1 || Val == 2 || Val == 4 || Val == 8 || Val == -1)
+      return true;
+
+  }
 
+  /// Return true if the immediate value can be used for a 2-bit reptition
+  /// count after it is encoded.
+  bool isRpt2Imm() const {
     int64_t Val;
-    if (!Imm->evaluateAsAbsolute(Val))
+    if (!isImm() || !Imm->evaluateAsAbsolute(Val))
       return false;
-    
-    if (Val == 0 || Val == 1 || Val == 2 || Val == 4 || Val == 8 || Val == -1)
+    if (Val >= 1 && Val <= 4)
       return true;
 
     return false;
   }
 
   StringRef getToken() const {
     assert(Kind == k_Tok && "Invalid access!");
     return Tok;

llvm/lib/Target/MSP430/Disassembler/MSP430Disassembler.cpp

static DecodeStatus DecodeGR16RegisterClass(MCInst &MI, uint64_t RegNo,
   unsigned Reg = GR16DecoderTable[RegNo];
   MI.addOperand(MCOperand::createReg(Reg));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeCGImm(MCInst &MI, uint64_t Bits, uint64_t Address,
                                 const void *Decoder);
 
+/// Decode the repetition count from the extension word in a 430X extended
+/// instruction.
+static DecodeStatus decodeRptImm(MCInst &MI, uint64_t Bits, uint64_t Address,
+                                 const void *Decoder);
+
 static DecodeStatus DecodeMemOperand(MCInst &MI, uint64_t Bits,
                                      uint64_t Address,
                                      const void *Decoder);
 
 #include "MSP430GenDisassemblerTables.inc"
 
 static DecodeStatus DecodeCGImm(MCInst &MI, uint64_t Bits, uint64_t Address,
                                 const void *Decoder) {
   int64_t Imm;
   switch (Bits) {
   default:
     llvm_unreachable("Invalid immediate value");
   case 0x22: Imm =  4; break;
   case 0x32: Imm =  8; break;
   case 0x03: Imm =  0; break;
   case 0x13: Imm =  1; break;
   case 0x23: Imm =  2; break;
   case 0x33: Imm = -1; break;
   }
   MI.addOperand(MCOperand::createImm(Imm));
   return MCDisassembler::Success;
 }
 
+static DecodeStatus decodeRptImm(MCInst &MI, uint64_t Bits, uint64_t Address,
+                                 const void *Decoder) {
+  if (Bits >= 16)
+    return MCDisassembler::Fail;
+  int64_t Imm = Bits + 1;
+  MI.addOperand(MCOperand::createImm(Imm));
+  return MCDisassembler::Success;
+}
+
 static DecodeStatus DecodeMemOperand(MCInst &MI, uint64_t Bits,
                                      uint64_t Address,
                                      const void *Decoder) {
   unsigned Reg = Bits & 15;
   unsigned Imm = Bits >> 4;
 
   if (DecodeGR16RegisterClass(MI, Reg, Address, Decoder) !=
       MCDisassembler::Success)

llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCCodeEmitter.cpp

 //===-- MSP430MCCodeEmitter.cpp - Convert MSP430 code to machine code -----===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the MSP430MCCodeEmitter class.
 //
 //===----------------------------------------------------------------------===//
 
-#include "MSP430.h"
-#include "MCTargetDesc/MSP430MCTargetDesc.h"
 #include "MCTargetDesc/MSP430FixupKinds.h"
+#include "MCTargetDesc/MSP430MCTargetDesc.h"
+#include "MSP430.h"
+#include "MSP430InstrInfo.h"
 
 #include "llvm/ADT/APFloat.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/MC/MCCodeEmitter.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCFixup.h"
 #include "llvm/MC/MCInst.h"
class MSP430MCCodeEmitter : public MCCodeEmitter {
   unsigned getPCRelImmOpValue(const MCInst &MI, unsigned Op,
                               SmallVectorImpl<MCFixup> &Fixups,
                               const MCSubtargetInfo &STI) const;
 
   unsigned getCGImmOpValue(const MCInst &MI, unsigned Op,
                            SmallVectorImpl<MCFixup> &Fixups,
                            const MCSubtargetInfo &STI) const;
 
+  /// Encode the repetition count for a 430X extended format exception
+  /// instruction.
+  unsigned getRpt2ImmOpValue(const MCInst &MI, unsigned Op,
+                             SmallVectorImpl<MCFixup> &Fixups,
+                             const MCSubtargetInfo &STI) const;
+
   unsigned getCCOpValue(const MCInst &MI, unsigned Op,
                         SmallVectorImpl<MCFixup> &Fixups,
                         const MCSubtargetInfo &STI) const;
 
 public:
   MSP430MCCodeEmitter(MCContext &ctx, MCInstrInfo const &MCII)
       : Ctx(ctx), MCII(MCII) {}
 
   void encodeInstruction(const MCInst &MI, raw_ostream &OS,
                          SmallVectorImpl<MCFixup> &Fixups,
                          const MCSubtargetInfo &STI) const override;
 };
 
+/// Move the extension word from the last word of the 64-bit encoded value, to
+/// the first word of the encoded value.
+static uint64_t fixExtensionWord(uint64_t EncodedValue) {
+  uint64_t ExtensionWord = EncodedValue >> 48;
+  EncodedValue <<= 16;
+  EncodedValue |= ExtensionWord;
+  return EncodedValue;
+}
+
 void MSP430MCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
                                             SmallVectorImpl<MCFixup> &Fixups,
                                             const MCSubtargetInfo &STI) const {
   const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
   // Get byte count of instruction.
   unsigned Size = Desc.getSize();
 
   // Initialize fixup offset
-  Offset = 2;
+  Offset = ((Desc.TSFlags & MSP430TSFlags::ExtensionWord) ? 4 : 2);
 
   uint64_t BinaryOpCode = getBinaryCodeForInstr(MI, Fixups, STI);
+  if (Desc.TSFlags & MSP430TSFlags::ExtensionWord)
+    BinaryOpCode = fixExtensionWord(BinaryOpCode);
+
   size_t WordCount = Size / 2;
 
   while (WordCount--) {
     support::endian::write(OS, (uint16_t)BinaryOpCode, support::little);
     BinaryOpCode >>= 16;
   }
 }
 
unsigned MSP430MCCodeEmitter::getCGImmOpValue(const MCInst &MI, unsigned Op,
   case 8:  return 0x32;
   case 0:  return 0x03;
   case 1:  return 0x13;
   case 2:  return 0x23;
   case -1: return 0x33;
   }
 }
 
+unsigned
+MSP430MCCodeEmitter::getRpt2ImmOpValue(const MCInst &MI, unsigned Op,
+                                       SmallVectorImpl<MCFixup> &Fixups,
+                                       const MCSubtargetInfo &STI) const {
+  const MCOperand &MO = MI.getOperand(Op);
+  assert(MO.isImm() && "expr operand expected");
+
+  int64_t Imm = MO.getImm();
+  assert((Imm >= 1 && Imm <= 4) && "invalid repetition count");
+  return Imm - 1;
+}
+
 unsigned MSP430MCCodeEmitter::getCCOpValue(const MCInst &MI, unsigned Op,
                                            SmallVectorImpl<MCFixup> &Fixups,
                                            const MCSubtargetInfo &STI) const {
   const MCOperand &MO = MI.getOperand(Op);
   assert(MO.isImm() && "Immediate operand expected");
   switch (MO.getImm()) {
   case MSP430CC::COND_NE: return 0;
   case MSP430CC::COND_E:  return 1;

llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp

 
 /// MSP430DAGToDAGISel - MSP430 specific code to select MSP430 machine
 /// instructions for SelectionDAG operations.
 ///
 namespace {
   class MSP430DAGToDAGISel : public SelectionDAGISel {
   public:
     MSP430DAGToDAGISel(MSP430TargetMachine &TM, CodeGenOpt::Level OptLevel)
-        : SelectionDAGISel(TM, OptLevel) {}
+        : SelectionDAGISel(TM, OptLevel), Subtarget(nullptr) {}
 
   private:
+    const MSP430Subtarget *Subtarget;
+
     StringRef getPassName() const override {
       return "MSP430 DAG->DAG Pattern Instruction Selection";
     }
 
+    bool runOnMachineFunction(MachineFunction &MF) override;
+
     bool MatchAddress(SDValue N, MSP430ISelAddressMode &AM);
     bool MatchWrapper(SDValue N, MSP430ISelAddressMode &AM);
     bool MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM);
 
     bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
                                       std::vector<SDValue> &OutOps) override;
 
     // Include the pieces autogenerated from the target description.
   #include "MSP430GenDAGISel.inc"
 
     // Main method to transform nodes into machine nodes.
     void Select(SDNode *N) override;
 
     bool tryIndexedLoad(SDNode *Op);
     bool tryIndexedBinOp(SDNode *Op, SDValue N1, SDValue N2, unsigned Opc8,
                          unsigned Opc16);
 
     bool SelectAddr(SDValue Addr, SDValue &Base, SDValue &Disp);
   };
 }  // end anonymous namespace
 
+bool MSP430DAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
+  Subtarget = &MF.getSubtarget<MSP430Subtarget>();
+  return SelectionDAGISel::runOnMachineFunction(MF);
+}
+
 /// createMSP430ISelDag - This pass converts a legalized DAG into a
 /// MSP430-specific DAG, ready for instruction scheduling.
 ///
 FunctionPass *llvm::createMSP430ISelDag(MSP430TargetMachine &TM,
                                         CodeGenOpt::Level OptLevel) {
   return new MSP430DAGToDAGISel(TM, OptLevel);
 }
 

llvm/lib/Target/MSP430/MSP430ISelLowering.h

enum NodeType : unsigned {
       /// DADD - Decimal addition with carry
       /// TODO Nothing generates a node of this type yet.
       DADD,
     };
   }
 
   class MSP430Subtarget;
   class MSP430TargetLowering : public TargetLowering {
+    const MSP430Subtarget *Subtarget;
+
   public:
     explicit MSP430TargetLowering(const TargetMachine &TM,
                                   const MSP430Subtarget &STI);
 
     MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
       return MVT::i8;
     }
 

llvm/lib/Target/MSP430/MSP430ISelLowering.cpp

 
 static cl::opt<bool>MSP430NoLegalImmediate(
   "msp430-no-legal-immediate", cl::Hidden,
   cl::desc("Enable non legal immediates (for testing purposes only)"),
   cl::init(false));
 
 MSP430TargetLowering::MSP430TargetLowering(const TargetMachine &TM,
                                            const MSP430Subtarget &STI)
-    : TargetLowering(TM) {
+    : TargetLowering(TM), Subtarget(&STI) {
 
   // Set up the register classes.
   addRegisterClass(MVT::i8,  &MSP430::GR8RegClass);
   addRegisterClass(MVT::i16, &MSP430::GR16RegClass);
 
   // Compute derived properties from the register classes
   computeRegisterProperties(STI.getRegisterInfo());
 

llvm/lib/Target/MSP430/MSP430InstrFormats.td

 
 class DestMode<bit val> {
   bit Value = val;
 }
 
 def DstReg      : DestMode<0>;   // r
 def DstMem      : DestMode<1>;   // m
 
+class ALKind<bit val> {
+  bit Value = val;
+}
+
+def ALAddr : ALKind<0>;
+def ALWord : ALKind<1>;
+
 // Generic MSP430 Format
 class MSP430Inst<dag outs, dag ins, int size, string asmstr> : Instruction {
-  field bits<48> Inst;
-  field bits<48> SoftFail = 0;
+  field bits<64> Inst;
+  field bits<64> SoftFail = 0;
 
   let Namespace = "MSP430";
 
   dag OutOperandList = outs;
   dag InOperandList  = ins;
 
   let AsmString = asmstr;
   let Size = size;
+
+  bit ExtensionWordFlag = 0;
+  let TSFlags{0} = ExtensionWordFlag;
 }
 
 // MSP430 Double Operand (Format I) Instructions
 class IForm<bits<4> opcode, DestMode ad, bit bw, SourceMode as, int size,
             dag outs, dag ins, string asmstr, list<dag> pattern>
   : MSP430Inst<outs, ins, size, asmstr> {
   let Pattern = pattern;
 
class CJForm<dag outs, dag ins, string asmstr, list<dag> pattern>
   bits<3> cond;
   bits<10> dst;
 
   let Inst{15-13} = 0b001;
   let Inst{12-10} = cond;
   let Inst{9-0} = dst;
 }
 
+// MSP430 Extended Format II Instruction Format Exception - Rotation.
+class IIExtExcRotForm<bits<2> opcode, ALKind al,
+                   dag outs, dag ins, string asmstr, list<dag> pattern>
+  : MSP430Inst<outs, ins, 2, asmstr> {
+  let Pattern = pattern;
+
+  bits<4> rd;
+  bits<2> cnt;
+
+  let Inst{15-12} = 0b0000;
+  let Inst{11-10} = cnt;
+  let Inst{9-8}   = opcode;
+  let Inst{7-5}   = 0b010;
+  let Inst{4}     = al.Value;
+  let Inst{3-0}   = rd;
+}
+
+class IIExtExcRotForm16<bits<2> opcode, dag outs, dag ins, string asmstr, list<dag> pattern>
+  : IIExtExcRotForm<opcode, ALWord, outs, ins, asmstr, pattern>;
+
+// The 430X extension word for register addressing modes.
+//
+// MSP430MCCodeEmitter expects the ExtensionWord field to be positioned at bits
+// [63:48] of the Inst field in the MSP430Inst that the instruction corresponds
+// to. encodeInstruction will rearrange the bits of the instruction to ensure
+// the ExtensionWord is positioned correctly in the final binary encoding.
+//
+// Until the MSP430 large memory model is supported, there's no benefit to using
+// non-register mode extended instructions, so they are not currently
+// implemented.
+class ExtensionWordRegForm<bit zc, bit rpt, ALKind al> {
+  bits<16> ExtensionWord;
+  bits<4> cnt = 0;
+
+  let ExtensionWord{15-9} = 0b0001100;
+  let ExtensionWord{8} = zc;
+  let ExtensionWord{7} = rpt;
+  let ExtensionWord{6} = al.Value;
+  let ExtensionWord{5-4} = 0b00;
+  let ExtensionWord{3-0} = cnt;
+}
+
+class II16rExtended<bits<3> opcode, bit zc, bit rpt,
+                  dag outs, dag ins, string asmstr, list<dag> pattern>
+  : IIForm16<opcode, SrcReg, 4, outs, ins, asmstr, pattern>,
+    ExtensionWordRegForm<zc, rpt, ALWord> {
+  let Pattern = pattern;
+  let ExtensionWordFlag = 1;
+  let Inst{63-48} = ExtensionWord;
+}
+
+class I16rExtended<bits<4> opcode, bit zc, bit rpt,
+                  dag outs, dag ins, string asmstr, list<dag> pattern>
+  : IForm16<opcode, DstReg, SrcReg, 4, outs, ins, asmstr, pattern>,
+    ExtensionWordRegForm<zc, rpt, ALWord> {
+  let Pattern = pattern;
+  let ExtensionWordFlag = 1;
+  let Inst{63-48} = ExtensionWord;
+}
+
+class II8rExtended<bits<3> opcode, bit zc, bit rpt,
+                  dag outs, dag ins, string asmstr, list<dag> pattern>
+  : IIForm8<opcode, SrcReg, 4, outs, ins, asmstr, pattern>,
+    ExtensionWordRegForm<zc, rpt, ALWord> {
+  let Pattern = pattern;
+  let ExtensionWordFlag = 1;
+  let Inst{63-48} = ExtensionWord;
+}
+
+class I8rExtended<bits<4> opcode, bit zc, bit rpt,
+                  dag outs, dag ins, string asmstr, list<dag> pattern>
+  : IForm8<opcode, DstReg, SrcReg, 4, outs, ins, asmstr, pattern>,
+    ExtensionWordRegForm<zc, rpt, ALWord> {
+  let Pattern = pattern;
+  let ExtensionWordFlag = 1;
+  let Inst{63-48} = ExtensionWord;
+}
+
 // Pseudo instructions
 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
   : MSP430Inst<outs, ins, 0, asmstr> {
   let Pattern = pattern;
 }

llvm/lib/Target/MSP430/MSP430InstrInfo.h

 
 #include "MSP430RegisterInfo.h"
 #include "llvm/CodeGen/TargetInstrInfo.h"
 
 #define GET_INSTRINFO_HEADER
 #include "MSP430GenInstrInfo.inc"
 
 namespace llvm {
+/// Namespace to describe the target-specific flags of an MSP430Inst.
+///
+/// The flag bit positions need to match the TSFlag bits set in the MSP430Inst
+/// TableGen class defined in MSP430InstrFormats.td.
+namespace MSP430TSFlags {
+enum {
+  /// This bit is set if the instruction is an MSP430X extended instruction with
+  /// an extension word.
+  ExtensionWord = 0x1,
+};
+} // namespace MSP430TSFlags
 
 class MSP430Subtarget;
 
 class MSP430InstrInfo : public MSP430GenInstrInfo {
   const MSP430RegisterInfo RI;
   virtual void anchor();
 public:
   explicit MSP430InstrInfo(MSP430Subtarget &STI);

llvm/lib/Target/MSP430/MSP430InstrInfo.td

 //===-- MSP430InstrInfo.td - MSP430 Instruction defs -------*- tablegen -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file describes the MSP430 instructions in TableGen format.
 //
 //===----------------------------------------------------------------------===//
 
 include "MSP430InstrFormats.td"
 
 //===----------------------------------------------------------------------===//
+// Feature predicates.
+//===----------------------------------------------------------------------===//
+
+// True when MSP430X extended instructions are available.
+def HasMSP430X : Predicate<"Subtarget->hasMSP430X()">;
+
+//===----------------------------------------------------------------------===//
 // Type Constraints.
 //===----------------------------------------------------------------------===//
 class SDTCisI8<int OpNum> : SDTCisVT<OpNum, i8>;
 class SDTCisI16<int OpNum> : SDTCisVT<OpNum, i16>;
 
 //===----------------------------------------------------------------------===//
 // Type Profiles.
 //===----------------------------------------------------------------------===//

 def : Pat<(store (subc (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
           (SUB8mm addr:$dst, addr:$src)>;
 
 // peephole patterns
 def : Pat<(and GR16:$src, 255), (ZEXT16r GR16:$src)>;
 def : Pat<(MSP430cmp (trunc (and_su GR16:$src, GR16:$src2)), 0),
           (BIT8rr (EXTRACT_SUBREG GR16:$src, subreg_8bit),
                   (EXTRACT_SUBREG GR16:$src2, subreg_8bit))>;
+
+include "MSP430InstrInfoExtended.td"

llvm/lib/Target/MSP430/MSP430InstrInfoExtended.td

+//===-- MSP430InstrInfoExtended.td - MSP430X Instruction defs -------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the MSP430X extended instructions in TableGen format.
+//
+//===----------------------------------------------------------------------===//
+
+// TODO: Most extended instructions have a .A version that enables 20-bit
+// operands. This requires support the large memory model to be implemented.
+//
+// Only the extended instructions that are useful in the small memory model
+// (16-bit pointers) are implemented so far. Instructions like MOVX are not
+// required in the small memory model, and have increased size/cycle count
+// compared to their 430 versions.
+
+def Rpt2ImmAsmOperand : AsmOperandClass {
+  let Name = "Rpt2Imm";
+  let RenderMethod = "addImmOperands";
+}
+
+def rpt2imm : Operand<i8>,
+              ImmLeaf<i8, [{return Imm >= 1 && Imm <= 4;}]> {
+  let ParserMatchClass = Rpt2ImmAsmOperand;
+  let EncoderMethod = "getRpt2ImmOpValue";
+  let DecoderMethod = "decodeRptImm";
+}
+
+//===----------------------------------------------------------------------===//
+//  Shift Instructions
+//
+let Predicates = [HasMSP430X] in {
+let Constraints = "$rs = $rd", Defs = [SR] in {
+  multiclass IIExtExcRot<string Mnemonic, bits<2> OpCode> {
+    def _16 : IIExtExcRotForm16<OpCode,
+                                (outs GR16:$rd), (ins GR16:$rs, rpt2imm:$cnt),
+                                !strconcat(Mnemonic, "\t$cnt, $rd"), []>;
+  }
+
+  defm RRAM : IIExtExcRot<"rram", 0b01>;
+  defm RRUM : IIExtExcRot<"rrum", 0b11>;
+  defm RLAM : IIExtExcRot<"rlam", 0b10>;
+
+  multiclass IIExtRot<string Mnemonic, bits<3> OpCode, bit ZC> {
+    def _8  :  II8rExtended<OpCode, ZC, 0,
+                            (outs GR8:$rd), (ins GR8:$rs),
+                            !strconcat(Mnemonic, ".b\t$rd"), []>;
+    def _16 : II16rExtended<OpCode, ZC, 0,
+                            (outs GR16:$rd), (ins GR16:$rs),
+                            !strconcat(Mnemonic, "\t$rd"), []>;
+  }
+  defm RRAX : IIExtRot<"rrax", 0b010, 0>;
+  // RRUX is encoded as RRCX with the ZC flag set.
+  defm RRUX : IIExtRot<"rrux", 0b000, 1>;
+
+  multiclass IExtRot<string Mnemonic, bits<4> OpCode> {
+    def _8  :  I8rExtended<OpCode, 0, 0,
+                            (outs GR8:$rd), (ins GR8:$rs),
+                            !strconcat(Mnemonic, ".b\t$rd"), []>;
+    def _16 : I16rExtended<OpCode, 0, 0,
+                            (outs GR16:$rd), (ins GR16:$rs),
+                            !strconcat(Mnemonic, "\t$rd"), []>;
+  }
+
+  // RLAX is encoded as ADDX.
+  defm RLAX : IExtRot<"rlax", 0b0101>;
+
+} // Defs = [SR], Constraints = "$rs = $rd"
+} // Predicates = [HasMSP430X]

llvm/test/MC/MSP430/shifts-430x-invalid.s

+// Tests to check for incorrect use of MSP430X shift instructions.
+// RUN: not llvm-mc --triple=msp430 -mcpu=msp430x < %s 2>&1 | FileCheck %s
+
+foo:
+// Check for an error when the reptition count is too large.
+  rrum #5, r12
+  rram #5, r12
+  rlam #5, r12
+// CHECK: :8: error: invalid operand for instruction
+// CHECK: :8: error: invalid operand for instruction
+// CHECK: :8: error: invalid operand for instruction
+
+// Check for an error when RxxX shifts have a shift amount operand.
+  rrux #3, r12
+  rrax #3, r12
+  rlax #3, r12
+// CHECK: :8: error: invalid operand for instruction
+// CHECK: :8: error: invalid operand for instruction
+// CHECK: :8: error: invalid operand for instruction

llvm/test/MC/MSP430/shifts-430x.s

+// Test the encoding of shift instructions for the 430X CPU.
+
+// RUN: llvm-mc -triple msp430 -mcpu=msp430x -show-encoding < %s | FileCheck %s
+rxxm:
+  rrum  #1, r12                         ; encoding: [0x5c,0x03]
+  rrum  #2, r12                         ; encoding: [0x5c,0x07]
+  rrum  #3, r12                         ; encoding: [0x5c,0x0b]
+  rrum  #4, r12                         ; encoding: [0x5c,0x0f]
+
+  rram  #1, r12                         ; encoding: [0x5c,0x01]
+  rram  #2, r12                         ; encoding: [0x5c,0x05]
+  rram  #3, r12                         ; encoding: [0x5c,0x09]
+  rram  #4, r12                         ; encoding: [0x5c,0x0d]
+
+  rlam  #1, r12                         ; encoding: [0x5c,0x02]
+  rlam  #2, r12                         ; encoding: [0x5c,0x06]
+  rlam  #3, r12                         ; encoding: [0x5c,0x0a]
+  rlam  #4, r12                         ; encoding: [0x5c,0x0e]
+
+// CHECK-LABEL: rxxm:
+// CHECK-NEXT: rrum #1, r12                         ; encoding: [0x5c,0x03]
+// CHECK: rrum  #2, r12                         ; encoding: [0x5c,0x07]
+// CHECK: rrum  #3, r12                         ; encoding: [0x5c,0x0b]
+// CHECK: rrum  #4, r12                         ; encoding: [0x5c,0x0f]
+
+// CHECK: rram  #1, r12                         ; encoding: [0x5c,0x01]
+// CHECK: rram  #2, r12                         ; encoding: [0x5c,0x05]
+// CHECK: rram  #3, r12                         ; encoding: [0x5c,0x09]
+// CHECK: rram  #4, r12                         ; encoding: [0x5c,0x0d]
+
+// CHECK: rlam  #1, r12                         ; encoding: [0x5c,0x02]
+// CHECK: rlam  #2, r12                         ; encoding: [0x5c,0x06]
+// CHECK: rlam  #3, r12                         ; encoding: [0x5c,0x0a]
+// CHECK: rlam  #4, r12                         ; encoding: [0x5c,0x0e]
+
+rrux:
+  rrux r12
+
+// CHECK-LABEL: rrux:
+// CHECK-NEXT: rrux r12                             ; encoding: [0x40,0x19,0x0c,0x10]
+
+rrux_b:
+  rrux.b r12
+
+// CHECK-LABEL: rrux_b:
+// CHECK-NEXT: rrux.b r12                             ; encoding: [0x40,0x19,0x4c,0x10]
+
+rrax:
+  rrax r12
+
+// CHECK-LABEL: rrax:
+// CHECK-NEXT: rrax r12                             ; encoding: [0x40,0x18,0x0c,0x11]
+
+rrax_b:
+  rrax.b r12
+
+// CHECK-LABEL: rrax_b:
+// CHECK-NEXT: rrax.b r12                             ; encoding: [0x40,0x18,0x4c,0x11]
+
+rlax:
+  rlax r12
+
+// CHECK-LABEL: rlax:
+// CHECK: rlax  r12                             ; encoding: [0x40,0x18,0x0c,0x5c]
+
+rlax_b:
+  rlax.b r12
+
+// CHECK-LABEL: rlax_b:
+// CHECK-NEXT: rlax.b r12                             ; encoding: [0x40,0x18,0x4c,0x5c]