[ARC] Improve code generated for i32 ADDC/ADDE and SUBC/SUBE

[marksl]

Summary

This change improves the code generated for long long addition and subtraction

[jordypotman]

Looks good to me.

llvm/lib/Target/ARC/ARCISelLowering.cpp

ARCTargetLowering::ARCTargetLowering(const TargetMachine &TM,
   // Operations to get us off of the ground.
   // Basic.
   setOperationAction(ISD::ADD, MVT::i32, Legal);
   setOperationAction(ISD::SUB, MVT::i32, Legal);
   setOperationAction(ISD::AND, MVT::i32, Legal);
   setOperationAction(ISD::SMAX, MVT::i32, Legal);
   setOperationAction(ISD::SMIN, MVT::i32, Legal);
 
+  setOperationAction(ISD::ADDC, MVT::i32, Legal);
+  setOperationAction(ISD::ADDE, MVT::i32, Legal);
+  setOperationAction(ISD::SUBC, MVT::i32, Legal);
+  setOperationAction(ISD::SUBE, MVT::i32, Legal);
+
   // Need barrel shifter.
   setOperationAction(ISD::SHL, MVT::i32, Legal);
   setOperationAction(ISD::SRA, MVT::i32, Legal);
   setOperationAction(ISD::SRL, MVT::i32, Legal);
   setOperationAction(ISD::ROTR, MVT::i32, Legal);
 
   setOperationAction(ISD::Constant, MVT::i32, Legal);
   setOperationAction(ISD::UNDEF, MVT::i32, Legal);

llvm/lib/Target/ARC/ARCInstrInfo.td

 defm : MultiPat<shl, ASL_rrr, ASL_rru6, ASL_rrlimm>;
 defm : MultiPat<srl, LSR_rrr, LSR_rru6, LSR_rrlimm>;
 defm : MultiPat<sra, ASR_rrr, ASR_rru6, ASR_rrlimm>;
 defm : MultiPat<rotr, ROR_rrr, ROR_rru6, ROR_rrlimm>;
 defm : MultiPat<mul, MPY_rrr, MPY_rru6, MPY_rrlimm>;
 defm : MultiPat<mulhs, MPYM_rrr, MPYM_rru6, MPYM_rrlimm>;
 defm : MultiPat<mulhu, MPYMU_rrr, MPYMU_rru6, MPYMU_rrlimm>;
 
+defm : MultiPat<addc, ADD_f_rrr, ADD_f_rru6, ADD_f_rrlimm>;
+defm : MultiPat<adde, ADC_f_rrr, ADC_f_rru6, ADC_f_rrlimm>;
+defm : MultiPat<subc, SUB_f_rrr, SUB_f_rru6, SUB_f_rrlimm>;
+defm : MultiPat<sube, SBC_f_rrr, SBC_f_rru6, SBC_f_rrlimm>;
+
 // ---------------------------------------------------------------------------
 // Unary Instruction definitions.
 // ---------------------------------------------------------------------------
 // General unary instruction definitions.
 defm SEXB : ArcUnaryGEN4Inst<0b000101, "sexb">;
 defm SEXH : ArcUnaryGEN4Inst<0b000110, "sexh">;
 
 // Extension unary instruction definitions.

llvm/test/CodeGen/ARC/alu.ll

 ; CHECK-DAG: mpym %r[[REG:[0-9]+]], %r{{[01]}}, %r{{[01]}}
 define i64 @muls64(i32 %a, i32 %b) nounwind {
   %a64 = sext i32 %a to i64
   %b64 = sext i32 %b to i64
   %v = mul i64 %a64, %b64
   ret i64 %v
 }
 
+; CHECK-LABEL: long_long_add
+; CHECK:      add.f %r0, %r0, %r2
+; CHECK-NEXT: adc.f %r1, %r1, %r3
+define i64 @long_long_add(i64 inreg %a, i64 inreg %b) #0 {
+entry:
+  %add = add nsw i64 %a, %b
+  ret i64 %add
+}
+
+; CHECK-LABEL: long_long_sub
+; CHECK:      sub.f %r0, %r0, %r2
+; CHECK-NEXT: sbc.f %r1, %r1, %r3
+define i64 @long_long_sub(i64 inreg %a, i64 inreg %b) #0 {
+entry:
+  %sub = sub nsw i64 %a, %b
+  ret i64 %sub
+}