This adds lowering rules for the llvm.readcyclecounter intrinsic along with a codegen test for the ARC backend. To perform the lowering, we needed to generate the LR (Load from Auxiliary Register) instruction to read from the COUNT0 timer register (which has number 33 or 0x22). Thus, this patch also adds support for the LR instruction with both LR_rs12 and LR_ru6 immediate formats along with custom disassembler code and tests.
Can this one be DecodeSOPwithRS12?
Can this one be DecodeSOPwithRU6?
I'd rather see you use two separate functions: DecodeSOPwithRU6 and DecodeSOPwithRS12