[ARC] Add codegen for the readcyclecounter intrinsic along with disassembly for associated instructions

[thomasjohns]

Summary

This adds lowering rules for the llvm.readcyclecounter intrinsic along with a codegen test for the ARC backend. To perform the lowering, we needed to generate the LR (Load from Auxiliary Register) instruction to read from the COUNT0 timer register (which has number 33 or 0x22). Thus, this patch also adds support for the LR instruction with both LR_rs12 and LR_ru6 immediate formats along with custom disassembler code and tests.

[thomasjohns]

llvm/lib/Target/ARC/Disassembler/ARCDisassembler.cpp

325

This aims to decode either form:
...ssssssSSSSSS
or
...uuuuuu000000
(S12 or U6). I assumed the leading bit of the S12 marks the sign. Is this correct @marksl ?

[marksl]

llvm/lib/Target/ARC/ARCISelLowering.cpp

172

Please use

setOperationAction(ISD::READCYCLECOUNTER,MVT::i64,
                   isTypeLegal(MVT::i64)?Legal:Custom);

llvm/lib/Target/ARC/ARCInstrFormats.td

417

Can this one be DecodeSOPwithRS12?

439

Can this one be DecodeSOPwithRU6?

llvm/lib/Target/ARC/Disassembler/ARCDisassembler.cpp

325

I'd rather see you use two separate functions: DecodeSOPwithRU6 and DecodeSOPwithRS12

[thomasjohns]

llvm/lib/Target/ARC/ARCISelLowering.cpp

172

Thanks, will do!

llvm/lib/Target/ARC/Disassembler/ARCDisassembler.cpp

325

Thanks, agreed that makes sense to me to separate them.

[thomasjohns]

Separate S12 and U6 single operand decoding into different methods. Check legality of i64 in ARCISelLowering.

[marksl]

Looks good

llvm/lib/Target/ARC/ARCISelLowering.h

public:
   /// target, for a load/store of the specified type.
   bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
                              unsigned AS,
                              Instruction *I = nullptr) const override;
 
 private:
   const ARCSubtarget &Subtarget;
 
+  void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
+                          SelectionDAG &DAG) const override;
+
   // Lower Operand helpers
   SDValue LowerCallArguments(SDValue Chain, CallingConv::ID CallConv,
                              bool isVarArg,
                              const SmallVectorImpl<ISD::InputArg> &Ins,
                              SDLoc dl, SelectionDAG &DAG,
                              SmallVectorImpl<SDValue> &InVals) const;
   // Lower Operand specifics
   SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;

llvm/lib/Target/ARC/ARCISelLowering.cpp

case ISD::SETLE:
     return ARCCC::LE;
   case ISD::SETNE:
     return ARCCC::NE;
   default:
     llvm_unreachable("Unhandled ISDCC code.");
   }
 }
 
+void ARCTargetLowering::ReplaceNodeResults(SDNode *N,
+                                           SmallVectorImpl<SDValue> &Results,
+                                           SelectionDAG &DAG) const {
+  LLVM_DEBUG(dbgs() << "[ARC-ISEL] ReplaceNodeResults ");
+  LLVM_DEBUG(N->dump(&DAG));
+  LLVM_DEBUG(dbgs() << "; use_count=" << N->use_size() << "\n");
+
+  switch (N->getOpcode()) {
+  case ISD::READCYCLECOUNTER:
+    if (N->getValueType(0) == MVT::i64) {
+      // We read the TIMER0 and zero-extend it to 64-bits as the intrinsic
+      // requires.
+      SDValue V =
+          DAG.getNode(ISD::READCYCLECOUNTER, SDLoc(N),
+                      DAG.getVTList(MVT::i32, MVT::Other), N->getOperand(0));
+      SDValue Op = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), MVT::i64, V);
+      Results.push_back(Op);
+      Results.push_back(V.getValue(1));
+    }
+    break;
+  default:
+    break;
+  }
+}
+
 ARCTargetLowering::ARCTargetLowering(const TargetMachine &TM,
                                      const ARCSubtarget &Subtarget)
     : TargetLowering(TM), Subtarget(Subtarget) {
   // Set up the register classes.
   addRegisterClass(MVT::i32, &ARC::GPR32RegClass);
 
   // Compute derived properties from the register classes
   computeRegisterProperties(Subtarget.getRegisterInfo());
ARCTargetLowering::ARCTargetLowering(const TargetMachine &TM,
 
   // Sign extend inreg
   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Custom);
 
   // TODO: Predicate these with `options.hasBitScan() ? Legal : Expand`
   //       when the HasBitScan predicate is available.
   setOperationAction(ISD::CTLZ, MVT::i32, Legal);
   setOperationAction(ISD::CTTZ, MVT::i32, Legal);
+
+  setOperationAction(ISD::READCYCLECOUNTER, MVT::i32, Legal);
+  setOperationAction(ISD::READCYCLECOUNTER, MVT::i64,
+                     isTypeLegal(MVT::i64) ? Legal : Custom);
 }
 
 const char *ARCTargetLowering::getTargetNodeName(unsigned Opcode) const {
   switch (Opcode) {
   case ARCISD::BL:
     return "ARCISD::BL";
   case ARCISD::CMOV:
     return "ARCISD::CMOV";
   case ARCISD::CMP:
SDValue ARCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
   case ISD::BR_CC:
     return LowerBR_CC(Op, DAG);
   case ISD::SIGN_EXTEND_INREG:
     return LowerSIGN_EXTEND_INREG(Op, DAG);
   case ISD::JumpTable:
     return LowerJumpTable(Op, DAG);
   case ISD::VASTART:
     return LowerVASTART(Op, DAG);
+  case ISD::READCYCLECOUNTER:
+    // As of LLVM 3.8, the lowering code insists that we customize it even
+    // though we've declared the i32 version as legal. This is because it only
+    // thinks i64 is the truly supported version. We've already converted the
+    // i64 version to a widened i32.
+    assert(Op.getSimpleValueType() == MVT::i32);
+    return Op;
   default:
     llvm_unreachable("unimplemented operand");
   }
 }

llvm/lib/Target/ARC/ARCInstrFormats.td

class F32_DOP_RS12<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
   let Inst{23-22} = 0b10;
   let Inst{21-16} = subop;
   let Inst{15} = F;
   let Inst{14-12} = B{5-3};
   let Inst{11-6} = S12{5-0};
   let Inst{5-0} = S12{11-6};
 }
 
+// 1-register, signed 12-bit immediate Dual Operand instruction.
+// This instruction uses B as the first operand (i.e., lr B, [%count0]).
+// |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
+// |B[2-0]  | 1| 0|            subop| F|B[5-3]  |S12[5-0]     |S12[11-6]  |
+class F32_SOP_RS12<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
+                   string asmstr, list<dag> pattern> :
+  InstARC<4, outs, ins, asmstr, pattern> {
+  bits<6> B;
+  bits<12> S12;
+
+  let Inst{31-27} = major;
+  let Inst{26-24} = B{2-0};
+  let Inst{23-22} = 0b10;
+  let Inst{21-16} = subop;
+  let Inst{15} = F;
+  let Inst{14-12} = B{5-3};
+  let Inst{11-6} = S12{5-0};
+  let Inst{5-0} = S12{11-6};
+
+  let DecoderMethod = "DecodeSOPwithRS12";
+}
+
+// 1-register, unsigned 6-bit immediate Dual Operand instruction.
+// This instruction uses B as the first operand.
+// |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
+// |B[2-0]  | 0| 1|            subop| F|B[5-3]  |U6           |0|0|0|0|0|0|
+class F32_SOP_RU6<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
+                  string asmstr, list<dag> pattern> :
+  InstARC<4, outs, ins, asmstr, pattern> {
+  bits<6> B;
+  bits<6> U6;
+
+  let Inst{31-27} = major;
+  let Inst{26-24} = B{2-0};
+  let Inst{23-22} = 0b01;
+  let Inst{21-16} = subop;
+  let Inst{15} = F;
+  let Inst{14-12} = B{5-3};
+  let Inst{11-6} = U6;
+  let Inst{5-0} = 0;
+
+  let DecoderMethod = "DecodeSOPwithRU6";
+}
+
 // 2-register, 32-bit immediate (LImm) Dual Operand instruction.
 // This instruction has the 32-bit immediate in bits 32-63, and
 // 62 in the C register operand slot, but is otherwise F32_DOP_RR.
 class F32_DOP_RLIMM<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
                     string asmstr, list<dag> pattern> :
   InstARC<8, outs, ins, asmstr, pattern> {
   bits<6> B;
   bits<6> A;

llvm/lib/Target/ARC/ARCInstrInfo.td

 // Pattern generation for different instruction variants.
 multiclass MultiPat<SDPatternOperator InFrag,
                Instruction RRR, Instruction RRU6, Instruction RRLImm> {
   def _rrr : Pat<(InFrag i32:$B, i32:$C), (RRR i32:$B, i32:$C)>;
   def _rru6 : Pat<(InFrag i32:$B, immU6:$U6), (RRU6 i32:$B, immU6:$U6)>;
   def _rrlimm : Pat<(InFrag i32:$B, imm32:$LImm), (RRLImm i32:$B, imm32:$LImm)>;
 }
 
+// NOTE: This could be specialized later with a custom `PrintMethod` for
+//       displaying the aux register name. E.g. `[%count0]` instead of [33].
+def AuxReg : Operand<i32>;
+
+def LR_rs12 : F32_SOP_RS12<0b00100, 0b101010, 0,
+                           (outs GPR32:$B), (ins AuxReg:$C),
+                           "lr\t$B, [$C]", []>;
+def LR_ru6 : F32_SOP_RU6<0b00100, 0b101010, 0,
+                         (outs GPR32:$B), (ins AuxReg:$C),
+                         "lr\t$B, [$C]", []>;
+
+def: Pat<(i32 readcyclecounter), (LR_rs12 0x21) >;  // read timer
+
 // ---------------------------------------------------------------------------
 // Instruction definitions and patterns for 3 operand binary instructions.
 // ---------------------------------------------------------------------------
 
 // Definitions for 3 operand binary instructions.
 defm ADD : ArcBinaryGEN4Inst<0b000000, "add",1>;
 defm SUB : ArcBinaryGEN4Inst<0b000010, "sub">;
 defm SUB1 : ArcBinaryGEN4Inst<0b010111, "sub1">;

llvm/lib/Target/ARC/Disassembler/ARCDisassembler.cpp

static DecodeStatus DecodeLdLImmInstruction(MCInst &, uint64_t, uint64_t,
                                             const void *);
 
 static DecodeStatus DecodeStLImmInstruction(MCInst &, uint64_t, uint64_t,
                                             const void *);
 
 static DecodeStatus DecodeLdRLImmInstruction(MCInst &, uint64_t, uint64_t,
                                              const void *);
 
+static DecodeStatus DecodeSOPwithRS12(MCInst &, uint64_t, uint64_t,
+                                      const void *);
+
+static DecodeStatus DecodeSOPwithRU6(MCInst &, uint64_t, uint64_t,
+                                     const void *);
+
 static DecodeStatus DecodeCCRU6Instruction(MCInst &, uint64_t, uint64_t,
                                            const void *);
 
 static DecodeStatus DecodeMoveHRegInstruction(MCInst &Inst, uint64_t, uint64_t,
                                               const void *);
 
 static const uint16_t GPR32DecoderTable[] = {
     ARC::R0,  ARC::R1,    ARC::R2,  ARC::R3,   ARC::R4,  ARC::R5,  ARC::R6,
static DecodeStatus DecodeCCRU6Instruction(MCInst &Inst, uint64_t Insn,
   using Field = decltype(Insn);
   Field U6Field = fieldFromInstruction(Insn, 6, 6);
   Inst.addOperand(MCOperand::createImm(U6Field));
   Field CCField = fieldFromInstruction(Insn, 0, 4);
   Inst.addOperand(MCOperand::createImm(CCField));
   return MCDisassembler::Success;
 }
 
+static DecodeStatus DecodeSOPwithRU6(MCInst &Inst, uint64_t Insn,
+                                     uint64_t Address, const void *Decoder) {
+  unsigned DstB = decodeBField(Insn);
+  DecodeGPR32RegisterClass(Inst, DstB, Address, Decoder);
+  using Field = decltype(Insn);
+  Field U6 = fieldFromInstruction(Insn, 6, 6);
+  Inst.addOperand(MCOperand::createImm(U6));
+  return MCDisassembler::Success;
+}
+
+static DecodeStatus DecodeSOPwithRS12(MCInst &Inst, uint64_t Insn,
+                                      uint64_t Address, const void *Decoder) {
+  unsigned DstB = decodeBField(Insn);
+  DecodeGPR32RegisterClass(Inst, DstB, Address, Decoder);
+  using Field = decltype(Insn);
+  Field Lower = fieldFromInstruction(Insn, 6, 6);
+  Field Upper = fieldFromInstruction(Insn, 0, 5);
+  Field Sign = fieldFromInstruction(Insn, 5, 1) ? -1 : 1;
+  Field Result = Sign * ((Upper << 6) + Lower);
+  Inst.addOperand(MCOperand::createImm(Result));
+  return MCDisassembler::Success;
+}
+
 DecodeStatus ARCDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
                                              ArrayRef<uint8_t> Bytes,
                                              uint64_t Address,
                                              raw_ostream &cStream) const {
   MCDisassembler::DecodeStatus Result;
   if (Bytes.size() < 2) {
     Size = 0;
     return Fail;

llvm/test/CodeGen/ARC/intrinsics.ll

 ; RUN: llc -march=arc < %s | FileCheck %s
 
 target triple = "arc"
 
 declare i32 @llvm.ctlz.i32(i32, i1)
 declare i32 @llvm.cttz.i32(i32, i1)
+declare i64 @llvm.readcyclecounter()
 
-; CHECK-LABEL: clz32:
+; CHECK-LABEL: test_ctlz_i32:
 ; CHECK:       fls.f   %r0, %r0
 ; CHECK-NEXT:  mov.eq  %r0, 32
 ; CHECK-NEXT:  rsub.ne %r0, %r0, 31
-define i32 @clz32(i32 %x) {
+define i32 @test_ctlz_i32(i32 %x) {
   %a = call i32 @llvm.ctlz.i32(i32 %x, i1 false)
   ret i32 %a
 }
 
-; CHECK-LABEL: ctz32:
+; CHECK-LABEL: test_cttz_i32:
 ; CHECK:       ffs.f   %r0, %r0
 ; CHECK-NEXT:  mov.eq  %r0, 32
-define i32 @ctz32(i32 %x) {
+define i32 @test_cttz_i32(i32 %x) {
   %a = call i32 @llvm.cttz.i32(i32 %x, i1 false)
   ret i32 %a
 }
+
+; CHECK-LABEL: test_readcyclecounter:
+; CHECK:       lr %r0, [33]
+; CHECK-NEXT:  mov %r1, 0
+define i64 @test_readcyclecounter() nounwind {
+  %a = call i64 @llvm.readcyclecounter()
+  ret i64 %a
+}

llvm/test/MC/Disassembler/ARC/ldst.txt

 # CHECK: st.aw   %r6, [%r2,64]
 0x40 0x1A 0x88 0x01
 
 # CHECK: ldb.x.di.aw %r0, [%r8,8]
 0x08 0x10 0xC0 0x1A
 
 # CHECK: stb.di.ab   %r0, [%r9,64]
 0x40 0x19 0x32 0x10
+
+# LR instructions with a U6 immediate bit pattern
+# ([33] maps to the [%count0] auxilary register)
+
+# CHECK: lr %r0, [33]
+0x6a 0x20 0x40 0x08
+
+# CHECK: lr %r7, [33]
+0x6a 0x27 0x40 0x08
+
+# CHECK: lr %r15, [33]
+0x6a 0x27 0x40 0x18
+
+# CHECK: lr %r22, [33]
+0x6a 0x26 0x40 0x28
+
+# LR instructions with an S12 immediate bit pattern
+
+# CHECK: lr %r0, [33]
+0xaa 0x20 0x40 0x08
+
+# The following don't necessarily map to real auxilary registers, but
+# the different range of numbers helps exercise the S12 decoder.
+
+# CHECK: lr %r0, [-33]
+0xaa 0x20 0x60 0x08
+
+# CHECK: lr %r0, [97]
+0xaa 0x20 0x41 0x08
+
+# CHECK: lr %r0, [-97]
+0xaa 0x20 0x61 0x08