[M68k][GloballSel] RegBankSelect implementation

[sushmaunnibhavi]

Summary

Implementation of RegBankSelect for the M68k backend.

[gandhi21299]

llvm/lib/Target/M68k/GlSel/M68kRegisterBankInfo.cpp

80

I don't see MRI used anywhere

llvm/lib/Target/M68k/GlSel/M68kRegisterBankInfo.h

46

please add a newline here

llvm/test/CodeGen/M68k/GlobalISel/reg_bank_test.ll

5

please add more CHECKS for MIR

[sushmaunnibhavi]

Updated patch according to @gandhi21299 comments.

[sushmaunnibhavi]

@myhsu , @gandhi21299 can you please review the patch?

[myhsu]

llvm/lib/Target/M68k/GlSel/M68kRegisterBankInfo.cpp

96

Why line 86, 92, and 96 are the same? Can we combine them?

llvm/lib/Target/M68k/GlSel/M68kRegisterBankInfo.h

44

why change this?

[sushmaunnibhavi]

llvm/lib/Target/M68k/GlSel/M68kRegisterBankInfo.cpp

96

Yes it can be combined.

[sushmaunnibhavi]

Updated patch according to @myhsu comments.

[myhsu]

llvm/lib/Target/M68k/GlSel/M68kRegisterBankInfo.cpp

49

Is it better to say "3 operands" instead of "3 ops" here? Because at first I thought it means 3 operators.

[sushmaunnibhavi]

Updated patch according to @myhsu comments.

[myhsu]

LGTM Cheers!
Please fix the unused variable though

llvm/lib/Target/M68k/GlSel/M68kRegisterBankInfo.cpp

79

This variable is not used anywhere

[myhsu]

And also please provide a summary of this patch

[sushmaunnibhavi]

Removed unused variables.

llvm/lib/Target/M68k/GlSel/M68kRegisterBankInfo.h

 #include "M68kGenRegisterBank.inc"
 #undef GET_TARGET_REGBANK_CLASS
 };
 
 /// This class provides the information for the target register banks.
 class M68kRegisterBankInfo final : public M68kGenRegisterBankInfo {
 public:
   M68kRegisterBankInfo(const TargetRegisterInfo &TRI);
+
+  const RegisterBank &getRegBankFromRegClass(const TargetRegisterClass &RC,
+                                             LLT) const override;
+
+  const InstructionMapping &
+  getInstrMapping(const MachineInstr &MI) const override;
 };
 } // end namespace llvm
 #endif

llvm/lib/Target/M68k/GlSel/M68kRegisterBankInfo.cpp

 //===-- M68kRegisterBankInfo.cpp -------------------------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 /// \file
 /// This file implements the targeting of the RegisterBankInfo class for M68k.
 /// \todo This should be generated by TableGen.
 //===----------------------------------------------------------------------===//
 
 #include "M68kRegisterBankInfo.h"
-#include "MCTargetDesc/M68kMCTargetDesc.h"
+#include "M68kInstrInfo.h" // For the register classes
+#include "M68kSubtarget.h"
 #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/TargetRegisterInfo.h"
 
 #define GET_TARGET_REGBANK_IMPL
 #include "M68kGenRegisterBank.inc"
-#undef GET_TARGET_REGBANK_IMPL
 
 using namespace llvm;
 
+// FIXME: TableGen this.
+// If it grows too much and TableGen still isn't ready to do the job, extract it
+// into an M68kGenRegisterBankInfo.def (similar to AArch64).
+namespace llvm {
+namespace M68k {
+enum PartialMappingIdx {
+  PMI_GPR,
+  PMI_Min = PMI_GPR,
+};
+
+RegisterBankInfo::PartialMapping PartMappings[]{
+    // GPR Partial Mapping
+    {0, 32, GPRRegBank},
+};
+
+enum ValueMappingIdx {
+  InvalidIdx = 0,
+  GPR3OpsIdx = 1,
+};
+
+RegisterBankInfo::ValueMapping ValueMappings[] = {
+    // invalid
+    {nullptr, 0},
+    // 3 operands in GPRs
+    {&PartMappings[PMI_GPR - PMI_Min], 1},
+    {&PartMappings[PMI_GPR - PMI_Min], 1},
+    {&PartMappings[PMI_GPR - PMI_Min], 1},
+
+};
+} // end namespace M68k
+} // end namespace llvm
+
 M68kRegisterBankInfo::M68kRegisterBankInfo(const TargetRegisterInfo &TRI)
     : M68kGenRegisterBankInfo() {}
+
+const RegisterBank &
+M68kRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC,
+                                             LLT) const {
+  return getRegBank(M68k::GPRRegBankID);
+}
+
+const RegisterBankInfo::InstructionMapping &
+M68kRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
+  auto Opc = MI.getOpcode();
+
+  if (!isPreISelGenericOpcode(Opc)) {
+    const InstructionMapping &Mapping = getInstrMappingImpl(MI);
+    if (Mapping.isValid())
+      return Mapping;
+  }
+
+  using namespace TargetOpcode;
+
+  unsigned NumOperands = MI.getNumOperands();
+  const ValueMapping *OperandsMapping = &M68k::ValueMappings[M68k::GPR3OpsIdx];
+
+  switch (Opc) {
+  case G_ADD:
+  case G_SUB:
+  case G_MUL:
+  case G_SDIV:
+  case G_UDIV:
+  case G_LOAD:
+  case G_STORE: {
+    OperandsMapping = &M68k::ValueMappings[M68k::GPR3OpsIdx];
+    break;
+  }
+
+  case G_CONSTANT:
+  case G_FRAME_INDEX:
+    OperandsMapping =
+        getOperandsMapping({&M68k::ValueMappings[M68k::GPR3OpsIdx], nullptr});
+    break;
+  default:
+    return getInvalidInstructionMapping();
+  }
+
+  return getInstructionMapping(DefaultMappingID, /*Cost=*/1, OperandsMapping,
+                               NumOperands);
+}

llvm/lib/Target/M68k/GlSel/M68kRegisterBanks.td

 //===-- M68kRegisterBanks.td - Describe the M68k Banks -------*- tablegen -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
 /// Define the M68k register banks used for GlobalISel.
 ///
 //===----------------------------------------------------------------------===//
 
 /// General Purpose Registers. Here we define a register bank with name AnyGPR
-def GPRRegBank : RegisterBank<"AnyGPR", [DR8]>;
+def GPRRegBank : RegisterBank<"AnyGPR", [XR32]>;

llvm/test/CodeGen/M68k/GlobalISel/reg_bank_test.ll

+; RUN: llc -mtriple=m68k -global-isel -stop-after=regbankselect < %s | FileCheck %s
+
+define i32 @test_add(i32 %x, i32 %y) {
+  ; CHECK-LABEL: name: test_add
+  ; CHECK: bb.1 (%ir-block.0):
+  ; CHECK:   [[G_F_I1:%[0-9]+]]:anygpr(p0) = G_FRAME_INDEX
+  ; CHECK:   [[G_LOAD1:%[0-9]+]]:anygpr(s32) = G_LOAD [[G_F_I1]](p0)
+  ; CHECK:   [[G_F_I2:%[0-9]+]]:anygpr(p0) = G_FRAME_INDEX
+  ; CHECK:   [[G_LOAD2:%[0-9]+]]:anygpr(s32) = G_LOAD [[G_F_I2]](p0)
+  ; CHECK:   [[G_ADD1:%[0-9]+]]:anygpr(s32) = G_ADD [[G_LOAD1]], [[G_LOAD2]]
+  ; CHECK:   $d0 = COPY [[G_ADD1]](s32)
+  ; CHECK:   RTS implicit $d0
+  %sum = add i32 %x, %y
+  ret i32 %sum
+}
+
+define i32 @test_sub(i32 %x, i32 %y) {
+  ; CHECK-LABEL: name: test_sub
+  ; CHECK: bb.1 (%ir-block.0):
+  ; CHECK:   [[G_F_I1:%[0-9]+]]:anygpr(p0) = G_FRAME_INDEX
+  ; CHECK:   [[G_LOAD1:%[0-9]+]]:anygpr(s32) = G_LOAD [[G_F_I1]](p0)
+  ; CHECK:   [[G_F_I2:%[0-9]+]]:anygpr(p0) = G_FRAME_INDEX
+  ; CHECK:   [[G_LOAD2:%[0-9]+]]:anygpr(s32) = G_LOAD [[G_F_I2]](p0)
+  ; CHECK:   [[G_SUB1:%[0-9]+]]:anygpr(s32) = G_SUB [[G_LOAD1]], [[G_LOAD2]]
+  ; CHECK:   $d0 = COPY [[G_SUB1]](s32)
+  ; CHECK:   RTS implicit $d0
+  %diff = sub i32 %x, %y
+  ret i32 %diff
+}