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Differential D107459

[X86] Rename Subtarget Tuning Feature Flag Prefix. NFC.
ClosedPublic

Authored by RKSimon on Aug 4 2021, 7:02 AM.

Details

Reviewers
craig.topper
pengfei
Commits
rGe78bf49a58ed: [X86] Rename Subtarget Tuning Feature Flag Prefix. NFC.
Summary

As suggested on D107370, this is a possible patch to rename the tuning feature flags to start with 'Tuning' instead of 'Feature'.

Unfortunately I'm not sure we should do this for security mitigation flags as the llvm/Support/X86TargetParser.def code uses 'llvm::X86::FEATURE_##' style stubs that include some of these flags - we're probably better off keeping the enum names as similar as possible?

Diff Detail

Event Timeline

RKSimon created this revision.Aug 4 2021, 7:02 AM
Herald added a subscriber: hiraditya. · View Herald TranscriptAug 4 2021, 7:02 AM
RKSimon requested review of this revision.Aug 4 2021, 7:02 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 4 2021, 7:02 AM
Harbormaster completed remote builds in B117900: Diff 364089.Aug 4 2021, 7:49 AM
pengfei accepted this revision.Aug 4 2021, 8:46 AM

LGTM. Thanks Simon. Quick implementation!

llvm/lib/Target/X86/X86TargetTransformInfo.h
49–50

Nit, it looks a bit strange in the middle of all TuningXXX. Maybe better to hoist to the top or give a separate comment?

This revision is now accepted and ready to land.Aug 4 2021, 8:46 AM
Closed by commit rGe78bf49a58ed: [X86] Rename Subtarget Tuning Feature Flag Prefix. NFC. (authored by RKSimon). · Explain WhyAug 5 2021, 5:09 AM
This revision was automatically updated to reflect the committed changes.
RKSimon added a commit: rGe78bf49a58ed: [X86] Rename Subtarget Tuning Feature Flag Prefix. NFC..

Revision Contents

PathSize
llvm/
lib/
Target/
X86/
MCTargetDesc/
6 lines
432 lines
6 lines
76 lines

Diff 364427

llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp

Show First 20 Lines • Show All 1,080 Lines • ▼ Show 20 Lines#endif
} }
} }
unsigned X86AsmBackend::getMaximumNopSize() const { unsigned X86AsmBackend::getMaximumNopSize() const {
if (STI.hasFeature(X86::Mode16Bit)) if (STI.hasFeature(X86::Mode16Bit))
return 4; return 4;
if (!STI.hasFeature(X86::FeatureNOPL) && !STI.hasFeature(X86::Mode64Bit)) if (!STI.hasFeature(X86::FeatureNOPL) && !STI.hasFeature(X86::Mode64Bit))
return 1; return 1;
if (STI.getFeatureBits()[X86::FeatureFast7ByteNOP]) if (STI.getFeatureBits()[X86::TuningFast7ByteNOP])
return 7; return 7;
if (STI.getFeatureBits()[X86::FeatureFast15ByteNOP]) if (STI.getFeatureBits()[X86::TuningFast15ByteNOP])
return 15; return 15;
if (STI.getFeatureBits()[X86::FeatureFast11ByteNOP]) if (STI.getFeatureBits()[X86::TuningFast11ByteNOP])
return 11; return 11;
// FIXME: handle 32-bit mode // FIXME: handle 32-bit mode
// 15-bytes is the longest single NOP instruction, but 10-bytes is // 15-bytes is the longest single NOP instruction, but 10-bytes is
// commonly the longest that can be efficiently decoded. // commonly the longest that can be efficiently decoded.
return 10; return 10;
} }
/// Write a sequence of optimal nops to the output, covering \p Count /// Write a sequence of optimal nops to the output, covering \p Count
▲ Show 20 Lines • Show All 536 Lines • Show Last 20 Lines

llvm/lib/Target/X86/X86.td

Show First 20 Lines • Show All 361 Lines • ▼ Show 20 Lines : SubtargetFeature<
"lvi-load-hardening", "UseLVILoadHardening", "true", "lvi-load-hardening", "UseLVILoadHardening", "true",
"Insert LFENCE instructions to prevent data speculatively injected " "Insert LFENCE instructions to prevent data speculatively injected "
"into loads from being used maliciously.">; "into loads from being used maliciously.">;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// X86 Subtarget Tuning features // X86 Subtarget Tuning features
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true", def TuningSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",
"SHLD instruction is slow">; "SHLD instruction is slow">;
def FeatureSlowPMULLD : SubtargetFeature<"slow-pmulld", "IsPMULLDSlow", "true", def TuningSlowPMULLD : SubtargetFeature<"slow-pmulld", "IsPMULLDSlow", "true",
"PMULLD instruction is slow">; "PMULLD instruction is slow">;
def FeatureSlowPMADDWD : SubtargetFeature<"slow-pmaddwd", "IsPMADDWDSlow", def TuningSlowPMADDWD : SubtargetFeature<"slow-pmaddwd", "IsPMADDWDSlow",
"true", "true",
"PMADDWD is slower than PMULLD">; "PMADDWD is slower than PMULLD">;
// FIXME: This should not apply to CPUs that do not have SSE. // FIXME: This should not apply to CPUs that do not have SSE.
def FeatureSlowUAMem16 : SubtargetFeature<"slow-unaligned-mem-16", def TuningSlowUAMem16 : SubtargetFeature<"slow-unaligned-mem-16",
"IsUAMem16Slow", "true", "IsUAMem16Slow", "true",
"Slow unaligned 16-byte memory access">; "Slow unaligned 16-byte memory access">;
def FeatureSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32", def TuningSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32",
"IsUAMem32Slow", "true", "IsUAMem32Slow", "true",
"Slow unaligned 32-byte memory access">; "Slow unaligned 32-byte memory access">;
def FeatureLEAForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true", def TuningLEAForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
"Use LEA for adjusting the stack pointer">; "Use LEA for adjusting the stack pointer">;
def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb", def TuningSlowDivide32 : SubtargetFeature<"idivl-to-divb",
"HasSlowDivide32", "true", "HasSlowDivide32", "true",
"Use 8-bit divide for positive values less than 256">; "Use 8-bit divide for positive values less than 256">;
def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divl", def TuningSlowDivide64 : SubtargetFeature<"idivq-to-divl",
"HasSlowDivide64", "true", "HasSlowDivide64", "true",
"Use 32-bit divide for positive values less than 2^32">; "Use 32-bit divide for positive values less than 2^32">;
def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions", def TuningPadShortFunctions : SubtargetFeature<"pad-short-functions",
"PadShortFunctions", "true", "PadShortFunctions", "true",
"Pad short functions">; "Pad short functions">;
// On some processors, instructions that implicitly take two memory operands are // On some processors, instructions that implicitly take two memory operands are
// slow. In practice, this means that CALL, PUSH, and POP with memory operands // slow. In practice, this means that CALL, PUSH, and POP with memory operands
// should be avoided in favor of a MOV + register CALL/PUSH/POP. // should be avoided in favor of a MOV + register CALL/PUSH/POP.
def FeatureSlowTwoMemOps : SubtargetFeature<"slow-two-mem-ops", def TuningSlowTwoMemOps : SubtargetFeature<"slow-two-mem-ops",
"SlowTwoMemOps", "true", "SlowTwoMemOps", "true",
"Two memory operand instructions are slow">; "Two memory operand instructions are slow">;
def FeatureLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true", def TuningLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true",
"LEA instruction needs inputs at AG stage">; "LEA instruction needs inputs at AG stage">;
def FeatureSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true", def TuningSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true",
"LEA instruction with certain arguments is slow">; "LEA instruction with certain arguments is slow">;
def FeatureSlow3OpsLEA : SubtargetFeature<"slow-3ops-lea", "Slow3OpsLEA", "true", def TuningSlow3OpsLEA : SubtargetFeature<"slow-3ops-lea", "Slow3OpsLEA", "true",
"LEA instruction with 3 ops or certain registers is slow">; "LEA instruction with 3 ops or certain registers is slow">;
def FeatureSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true", def TuningSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true",
"INC and DEC instructions are slower than ADD and SUB">; "INC and DEC instructions are slower than ADD and SUB">;
def FeaturePOPCNTFalseDeps : SubtargetFeature<"false-deps-popcnt", def TuningPOPCNTFalseDeps : SubtargetFeature<"false-deps-popcnt",
"HasPOPCNTFalseDeps", "true", "HasPOPCNTFalseDeps", "true",
"POPCNT has a false dependency on dest register">; "POPCNT has a false dependency on dest register">;
def FeatureLZCNTFalseDeps : SubtargetFeature<"false-deps-lzcnt-tzcnt", def TuningLZCNTFalseDeps : SubtargetFeature<"false-deps-lzcnt-tzcnt",
"HasLZCNTFalseDeps", "true", "HasLZCNTFalseDeps", "true",
"LZCNT/TZCNT have a false dependency on dest register">; "LZCNT/TZCNT have a false dependency on dest register">;
// On recent X86 (port bound) processors, its preferable to combine to a single shuffle // On recent X86 (port bound) processors, its preferable to combine to a single shuffle
// using a variable mask over multiple fixed shuffles. // using a variable mask over multiple fixed shuffles.
def FeatureFastVariableCrossLaneShuffle def TuningFastVariableCrossLaneShuffle
: SubtargetFeature<"fast-variable-crosslane-shuffle", : SubtargetFeature<"fast-variable-crosslane-shuffle",
"HasFastVariableCrossLaneShuffle", "HasFastVariableCrossLaneShuffle",
"true", "Cross-lane shuffles with variable masks are fast">; "true", "Cross-lane shuffles with variable masks are fast">;
def FeatureFastVariablePerLaneShuffle def TuningFastVariablePerLaneShuffle
: SubtargetFeature<"fast-variable-perlane-shuffle", : SubtargetFeature<"fast-variable-perlane-shuffle",
"HasFastVariablePerLaneShuffle", "HasFastVariablePerLaneShuffle",
"true", "Per-lane shuffles with variable masks are fast">; "true", "Per-lane shuffles with variable masks are fast">;
// On some X86 processors, a vzeroupper instruction should be inserted after // On some X86 processors, a vzeroupper instruction should be inserted after
// using ymm/zmm registers before executing code that may use SSE instructions. // using ymm/zmm registers before executing code that may use SSE instructions.
def FeatureInsertVZEROUPPER def TuningInsertVZEROUPPER
: SubtargetFeature<"vzeroupper", : SubtargetFeature<"vzeroupper",
"InsertVZEROUPPER", "InsertVZEROUPPER",
"true", "Should insert vzeroupper instructions">; "true", "Should insert vzeroupper instructions">;
// FeatureFastScalarFSQRT should be enabled if scalar FSQRT has shorter latency // TuningFastScalarFSQRT should be enabled if scalar FSQRT has shorter latency
// than the corresponding NR code. FeatureFastVectorFSQRT should be enabled if // than the corresponding NR code. TuningFastVectorFSQRT should be enabled if
// vector FSQRT has higher throughput than the corresponding NR code. // vector FSQRT has higher throughput than the corresponding NR code.
// The idea is that throughput bound code is likely to be vectorized, so for // The idea is that throughput bound code is likely to be vectorized, so for
// vectorized code we should care about the throughput of SQRT operations. // vectorized code we should care about the throughput of SQRT operations.
// But if the code is scalar that probably means that the code has some kind of // But if the code is scalar that probably means that the code has some kind of
// dependency and we should care more about reducing the latency. // dependency and we should care more about reducing the latency.
def FeatureFastScalarFSQRT def TuningFastScalarFSQRT
: SubtargetFeature<"fast-scalar-fsqrt", "HasFastScalarFSQRT", : SubtargetFeature<"fast-scalar-fsqrt", "HasFastScalarFSQRT",
"true", "Scalar SQRT is fast (disable Newton-Raphson)">; "true", "Scalar SQRT is fast (disable Newton-Raphson)">;
def FeatureFastVectorFSQRT def TuningFastVectorFSQRT
: SubtargetFeature<"fast-vector-fsqrt", "HasFastVectorFSQRT", : SubtargetFeature<"fast-vector-fsqrt", "HasFastVectorFSQRT",
"true", "Vector SQRT is fast (disable Newton-Raphson)">; "true", "Vector SQRT is fast (disable Newton-Raphson)">;
// If lzcnt has equivalent latency/throughput to most simple integer ops, it can // If lzcnt has equivalent latency/throughput to most simple integer ops, it can
// be used to replace test/set sequences. // be used to replace test/set sequences.
def FeatureFastLZCNT def TuningFastLZCNT
: SubtargetFeature< : SubtargetFeature<
"fast-lzcnt", "HasFastLZCNT", "true", "fast-lzcnt", "HasFastLZCNT", "true",
"LZCNT instructions are as fast as most simple integer ops">; "LZCNT instructions are as fast as most simple integer ops">;
// If the target can efficiently decode NOPs upto 7-bytes in length. // If the target can efficiently decode NOPs upto 7-bytes in length.
def FeatureFast7ByteNOP def TuningFast7ByteNOP
: SubtargetFeature< : SubtargetFeature<
"fast-7bytenop", "HasFast7ByteNOP", "true", "fast-7bytenop", "HasFast7ByteNOP", "true",
"Target can quickly decode up to 7 byte NOPs">; "Target can quickly decode up to 7 byte NOPs">;
// If the target can efficiently decode NOPs upto 11-bytes in length. // If the target can efficiently decode NOPs upto 11-bytes in length.
def FeatureFast11ByteNOP def TuningFast11ByteNOP
: SubtargetFeature< : SubtargetFeature<
"fast-11bytenop", "HasFast11ByteNOP", "true", "fast-11bytenop", "HasFast11ByteNOP", "true",
"Target can quickly decode up to 11 byte NOPs">; "Target can quickly decode up to 11 byte NOPs">;
// If the target can efficiently decode NOPs upto 15-bytes in length. // If the target can efficiently decode NOPs upto 15-bytes in length.
def FeatureFast15ByteNOP def TuningFast15ByteNOP
: SubtargetFeature< : SubtargetFeature<
"fast-15bytenop", "HasFast15ByteNOP", "true", "fast-15bytenop", "HasFast15ByteNOP", "true",
"Target can quickly decode up to 15 byte NOPs">; "Target can quickly decode up to 15 byte NOPs">;
// Sandy Bridge and newer processors can use SHLD with the same source on both // Sandy Bridge and newer processors can use SHLD with the same source on both
// inputs to implement rotate to avoid the partial flag update of the normal // inputs to implement rotate to avoid the partial flag update of the normal
// rotate instructions. // rotate instructions.
def FeatureFastSHLDRotate def TuningFastSHLDRotate
: SubtargetFeature< : SubtargetFeature<
"fast-shld-rotate", "HasFastSHLDRotate", "true", "fast-shld-rotate", "HasFastSHLDRotate", "true",
"SHLD can be used as a faster rotate">; "SHLD can be used as a faster rotate">;
// Bulldozer and newer processors can merge CMP/TEST (but not other // Bulldozer and newer processors can merge CMP/TEST (but not other
// instructions) with conditional branches. // instructions) with conditional branches.
def FeatureBranchFusion def TuningBranchFusion
: SubtargetFeature<"branchfusion", "HasBranchFusion", "true", : SubtargetFeature<"branchfusion", "HasBranchFusion", "true",
"CMP/TEST can be fused with conditional branches">; "CMP/TEST can be fused with conditional branches">;
// Sandy Bridge and newer processors have many instructions that can be // Sandy Bridge and newer processors have many instructions that can be
// fused with conditional branches and pass through the CPU as a single // fused with conditional branches and pass through the CPU as a single
// operation. // operation.
def FeatureMacroFusion def TuningMacroFusion
: SubtargetFeature<"macrofusion", "HasMacroFusion", "true", : SubtargetFeature<"macrofusion", "HasMacroFusion", "true",
"Various instructions can be fused with conditional branches">; "Various instructions can be fused with conditional branches">;
// Gather is available since Haswell (AVX2 set). So technically, we can // Gather is available since Haswell (AVX2 set). So technically, we can
// generate Gathers on all AVX2 processors. But the overhead on HSW is high. // generate Gathers on all AVX2 processors. But the overhead on HSW is high.
// Skylake Client processor has faster Gathers than HSW and performance is // Skylake Client processor has faster Gathers than HSW and performance is
// similar to Skylake Server (AVX-512). // similar to Skylake Server (AVX-512).
def FeatureFastGather def TuningFastGather
: SubtargetFeature<"fast-gather", "HasFastGather", "true", : SubtargetFeature<"fast-gather", "HasFastGather", "true",
"Indicates if gather is reasonably fast">; "Indicates if gather is reasonably fast">;
def FeaturePrefer128Bit def TuningPrefer128Bit
: SubtargetFeature<"prefer-128-bit", "Prefer128Bit", "true", : SubtargetFeature<"prefer-128-bit", "Prefer128Bit", "true",
"Prefer 128-bit AVX instructions">; "Prefer 128-bit AVX instructions">;
def FeaturePrefer256Bit def TuningPrefer256Bit
: SubtargetFeature<"prefer-256-bit", "Prefer256Bit", "true", : SubtargetFeature<"prefer-256-bit", "Prefer256Bit", "true",
"Prefer 256-bit AVX instructions">; "Prefer 256-bit AVX instructions">;
def FeaturePreferMaskRegisters def TuningPreferMaskRegisters
: SubtargetFeature<"prefer-mask-registers", "PreferMaskRegisters", "true", : SubtargetFeature<"prefer-mask-registers", "PreferMaskRegisters", "true",
"Prefer AVX512 mask registers over PTEST/MOVMSK">; "Prefer AVX512 mask registers over PTEST/MOVMSK">;
def FeatureFastBEXTR : SubtargetFeature<"fast-bextr", "HasFastBEXTR", "true", def TuningFastBEXTR : SubtargetFeature<"fast-bextr", "HasFastBEXTR", "true",
"Indicates that the BEXTR instruction is implemented as a single uop " "Indicates that the BEXTR instruction is implemented as a single uop "
"with good throughput">; "with good throughput">;
// Combine vector math operations with shuffles into horizontal math // Combine vector math operations with shuffles into horizontal math
// instructions if a CPU implements horizontal operations (introduced with // instructions if a CPU implements horizontal operations (introduced with
// SSE3) with better latency/throughput than the alternative sequence. // SSE3) with better latency/throughput than the alternative sequence.
def FeatureFastHorizontalOps def TuningFastHorizontalOps
: SubtargetFeature< : SubtargetFeature<
"fast-hops", "HasFastHorizontalOps", "true", "fast-hops", "HasFastHorizontalOps", "true",
"Prefer horizontal vector math instructions (haddp, phsub, etc.) over " "Prefer horizontal vector math instructions (haddp, phsub, etc.) over "
"normal vector instructions with shuffles">; "normal vector instructions with shuffles">;
def FeatureFastScalarShiftMasks def TuningFastScalarShiftMasks
: SubtargetFeature< : SubtargetFeature<
"fast-scalar-shift-masks", "HasFastScalarShiftMasks", "true", "fast-scalar-shift-masks", "HasFastScalarShiftMasks", "true",
"Prefer a left/right scalar logical shift pair over a shift+and pair">; "Prefer a left/right scalar logical shift pair over a shift+and pair">;
def FeatureFastVectorShiftMasks def TuningFastVectorShiftMasks
: SubtargetFeature< : SubtargetFeature<
"fast-vector-shift-masks", "HasFastVectorShiftMasks", "true", "fast-vector-shift-masks", "HasFastVectorShiftMasks", "true",
"Prefer a left/right vector logical shift pair over a shift+and pair">; "Prefer a left/right vector logical shift pair over a shift+and pair">;
def FeatureFastMOVBE def TuningFastMOVBE
: SubtargetFeature<"fast-movbe", "HasFastMOVBE", "true", : SubtargetFeature<"fast-movbe", "HasFastMOVBE", "true",
"Prefer a movbe over a single-use load + bswap / single-use bswap + store">; "Prefer a movbe over a single-use load + bswap / single-use bswap + store">;
def FeatureUseGLMDivSqrtCosts def TuningUseGLMDivSqrtCosts
: SubtargetFeature<"use-glm-div-sqrt-costs", "UseGLMDivSqrtCosts", "true", : SubtargetFeature<"use-glm-div-sqrt-costs", "UseGLMDivSqrtCosts", "true",
"Use Goldmont specific floating point div/sqrt costs">; "Use Goldmont specific floating point div/sqrt costs">;
// Enable use of alias analysis during code generation. // Enable use of alias analysis during code generation.
def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true", def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true",
"Use alias analysis during codegen">; "Use alias analysis during codegen">;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines list<SubtargetFeature> X86_64V4Features = !listconcat(X86_64V3Features, [
FeatureBWI, FeatureBWI,
FeatureCDI, FeatureCDI,
FeatureDQI, FeatureDQI,
FeatureVLX, FeatureVLX,
]); ]);
// Nehalem // Nehalem
list<SubtargetFeature> NHMFeatures = X86_64V2Features; list<SubtargetFeature> NHMFeatures = X86_64V2Features;
list<SubtargetFeature> NHMTuning = [FeatureMacroFusion, list<SubtargetFeature> NHMTuning = [TuningMacroFusion,
FeatureInsertVZEROUPPER]; TuningInsertVZEROUPPER];
// Westmere // Westmere
list<SubtargetFeature> WSMAdditionalFeatures = [FeaturePCLMUL]; list<SubtargetFeature> WSMAdditionalFeatures = [FeaturePCLMUL];
list<SubtargetFeature> WSMTuning = NHMTuning; list<SubtargetFeature> WSMTuning = NHMTuning;
list<SubtargetFeature> WSMFeatures = list<SubtargetFeature> WSMFeatures =
!listconcat(NHMFeatures, WSMAdditionalFeatures); !listconcat(NHMFeatures, WSMAdditionalFeatures);
// Sandybridge // Sandybridge
list<SubtargetFeature> SNBAdditionalFeatures = [FeatureAVX, list<SubtargetFeature> SNBAdditionalFeatures = [FeatureAVX,
FeatureXSAVE, FeatureXSAVE,
FeatureXSAVEOPT]; FeatureXSAVEOPT];
list<SubtargetFeature> SNBTuning = [FeatureMacroFusion, list<SubtargetFeature> SNBTuning = [TuningMacroFusion,
FeatureSlow3OpsLEA, TuningSlow3OpsLEA,
FeatureSlowDivide64, TuningSlowDivide64,
FeatureSlowUAMem32, TuningSlowUAMem32,
FeatureFastScalarFSQRT, TuningFastScalarFSQRT,
FeatureFastSHLDRotate, TuningFastSHLDRotate,
FeatureFast15ByteNOP, TuningFast15ByteNOP,
FeaturePOPCNTFalseDeps, TuningPOPCNTFalseDeps,
FeatureInsertVZEROUPPER]; TuningInsertVZEROUPPER];
list<SubtargetFeature> SNBFeatures = list<SubtargetFeature> SNBFeatures =
!listconcat(WSMFeatures, SNBAdditionalFeatures); !listconcat(WSMFeatures, SNBAdditionalFeatures);
// Ivybridge // Ivybridge
list<SubtargetFeature> IVBAdditionalFeatures = [FeatureRDRAND, list<SubtargetFeature> IVBAdditionalFeatures = [FeatureRDRAND,
FeatureF16C, FeatureF16C,
FeatureFSGSBase]; FeatureFSGSBase];
list<SubtargetFeature> IVBTuning = SNBTuning; list<SubtargetFeature> IVBTuning = SNBTuning;
list<SubtargetFeature> IVBFeatures = list<SubtargetFeature> IVBFeatures =
!listconcat(SNBFeatures, IVBAdditionalFeatures); !listconcat(SNBFeatures, IVBAdditionalFeatures);
// Haswell // Haswell
list<SubtargetFeature> HSWAdditionalFeatures = [FeatureAVX2, list<SubtargetFeature> HSWAdditionalFeatures = [FeatureAVX2,
FeatureBMI, FeatureBMI,
FeatureBMI2, FeatureBMI2,
FeatureERMSB, FeatureERMSB,
FeatureFMA, FeatureFMA,
FeatureINVPCID, FeatureINVPCID,
FeatureLZCNT, FeatureLZCNT,
FeatureMOVBE]; FeatureMOVBE];
list<SubtargetFeature> HSWTuning = [FeatureMacroFusion, list<SubtargetFeature> HSWTuning = [TuningMacroFusion,
FeatureSlow3OpsLEA, TuningSlow3OpsLEA,
FeatureSlowDivide64, TuningSlowDivide64,
FeatureFastScalarFSQRT, TuningFastScalarFSQRT,
FeatureFastSHLDRotate, TuningFastSHLDRotate,
FeatureFast15ByteNOP, TuningFast15ByteNOP,
FeatureFastVariableCrossLaneShuffle, TuningFastVariableCrossLaneShuffle,
FeatureFastVariablePerLaneShuffle, TuningFastVariablePerLaneShuffle,
FeaturePOPCNTFalseDeps, TuningPOPCNTFalseDeps,
FeatureLZCNTFalseDeps, TuningLZCNTFalseDeps,
FeatureInsertVZEROUPPER]; TuningInsertVZEROUPPER];
list<SubtargetFeature> HSWFeatures = list<SubtargetFeature> HSWFeatures =
!listconcat(IVBFeatures, HSWAdditionalFeatures); !listconcat(IVBFeatures, HSWAdditionalFeatures);
// Broadwell // Broadwell
list<SubtargetFeature> BDWAdditionalFeatures = [FeatureADX, list<SubtargetFeature> BDWAdditionalFeatures = [FeatureADX,
FeatureRDSEED, FeatureRDSEED,
FeaturePRFCHW]; FeaturePRFCHW];
list<SubtargetFeature> BDWTuning = HSWTuning; list<SubtargetFeature> BDWTuning = HSWTuning;
list<SubtargetFeature> BDWFeatures = list<SubtargetFeature> BDWFeatures =
!listconcat(HSWFeatures, BDWAdditionalFeatures); !listconcat(HSWFeatures, BDWAdditionalFeatures);
// Skylake // Skylake
list<SubtargetFeature> SKLAdditionalFeatures = [FeatureAES, list<SubtargetFeature> SKLAdditionalFeatures = [FeatureAES,
FeatureXSAVEC, FeatureXSAVEC,
FeatureXSAVES, FeatureXSAVES,
FeatureCLFLUSHOPT]; FeatureCLFLUSHOPT];
list<SubtargetFeature> SKLTuning = [FeatureFastGather, list<SubtargetFeature> SKLTuning = [TuningFastGather,
FeatureMacroFusion, TuningMacroFusion,
FeatureSlow3OpsLEA, TuningSlow3OpsLEA,
FeatureSlowDivide64, TuningSlowDivide64,
FeatureFastScalarFSQRT, TuningFastScalarFSQRT,
FeatureFastVectorFSQRT, TuningFastVectorFSQRT,
FeatureFastSHLDRotate, TuningFastSHLDRotate,
FeatureFast15ByteNOP, TuningFast15ByteNOP,
FeatureFastVariableCrossLaneShuffle, TuningFastVariableCrossLaneShuffle,
FeatureFastVariablePerLaneShuffle, TuningFastVariablePerLaneShuffle,
FeaturePOPCNTFalseDeps, TuningPOPCNTFalseDeps,
FeatureInsertVZEROUPPER]; TuningInsertVZEROUPPER];
list<SubtargetFeature> SKLFeatures = list<SubtargetFeature> SKLFeatures =
!listconcat(BDWFeatures, SKLAdditionalFeatures); !listconcat(BDWFeatures, SKLAdditionalFeatures);
// Skylake-AVX512 // Skylake-AVX512
list<SubtargetFeature> SKXAdditionalFeatures = [FeatureAES, list<SubtargetFeature> SKXAdditionalFeatures = [FeatureAES,
FeatureXSAVEC, FeatureXSAVEC,
FeatureXSAVES, FeatureXSAVES,
FeatureCLFLUSHOPT, FeatureCLFLUSHOPT,
FeatureAVX512, FeatureAVX512,
FeatureCDI, FeatureCDI,
FeatureDQI, FeatureDQI,
FeatureBWI, FeatureBWI,
FeatureVLX, FeatureVLX,
FeaturePKU, FeaturePKU,
FeatureCLWB]; FeatureCLWB];
list<SubtargetFeature> SKXTuning = [FeatureFastGather, list<SubtargetFeature> SKXTuning = [TuningFastGather,
FeatureMacroFusion, TuningMacroFusion,
FeatureSlow3OpsLEA, TuningSlow3OpsLEA,
FeatureSlowDivide64, TuningSlowDivide64,
FeatureFastScalarFSQRT, TuningFastScalarFSQRT,
FeatureFastVectorFSQRT, TuningFastVectorFSQRT,
FeatureFastSHLDRotate, TuningFastSHLDRotate,
FeatureFast15ByteNOP, TuningFast15ByteNOP,
FeatureFastVariableCrossLaneShuffle, TuningFastVariableCrossLaneShuffle,
FeatureFastVariablePerLaneShuffle, TuningFastVariablePerLaneShuffle,
FeaturePrefer256Bit, TuningPrefer256Bit,
FeaturePOPCNTFalseDeps, TuningPOPCNTFalseDeps,
FeatureInsertVZEROUPPER]; TuningInsertVZEROUPPER];
list<SubtargetFeature> SKXFeatures = list<SubtargetFeature> SKXFeatures =
!listconcat(BDWFeatures, SKXAdditionalFeatures); !listconcat(BDWFeatures, SKXAdditionalFeatures);
// Cascadelake // Cascadelake
list<SubtargetFeature> CLXAdditionalFeatures = [FeatureVNNI]; list<SubtargetFeature> CLXAdditionalFeatures = [FeatureVNNI];
list<SubtargetFeature> CLXTuning = SKXTuning; list<SubtargetFeature> CLXTuning = SKXTuning;
list<SubtargetFeature> CLXFeatures = list<SubtargetFeature> CLXFeatures =
!listconcat(SKXFeatures, CLXAdditionalFeatures); !listconcat(SKXFeatures, CLXAdditionalFeatures);
Show All 9 Lines list<SubtargetFeature> CNLAdditionalFeatures = [FeatureAVX512,
FeatureCDI, FeatureCDI,
FeatureDQI, FeatureDQI,
FeatureBWI, FeatureBWI,
FeatureVLX, FeatureVLX,
FeaturePKU, FeaturePKU,
FeatureVBMI, FeatureVBMI,
FeatureIFMA, FeatureIFMA,
FeatureSHA]; FeatureSHA];
list<SubtargetFeature> CNLTuning = [FeatureFastGather, list<SubtargetFeature> CNLTuning = [TuningFastGather,
FeatureMacroFusion, TuningMacroFusion,
FeatureSlow3OpsLEA, TuningSlow3OpsLEA,
FeatureSlowDivide64, TuningSlowDivide64,
FeatureFastScalarFSQRT, TuningFastScalarFSQRT,
FeatureFastVectorFSQRT, TuningFastVectorFSQRT,
FeatureFastSHLDRotate, TuningFastSHLDRotate,
FeatureFast15ByteNOP, TuningFast15ByteNOP,
FeatureFastVariableCrossLaneShuffle, TuningFastVariableCrossLaneShuffle,
FeatureFastVariablePerLaneShuffle, TuningFastVariablePerLaneShuffle,
FeaturePrefer256Bit, TuningPrefer256Bit,
FeatureInsertVZEROUPPER]; TuningInsertVZEROUPPER];
list<SubtargetFeature> CNLFeatures = list<SubtargetFeature> CNLFeatures =
!listconcat(SKLFeatures, CNLAdditionalFeatures); !listconcat(SKLFeatures, CNLAdditionalFeatures);
// Icelake // Icelake
list<SubtargetFeature> ICLAdditionalFeatures = [FeatureBITALG, list<SubtargetFeature> ICLAdditionalFeatures = [FeatureBITALG,
FeatureVAES, FeatureVAES,
FeatureVBMI2, FeatureVBMI2,
FeatureVNNI, FeatureVNNI,
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines list<SubtargetFeature> AtomFeatures = [FeatureX87,
FeatureSSSE3, FeatureSSSE3,
FeatureFXSR, FeatureFXSR,
FeatureNOPL, FeatureNOPL,
Feature64Bit, Feature64Bit,
FeatureCMPXCHG16B, FeatureCMPXCHG16B,
FeatureMOVBE, FeatureMOVBE,
FeatureLAHFSAHF]; FeatureLAHFSAHF];
list<SubtargetFeature> AtomTuning = [ProcIntelAtom, list<SubtargetFeature> AtomTuning = [ProcIntelAtom,
FeatureSlowUAMem16, TuningSlowUAMem16,
FeatureLEAForSP, TuningLEAForSP,
FeatureSlowDivide32, TuningSlowDivide32,
FeatureSlowDivide64, TuningSlowDivide64,
FeatureSlowTwoMemOps, TuningSlowTwoMemOps,
FeatureLEAUsesAG, TuningLEAUsesAG,
FeaturePadShortFunctions, TuningPadShortFunctions,
FeatureInsertVZEROUPPER]; TuningInsertVZEROUPPER];
// Silvermont // Silvermont
list<SubtargetFeature> SLMAdditionalFeatures = [FeatureSSE42, list<SubtargetFeature> SLMAdditionalFeatures = [FeatureSSE42,
FeaturePOPCNT, FeaturePOPCNT,
FeaturePCLMUL, FeaturePCLMUL,
FeaturePRFCHW, FeaturePRFCHW,
FeatureRDRAND]; FeatureRDRAND];
list<SubtargetFeature> SLMTuning = [ProcIntelSLM, list<SubtargetFeature> SLMTuning = [ProcIntelSLM,
FeatureSlowTwoMemOps, TuningSlowTwoMemOps,
FeatureSlowLEA, TuningSlowLEA,
FeatureSlowIncDec, TuningSlowIncDec,
FeatureSlowDivide64, TuningSlowDivide64,
FeatureSlowPMULLD, TuningSlowPMULLD,
FeatureFast7ByteNOP, TuningFast7ByteNOP,
FeatureFastMOVBE, TuningFastMOVBE,
FeaturePOPCNTFalseDeps, TuningPOPCNTFalseDeps,
FeatureInsertVZEROUPPER]; TuningInsertVZEROUPPER];
list<SubtargetFeature> SLMFeatures = list<SubtargetFeature> SLMFeatures =
!listconcat(AtomFeatures, SLMAdditionalFeatures); !listconcat(AtomFeatures, SLMAdditionalFeatures);
// Goldmont // Goldmont
list<SubtargetFeature> GLMAdditionalFeatures = [FeatureAES, list<SubtargetFeature> GLMAdditionalFeatures = [FeatureAES,
FeatureSHA, FeatureSHA,
FeatureRDSEED, FeatureRDSEED,
FeatureXSAVE, FeatureXSAVE,
FeatureXSAVEOPT, FeatureXSAVEOPT,
FeatureXSAVEC, FeatureXSAVEC,
FeatureXSAVES, FeatureXSAVES,
FeatureCLFLUSHOPT, FeatureCLFLUSHOPT,
FeatureFSGSBase]; FeatureFSGSBase];
list<SubtargetFeature> GLMTuning = [FeatureUseGLMDivSqrtCosts, list<SubtargetFeature> GLMTuning = [TuningUseGLMDivSqrtCosts,
FeatureSlowTwoMemOps, TuningSlowTwoMemOps,
FeatureSlowLEA, TuningSlowLEA,
FeatureSlowIncDec, TuningSlowIncDec,
FeatureFastMOVBE, TuningFastMOVBE,
FeaturePOPCNTFalseDeps, TuningPOPCNTFalseDeps,
FeatureInsertVZEROUPPER]; TuningInsertVZEROUPPER];
list<SubtargetFeature> GLMFeatures = list<SubtargetFeature> GLMFeatures =
!listconcat(SLMFeatures, GLMAdditionalFeatures); !listconcat(SLMFeatures, GLMAdditionalFeatures);
// Goldmont Plus // Goldmont Plus
list<SubtargetFeature> GLPAdditionalFeatures = [FeaturePTWRITE, list<SubtargetFeature> GLPAdditionalFeatures = [FeaturePTWRITE,
FeatureRDPID]; FeatureRDPID];
list<SubtargetFeature> GLPTuning = [FeatureUseGLMDivSqrtCosts, list<SubtargetFeature> GLPTuning = [TuningUseGLMDivSqrtCosts,
FeatureSlowTwoMemOps, TuningSlowTwoMemOps,
FeatureSlowLEA, TuningSlowLEA,
FeatureSlowIncDec, TuningSlowIncDec,
FeatureFastMOVBE, TuningFastMOVBE,
FeatureInsertVZEROUPPER]; TuningInsertVZEROUPPER];
list<SubtargetFeature> GLPFeatures = list<SubtargetFeature> GLPFeatures =
!listconcat(GLMFeatures, GLPAdditionalFeatures); !listconcat(GLMFeatures, GLPAdditionalFeatures);
// Tremont // Tremont
list<SubtargetFeature> TRMAdditionalFeatures = [FeatureCLWB, list<SubtargetFeature> TRMAdditionalFeatures = [FeatureCLWB,
FeatureGFNI]; FeatureGFNI];
list<SubtargetFeature> TRMTuning = GLPTuning; list<SubtargetFeature> TRMTuning = GLPTuning;
list<SubtargetFeature> TRMFeatures = list<SubtargetFeature> TRMFeatures =
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines list<SubtargetFeature> KNLFeatures = [FeatureX87,
FeatureADX, FeatureADX,
FeatureRDSEED, FeatureRDSEED,
FeatureMOVBE, FeatureMOVBE,
FeatureLZCNT, FeatureLZCNT,
FeatureBMI, FeatureBMI,
FeatureBMI2, FeatureBMI2,
FeatureFMA, FeatureFMA,
FeaturePRFCHW]; FeaturePRFCHW];
list<SubtargetFeature> KNLTuning = [FeatureSlowDivide64, list<SubtargetFeature> KNLTuning = [TuningSlowDivide64,
FeatureSlow3OpsLEA, TuningSlow3OpsLEA,
FeatureSlowIncDec, TuningSlowIncDec,
FeatureSlowTwoMemOps, TuningSlowTwoMemOps,
FeaturePreferMaskRegisters, TuningPreferMaskRegisters,
FeatureFastGather, TuningFastGather,
FeatureFastMOVBE, TuningFastMOVBE,
FeatureSlowPMADDWD]; TuningSlowPMADDWD];
// TODO Add AVX5124FMAPS/AVX5124VNNIW features // TODO Add AVX5124FMAPS/AVX5124VNNIW features
list<SubtargetFeature> KNMFeatures = list<SubtargetFeature> KNMFeatures =
!listconcat(KNLFeatures, [FeatureVPOPCNTDQ]); !listconcat(KNLFeatures, [FeatureVPOPCNTDQ]);
// Barcelona // Barcelona
list<SubtargetFeature> BarcelonaFeatures = [FeatureX87, list<SubtargetFeature> BarcelonaFeatures = [FeatureX87,
FeatureCMPXCHG8B, FeatureCMPXCHG8B,
FeatureSSE4A, FeatureSSE4A,
Feature3DNowA, Feature3DNowA,
FeatureFXSR, FeatureFXSR,
FeatureNOPL, FeatureNOPL,
FeatureCMPXCHG16B, FeatureCMPXCHG16B,
FeaturePRFCHW, FeaturePRFCHW,
FeatureLZCNT, FeatureLZCNT,
FeaturePOPCNT, FeaturePOPCNT,
FeatureLAHFSAHF, FeatureLAHFSAHF,
FeatureCMOV, FeatureCMOV,
Feature64Bit]; Feature64Bit];
list<SubtargetFeature> BarcelonaTuning = [FeatureFastScalarShiftMasks, list<SubtargetFeature> BarcelonaTuning = [TuningFastScalarShiftMasks,
FeatureSlowSHLD, TuningSlowSHLD,
FeatureInsertVZEROUPPER]; TuningInsertVZEROUPPER];
// Bobcat // Bobcat
list<SubtargetFeature> BtVer1Features = [FeatureX87, list<SubtargetFeature> BtVer1Features = [FeatureX87,
FeatureCMPXCHG8B, FeatureCMPXCHG8B,
FeatureCMOV, FeatureCMOV,
FeatureMMX, FeatureMMX,
FeatureSSSE3, FeatureSSSE3,
FeatureSSE4A, FeatureSSE4A,
FeatureFXSR, FeatureFXSR,
FeatureNOPL, FeatureNOPL,
Feature64Bit, Feature64Bit,
FeatureCMPXCHG16B, FeatureCMPXCHG16B,
FeaturePRFCHW, FeaturePRFCHW,
FeatureLZCNT, FeatureLZCNT,
FeaturePOPCNT, FeaturePOPCNT,
FeatureLAHFSAHF]; FeatureLAHFSAHF];
list<SubtargetFeature> BtVer1Tuning = [FeatureFast15ByteNOP, list<SubtargetFeature> BtVer1Tuning = [TuningFast15ByteNOP,
FeatureFastScalarShiftMasks, TuningFastScalarShiftMasks,
FeatureFastVectorShiftMasks, TuningFastVectorShiftMasks,
FeatureSlowSHLD, TuningSlowSHLD,
FeatureInsertVZEROUPPER]; TuningInsertVZEROUPPER];
// Jaguar // Jaguar
list<SubtargetFeature> BtVer2AdditionalFeatures = [FeatureAVX, list<SubtargetFeature> BtVer2AdditionalFeatures = [FeatureAVX,
FeatureAES, FeatureAES,
FeaturePCLMUL, FeaturePCLMUL,
FeatureBMI, FeatureBMI,
FeatureF16C, FeatureF16C,
FeatureMOVBE, FeatureMOVBE,
FeatureXSAVE, FeatureXSAVE,
FeatureXSAVEOPT]; FeatureXSAVEOPT];
list<SubtargetFeature> BtVer2Tuning = [FeatureFastLZCNT, list<SubtargetFeature> BtVer2Tuning = [TuningFastLZCNT,
FeatureFastBEXTR, TuningFastBEXTR,
FeatureFastHorizontalOps, TuningFastHorizontalOps,
FeatureFast15ByteNOP, TuningFast15ByteNOP,
FeatureFastScalarShiftMasks, TuningFastScalarShiftMasks,
FeatureFastVectorShiftMasks, TuningFastVectorShiftMasks,
FeatureFastMOVBE, TuningFastMOVBE,
FeatureSlowSHLD]; TuningSlowSHLD];
list<SubtargetFeature> BtVer2Features = list<SubtargetFeature> BtVer2Features =
!listconcat(BtVer1Features, BtVer2AdditionalFeatures); !listconcat(BtVer1Features, BtVer2AdditionalFeatures);
// Bulldozer // Bulldozer
list<SubtargetFeature> BdVer1Features = [FeatureX87, list<SubtargetFeature> BdVer1Features = [FeatureX87,
FeatureCMPXCHG8B, FeatureCMPXCHG8B,
FeatureCMOV, FeatureCMOV,
FeatureXOP, FeatureXOP,
Feature64Bit, Feature64Bit,
FeatureCMPXCHG16B, FeatureCMPXCHG16B,
FeatureAES, FeatureAES,
FeaturePRFCHW, FeaturePRFCHW,
FeaturePCLMUL, FeaturePCLMUL,
FeatureMMX, FeatureMMX,
FeatureFXSR, FeatureFXSR,
FeatureNOPL, FeatureNOPL,
FeatureLZCNT, FeatureLZCNT,
FeaturePOPCNT, FeaturePOPCNT,
FeatureXSAVE, FeatureXSAVE,
FeatureLWP, FeatureLWP,
FeatureLAHFSAHF]; FeatureLAHFSAHF];
list<SubtargetFeature> BdVer1Tuning = [FeatureSlowSHLD, list<SubtargetFeature> BdVer1Tuning = [TuningSlowSHLD,
FeatureFast11ByteNOP, TuningFast11ByteNOP,
FeatureFastScalarShiftMasks, TuningFastScalarShiftMasks,
FeatureBranchFusion, TuningBranchFusion,
FeatureInsertVZEROUPPER]; TuningInsertVZEROUPPER];
// PileDriver // PileDriver
list<SubtargetFeature> BdVer2AdditionalFeatures = [FeatureF16C, list<SubtargetFeature> BdVer2AdditionalFeatures = [FeatureF16C,
FeatureBMI, FeatureBMI,
FeatureTBM, FeatureTBM,
FeatureFMA]; FeatureFMA];
list<SubtargetFeature> BdVer2AdditionalTuning = [FeatureFastBEXTR, list<SubtargetFeature> BdVer2AdditionalTuning = [TuningFastBEXTR,
FeatureFastMOVBE]; TuningFastMOVBE];
list<SubtargetFeature> BdVer2Tuning = list<SubtargetFeature> BdVer2Tuning =
!listconcat(BdVer1Tuning, BdVer2AdditionalTuning); !listconcat(BdVer1Tuning, BdVer2AdditionalTuning);
list<SubtargetFeature> BdVer2Features = list<SubtargetFeature> BdVer2Features =
!listconcat(BdVer1Features, BdVer2AdditionalFeatures); !listconcat(BdVer1Features, BdVer2AdditionalFeatures);
// Steamroller // Steamroller
list<SubtargetFeature> BdVer3AdditionalFeatures = [FeatureXSAVEOPT, list<SubtargetFeature> BdVer3AdditionalFeatures = [FeatureXSAVEOPT,
FeatureFSGSBase]; FeatureFSGSBase];
Show All 40 Lines list<SubtargetFeature> ZNFeatures = [FeatureADX,
FeatureRDSEED, FeatureRDSEED,
FeatureSHA, FeatureSHA,
FeatureSSE4A, FeatureSSE4A,
FeatureX87, FeatureX87,
FeatureXSAVE, FeatureXSAVE,
FeatureXSAVEC, FeatureXSAVEC,
FeatureXSAVEOPT, FeatureXSAVEOPT,
FeatureXSAVES]; FeatureXSAVES];
list<SubtargetFeature> ZNTuning = [FeatureFastLZCNT, list<SubtargetFeature> ZNTuning = [TuningFastLZCNT,
FeatureFastBEXTR, TuningFastBEXTR,
FeatureFast15ByteNOP, TuningFast15ByteNOP,
FeatureBranchFusion, TuningBranchFusion,
FeatureFastScalarShiftMasks, TuningFastScalarShiftMasks,
FeatureFastMOVBE, TuningFastMOVBE,
FeatureSlowSHLD, TuningSlowSHLD,
FeatureInsertVZEROUPPER]; TuningInsertVZEROUPPER];
list<SubtargetFeature> ZN2AdditionalFeatures = [FeatureCLWB, list<SubtargetFeature> ZN2AdditionalFeatures = [FeatureCLWB,
FeatureRDPID, FeatureRDPID,
FeatureWBNOINVD]; FeatureWBNOINVD];
list<SubtargetFeature> ZN2Tuning = ZNTuning; list<SubtargetFeature> ZN2Tuning = ZNTuning;
list<SubtargetFeature> ZN2Features = list<SubtargetFeature> ZN2Features =
!listconcat(ZNFeatures, ZN2AdditionalFeatures); !listconcat(ZNFeatures, ZN2AdditionalFeatures);
list<SubtargetFeature> ZN3AdditionalFeatures = [FeatureFSRM, list<SubtargetFeature> ZN3AdditionalFeatures = [FeatureFSRM,
FeatureINVPCID, FeatureINVPCID,
FeaturePKU, FeaturePKU,
FeatureVAES, FeatureVAES,
FeatureVPCLMULQDQ]; FeatureVPCLMULQDQ];
list<SubtargetFeature> ZN3AdditionalTuning = list<SubtargetFeature> ZN3AdditionalTuning =
[FeatureMacroFusion, [TuningMacroFusion,
FeatureFastVariablePerLaneShuffle]; TuningFastVariablePerLaneShuffle];
list<SubtargetFeature> ZN3Tuning = list<SubtargetFeature> ZN3Tuning =
!listconcat(ZNTuning, ZN3AdditionalTuning); !listconcat(ZNTuning, ZN3AdditionalTuning);
list<SubtargetFeature> ZN3Features = list<SubtargetFeature> ZN3Features =
!listconcat(ZN2Features, ZN3AdditionalFeatures); !listconcat(ZN2Features, ZN3AdditionalFeatures);
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// X86 processors supported. // X86 processors supported.
Show All 10 Lines
// NOTE: CMPXCHG8B is here for legacy compatibility so that it is only disabled // NOTE: CMPXCHG8B is here for legacy compatibility so that it is only disabled
// if i386/i486 is specifically requested. // if i386/i486 is specifically requested.
// NOTE: 64Bit is here as "generic" is the default llc CPU. The X86Subtarget // NOTE: 64Bit is here as "generic" is the default llc CPU. The X86Subtarget
// constructor checks that any CPU used in 64-bit mode has Feature64Bit enabled. // constructor checks that any CPU used in 64-bit mode has Feature64Bit enabled.
// It has no effect on code generation. // It has no effect on code generation.
def : ProcModel<"generic", SandyBridgeModel, def : ProcModel<"generic", SandyBridgeModel,
[FeatureX87, FeatureCMPXCHG8B, Feature64Bit], [FeatureX87, FeatureCMPXCHG8B, Feature64Bit],
[FeatureSlow3OpsLEA, [TuningSlow3OpsLEA,
FeatureSlowDivide64, TuningSlowDivide64,
FeatureSlowIncDec, TuningSlowIncDec,
FeatureMacroFusion, TuningMacroFusion,
FeatureInsertVZEROUPPER]>; TuningInsertVZEROUPPER]>;
def : Proc<"i386", [FeatureX87], def : Proc<"i386", [FeatureX87],
[FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
def : Proc<"i486", [FeatureX87], def : Proc<"i486", [FeatureX87],
[FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
def : Proc<"i586", [FeatureX87, FeatureCMPXCHG8B], def : Proc<"i586", [FeatureX87, FeatureCMPXCHG8B],
[FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
def : Proc<"pentium", [FeatureX87, FeatureCMPXCHG8B], def : Proc<"pentium", [FeatureX87, FeatureCMPXCHG8B],
[FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
def : Proc<"pentium-mmx", [FeatureX87, FeatureCMPXCHG8B, FeatureMMX], def : Proc<"pentium-mmx", [FeatureX87, FeatureCMPXCHG8B, FeatureMMX],
[FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
def : Proc<"i686", [FeatureX87, FeatureCMPXCHG8B, FeatureCMOV], def : Proc<"i686", [FeatureX87, FeatureCMPXCHG8B, FeatureCMOV],
[FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
def : Proc<"pentiumpro", [FeatureX87, FeatureCMPXCHG8B, FeatureCMOV, def : Proc<"pentiumpro", [FeatureX87, FeatureCMPXCHG8B, FeatureCMOV,
FeatureNOPL], FeatureNOPL],
[FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
def : Proc<"pentium2", [FeatureX87, FeatureCMPXCHG8B, FeatureMMX, FeatureCMOV, def : Proc<"pentium2", [FeatureX87, FeatureCMPXCHG8B, FeatureMMX, FeatureCMOV,
FeatureFXSR, FeatureNOPL], FeatureFXSR, FeatureNOPL],
[FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
foreach P = ["pentium3", "pentium3m"] in { foreach P = ["pentium3", "pentium3m"] in {
def : Proc<P, [FeatureX87, FeatureCMPXCHG8B, FeatureMMX, def : Proc<P, [FeatureX87, FeatureCMPXCHG8B, FeatureMMX,
FeatureSSE1, FeatureFXSR, FeatureNOPL, FeatureCMOV], FeatureSSE1, FeatureFXSR, FeatureNOPL, FeatureCMOV],
[FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
} }
// Enable the PostRAScheduler for SSE2 and SSE3 class cpus. // Enable the PostRAScheduler for SSE2 and SSE3 class cpus.
// The intent is to enable it for pentium4 which is the current default // The intent is to enable it for pentium4 which is the current default
// processor in a vanilla 32-bit clang compilation when no specific // processor in a vanilla 32-bit clang compilation when no specific
// architecture is specified. This generally gives a nice performance // architecture is specified. This generally gives a nice performance
// increase on silvermont, with largely neutral behavior on other // increase on silvermont, with largely neutral behavior on other
// contemporary large core processors. // contemporary large core processors.
// pentium-m, pentium4m, prescott and nocona are included as a preventative // pentium-m, pentium4m, prescott and nocona are included as a preventative
// measure to avoid performance surprises, in case clang's default cpu // measure to avoid performance surprises, in case clang's default cpu
// changes slightly. // changes slightly.
def : ProcModel<"pentium-m", GenericPostRAModel, def : ProcModel<"pentium-m", GenericPostRAModel,
[FeatureX87, FeatureCMPXCHG8B, FeatureMMX, FeatureSSE2, [FeatureX87, FeatureCMPXCHG8B, FeatureMMX, FeatureSSE2,
FeatureFXSR, FeatureNOPL, FeatureCMOV], FeatureFXSR, FeatureNOPL, FeatureCMOV],
[FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
foreach P = ["pentium4", "pentium4m"] in { foreach P = ["pentium4", "pentium4m"] in {
def : ProcModel<P, GenericPostRAModel, def : ProcModel<P, GenericPostRAModel,
[FeatureX87, FeatureCMPXCHG8B, FeatureMMX, FeatureSSE2, [FeatureX87, FeatureCMPXCHG8B, FeatureMMX, FeatureSSE2,
FeatureFXSR, FeatureNOPL, FeatureCMOV], FeatureFXSR, FeatureNOPL, FeatureCMOV],
[FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
} }
// Intel Quark. // Intel Quark.
def : Proc<"lakemont", [FeatureCMPXCHG8B], def : Proc<"lakemont", [FeatureCMPXCHG8B],
[FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
// Intel Core Duo. // Intel Core Duo.
def : ProcModel<"yonah", SandyBridgeModel, def : ProcModel<"yonah", SandyBridgeModel,
[FeatureX87, FeatureCMPXCHG8B, FeatureMMX, FeatureSSE3, [FeatureX87, FeatureCMPXCHG8B, FeatureMMX, FeatureSSE3,
FeatureFXSR, FeatureNOPL, FeatureCMOV], FeatureFXSR, FeatureNOPL, FeatureCMOV],
[FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
// NetBurst. // NetBurst.
def : ProcModel<"prescott", GenericPostRAModel, def : ProcModel<"prescott", GenericPostRAModel,
[FeatureX87, FeatureCMPXCHG8B, FeatureMMX, FeatureSSE3, [FeatureX87, FeatureCMPXCHG8B, FeatureMMX, FeatureSSE3,
FeatureFXSR, FeatureNOPL, FeatureCMOV], FeatureFXSR, FeatureNOPL, FeatureCMOV],
[FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
def : ProcModel<"nocona", GenericPostRAModel, [ def : ProcModel<"nocona", GenericPostRAModel, [
FeatureX87, FeatureX87,
FeatureCMPXCHG8B, FeatureCMPXCHG8B,
FeatureCMOV, FeatureCMOV,
FeatureMMX, FeatureMMX,
FeatureSSE3, FeatureSSE3,
FeatureFXSR, FeatureFXSR,
FeatureNOPL, FeatureNOPL,
Feature64Bit, Feature64Bit,
FeatureCMPXCHG16B, FeatureCMPXCHG16B,
], ],
[ [
FeatureSlowUAMem16, TuningSlowUAMem16,
FeatureInsertVZEROUPPER TuningInsertVZEROUPPER
]>; ]>;
// Intel Core 2 Solo/Duo. // Intel Core 2 Solo/Duo.
def : ProcModel<"core2", SandyBridgeModel, [ def : ProcModel<"core2", SandyBridgeModel, [
FeatureX87, FeatureX87,
FeatureCMPXCHG8B, FeatureCMPXCHG8B,
FeatureCMOV, FeatureCMOV,
FeatureMMX, FeatureMMX,
FeatureSSSE3, FeatureSSSE3,
FeatureFXSR, FeatureFXSR,
FeatureNOPL, FeatureNOPL,
Feature64Bit, Feature64Bit,
FeatureCMPXCHG16B, FeatureCMPXCHG16B,
FeatureLAHFSAHF FeatureLAHFSAHF
], ],
[ [
FeatureMacroFusion, TuningMacroFusion,
FeatureSlowUAMem16, TuningSlowUAMem16,
FeatureInsertVZEROUPPER TuningInsertVZEROUPPER
]>; ]>;
def : ProcModel<"penryn", SandyBridgeModel, [ def : ProcModel<"penryn", SandyBridgeModel, [
FeatureX87, FeatureX87,
FeatureCMPXCHG8B, FeatureCMPXCHG8B,
FeatureCMOV, FeatureCMOV,
FeatureMMX, FeatureMMX,
FeatureSSE41, FeatureSSE41,
FeatureFXSR, FeatureFXSR,
FeatureNOPL, FeatureNOPL,
Feature64Bit, Feature64Bit,
FeatureCMPXCHG16B, FeatureCMPXCHG16B,
FeatureLAHFSAHF FeatureLAHFSAHF
], ],
[ [
FeatureMacroFusion, TuningMacroFusion,
FeatureSlowUAMem16, TuningSlowUAMem16,
FeatureInsertVZEROUPPER TuningInsertVZEROUPPER
]>; ]>;
// Atom CPUs. // Atom CPUs.
foreach P = ["bonnell", "atom"] in { foreach P = ["bonnell", "atom"] in {
def : ProcModel<P, AtomModel, ProcessorFeatures.AtomFeatures, def : ProcModel<P, AtomModel, ProcessorFeatures.AtomFeatures,
ProcessorFeatures.AtomTuning>; ProcessorFeatures.AtomTuning>;
} }
▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Lines
def : ProcModel<"sapphirerapids", SkylakeServerModel, def : ProcModel<"sapphirerapids", SkylakeServerModel,
ProcessorFeatures.SPRFeatures, ProcessorFeatures.SPRTuning>; ProcessorFeatures.SPRFeatures, ProcessorFeatures.SPRTuning>;
def : ProcModel<"alderlake", SkylakeClientModel, def : ProcModel<"alderlake", SkylakeClientModel,
ProcessorFeatures.ADLFeatures, ProcessorFeatures.ADLTuning>; ProcessorFeatures.ADLFeatures, ProcessorFeatures.ADLTuning>;
// AMD CPUs. // AMD CPUs.
def : Proc<"k6", [FeatureX87, FeatureCMPXCHG8B, FeatureMMX], def : Proc<"k6", [FeatureX87, FeatureCMPXCHG8B, FeatureMMX],
[FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
def : Proc<"k6-2", [FeatureX87, FeatureCMPXCHG8B, Feature3DNow], def : Proc<"k6-2", [FeatureX87, FeatureCMPXCHG8B, Feature3DNow],
[FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
def : Proc<"k6-3", [FeatureX87, FeatureCMPXCHG8B, Feature3DNow], def : Proc<"k6-3", [FeatureX87, FeatureCMPXCHG8B, Feature3DNow],
[FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
foreach P = ["athlon", "athlon-tbird"] in { foreach P = ["athlon", "athlon-tbird"] in {
def : Proc<P, [FeatureX87, FeatureCMPXCHG8B, FeatureCMOV, Feature3DNowA, def : Proc<P, [FeatureX87, FeatureCMPXCHG8B, FeatureCMOV, Feature3DNowA,
FeatureNOPL], FeatureNOPL],
[FeatureSlowSHLD, FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; [TuningSlowSHLD, TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
} }
foreach P = ["athlon-4", "athlon-xp", "athlon-mp"] in { foreach P = ["athlon-4", "athlon-xp", "athlon-mp"] in {
def : Proc<P, [FeatureX87, FeatureCMPXCHG8B, FeatureCMOV, def : Proc<P, [FeatureX87, FeatureCMPXCHG8B, FeatureCMOV,
FeatureSSE1, Feature3DNowA, FeatureFXSR, FeatureNOPL], FeatureSSE1, Feature3DNowA, FeatureFXSR, FeatureNOPL],
[FeatureSlowSHLD, FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; [TuningSlowSHLD, TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
} }
foreach P = ["k8", "opteron", "athlon64", "athlon-fx"] in { foreach P = ["k8", "opteron", "athlon64", "athlon-fx"] in {
def : Proc<P, [FeatureX87, FeatureCMPXCHG8B, FeatureSSE2, Feature3DNowA, def : Proc<P, [FeatureX87, FeatureCMPXCHG8B, FeatureSSE2, Feature3DNowA,
FeatureFXSR, FeatureNOPL, Feature64Bit, FeatureCMOV], FeatureFXSR, FeatureNOPL, Feature64Bit, FeatureCMOV],
[FeatureFastScalarShiftMasks, FeatureSlowSHLD, FeatureSlowUAMem16, [TuningFastScalarShiftMasks, TuningSlowSHLD, TuningSlowUAMem16,
FeatureInsertVZEROUPPER]>; TuningInsertVZEROUPPER]>;
} }
foreach P = ["k8-sse3", "opteron-sse3", "athlon64-sse3"] in { foreach P = ["k8-sse3", "opteron-sse3", "athlon64-sse3"] in {
def : Proc<P, [FeatureX87, FeatureCMPXCHG8B, FeatureSSE3, Feature3DNowA, def : Proc<P, [FeatureX87, FeatureCMPXCHG8B, FeatureSSE3, Feature3DNowA,
FeatureFXSR, FeatureNOPL, FeatureCMPXCHG16B, FeatureCMOV, FeatureFXSR, FeatureNOPL, FeatureCMPXCHG16B, FeatureCMOV,
Feature64Bit], Feature64Bit],
[FeatureFastScalarShiftMasks, FeatureSlowSHLD, FeatureSlowUAMem16, [TuningFastScalarShiftMasks, TuningSlowSHLD, TuningSlowUAMem16,
FeatureInsertVZEROUPPER]>; TuningInsertVZEROUPPER]>;
} }
foreach P = ["amdfam10", "barcelona"] in { foreach P = ["amdfam10", "barcelona"] in {
def : Proc<P, ProcessorFeatures.BarcelonaFeatures, def : Proc<P, ProcessorFeatures.BarcelonaFeatures,
ProcessorFeatures.BarcelonaTuning>; ProcessorFeatures.BarcelonaTuning>;
} }
// Bobcat // Bobcat
Show All 19 Lines
def : ProcModel<"znver1", Znver1Model, ProcessorFeatures.ZNFeatures, def : ProcModel<"znver1", Znver1Model, ProcessorFeatures.ZNFeatures,
ProcessorFeatures.ZNTuning>; ProcessorFeatures.ZNTuning>;
def : ProcModel<"znver2", Znver2Model, ProcessorFeatures.ZN2Features, def : ProcModel<"znver2", Znver2Model, ProcessorFeatures.ZN2Features,
ProcessorFeatures.ZN2Tuning>; ProcessorFeatures.ZN2Tuning>;
def : ProcModel<"znver3", Znver3Model, ProcessorFeatures.ZN3Features, def : ProcModel<"znver3", Znver3Model, ProcessorFeatures.ZN3Features,
ProcessorFeatures.ZN3Tuning>; ProcessorFeatures.ZN3Tuning>;
def : Proc<"geode", [FeatureX87, FeatureCMPXCHG8B, Feature3DNowA], def : Proc<"geode", [FeatureX87, FeatureCMPXCHG8B, Feature3DNowA],
[FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
def : Proc<"winchip-c6", [FeatureX87, FeatureMMX], def : Proc<"winchip-c6", [FeatureX87, FeatureMMX],
[FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
def : Proc<"winchip2", [FeatureX87, Feature3DNow], def : Proc<"winchip2", [FeatureX87, Feature3DNow],
[FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
def : Proc<"c3", [FeatureX87, Feature3DNow], def : Proc<"c3", [FeatureX87, Feature3DNow],
[FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
def : Proc<"c3-2", [FeatureX87, FeatureCMPXCHG8B, FeatureMMX, def : Proc<"c3-2", [FeatureX87, FeatureCMPXCHG8B, FeatureMMX,
FeatureSSE1, FeatureFXSR, FeatureCMOV], FeatureSSE1, FeatureFXSR, FeatureCMOV],
[FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>; [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
// We also provide a generic 64-bit specific x86 processor model which tries to // We also provide a generic 64-bit specific x86 processor model which tries to
// be good for modern chips without enabling instruction set encodings past the // be good for modern chips without enabling instruction set encodings past the
// basic SSE2 and 64-bit ones. It disables slow things from any mainstream and // basic SSE2 and 64-bit ones. It disables slow things from any mainstream and
// modern 64-bit x86 chip, and enables features that are generally beneficial. // modern 64-bit x86 chip, and enables features that are generally beneficial.
// //
// We currently use the Sandy Bridge model as the default scheduling model as // We currently use the Sandy Bridge model as the default scheduling model as
// we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which // we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which
// covers a huge swath of x86 processors. If there are specific scheduling // covers a huge swath of x86 processors. If there are specific scheduling
// knobs which need to be tuned differently for AMD chips, we might consider // knobs which need to be tuned differently for AMD chips, we might consider
// forming a common base for them. // forming a common base for them.
def : ProcModel<"x86-64", SandyBridgeModel, ProcessorFeatures.X86_64V1Features, def : ProcModel<"x86-64", SandyBridgeModel, ProcessorFeatures.X86_64V1Features,
[ [
FeatureSlow3OpsLEA, TuningSlow3OpsLEA,
FeatureSlowDivide64, TuningSlowDivide64,
FeatureSlowIncDec, TuningSlowIncDec,
FeatureMacroFusion, TuningMacroFusion,
FeatureInsertVZEROUPPER TuningInsertVZEROUPPER
]>; ]>;
// x86-64 micro-architecture levels. // x86-64 micro-architecture levels.
def : ProcModel<"x86-64-v2", SandyBridgeModel, ProcessorFeatures.X86_64V2Features, def : ProcModel<"x86-64-v2", SandyBridgeModel, ProcessorFeatures.X86_64V2Features,
ProcessorFeatures.SNBTuning>; ProcessorFeatures.SNBTuning>;
// Close to Haswell. // Close to Haswell.
def : ProcModel<"x86-64-v3", HaswellModel, ProcessorFeatures.X86_64V3Features, def : ProcModel<"x86-64-v3", HaswellModel, ProcessorFeatures.X86_64V3Features,
ProcessorFeatures.HSWTuning>; ProcessorFeatures.HSWTuning>;
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llvm/lib/Target/X86/X86MCInstLower.cpp

Show First 20 Lines • Show All 1,088 Lines • ▼ Show 20 Linesstatic unsigned emitNop(MCStreamer &OS, unsigned NumBytes,
const X86Subtarget *Subtarget) { const X86Subtarget *Subtarget) {
// Determine the longest nop which can be efficiently decoded for the given // Determine the longest nop which can be efficiently decoded for the given
// target cpu. 15-bytes is the longest single NOP instruction, but some // target cpu. 15-bytes is the longest single NOP instruction, but some
// platforms can't decode the longest forms efficiently. // platforms can't decode the longest forms efficiently.
unsigned MaxNopLength = 1; unsigned MaxNopLength = 1;
if (Subtarget->is64Bit()) { if (Subtarget->is64Bit()) {
// FIXME: We can use NOOPL on 32-bit targets with FeatureNOPL, but the // FIXME: We can use NOOPL on 32-bit targets with FeatureNOPL, but the
// IndexReg/BaseReg below need to be updated. // IndexReg/BaseReg below need to be updated.
if (Subtarget->hasFeature(X86::FeatureFast7ByteNOP)) if (Subtarget->hasFeature(X86::TuningFast7ByteNOP))
MaxNopLength = 7; MaxNopLength = 7;
else if (Subtarget->hasFeature(X86::FeatureFast15ByteNOP)) else if (Subtarget->hasFeature(X86::TuningFast15ByteNOP))
MaxNopLength = 15; MaxNopLength = 15;
else if (Subtarget->hasFeature(X86::FeatureFast11ByteNOP)) else if (Subtarget->hasFeature(X86::TuningFast11ByteNOP))
MaxNopLength = 11; MaxNopLength = 11;
else else
MaxNopLength = 10; MaxNopLength = 10;
} if (Subtarget->is32Bit()) } if (Subtarget->is32Bit())
MaxNopLength = 2; MaxNopLength = 2;
// Cap a single nop emission at the profitable value for the target // Cap a single nop emission at the profitable value for the target
NumBytes = std::min(NumBytes, MaxNopLength); NumBytes = std::min(NumBytes, MaxNopLength);
▲ Show 20 Lines • Show All 1,522 Lines • Show Last 20 Lines

llvm/lib/Target/X86/X86TargetTransformInfo.h

Show All 39 Lines const FeatureBitset InlineFeatureIgnoreList = {
// mode. // mode.
X86::Feature64Bit, X86::Feature64Bit,
// These features don't have any intrinsics or ABI effect. // These features don't have any intrinsics or ABI effect.
X86::FeatureNOPL, X86::FeatureNOPL,
X86::FeatureCMPXCHG16B, X86::FeatureCMPXCHG16B,
X86::FeatureLAHFSAHF, X86::FeatureLAHFSAHF,
// Codegen control options. // Some older targets can be setup to fold unaligned loads.
X86::FeatureFast11ByteNOP,
X86::FeatureFast15ByteNOP,
X86::FeatureFastBEXTR,
X86::FeatureFastHorizontalOps,
X86::FeatureFastLZCNT,
X86::FeatureFastScalarFSQRT,
X86::FeatureFastSHLDRotate,
X86::FeatureFastScalarShiftMasks,
X86::FeatureFastVectorShiftMasks,
X86::FeatureFastVariableCrossLaneShuffle,
X86::FeatureFastVariablePerLaneShuffle,
X86::FeatureFastVectorFSQRT,
X86::FeatureLEAForSP,
X86::FeatureLEAUsesAG,
X86::FeatureLZCNTFalseDeps,
X86::FeatureBranchFusion,
X86::FeatureMacroFusion,
X86::FeaturePadShortFunctions,
X86::FeaturePOPCNTFalseDeps,
X86::FeatureSSEUnalignedMem, X86::FeatureSSEUnalignedMem,
X86::FeatureSlow3OpsLEA,
pengfeiUnsubmitted
Not Done
ReplyInline Actions

Nit, it looks a bit strange in the middle of all TuningXXX. Maybe better to hoist to the top or give a separate comment?

pengfei: Nit, it looks a bit strange in the middle of all TuningXXX. Maybe better to hoist to the top or…
X86::FeatureSlowDivide32, // Codegen control options.
X86::FeatureSlowDivide64, X86::TuningFast11ByteNOP,
X86::FeatureSlowIncDec, X86::TuningFast15ByteNOP,
X86::FeatureSlowLEA, X86::TuningFastBEXTR,
X86::FeatureSlowPMADDWD, X86::TuningFastHorizontalOps,
X86::FeatureSlowPMULLD, X86::TuningFastLZCNT,
X86::FeatureSlowSHLD, X86::TuningFastScalarFSQRT,
X86::FeatureSlowTwoMemOps, X86::TuningFastSHLDRotate,
X86::FeatureSlowUAMem16, X86::TuningFastScalarShiftMasks,
X86::FeaturePreferMaskRegisters, X86::TuningFastVectorShiftMasks,
X86::FeatureInsertVZEROUPPER, X86::TuningFastVariableCrossLaneShuffle,
X86::FeatureUseGLMDivSqrtCosts, X86::TuningFastVariablePerLaneShuffle,
X86::TuningFastVectorFSQRT,
X86::TuningLEAForSP,
X86::TuningLEAUsesAG,
X86::TuningLZCNTFalseDeps,
X86::TuningBranchFusion,
X86::TuningMacroFusion,
X86::TuningPadShortFunctions,
X86::TuningPOPCNTFalseDeps,
X86::TuningSlow3OpsLEA,
X86::TuningSlowDivide32,
X86::TuningSlowDivide64,
X86::TuningSlowIncDec,
X86::TuningSlowLEA,
X86::TuningSlowPMADDWD,
X86::TuningSlowPMULLD,
X86::TuningSlowSHLD,
X86::TuningSlowTwoMemOps,
X86::TuningSlowUAMem16,
X86::TuningPreferMaskRegisters,
X86::TuningInsertVZEROUPPER,
X86::TuningUseGLMDivSqrtCosts,
// Perf-tuning flags. // Perf-tuning flags.
X86::FeatureFastGather, X86::TuningFastGather,
X86::FeatureSlowUAMem32, X86::TuningSlowUAMem32,
// Based on whether user set the -mprefer-vector-width command line. // Based on whether user set the -mprefer-vector-width command line.
X86::FeaturePrefer128Bit, X86::TuningPrefer128Bit,
X86::FeaturePrefer256Bit, X86::TuningPrefer256Bit,
// CPU name enums. These just follow CPU string. // CPU name enums. These just follow CPU string.
X86::ProcIntelAtom, X86::ProcIntelAtom,
X86::ProcIntelSLM, X86::ProcIntelSLM,
}; };
public: public:
explicit X86TTIImpl(const X86TargetMachine *TM, const Function &F) explicit X86TTIImpl(const X86TargetMachine *TM, const Function &F)
▲ Show 20 Lines • Show All 165 Lines • Show Last 20 Lines