[llvm-mca] Store extra information about the driver flags used for the simulation

[markoshorro]

Summary

Added information stored in PipelineOptions and the MCSubtargetInfo.

Should this information be also printed in the "classic" report? This would require updating almost all tests.

[andreadb]

llvm/test/tools/llvm-mca/JSON/X86/views.s

163–174

I think that we should just ignore flags like -dispatch, -squeue, -lqueue, etc. if their value hasn't been changed by the user. I suggest to only report flags whose value doesn't correspond to their default.

The only exceptions would be mcpu/march/mtriple which (at least in my opinion) should always be present for completeness.

[markoshorro]

llvm/test/tools/llvm-mca/JSON/X86/views.s

163–174

Ok, I agree! Do you think this information should be printed as well in the classic report?

[andreadb]

llvm/test/tools/llvm-mca/JSON/X86/views.s

163–174

I think it should only be printed for the json output.

[markoshorro]

Added new test for output with custom parameters. Only printing parameters if values are not default.

[andreadb]

A couple of minor nits. Otherwise it LGTM.

llvm/tools/llvm-mca/PipelinePrinter.cpp

55–56

Please move this early exit before the check at line 52. We don't care about printing the register-file-size if this is an in-order processor (as we don't simulate register renaming).

Also, add an empty line after it to make the code slightly more readable.

[markoshorro]

Minor edits for readability and avoiding unnecessary information when inorder simulation

llvm/test/tools/llvm-mca/JSON/X86/instruction-tables-multiple-anonymous-regions.s

 # CHECK-NEXT:             "InstructionIndex": 1,
 # CHECK-NEXT:             "ResourceIndex": 8,
 # CHECK-NEXT:             "ResourceUsage": 0.25
 # CHECK-NEXT:           }
 # CHECK-NEXT:         ]
 # CHECK-NEXT:       }
 # CHECK-NEXT:     }
 # CHECK-NEXT:   ],
+# CHECK-NEXT:   "SimulationParameters": {
+# CHECK-NEXT:     "-decoder-throughput": 0,
+# CHECK-NEXT:     "-dispatch": 0,
+# CHECK-NEXT:     "-lqueue": 0,
+# CHECK-NEXT:     "-march": "x86_64",
+# CHECK-NEXT:     "-mcpu": "haswell",
+# CHECK-NEXT:     "-micro-op-queue-size": 0,
+# CHECK-NEXT:     "-mtriple": "x86_64-unknown-unknown",
+# CHECK-NEXT:     "-noalias": true,
+# CHECK-NEXT:     "-register-file-size": 0,
+# CHECK-NEXT:     "-squeue": 0
+# CHECK-NEXT:   },
 # CHECK-NEXT:   "TargetInfo": {
 # CHECK-NEXT:     "CPUName": "haswell",
 # CHECK-NEXT:     "Resources": [
 # CHECK-NEXT:       "HWDivider",
 # CHECK-NEXT:       "HWFPDivider",
 # CHECK-NEXT:       "HWPort0",
 # CHECK-NEXT:       "HWPort1",
 # CHECK-NEXT:       "HWPort2",
 # CHECK-NEXT:       "HWPort3",
 # CHECK-NEXT:       "HWPort4",
 # CHECK-NEXT:       "HWPort5",
 # CHECK-NEXT:       "HWPort6",
 # CHECK-NEXT:       "HWPort7"
 # CHECK-NEXT:     ]
 # CHECK-NEXT:   }
 # CHECK-NEXT: }

llvm/test/tools/llvm-mca/JSON/X86/instruction-tables-multiple-regions.s

 # CHECK-NEXT:             "InstructionIndex": 2,
 # CHECK-NEXT:             "ResourceIndex": 8,
 # CHECK-NEXT:             "ResourceUsage": 0.5
 # CHECK-NEXT:           }
 # CHECK-NEXT:         ]
 # CHECK-NEXT:       }
 # CHECK-NEXT:     }
 # CHECK-NEXT:   ],
+# CHECK-NEXT:   "SimulationParameters": {
+# CHECK-NEXT:     "-decoder-throughput": 0,
+# CHECK-NEXT:     "-dispatch": 0,
+# CHECK-NEXT:     "-lqueue": 0,
+# CHECK-NEXT:     "-march": "x86_64",
+# CHECK-NEXT:     "-mcpu": "haswell",
+# CHECK-NEXT:     "-micro-op-queue-size": 0,
+# CHECK-NEXT:     "-mtriple": "x86_64-unknown-unknown",
+# CHECK-NEXT:     "-noalias": true,
+# CHECK-NEXT:     "-register-file-size": 0,
+# CHECK-NEXT:     "-squeue": 0
+# CHECK-NEXT:   },
 # CHECK-NEXT:   "TargetInfo": {
 # CHECK-NEXT:     "CPUName": "haswell",
 # CHECK-NEXT:     "Resources": [
 # CHECK-NEXT:       "HWDivider",
 # CHECK-NEXT:       "HWFPDivider",
 # CHECK-NEXT:       "HWPort0",
 # CHECK-NEXT:       "HWPort1",
 # CHECK-NEXT:       "HWPort2",
 # CHECK-NEXT:       "HWPort3",
 # CHECK-NEXT:       "HWPort4",
 # CHECK-NEXT:       "HWPort5",
 # CHECK-NEXT:       "HWPort6",
 # CHECK-NEXT:       "HWPort7"
 # CHECK-NEXT:     ]
 # CHECK-NEXT:   }
 # CHECK-NEXT: }

llvm/test/tools/llvm-mca/JSON/X86/views-multiple-anonymous-regions.s

 # CHECK-NEXT:             "CycleIssued": 10,
 # CHECK-NEXT:             "CycleReady": 10,
 # CHECK-NEXT:             "CycleRetired": 12
 # CHECK-NEXT:           }
 # CHECK-NEXT:         ]
 # CHECK-NEXT:       }
 # CHECK-NEXT:     }
 # CHECK-NEXT:   ],
+# CHECK-NEXT:   "SimulationParameters": {
+# CHECK-NEXT:     "-decoder-throughput": 0,
+# CHECK-NEXT:     "-dispatch": 0,
+# CHECK-NEXT:     "-lqueue": 0,
+# CHECK-NEXT:     "-march": "x86_64",
+# CHECK-NEXT:     "-mcpu": "haswell",
+# CHECK-NEXT:     "-micro-op-queue-size": 0,
+# CHECK-NEXT:     "-mtriple": "x86_64-unknown-unknown",
+# CHECK-NEXT:     "-noalias": true,
+# CHECK-NEXT:     "-register-file-size": 0,
+# CHECK-NEXT:     "-squeue": 0
+# CHECK-NEXT:   },
 # CHECK-NEXT:   "TargetInfo": {
 # CHECK-NEXT:     "CPUName": "haswell",
 # CHECK-NEXT:     "Resources": [
 # CHECK-NEXT:       "HWDivider",
 # CHECK-NEXT:       "HWFPDivider",
 # CHECK-NEXT:       "HWPort0",
 # CHECK-NEXT:       "HWPort1",
 # CHECK-NEXT:       "HWPort2",
 # CHECK-NEXT:       "HWPort3",
 # CHECK-NEXT:       "HWPort4",
 # CHECK-NEXT:       "HWPort5",
 # CHECK-NEXT:       "HWPort6",
 # CHECK-NEXT:       "HWPort7"
 # CHECK-NEXT:     ]
 # CHECK-NEXT:   }
 # CHECK-NEXT: }

llvm/test/tools/llvm-mca/JSON/X86/views-multiple-region.s

 # CHECK-NEXT:             "CycleIssued": 1,
 # CHECK-NEXT:             "CycleReady": 0,
 # CHECK-NEXT:             "CycleRetired": 3
 # CHECK-NEXT:           }
 # CHECK-NEXT:         ]
 # CHECK-NEXT:       }
 # CHECK-NEXT:     }
 # CHECK-NEXT:   ],
+# CHECK-NEXT:   "SimulationParameters": {
+# CHECK-NEXT:     "-decoder-throughput": 0,
+# CHECK-NEXT:     "-dispatch": 0,
+# CHECK-NEXT:     "-lqueue": 0,
+# CHECK-NEXT:     "-march": "x86_64",
+# CHECK-NEXT:     "-mcpu": "haswell",
+# CHECK-NEXT:     "-micro-op-queue-size": 0,
+# CHECK-NEXT:     "-mtriple": "x86_64-unknown-unknown",
+# CHECK-NEXT:     "-noalias": true,
+# CHECK-NEXT:     "-register-file-size": 0,
+# CHECK-NEXT:     "-squeue": 0
+# CHECK-NEXT:   },
 # CHECK-NEXT:   "TargetInfo": {
 # CHECK-NEXT:     "CPUName": "haswell",
 # CHECK-NEXT:     "Resources": [
 # CHECK-NEXT:       "HWDivider",
 # CHECK-NEXT:       "HWFPDivider",
 # CHECK-NEXT:       "HWPort0",
 # CHECK-NEXT:       "HWPort1",
 # CHECK-NEXT:       "HWPort2",
 # CHECK-NEXT:       "HWPort3",
 # CHECK-NEXT:       "HWPort4",
 # CHECK-NEXT:       "HWPort5",
 # CHECK-NEXT:       "HWPort6",
 # CHECK-NEXT:       "HWPort7"
 # CHECK-NEXT:     ]
 # CHECK-NEXT:   }
 # CHECK-NEXT: }

llvm/test/tools/llvm-mca/JSON/X86/views.s

 # CHECK-NEXT:             "CycleIssued": 1,
 # CHECK-NEXT:             "CycleReady": 0,
 # CHECK-NEXT:             "CycleRetired": 3
 # CHECK-NEXT:           }
 # CHECK-NEXT:         ]
 # CHECK-NEXT:       }
 # CHECK-NEXT:     }
 # CHECK-NEXT:   ],
+# CHECK-NEXT:   "SimulationParameters": {
+# CHECK-NEXT:     "-decoder-throughput": 0,
+# CHECK-NEXT:     "-dispatch": 0,
+# CHECK-NEXT:     "-lqueue": 0,
+# CHECK-NEXT:     "-march": "x86_64",
+# CHECK-NEXT:     "-mcpu": "haswell",
+# CHECK-NEXT:     "-micro-op-queue-size": 0,
+# CHECK-NEXT:     "-mtriple": "x86_64-unknown-unknown",
+# CHECK-NEXT:     "-noalias": true,
+# CHECK-NEXT:     "-register-file-size": 0,
+# CHECK-NEXT:     "-squeue": 0
+# CHECK-NEXT:   },
 # CHECK-NEXT:   "TargetInfo": {
 # CHECK-NEXT:     "CPUName": "haswell",
 # CHECK-NEXT:     "Resources": [
 # CHECK-NEXT:       "HWDivider",
 # CHECK-NEXT:       "HWFPDivider",
 # CHECK-NEXT:       "HWPort0",
 # CHECK-NEXT:       "HWPort1",
 # CHECK-NEXT:       "HWPort2",
 # CHECK-NEXT:       "HWPort3",
 # CHECK-NEXT:       "HWPort4",
 # CHECK-NEXT:       "HWPort5",
 # CHECK-NEXT:       "HWPort6",
 # CHECK-NEXT:       "HWPort7"
 # CHECK-NEXT:     ]
 # CHECK-NEXT:   }
 # CHECK-NEXT: }

llvm/tools/llvm-mca/PipelinePrinter.h

 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_TOOLS_LLVM_MCA_PIPELINEPRINTER_H
 #define LLVM_TOOLS_LLVM_MCA_PIPELINEPRINTER_H
 
 #include "Views/View.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/MCA/Context.h"
 #include "llvm/MCA/Pipeline.h"
 #include "llvm/Support/raw_ostream.h"
 
 #define DEBUG_TYPE "llvm-mca"
 
 namespace llvm {
 namespace mca {
 
 class CodeRegion;
 
 /// A printer class that knows how to collects statistics on the
 /// code analyzed by the llvm-mca tool.
 ///
 /// This class knows how to print out the analysis information collected
 /// during the execution of the code. Internally, it delegates to other
 /// classes the task of printing out timeline information as well as
 /// resource pressure.
 class PipelinePrinter {
   Pipeline &P;
   const CodeRegion &Region;
   unsigned RegionIdx;
   const MCSubtargetInfo &STI;
+  const PipelineOptions &PO;
   llvm::SmallVector<std::unique_ptr<View>, 8> Views;
 
   void printRegionHeader(llvm::raw_ostream &OS) const;
   json::Object getJSONReportRegion() const;
   json::Object getJSONTargetInfo() const;
+  json::Object getJSONSimulationParameters() const;
 
 public:
   PipelinePrinter(Pipeline &Pipe, const CodeRegion &R, unsigned Idx,
-                  const MCSubtargetInfo &STI)
-      : P(Pipe), Region(R), RegionIdx(Idx), STI(STI), Views() {}
+                  const MCSubtargetInfo &STI, const PipelineOptions &PO)
+      : P(Pipe), Region(R), RegionIdx(Idx), STI(STI), PO(PO), Views() {}
 
   void addView(std::unique_ptr<View> V) {
     P.addEventListener(V.get());
     Views.emplace_back(std::move(V));
   }
 
   void printReport(llvm::raw_ostream &OS) const;
   void printReport(json::Object &JO) const;
 };
 } // namespace mca
 } // namespace llvm
 
 #endif // LLVM_TOOLS_LLVM_MCA_PIPELINEPRINTER_H

llvm/tools/llvm-mca/PipelinePrinter.cpp

json::Object PipelinePrinter::getJSONReportRegion() const {
   JO.try_emplace("Name", RegionName);
   for (const auto &V : Views)
     if (V->isSerializable())
       JO.try_emplace(V->getNameAsString().str(), V->toJSON());
 
   return JO;
 }
 
+json::Object PipelinePrinter::getJSONSimulationParameters() const {
+  json::Object SimParameters({{"-mcpu", STI.getCPU()},
+                              {"-mtriple", STI.getTargetTriple().getTriple()},
+                              {"-march", STI.getTargetTriple().getArchName()},
+                              {"-register-file-size", PO.RegisterFileSize}});
+  const MCSchedModel &SM = STI.getSchedModel();
+  if (!SM.isOutOfOrder())
+    return SimParameters;
+  SimParameters.try_emplace("-noalias", PO.AssumeNoAlias);
+  SimParameters.try_emplace("-decoder-throughput", PO.DecodersThroughput);
+  SimParameters.try_emplace("-micro-op-queue-size", PO.MicroOpQueueSize);
+  SimParameters.try_emplace("-dispatch", PO.DispatchWidth);
+  SimParameters.try_emplace("-lqueue", PO.LoadQueueSize);
+  SimParameters.try_emplace("-squeue", PO.StoreQueueSize);
+
+  return SimParameters;
+}
+
 json::Object PipelinePrinter::getJSONTargetInfo() const {
   json::Array Resources;
   const MCSchedModel &SM = STI.getSchedModel();
   StringRef MCPU = STI.getCPU();
 
   for (unsigned I = 1, E = SM.getNumProcResourceKinds(); I < E; ++I) {
     const MCProcResourceDesc &ProcResource = *SM.getProcResource(I);
     unsigned NumUnits = ProcResource.NumUnits;
for (unsigned J = 0; J < NumUnits; ++J) {
       Resources.push_back(ResourceName);
     }
   }
 
   return json::Object({{"CPUName", MCPU}, {"Resources", std::move(Resources)}});
 }
 
 void PipelinePrinter::printReport(json::Object &JO) const {
-  if (!RegionIdx)
-    JO.try_emplace("TargetInfo", getJSONTargetInfo());
-
   if (!RegionIdx) {
+    JO.try_emplace("TargetInfo", getJSONTargetInfo());
+    JO.try_emplace("SimulationParameters", getJSONSimulationParameters());
     // Construct an array of regions.
     JO.try_emplace("CodeRegions", json::Array());
   }
 
   json::Array *Regions = JO.getArray("CodeRegions");
   assert(Regions && "This array must exist!");
   Regions->push_back(getJSONReportRegion());
 }

llvm/tools/llvm-mca/llvm-mca.cpp

for (const std::unique_ptr<mca::CodeRegion> &Region : Regions) {
     mca::SourceMgr S(LoweredSequence, PrintInstructionTables ? 1 : Iterations);
 
     if (PrintInstructionTables) {
       //  Create a pipeline, stages, and a printer.
       auto P = std::make_unique<mca::Pipeline>();
       P->appendStage(std::make_unique<mca::EntryStage>(S));
       P->appendStage(std::make_unique<mca::InstructionTables>(SM));
 
-      mca::PipelinePrinter Printer(*P, *Region, RegionIdx, *STI);
+      mca::PipelinePrinter Printer(*P, *Region, RegionIdx, *STI, PO);
       if (PrintJson) {
         Printer.addView(
             std::make_unique<mca::InstructionView>(*STI, *IP, Insts));
       }
 
       // Create the views for this pipeline, execute, and emit a report.
       if (PrintInstructionInfoView) {
         Printer.addView(std::make_unique<mca::InstructionInfoView>(
for (const std::unique_ptr<mca::CodeRegion> &Region : Regions) {
     // mca::Instruction or any objects that can be reconstructed
     // from the target information).
     std::unique_ptr<mca::CustomBehaviour> CB =
         createCustomBehaviour(TheTriple, *STI, S, *MCII);
 
     // Create a basic pipeline simulating an out-of-order backend.
     auto P = MCA.createDefaultPipeline(PO, S, *CB);
 
-    mca::PipelinePrinter Printer(*P, *Region, RegionIdx, *STI);
+    mca::PipelinePrinter Printer(*P, *Region, RegionIdx, *STI, PO);
 
     // When we output JSON, we add a view that contains the instructions
     // and CPU resource information.
     if (PrintJson) {
       auto IV = std::make_unique<mca::InstructionView>(*STI, *IP, Insts);
       Printer.addView(std::move(IV));
     }