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Differential D104952

[hexagon] Add {hvx,}hexagon_{protos,circ_brev...}
AcceptedPublic

Authored by bcain on Jun 25 2021, 2:15 PM.

Details

Reviewers
kparzysz
Summary

Add definitions for Hexagon, Hexagon circular/bit-reverse and HVX
intrinsics.

Diff Detail

Event Timeline

bcain created this revision.Jun 25 2021, 2:15 PM
Herald added a subscriber: mgorny. · View Herald TranscriptJun 25 2021, 2:15 PM
bcain requested review of this revision.Jun 25 2021, 2:15 PM
Herald added a project: Restricted Project. · View Herald TranscriptJun 25 2021, 2:15 PM
Herald added a subscriber: cfe-commits. · View Herald Transcript
Harbormaster completed remote builds in B111073: Diff 354603.Jun 25 2021, 2:52 PM
bcain added a comment.Jun 25 2021, 3:41 PM

It occurs to me now that some of these are not very useful in the absence of hexagon_types.h. So I will add that one too and change the tests to use those definitions instead.

bcain updated this revision to Diff 354758.Jun 27 2021, 10:21 AM

Add hexagon_types.h and additional test cases. Updated existing test case to use types defined in hexagon_types.h.

Harbormaster completed remote builds in B111193: Diff 354758.Jun 27 2021, 11:07 AM
bcain added a comment.Jun 27 2021, 10:20 PM

Should I clang format the headers? I prefer keeping the historical formatting intact. But if the submission should conform then I suppose I'll just accept the wrapped text suggested by clang-format.

bcain updated this revision to Diff 355234.Jun 29 2021, 7:39 AM

Removed some unavailable instructions.

Added include order fix in hexagon_circ_brev

kparzysz accepted this revision.Jun 29 2021, 7:53 AM
This revision is now accepted and ready to land.Jun 29 2021, 7:53 AM
Harbormaster completed remote builds in B111528: Diff 355234.Jun 29 2021, 8:27 AM

Revision Contents

PathSize
clang/
lib/
Headers/
4 lines
298 lines
8450 lines
2653 lines
4392 lines
test/
Headers/
37 lines
28 lines
37 lines

Diff 355234

clang/lib/Headers/CMakeLists.txt

Show First 20 Lines • Show All 60 Lines • ▼ Show 20 Linesset(files
emmintrin.h emmintrin.h
enqcmdintrin.h enqcmdintrin.h
f16cintrin.h f16cintrin.h
float.h float.h
fma4intrin.h fma4intrin.h
fmaintrin.h fmaintrin.h
fxsrintrin.h fxsrintrin.h
gfniintrin.h gfniintrin.h
hexagon_circ_brev_intrinsics.h
hexagon_protos.h
hexagon_types.h
hvx_hexagon_protos.h
hresetintrin.h hresetintrin.h
htmintrin.h htmintrin.h
htmxlintrin.h htmxlintrin.h
ia32intrin.h ia32intrin.h
immintrin.h immintrin.h
intrin.h intrin.h
inttypes.h inttypes.h
invpcidintrin.h invpcidintrin.h
▲ Show 20 Lines • Show All 170 Lines • Show Last 20 Lines

clang/lib/Headers/hexagon_circ_brev_intrinsics.h

  • This file was added.
//===----------------------------------------------------------------------===//
Lint: Pre-merge checks
Inline Actions

clang-tidy: warning: header is missing header guard [llvm-header-guard]
not useful

Lint: Pre-merge checks: clang-tidy: warning: header is missing header guard [llvm-header-guard] [[https://github.
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
#ifndef _HEXAGON_CIRC_BREV_INTRINSICS_H_
#define _HEXAGON_CIRC_BREV_INTRINSICS_H_ 1
#include <hexagon_protos.h>
Lint: Pre-merge checks
Inline Actions

clang-tidy: error: 'hexagon_protos.h' file not found with <angled> include; use "quotes" instead [clang-diagnostic-error]
not useful
clang-tidy: error: 'hexagon_protos.h' file not found with <angled> include; use "quotes" instead [clang-diagnostic-error]
not useful
clang-tidy: error: 'hexagon_protos.h' file not found with <angled> include; use "quotes" instead [clang-diagnostic-error]
not useful

Lint: Pre-merge checks: clang-tidy: error: 'hexagon_protos.h' file not found with <angled> include; use "quotes"…
#include <stdint.h>
/* Circular Load */
/* ==========================================================================
Assembly Syntax: Return=instruction()
C Intrinsic Prototype: void Q6_circ_load_update_D(Word64 dst, Word64 *ptr, UWord32 incr, UWord32 bufsize, UWord32 K)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: void Q6_circ_load_update_D(Word64 dst, Word64 *ptr, UWord32 incr, UWord32 bufsize, UWord32 K)
-   Instruction Type:      InstructionType
+   C Intrinsic Prototype: void Q6_circ_load_update_D(Word64 dst, Word64 *ptr,
+   UWord32 incr, UWord32 bufsize, UWord32 K) Instruction Type: InstructionType
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: void…
Instruction Type: InstructionType
Execution Slots: SLOT0123
========================================================================== */
#define Q6_circ_load_update_D(dest,ptr,incr,bufsize,K) \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_circ_load_update_D(dest,ptr,incr,bufsize,K)  \
-    { ptr = (int64_t *) HEXAGON_circ_ldd (ptr, &(dest), ((((K)+1)<<24)|((bufsize)<<3)), ((incr)*8)); }
+#define Q6_circ_load_update_D(dest, ptr, incr, bufsize, K)                     \
+  {                                                                            \
+    ptr = (int64_t *)HEXAGON_circ_ldd(                                         \
+        ptr, &(dest), ((((K) + 1) << 24) | ((bufsize) << 3)), ((incr)*8));     \
+  }
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_circ_load_update_D(dest,ptr,incr,bufsize…
{ ptr = (int64_t *) HEXAGON_circ_ldd (ptr, &(dest), ((((K)+1)<<24)|((bufsize)<<3)), ((incr)*8)); }
/* ==========================================================================
Assembly Syntax: Return=instruction()
C Intrinsic Prototype: void Q6_circ_load_update_W(Word32 dst, Word32 *ptr, UWord32 incr, UWord32 bufsize, UWord32 K)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: void Q6_circ_load_update_W(Word32 dst, Word32 *ptr, UWord32 incr, UWord32 bufsize, UWord32 K)
-   Instruction Type:      InstructionType
+   C Intrinsic Prototype: void Q6_circ_load_update_W(Word32 dst, Word32 *ptr,
+   UWord32 incr, UWord32 bufsize, UWord32 K) Instruction Type: InstructionType
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: void…
Instruction Type: InstructionType
Execution Slots: SLOT0123
========================================================================== */
#define Q6_circ_load_update_W(dest,ptr,incr,bufsize,K) \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_circ_load_update_W(dest,ptr,incr,bufsize,K)  \
-    { ptr = (int *) HEXAGON_circ_ldw (ptr, &(dest), (((K)<<24)|((bufsize)<<2)), ((incr)*4)); }
+#define Q6_circ_load_update_W(dest, ptr, incr, bufsize, K)                     \
+  {                                                                            \
+    ptr = (int *)HEXAGON_circ_ldw(                                             \
+        ptr, &(dest), (((K) << 24) | ((bufsize) << 2)), ((incr)*4));           \
+  }
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_circ_load_update_W(dest,ptr,incr,bufsize…
{ ptr = (int *) HEXAGON_circ_ldw (ptr, &(dest), (((K)<<24)|((bufsize)<<2)), ((incr)*4)); }
/* ==========================================================================
Assembly Syntax: Return=instruction()
C Intrinsic Prototype: void Q6_circ_load_update_H(Word16 dst, Word16 *ptr, UWord32 incr, UWord32 bufsize, UWord32 K)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: void Q6_circ_load_update_H(Word16 dst, Word16 *ptr, UWord32 incr, UWord32 bufsize, UWord32 K)
-   Instruction Type:      InstructionType
+   C Intrinsic Prototype: void Q6_circ_load_update_H(Word16 dst, Word16 *ptr,
+   UWord32 incr, UWord32 bufsize, UWord32 K) Instruction Type: InstructionType
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: void…
Instruction Type: InstructionType
Execution Slots: SLOT0123
========================================================================== */
#define Q6_circ_load_update_H(dest,ptr,incr,bufsize,K) \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_circ_load_update_H(dest,ptr,incr,bufsize,K)  \
-    { ptr = (int16_t *) HEXAGON_circ_ldh (ptr, &(dest), ((((K)-1)<<24)|((bufsize)<<1)), ((incr)*2)); }
+#define Q6_circ_load_update_H(dest, ptr, incr, bufsize, K)                     \
+  {                                                                            \
+    ptr = (int16_t *)HEXAGON_circ_ldh(                                         \
+        ptr, &(dest), ((((K)-1) << 24) | ((bufsize) << 1)), ((incr)*2));       \
+  }
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_circ_load_update_H(dest,ptr,incr,bufsize…
{ ptr = (int16_t *) HEXAGON_circ_ldh (ptr, &(dest), ((((K)-1)<<24)|((bufsize)<<1)), ((incr)*2)); }
/* ==========================================================================
Assembly Syntax: Return=instruction()
C Intrinsic Prototype: void Q6_circ_load_update_UH( UWord16 dst, UWord16 *ptr, UWord32 incr, UWord32 bufsize, UWord32 K)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: void Q6_circ_load_update_UH( UWord16 dst,  UWord16 *ptr, UWord32 incr, UWord32 bufsize, UWord32 K)
-   Instruction Type:      InstructionType
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: void Q6_circ_load_update_UH( UWord16 dst,  UWord16
+   *ptr, UWord32 incr, UWord32 bufsize, UWord32 K) Instruction Type:
+   InstructionType Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: void…
Instruction Type: InstructionType
Execution Slots: SLOT0123
========================================================================== */
#define Q6_circ_load_update_UH(dest,ptr,incr,bufsize,K) \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_circ_load_update_UH(dest,ptr,incr,bufsize,K) \
-    { ptr = (uint16_t *) HEXAGON_circ_lduh (ptr, &(dest), ((((K)-1)<<24)|((bufsize)<<1)), ((incr)*2)); }
+#define Q6_circ_load_update_UH(dest, ptr, incr, bufsize, K)                    \
+  {                                                                            \
+    ptr = (uint16_t *)HEXAGON_circ_lduh(                                       \
+        ptr, &(dest), ((((K)-1) << 24) | ((bufsize) << 1)), ((incr)*2));       \
+  }
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_circ_load_update_UH(dest,ptr,incr…
{ ptr = (uint16_t *) HEXAGON_circ_lduh (ptr, &(dest), ((((K)-1)<<24)|((bufsize)<<1)), ((incr)*2)); }
/* ==========================================================================
Assembly Syntax: Return=instruction()
C Intrinsic Prototype: void Q6_circ_load_update_B(Word8 dst, Word8 *ptr, UWord32 incr, UWord32 bufsize, UWord32 K)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: void Q6_circ_load_update_B(Word8 dst, Word8 *ptr, UWord32 incr, UWord32 bufsize, UWord32 K)
-   Instruction Type:      InstructionType
+   C Intrinsic Prototype: void Q6_circ_load_update_B(Word8 dst, Word8 *ptr,
+   UWord32 incr, UWord32 bufsize, UWord32 K) Instruction Type: InstructionType
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: void…
Instruction Type: InstructionType
Execution Slots: SLOT0123
========================================================================== */
#define Q6_circ_load_update_B(dest,ptr,incr,bufsize,K) \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_circ_load_update_B(dest,ptr,incr,bufsize,K)  \
-    { ptr = (int8_t *) HEXAGON_circ_ldb (ptr, &(dest), ((((K)-2)<<24)|(bufsize)), incr); }
+#define Q6_circ_load_update_B(dest, ptr, incr, bufsize, K)                     \
+  {                                                                            \
+    ptr = (int8_t *)HEXAGON_circ_ldb(ptr, &(dest),                             \
+                                     ((((K)-2) << 24) | (bufsize)), incr);     \
+  }
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_circ_load_update_B(dest,ptr,incr,bufsize…
{ ptr = (int8_t *) HEXAGON_circ_ldb (ptr, &(dest), ((((K)-2)<<24)|(bufsize)), incr); }
/* ==========================================================================
Assembly Syntax: Return=instruction()
C Intrinsic Prototype: void Q6_circ_load_update_UB(UWord8 dst, UWord8 *ptr, UWord32 incr, UWord32 bufsize, UWord32 K)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: void  Q6_circ_load_update_UB(UWord8 dst, UWord8 *ptr, UWord32 incr, UWord32 bufsize, UWord32 K)
-   Instruction Type:      InstructionType
+   C Intrinsic Prototype: void  Q6_circ_load_update_UB(UWord8 dst, UWord8 *ptr,
+   UWord32 incr, UWord32 bufsize, UWord32 K) Instruction Type: InstructionType
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: void…
Instruction Type: InstructionType
Execution Slots: SLOT0123
========================================================================== */
#define Q6_circ_load_update_UB(dest,ptr,incr,bufsize,K) \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_circ_load_update_UB(dest,ptr,incr,bufsize,K) \
-    { ptr = (uint8_t *) HEXAGON_circ_ldub (ptr, &(dest), ((((K)-2)<<24)|(bufsize)), incr); }
+#define Q6_circ_load_update_UB(dest, ptr, incr, bufsize, K)                    \
+  {                                                                            \
+    ptr = (uint8_t *)HEXAGON_circ_ldub(ptr, &(dest),                           \
+                                       ((((K)-2) << 24) | (bufsize)), incr);   \
+  }
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_circ_load_update_UB(dest,ptr,incr…
{ ptr = (uint8_t *) HEXAGON_circ_ldub (ptr, &(dest), ((((K)-2)<<24)|(bufsize)), incr); }
/* Circular Store */
/* ==========================================================================
Assembly Syntax: Return=instruction()
C Intrinsic Prototype: void Q6_circ_store_update_D(Word64 *src, Word64 *ptr, UWord32 incr, UWord32 bufsize, UWord32 K)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: void Q6_circ_store_update_D(Word64 *src, Word64 *ptr, UWord32 incr, UWord32 bufsize, UWord32 K)
-   Instruction Type:      InstructionType
+   C Intrinsic Prototype: void Q6_circ_store_update_D(Word64 *src, Word64 *ptr,
+   UWord32 incr, UWord32 bufsize, UWord32 K) Instruction Type: InstructionType
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: void…
Instruction Type: InstructionType
Execution Slots: SLOT0123
========================================================================== */
#define Q6_circ_store_update_D(src,ptr,incr,bufsize,K) \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_circ_store_update_D(src,ptr,incr,bufsize,K)  \
-    { ptr = (int64_t *) HEXAGON_circ_std (ptr, src, ((((K)+1)<<24)|((bufsize)<<3)), ((incr)*8)); }
+#define Q6_circ_store_update_D(src, ptr, incr, bufsize, K)                     \
+  {                                                                            \
+    ptr = (int64_t *)HEXAGON_circ_std(                                         \
+        ptr, src, ((((K) + 1) << 24) | ((bufsize) << 3)), ((incr)*8));         \
+  }
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_circ_store_update_D(src,ptr,incr,bufsize…
{ ptr = (int64_t *) HEXAGON_circ_std (ptr, src, ((((K)+1)<<24)|((bufsize)<<3)), ((incr)*8)); }
/* ==========================================================================
Assembly Syntax: Return=instruction()
C Intrinsic Prototype: void Q6_circ_store_update_W(Word32 *src, Word32 *ptr, UWord32 incr, UWord32 bufsize, UWord32 K)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: void Q6_circ_store_update_W(Word32 *src, Word32 *ptr, UWord32 incr, UWord32 bufsize, UWord32 K)
-   Instruction Type:      InstructionType
+   C Intrinsic Prototype: void Q6_circ_store_update_W(Word32 *src, Word32 *ptr,
+   UWord32 incr, UWord32 bufsize, UWord32 K) Instruction Type: InstructionType
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: void…
Instruction Type: InstructionType
Execution Slots: SLOT0123
========================================================================== */
#define Q6_circ_store_update_W(src,ptr,incr,bufsize,K) \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_circ_store_update_W(src,ptr,incr,bufsize,K)  \
-    { ptr = (int *) HEXAGON_circ_stw (ptr, src, (((K)<<24)|((bufsize)<<2)), ((incr)*4)); }
+#define Q6_circ_store_update_W(src, ptr, incr, bufsize, K)                     \
+  {                                                                            \
+    ptr = (int *)HEXAGON_circ_stw(ptr, src, (((K) << 24) | ((bufsize) << 2)),  \
+                                  ((incr)*4));                                 \
+  }
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_circ_store_update_W(src,ptr,incr,bufsize…
{ ptr = (int *) HEXAGON_circ_stw (ptr, src, (((K)<<24)|((bufsize)<<2)), ((incr)*4)); }
/* ==========================================================================
Assembly Syntax: Return=instruction()
C Intrinsic Prototype: void Q6_circ_store_update_HL(Word16 *src, Word16 *ptr, UWord32 incr, UWord32 bufsize, UWord32 K)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: void Q6_circ_store_update_HL(Word16 *src, Word16 *ptr, UWord32 incr, UWord32 bufsize, UWord32 K)
-   Instruction Type:      InstructionType
+   C Intrinsic Prototype: void Q6_circ_store_update_HL(Word16 *src, Word16 *ptr,
+   UWord32 incr, UWord32 bufsize, UWord32 K) Instruction Type: InstructionType
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: void…
Instruction Type: InstructionType
Execution Slots: SLOT0123
========================================================================== */
#define Q6_circ_store_update_HL(src,ptr,incr,bufsize,K) \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_circ_store_update_HL(src,ptr,incr,bufsize,K) \
-    { ptr = (int16_t *) HEXAGON_circ_sth (ptr, src, ((((K)-1)<<24)|((bufsize)<<1)), ((incr)*2)); }
+#define Q6_circ_store_update_HL(src, ptr, incr, bufsize, K)                    \
+  {                                                                            \
+    ptr = (int16_t *)HEXAGON_circ_sth(                                         \
+        ptr, src, ((((K)-1) << 24) | ((bufsize) << 1)), ((incr)*2));           \
+  }
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_circ_store_update_HL(src,ptr,incr…
{ ptr = (int16_t *) HEXAGON_circ_sth (ptr, src, ((((K)-1)<<24)|((bufsize)<<1)), ((incr)*2)); }
/* ==========================================================================
Assembly Syntax: Return=instruction()
C Intrinsic Prototype: void Q6_circ_store_update_HH(Word16 *src, Word16 *ptr, UWord32 incr, UWord32 bufsize, UWord32 K)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: void Q6_circ_store_update_HH(Word16 *src, Word16 *ptr, UWord32 incr, UWord32 bufsize, UWord32 K)
-   Instruction Type:      InstructionType
+   C Intrinsic Prototype: void Q6_circ_store_update_HH(Word16 *src, Word16 *ptr,
+   UWord32 incr, UWord32 bufsize, UWord32 K) Instruction Type: InstructionType
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: void…
Instruction Type: InstructionType
Execution Slots: SLOT0123
========================================================================== */
#define Q6_circ_store_update_HH(src,ptr,incr,bufsize,K) \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_circ_store_update_HH(src,ptr,incr,bufsize,K) \
-    { ptr = (int16_t *) HEXAGON_circ_sthhi (ptr, src, ((((K)-1)<<24)|((bufsize)<<1)), ((incr)*2)); }
+#define Q6_circ_store_update_HH(src, ptr, incr, bufsize, K)                    \
+  {                                                                            \
+    ptr = (int16_t *)HEXAGON_circ_sthhi(                                       \
+        ptr, src, ((((K)-1) << 24) | ((bufsize) << 1)), ((incr)*2));           \
+  }
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_circ_store_update_HH(src,ptr,incr…
{ ptr = (int16_t *) HEXAGON_circ_sthhi (ptr, src, ((((K)-1)<<24)|((bufsize)<<1)), ((incr)*2)); }
/* ==========================================================================
Assembly Syntax: Return=instruction()
C Intrinsic Prototype: void Q6_circ_store_update_B(Word8 *src, Word8 *ptr, UWord32 I4, UWord32 bufsize, UWord64 K)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: void Q6_circ_store_update_B(Word8 *src, Word8 *ptr, UWord32 I4, UWord32 bufsize,  UWord64 K)
-   Instruction Type:      InstructionType
+   C Intrinsic Prototype: void Q6_circ_store_update_B(Word8 *src, Word8 *ptr,
+   UWord32 I4, UWord32 bufsize,  UWord64 K) Instruction Type: InstructionType
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: void…
Instruction Type: InstructionType
Execution Slots: SLOT0123
========================================================================== */
#define Q6_circ_store_update_B(src,ptr,incr,bufsize,K) \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_circ_store_update_B(src,ptr,incr,bufsize,K)  \
-    { ptr = (int8_t *) HEXAGON_circ_stb (ptr, src, ((((K)-2)<<24)|(bufsize)), incr); }
-
+#define Q6_circ_store_update_B(src, ptr, incr, bufsize, K)                     \
+  {                                                                            \
+    ptr = (int8_t *)HEXAGON_circ_stb(ptr, src, ((((K)-2) << 24) | (bufsize)),  \
+                                     incr);                                    \
+  }
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_circ_store_update_B(src,ptr,incr,bufsize…
{ ptr = (int8_t *) HEXAGON_circ_stb (ptr, src, ((((K)-2)<<24)|(bufsize)), incr); }
/* Bit Reverse Load */
/* ==========================================================================
Assembly Syntax: Return=instruction()
C Intrinsic Prototype: void Q6_bitrev_load_update_D(Word64 dst, Word64 *ptr, UWord32 Iu4)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: void Q6_bitrev_load_update_D(Word64 dst, Word64 *ptr, UWord32 Iu4)
-   Instruction Type:      InstructionType
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: void Q6_bitrev_load_update_D(Word64 dst, Word64 *ptr,
+   UWord32 Iu4) Instruction Type:      InstructionType Execution Slots: SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: void…
Instruction Type: InstructionType
Execution Slots: SLOT0123
========================================================================== */
#define Q6_bitrev_load_update_D(dest,ptr,log2bufsize) \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_bitrev_load_update_D(dest,ptr,log2bufsize) \
-    { ptr = (int64_t *) HEXAGON_brev_ldd (ptr, &(dest), (1<<(16-((log2bufsize) + 3)))); }
+#define Q6_bitrev_load_update_D(dest, ptr, log2bufsize)                        \
+  {                                                                            \
+    ptr = (int64_t *)HEXAGON_brev_ldd(ptr, &(dest),                            \
+                                      (1 << (16 - ((log2bufsize) + 3))));      \
+  }
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_bitrev_load_update_D(dest,ptr…
{ ptr = (int64_t *) HEXAGON_brev_ldd (ptr, &(dest), (1<<(16-((log2bufsize) + 3)))); }
/* ==========================================================================
Assembly Syntax: Return=instruction()
C Intrinsic Prototype: void Q6_bitrev_load_update_W(Word32 dst, Word32 *ptr, UWord32 Iu4)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: void Q6_bitrev_load_update_W(Word32 dst, Word32 *ptr, UWord32 Iu4)
-   Instruction Type:      InstructionType
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: void Q6_bitrev_load_update_W(Word32 dst, Word32 *ptr,
+   UWord32 Iu4) Instruction Type:      InstructionType Execution Slots: SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: void…
Instruction Type: InstructionType
Execution Slots: SLOT0123
========================================================================== */
#define Q6_bitrev_load_update_W(dest,ptr,log2bufsize) \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_bitrev_load_update_W(dest,ptr,log2bufsize) \
-    { ptr = (int *) HEXAGON_brev_ldw (ptr, &(dest), (1<<(16-((log2bufsize) + 2)))); }
+#define Q6_bitrev_load_update_W(dest, ptr, log2bufsize)                        \
+  {                                                                            \
+    ptr = (int *)HEXAGON_brev_ldw(ptr, &(dest),                                \
+                                  (1 << (16 - ((log2bufsize) + 2))));          \
+  }
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_bitrev_load_update_W(dest,ptr…
{ ptr = (int *) HEXAGON_brev_ldw (ptr, &(dest), (1<<(16-((log2bufsize) + 2)))); }
/* ==========================================================================
Assembly Syntax: Return=instruction()
C Intrinsic Prototype: void Q6_bitrev_load_update_H(Word16 dst, Word16 *ptr, UWord32 Iu4)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: void Q6_bitrev_load_update_H(Word16 dst, Word16 *ptr, UWord32 Iu4)
-   Instruction Type:      InstructionType
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: void Q6_bitrev_load_update_H(Word16 dst, Word16 *ptr,
+   UWord32 Iu4) Instruction Type:      InstructionType Execution Slots: SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: void…
Instruction Type: InstructionType
Execution Slots: SLOT0123
========================================================================== */
#define Q6_bitrev_load_update_H(dest,ptr,log2bufsize) \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_bitrev_load_update_H(dest,ptr,log2bufsize) \
-    { ptr = (int16_t *) HEXAGON_brev_ldh (ptr, &(dest), (1<<(16-((log2bufsize) + 1)))); }
+#define Q6_bitrev_load_update_H(dest, ptr, log2bufsize)                        \
+  {                                                                            \
+    ptr = (int16_t *)HEXAGON_brev_ldh(ptr, &(dest),                            \
+                                      (1 << (16 - ((log2bufsize) + 1))));      \
+  }
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_bitrev_load_update_H(dest,ptr…
{ ptr = (int16_t *) HEXAGON_brev_ldh (ptr, &(dest), (1<<(16-((log2bufsize) + 1)))); }
/* ==========================================================================
Assembly Syntax: Return=instruction()
C Intrinsic Prototype: void Q6_bitrev_load_update_UH(UWord16 dst, UWord16 *ptr, UWord32 Iu4)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: void Q6_bitrev_load_update_UH(UWord16 dst,  UWord16 *ptr, UWord32 Iu4)
-   Instruction Type:      InstructionType
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: void Q6_bitrev_load_update_UH(UWord16 dst,  UWord16
+   *ptr, UWord32 Iu4) Instruction Type:      InstructionType Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: void…
Instruction Type: InstructionType
Execution Slots: SLOT0123
========================================================================== */
#define Q6_bitrev_load_update_UH(dest,ptr,log2bufsize) \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_bitrev_load_update_UH(dest,ptr,log2bufsize) \
-    { ptr = (uint16_t *) HEXAGON_brev_lduh (ptr, &(dest), (1<<(16-((log2bufsize) + 1)))); }
+#define Q6_bitrev_load_update_UH(dest, ptr, log2bufsize)                       \
+  {                                                                            \
+    ptr = (uint16_t *)HEXAGON_brev_lduh(ptr, &(dest),                          \
+                                        (1 << (16 - ((log2bufsize) + 1))));    \
+  }
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_bitrev_load_update_UH(dest,ptr…
{ ptr = (uint16_t *) HEXAGON_brev_lduh (ptr, &(dest), (1<<(16-((log2bufsize) + 1)))); }
/* ==========================================================================
Assembly Syntax: Return=instruction()
C Intrinsic Prototype: void Q6_bitrev_load_update_B(Word8 dst, Word8 *ptr, UWord32 Iu4)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: void Q6_bitrev_load_update_B(Word8 dst, Word8 *ptr, UWord32 Iu4)
-   Instruction Type:      InstructionType
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: void Q6_bitrev_load_update_B(Word8 dst, Word8 *ptr,
+   UWord32 Iu4) Instruction Type:      InstructionType Execution Slots: SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: void…
Instruction Type: InstructionType
Execution Slots: SLOT0123
========================================================================== */
#define Q6_bitrev_load_update_B(dest,ptr,log2bufsize) \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_bitrev_load_update_B(dest,ptr,log2bufsize) \
-    { ptr = (int8_t *) HEXAGON_brev_ldb (ptr, &(dest), (1<<(16-((log2bufsize))))); }
+#define Q6_bitrev_load_update_B(dest, ptr, log2bufsize)                        \
+  {                                                                            \
+    ptr = (int8_t *)HEXAGON_brev_ldb(ptr, &(dest),                             \
+                                     (1 << (16 - ((log2bufsize)))));           \
+  }
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_bitrev_load_update_B(dest,ptr…
{ ptr = (int8_t *) HEXAGON_brev_ldb (ptr, &(dest), (1<<(16-((log2bufsize))))); }
/* ==========================================================================
Assembly Syntax: Return=instruction()
C Intrinsic Prototype: void Q6_bitrev_load_update_UB(UWord8 dst, UWord8 *ptr, UWord32 Iu4)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: void Q6_bitrev_load_update_UB(UWord8 dst, UWord8 *ptr, UWord32 Iu4)
-   Instruction Type:      InstructionType
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: void Q6_bitrev_load_update_UB(UWord8 dst, UWord8 *ptr,
+   UWord32 Iu4) Instruction Type:      InstructionType Execution Slots: SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: void…
Instruction Type: InstructionType
Execution Slots: SLOT0123
========================================================================== */
#define Q6_bitrev_load_update_UB(dest,ptr,log2bufsize) \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_bitrev_load_update_UB(dest,ptr,log2bufsize) \
-    { ptr = (uint8_t *) HEXAGON_brev_ldub (ptr, &(dest), (1<<(16-((log2bufsize))))); }
+#define Q6_bitrev_load_update_UB(dest, ptr, log2bufsize)                       \
+  {                                                                            \
+    ptr = (uint8_t *)HEXAGON_brev_ldub(ptr, &(dest),                           \
+                                       (1 << (16 - ((log2bufsize)))));         \
+  }
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_bitrev_load_update_UB(dest,ptr…
{ ptr = (uint8_t *) HEXAGON_brev_ldub (ptr, &(dest), (1<<(16-((log2bufsize))))); }
/* Bit Reverse Store */
/* ==========================================================================
Assembly Syntax: Return=instruction()
C Intrinsic Prototype: void Q6_bitrev_store_update_D(Word64 *src, Word64 *ptr, UWord32 Iu4)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: void Q6_bitrev_store_update_D(Word64 *src, Word64 *ptr, UWord32 Iu4)
-   Instruction Type:      InstructionType
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: void Q6_bitrev_store_update_D(Word64 *src, Word64
+   *ptr, UWord32 Iu4) Instruction Type:      InstructionType Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: void…
Instruction Type: InstructionType
Execution Slots: SLOT0123
========================================================================== */
#define Q6_bitrev_store_update_D(src,ptr,log2bufsize) \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_bitrev_store_update_D(src,ptr,log2bufsize)   \
-    { ptr = (int64_t *) HEXAGON_brev_std (ptr, src, (1<<(16-((log2bufsize) + 3)))); }
+#define Q6_bitrev_store_update_D(src, ptr, log2bufsize)                        \
+  {                                                                            \
+    ptr = (int64_t *)HEXAGON_brev_std(ptr, src,                                \
+                                      (1 << (16 - ((log2bufsize) + 3))));      \
+  }
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_bitrev_store_update_D(src,ptr…
{ ptr = (int64_t *) HEXAGON_brev_std (ptr, src, (1<<(16-((log2bufsize) + 3)))); }
/* ==========================================================================
Assembly Syntax: Return=instruction()
C Intrinsic Prototype: void Q6_bitrev_store_update_W(Word32 *src, Word32 *ptr, UWord32 Iu4)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: void Q6_bitrev_store_update_W(Word32 *src, Word32 *ptr, UWord32 Iu4)
-   Instruction Type:      InstructionType
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: void Q6_bitrev_store_update_W(Word32 *src, Word32
+   *ptr, UWord32 Iu4) Instruction Type:      InstructionType Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: void…
Instruction Type: InstructionType
Execution Slots: SLOT0123
========================================================================== */
#define Q6_bitrev_store_update_W(src,ptr,log2bufsize) \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_bitrev_store_update_W(src,ptr,log2bufsize)   \
-    { ptr = (int *) HEXAGON_brev_stw (ptr, src, (1<<(16-((log2bufsize) + 2)))); }
+#define Q6_bitrev_store_update_W(src, ptr, log2bufsize)                        \
+  {                                                                            \
+    ptr =                                                                      \
+        (int *)HEXAGON_brev_stw(ptr, src, (1 << (16 - ((log2bufsize) + 2))));  \
+  }
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_bitrev_store_update_W(src,ptr…
{ ptr = (int *) HEXAGON_brev_stw (ptr, src, (1<<(16-((log2bufsize) + 2)))); }
/* ==========================================================================
Assembly Syntax: Return=instruction()
C Intrinsic Prototype: void Q6_bitrev_store_update_HL(Word16 *src, Word16 *ptr, Word32 Iu4)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: void Q6_bitrev_store_update_HL(Word16 *src, Word16 *ptr, Word32 Iu4)
-   Instruction Type:      InstructionType
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: void Q6_bitrev_store_update_HL(Word16 *src, Word16
+   *ptr, Word32 Iu4) Instruction Type:      InstructionType Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: void…
Instruction Type: InstructionType
Execution Slots: SLOT0123
========================================================================== */
#define Q6_bitrev_store_update_HL(src,ptr,log2bufsize) \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_bitrev_store_update_HL(src,ptr,log2bufsize)   \
-    { ptr = (int16_t *) HEXAGON_brev_sth (ptr, src, (1<<(16-((log2bufsize) + 1)))); }
+#define Q6_bitrev_store_update_HL(src, ptr, log2bufsize)                       \
+  {                                                                            \
+    ptr = (int16_t *)HEXAGON_brev_sth(ptr, src,                                \
+                                      (1 << (16 - ((log2bufsize) + 1))));      \
+  }
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_bitrev_store_update_HL(src,ptr…
{ ptr = (int16_t *) HEXAGON_brev_sth (ptr, src, (1<<(16-((log2bufsize) + 1)))); }
/* ==========================================================================
Assembly Syntax: Return=instruction()
C Intrinsic Prototype: void Q6_bitrev_store_update_HH(Word16 *src, Word16 *ptr, UWord32 Iu4)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: void Q6_bitrev_store_update_HH(Word16 *src, Word16 *ptr, UWord32 Iu4)
-   Instruction Type:      InstructionType
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: void Q6_bitrev_store_update_HH(Word16 *src, Word16
+   *ptr, UWord32 Iu4) Instruction Type:      InstructionType Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: void…
Instruction Type: InstructionType
Execution Slots: SLOT0123
========================================================================== */
#define Q6_bitrev_store_update_HH(src,ptr,log2bufsize) \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_bitrev_store_update_HH(src,ptr,log2bufsize)   \
-    { ptr = (int16_t *) HEXAGON_brev_sthhi (ptr, src, (1<<(16-((log2bufsize) + 1)))); }
+#define Q6_bitrev_store_update_HH(src, ptr, log2bufsize)                       \
+  {                                                                            \
+    ptr = (int16_t *)HEXAGON_brev_sthhi(ptr, src,                              \
+                                        (1 << (16 - ((log2bufsize) + 1))));    \
+  }
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_bitrev_store_update_HH(src,ptr…
{ ptr = (int16_t *) HEXAGON_brev_sthhi (ptr, src, (1<<(16-((log2bufsize) + 1)))); }
/* ==========================================================================
Assembly Syntax: Return=instruction()
C Intrinsic Prototype: void Q6_bitrev_store_update_B(Word8 *src, Word8 *ptr, UWord32 Iu4)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: void Q6_bitrev_store_update_B(Word8 *src, Word8 *ptr, UWord32 Iu4)
-   Instruction Type:      InstructionType
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: void Q6_bitrev_store_update_B(Word8 *src, Word8 *ptr,
+   UWord32 Iu4) Instruction Type:      InstructionType Execution Slots: SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: void…
Instruction Type: InstructionType
Execution Slots: SLOT0123
========================================================================== */
#define Q6_bitrev_store_update_B(src,ptr,log2bufsize) \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_bitrev_store_update_B(src,ptr,log2bufsize)   \
-    { ptr = (int8_t *) HEXAGON_brev_stb (ptr, src, (1<<(16-((log2bufsize))))); }
+#define Q6_bitrev_store_update_B(src, ptr, log2bufsize)                        \
+  { ptr = (int8_t *)HEXAGON_brev_stb(ptr, src, (1 << (16 - ((log2bufsize))))); }
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_bitrev_store_update_B(src,ptr…
{ ptr = (int8_t *) HEXAGON_brev_stb (ptr, src, (1<<(16-((log2bufsize))))); }
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-
-#define HEXAGON_circ_ldd  __builtin_circ_ldd
-#define HEXAGON_circ_ldw  __builtin_circ_ldw
-#define HEXAGON_circ_ldh  __builtin_circ_ldh
+#define HEXAGON_circ_ldd __builtin_circ_ldd
+#define HEXAGON_circ_ldw __builtin_circ_ldw
+#define HEXAGON_circ_ldh __builtin_circ_ldh
Lint: Pre-merge checks: clang-format: please reformat the code ``` - -#define HEXAGON_circ_ldd __builtin_circ_ldd…
#define HEXAGON_circ_ldd __builtin_circ_ldd
#define HEXAGON_circ_ldw __builtin_circ_ldw
#define HEXAGON_circ_ldh __builtin_circ_ldh
#define HEXAGON_circ_lduh __builtin_circ_lduh
#define HEXAGON_circ_ldb __builtin_circ_ldb
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define HEXAGON_circ_ldb  __builtin_circ_ldb
+#define HEXAGON_circ_ldb __builtin_circ_ldb
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_circ_ldb __builtin_circ_ldb…
#define HEXAGON_circ_ldub __builtin_circ_ldub
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-
-#define HEXAGON_circ_std  __builtin_circ_std
-#define HEXAGON_circ_stw  __builtin_circ_stw
-#define HEXAGON_circ_sth  __builtin_circ_sth
+#define HEXAGON_circ_std __builtin_circ_std
+#define HEXAGON_circ_stw __builtin_circ_stw
+#define HEXAGON_circ_sth __builtin_circ_sth
Lint: Pre-merge checks: clang-format: please reformat the code ``` - -#define HEXAGON_circ_std __builtin_circ_std…
#define HEXAGON_circ_std __builtin_circ_std
#define HEXAGON_circ_stw __builtin_circ_stw
#define HEXAGON_circ_sth __builtin_circ_sth
#define HEXAGON_circ_sthhi __builtin_circ_sthhi
#define HEXAGON_circ_stb __builtin_circ_stb
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define HEXAGON_circ_stb  __builtin_circ_stb
+#define HEXAGON_circ_stb __builtin_circ_stb
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_circ_stb __builtin_circ_stb…
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-
-#define HEXAGON_brev_ldd  __builtin_brev_ldd
-#define HEXAGON_brev_ldw  __builtin_brev_ldw
-#define HEXAGON_brev_ldh  __builtin_brev_ldh
+#define HEXAGON_brev_ldd __builtin_brev_ldd
+#define HEXAGON_brev_ldw __builtin_brev_ldw
+#define HEXAGON_brev_ldh __builtin_brev_ldh
Lint: Pre-merge checks: clang-format: please reformat the code ``` - -#define HEXAGON_brev_ldd __builtin_brev_ldd…
#define HEXAGON_brev_ldd __builtin_brev_ldd
#define HEXAGON_brev_ldw __builtin_brev_ldw
#define HEXAGON_brev_ldh __builtin_brev_ldh
#define HEXAGON_brev_lduh __builtin_brev_lduh
#define HEXAGON_brev_ldb __builtin_brev_ldb
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define HEXAGON_brev_ldb  __builtin_brev_ldb
+#define HEXAGON_brev_ldb __builtin_brev_ldb
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_brev_ldb __builtin_brev_ldb…
#define HEXAGON_brev_ldub __builtin_brev_ldub
#define HEXAGON_brev_std __builtin_brev_std
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define HEXAGON_brev_std  __builtin_brev_std
-#define HEXAGON_brev_stw  __builtin_brev_stw
-#define HEXAGON_brev_sth  __builtin_brev_sth
+#define HEXAGON_brev_std __builtin_brev_std
+#define HEXAGON_brev_stw __builtin_brev_stw
+#define HEXAGON_brev_sth __builtin_brev_sth
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_brev_std __builtin_brev_std…
#define HEXAGON_brev_stw __builtin_brev_stw
#define HEXAGON_brev_sth __builtin_brev_sth
#define HEXAGON_brev_sthhi __builtin_brev_sthhi
#define HEXAGON_brev_stb __builtin_brev_stb
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define HEXAGON_brev_stb  __builtin_brev_stb
+#define HEXAGON_brev_stb __builtin_brev_stb
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_brev_stb __builtin_brev_stb…
#ifdef __HVX__
/* ==========================================================================
Assembly Syntax: if (Qt) vmem(Rt+#0) = Vs
C Intrinsic Prototype: void Q6_vmaskedstoreq_QAV(HVX_VectorPred Qt, HVX_VectorAddress A, HVX_Vector Vs)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: void Q6_vmaskedstoreq_QAV(HVX_VectorPred Qt, HVX_VectorAddress A, HVX_Vector Vs)
-   Instruction Type:      COPROC_VMEM
+   C Intrinsic Prototype: void Q6_vmaskedstoreq_QAV(HVX_VectorPred Qt,
+   HVX_VectorAddress A, HVX_Vector Vs) Instruction Type:      COPROC_VMEM
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: void Q6_vmaskedstoreq_QAV…
Instruction Type: COPROC_VMEM
Execution Slots: SLOT0
========================================================================== */
#define Q6_vmaskedstoreq_QAV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaskedstoreq)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_vmaskedstoreq_QAV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaskedstoreq)
+#define Q6_vmaskedstoreq_QAV                                                   \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaskedstoreq)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_vmaskedstoreq_QAV __BUILTIN_VECTOR_WRAP…
/* ==========================================================================
Assembly Syntax: if (!Qt) vmem(Rt+#0) = Vs
C Intrinsic Prototype: void Q6_vmaskedstorenq_QAV(HVX_VectorPred Qt, HVX_VectorAddress A, HVX_Vector Vs)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: void Q6_vmaskedstorenq_QAV(HVX_VectorPred Qt, HVX_VectorAddress A, HVX_Vector Vs)
-   Instruction Type:      COPROC_VMEM
+   C Intrinsic Prototype: void Q6_vmaskedstorenq_QAV(HVX_VectorPred Qt,
+   HVX_VectorAddress A, HVX_Vector Vs) Instruction Type:      COPROC_VMEM
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: void…
Instruction Type: COPROC_VMEM
Execution Slots: SLOT0
========================================================================== */
#define Q6_vmaskedstorenq_QAV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaskedstorenq)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_vmaskedstorenq_QAV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaskedstorenq)
+#define Q6_vmaskedstorenq_QAV                                                  \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaskedstorenq)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_vmaskedstorenq_QAV __BUILTIN_VECTOR_WRAP…
/* ==========================================================================
Assembly Syntax: if (Qt) vmem(Rt+#0):nt = Vs
C Intrinsic Prototype: void Q6_vmaskedstorentq_QAV(HVX_VectorPred Qt, HVX_VectorAddress A, HVX_Vector Vs)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: void Q6_vmaskedstorentq_QAV(HVX_VectorPred Qt, HVX_VectorAddress A, HVX_Vector Vs)
-   Instruction Type:      COPROC_VMEM
+   C Intrinsic Prototype: void Q6_vmaskedstorentq_QAV(HVX_VectorPred Qt,
+   HVX_VectorAddress A, HVX_Vector Vs) Instruction Type:      COPROC_VMEM
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: void…
Instruction Type: COPROC_VMEM
Execution Slots: SLOT0
========================================================================== */
#define Q6_vmaskedstorentq_QAV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaskedstorentq)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_vmaskedstorentq_QAV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaskedstorentq)
+#define Q6_vmaskedstorentq_QAV                                                 \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaskedstorentq)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_vmaskedstorentq_QAV…
/* ==========================================================================
Assembly Syntax: if (!Qt) vmem(Rt+#0):nt = Vs
C Intrinsic Prototype: void Q6_vmaskedstorentnq_QAV(HVX_VectorPred Qt, HVX_VectorAddress A, HVX_Vector Vs)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: void Q6_vmaskedstorentnq_QAV(HVX_VectorPred Qt, HVX_VectorAddress A, HVX_Vector Vs)
-   Instruction Type:      COPROC_VMEM
+   C Intrinsic Prototype: void Q6_vmaskedstorentnq_QAV(HVX_VectorPred Qt,
+   HVX_VectorAddress A, HVX_Vector Vs) Instruction Type:      COPROC_VMEM
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: void…
Instruction Type: COPROC_VMEM
Execution Slots: SLOT0
========================================================================== */
#define Q6_vmaskedstorentnq_QAV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaskedstorentnq)
Lint: Pre-merge checks
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clang-format: please reformat the code

-#define Q6_vmaskedstorentnq_QAV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaskedstorentnq)
+#define Q6_vmaskedstorentnq_QAV                                                \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaskedstorentnq)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_vmaskedstorentnq_QAV…
#endif
Lint: Pre-merge checks
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clang-format: please reformat the code

-
-#endif  /* #ifndef _HEXAGON_CIRC_BREV_INTRINSICS_H_ */
+#endif /* #ifndef _HEXAGON_CIRC_BREV_INTRINSICS_H_ */
Lint: Pre-merge checks: clang-format: please reformat the code ``` - -#endif /* #ifndef…
#endif /* #ifndef _HEXAGON_CIRC_BREV_INTRINSICS_H_ */
#ifdef __NOT_DEFINED__
/*** comment block template ***/
/* ==========================================================================
Assembly Syntax: Return=instruction()
C Intrinsic Prototype: ReturnType Intrinsic(ParamType Rs, ParamType Rt)
Instruction Type: InstructionType
Execution Slots: SLOT0123
========================================================================== */
#endif /*** __NOT_DEFINED__ ***/

clang/lib/Headers/hexagon_protos.h

  • This file was added.
  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
//===----------------------------------------------------------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
// Automatically generated file, do not edit!
//===----------------------------------------------------------------------===//
Lint: Pre-merge checks
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clang-format: please reformat the code

-
-
Lint: Pre-merge checks: clang-format: please reformat the code ``` - - ```
#ifndef __HEXAGON_PROTOS_H_
Lint: Pre-merge checks
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clang-tidy: warning: header guard does not follow preferred style [llvm-header-guard]
not useful

Lint: Pre-merge checks: clang-tidy: warning: header guard does not follow preferred style [llvm-header-guard] [[https…
#define __HEXAGON_PROTOS_H_ 1
/* ==========================================================================
Assembly Syntax: Rd32=abs(Rs32)
C Intrinsic Prototype: Word32 Q6_R_abs_R(Word32 Rs)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_abs_R __builtin_HEXAGON_A2_abs
/* ==========================================================================
Assembly Syntax: Rdd32=abs(Rss32)
C Intrinsic Prototype: Word64 Q6_P_abs_P(Word64 Rss)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_abs_P __builtin_HEXAGON_A2_absp
/* ==========================================================================
Assembly Syntax: Rd32=abs(Rs32):sat
C Intrinsic Prototype: Word32 Q6_R_abs_R_sat(Word32 Rs)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_abs_R_sat __builtin_HEXAGON_A2_abssat
/* ==========================================================================
Assembly Syntax: Rd32=add(Rs32,Rt32)
C Intrinsic Prototype: Word32 Q6_R_add_RR(Word32 Rs, Word32 Rt)
Instruction Type: ALU32_3op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_R_add_RR __builtin_HEXAGON_A2_add
/* ==========================================================================
Assembly Syntax: Rd32=add(Rt32.h,Rs32.h):<<16
C Intrinsic Prototype: Word32 Q6_R_add_RhRh_s16(Word32 Rt, Word32 Rs)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_add_RhRh_s16 __builtin_HEXAGON_A2_addh_h16_hh
/* ==========================================================================
Assembly Syntax: Rd32=add(Rt32.h,Rs32.l):<<16
C Intrinsic Prototype: Word32 Q6_R_add_RhRl_s16(Word32 Rt, Word32 Rs)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_add_RhRl_s16 __builtin_HEXAGON_A2_addh_h16_hl
/* ==========================================================================
Assembly Syntax: Rd32=add(Rt32.l,Rs32.h):<<16
C Intrinsic Prototype: Word32 Q6_R_add_RlRh_s16(Word32 Rt, Word32 Rs)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_add_RlRh_s16 __builtin_HEXAGON_A2_addh_h16_lh
/* ==========================================================================
Assembly Syntax: Rd32=add(Rt32.l,Rs32.l):<<16
C Intrinsic Prototype: Word32 Q6_R_add_RlRl_s16(Word32 Rt, Word32 Rs)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_add_RlRl_s16 __builtin_HEXAGON_A2_addh_h16_ll
/* ==========================================================================
Assembly Syntax: Rd32=add(Rt32.h,Rs32.h):sat:<<16
C Intrinsic Prototype: Word32 Q6_R_add_RhRh_sat_s16(Word32 Rt, Word32 Rs)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_add_RhRh_sat_s16 __builtin_HEXAGON_A2_addh_h16_sat_hh
/* ==========================================================================
Assembly Syntax: Rd32=add(Rt32.h,Rs32.l):sat:<<16
C Intrinsic Prototype: Word32 Q6_R_add_RhRl_sat_s16(Word32 Rt, Word32 Rs)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_add_RhRl_sat_s16 __builtin_HEXAGON_A2_addh_h16_sat_hl
/* ==========================================================================
Assembly Syntax: Rd32=add(Rt32.l,Rs32.h):sat:<<16
C Intrinsic Prototype: Word32 Q6_R_add_RlRh_sat_s16(Word32 Rt, Word32 Rs)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_add_RlRh_sat_s16 __builtin_HEXAGON_A2_addh_h16_sat_lh
/* ==========================================================================
Assembly Syntax: Rd32=add(Rt32.l,Rs32.l):sat:<<16
C Intrinsic Prototype: Word32 Q6_R_add_RlRl_sat_s16(Word32 Rt, Word32 Rs)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_add_RlRl_sat_s16 __builtin_HEXAGON_A2_addh_h16_sat_ll
/* ==========================================================================
Assembly Syntax: Rd32=add(Rt32.l,Rs32.h)
C Intrinsic Prototype: Word32 Q6_R_add_RlRh(Word32 Rt, Word32 Rs)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_add_RlRh __builtin_HEXAGON_A2_addh_l16_hl
/* ==========================================================================
Assembly Syntax: Rd32=add(Rt32.l,Rs32.l)
C Intrinsic Prototype: Word32 Q6_R_add_RlRl(Word32 Rt, Word32 Rs)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_add_RlRl __builtin_HEXAGON_A2_addh_l16_ll
/* ==========================================================================
Assembly Syntax: Rd32=add(Rt32.l,Rs32.h):sat
C Intrinsic Prototype: Word32 Q6_R_add_RlRh_sat(Word32 Rt, Word32 Rs)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_add_RlRh_sat __builtin_HEXAGON_A2_addh_l16_sat_hl
/* ==========================================================================
Assembly Syntax: Rd32=add(Rt32.l,Rs32.l):sat
C Intrinsic Prototype: Word32 Q6_R_add_RlRl_sat(Word32 Rt, Word32 Rs)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_add_RlRl_sat __builtin_HEXAGON_A2_addh_l16_sat_ll
/* ==========================================================================
Assembly Syntax: Rd32=add(Rs32,#s16)
C Intrinsic Prototype: Word32 Q6_R_add_RI(Word32 Rs, Word32 Is16)
Instruction Type: ALU32_ADDI
Execution Slots: SLOT0123
========================================================================== */
#define Q6_R_add_RI __builtin_HEXAGON_A2_addi
/* ==========================================================================
Assembly Syntax: Rdd32=add(Rss32,Rtt32)
C Intrinsic Prototype: Word64 Q6_P_add_PP(Word64 Rss, Word64 Rtt)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_add_PP __builtin_HEXAGON_A2_addp
/* ==========================================================================
Assembly Syntax: Rdd32=add(Rss32,Rtt32):sat
C Intrinsic Prototype: Word64 Q6_P_add_PP_sat(Word64 Rss, Word64 Rtt)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_add_PP_sat __builtin_HEXAGON_A2_addpsat
/* ==========================================================================
Assembly Syntax: Rd32=add(Rs32,Rt32):sat
C Intrinsic Prototype: Word32 Q6_R_add_RR_sat(Word32 Rs, Word32 Rt)
Instruction Type: ALU32_3op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_R_add_RR_sat __builtin_HEXAGON_A2_addsat
/* ==========================================================================
Assembly Syntax: Rdd32=add(Rs32,Rtt32)
C Intrinsic Prototype: Word64 Q6_P_add_RP(Word32 Rs, Word64 Rtt)
Instruction Type: ALU64
Execution Slots: SLOT0123
========================================================================== */
#define Q6_P_add_RP __builtin_HEXAGON_A2_addsp
/* ==========================================================================
Assembly Syntax: Rd32=and(Rs32,Rt32)
C Intrinsic Prototype: Word32 Q6_R_and_RR(Word32 Rs, Word32 Rt)
Instruction Type: ALU32_3op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_R_and_RR __builtin_HEXAGON_A2_and
/* ==========================================================================
Assembly Syntax: Rd32=and(Rs32,#s10)
C Intrinsic Prototype: Word32 Q6_R_and_RI(Word32 Rs, Word32 Is10)
Instruction Type: ALU32_2op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_R_and_RI __builtin_HEXAGON_A2_andir
/* ==========================================================================
Assembly Syntax: Rdd32=and(Rss32,Rtt32)
C Intrinsic Prototype: Word64 Q6_P_and_PP(Word64 Rss, Word64 Rtt)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_and_PP __builtin_HEXAGON_A2_andp
/* ==========================================================================
Assembly Syntax: Rd32=aslh(Rs32)
C Intrinsic Prototype: Word32 Q6_R_aslh_R(Word32 Rs)
Instruction Type: ALU32_2op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_R_aslh_R __builtin_HEXAGON_A2_aslh
/* ==========================================================================
Assembly Syntax: Rd32=asrh(Rs32)
C Intrinsic Prototype: Word32 Q6_R_asrh_R(Word32 Rs)
Instruction Type: ALU32_2op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_R_asrh_R __builtin_HEXAGON_A2_asrh
/* ==========================================================================
Assembly Syntax: Rd32=combine(Rt32.h,Rs32.h)
C Intrinsic Prototype: Word32 Q6_R_combine_RhRh(Word32 Rt, Word32 Rs)
Instruction Type: ALU32_3op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_R_combine_RhRh __builtin_HEXAGON_A2_combine_hh
/* ==========================================================================
Assembly Syntax: Rd32=combine(Rt32.h,Rs32.l)
C Intrinsic Prototype: Word32 Q6_R_combine_RhRl(Word32 Rt, Word32 Rs)
Instruction Type: ALU32_3op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_R_combine_RhRl __builtin_HEXAGON_A2_combine_hl
/* ==========================================================================
Assembly Syntax: Rd32=combine(Rt32.l,Rs32.h)
C Intrinsic Prototype: Word32 Q6_R_combine_RlRh(Word32 Rt, Word32 Rs)
Instruction Type: ALU32_3op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_R_combine_RlRh __builtin_HEXAGON_A2_combine_lh
/* ==========================================================================
Assembly Syntax: Rd32=combine(Rt32.l,Rs32.l)
C Intrinsic Prototype: Word32 Q6_R_combine_RlRl(Word32 Rt, Word32 Rs)
Instruction Type: ALU32_3op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_R_combine_RlRl __builtin_HEXAGON_A2_combine_ll
/* ==========================================================================
Assembly Syntax: Rdd32=combine(#s8,#S8)
C Intrinsic Prototype: Word64 Q6_P_combine_II(Word32 Is8, Word32 IS8)
Instruction Type: ALU32_2op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_P_combine_II __builtin_HEXAGON_A2_combineii
/* ==========================================================================
Assembly Syntax: Rdd32=combine(Rs32,Rt32)
C Intrinsic Prototype: Word64 Q6_P_combine_RR(Word32 Rs, Word32 Rt)
Instruction Type: ALU32_3op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_P_combine_RR __builtin_HEXAGON_A2_combinew
/* ==========================================================================
Assembly Syntax: Rd32=max(Rs32,Rt32)
C Intrinsic Prototype: Word32 Q6_R_max_RR(Word32 Rs, Word32 Rt)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_max_RR __builtin_HEXAGON_A2_max
/* ==========================================================================
Assembly Syntax: Rdd32=max(Rss32,Rtt32)
C Intrinsic Prototype: Word64 Q6_P_max_PP(Word64 Rss, Word64 Rtt)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_max_PP __builtin_HEXAGON_A2_maxp
/* ==========================================================================
Assembly Syntax: Rd32=maxu(Rs32,Rt32)
C Intrinsic Prototype: UWord32 Q6_R_maxu_RR(Word32 Rs, Word32 Rt)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_maxu_RR __builtin_HEXAGON_A2_maxu
/* ==========================================================================
Assembly Syntax: Rdd32=maxu(Rss32,Rtt32)
C Intrinsic Prototype: UWord64 Q6_P_maxu_PP(Word64 Rss, Word64 Rtt)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_maxu_PP __builtin_HEXAGON_A2_maxup
/* ==========================================================================
Assembly Syntax: Rd32=min(Rt32,Rs32)
C Intrinsic Prototype: Word32 Q6_R_min_RR(Word32 Rt, Word32 Rs)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_min_RR __builtin_HEXAGON_A2_min
/* ==========================================================================
Assembly Syntax: Rdd32=min(Rtt32,Rss32)
C Intrinsic Prototype: Word64 Q6_P_min_PP(Word64 Rtt, Word64 Rss)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_min_PP __builtin_HEXAGON_A2_minp
/* ==========================================================================
Assembly Syntax: Rd32=minu(Rt32,Rs32)
C Intrinsic Prototype: UWord32 Q6_R_minu_RR(Word32 Rt, Word32 Rs)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_minu_RR __builtin_HEXAGON_A2_minu
/* ==========================================================================
Assembly Syntax: Rdd32=minu(Rtt32,Rss32)
C Intrinsic Prototype: UWord64 Q6_P_minu_PP(Word64 Rtt, Word64 Rss)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_minu_PP __builtin_HEXAGON_A2_minup
/* ==========================================================================
Assembly Syntax: Rd32=neg(Rs32)
C Intrinsic Prototype: Word32 Q6_R_neg_R(Word32 Rs)
Instruction Type: ALU32_2op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_R_neg_R __builtin_HEXAGON_A2_neg
/* ==========================================================================
Assembly Syntax: Rdd32=neg(Rss32)
C Intrinsic Prototype: Word64 Q6_P_neg_P(Word64 Rss)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_neg_P __builtin_HEXAGON_A2_negp
/* ==========================================================================
Assembly Syntax: Rd32=neg(Rs32):sat
C Intrinsic Prototype: Word32 Q6_R_neg_R_sat(Word32 Rs)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_neg_R_sat __builtin_HEXAGON_A2_negsat
/* ==========================================================================
Assembly Syntax: Rd32=not(Rs32)
C Intrinsic Prototype: Word32 Q6_R_not_R(Word32 Rs)
Instruction Type: ALU32_2op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_R_not_R __builtin_HEXAGON_A2_not
/* ==========================================================================
Assembly Syntax: Rdd32=not(Rss32)
C Intrinsic Prototype: Word64 Q6_P_not_P(Word64 Rss)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_not_P __builtin_HEXAGON_A2_notp
/* ==========================================================================
Assembly Syntax: Rd32=or(Rs32,Rt32)
C Intrinsic Prototype: Word32 Q6_R_or_RR(Word32 Rs, Word32 Rt)
Instruction Type: ALU32_3op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_R_or_RR __builtin_HEXAGON_A2_or
/* ==========================================================================
Assembly Syntax: Rd32=or(Rs32,#s10)
C Intrinsic Prototype: Word32 Q6_R_or_RI(Word32 Rs, Word32 Is10)
Instruction Type: ALU32_2op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_R_or_RI __builtin_HEXAGON_A2_orir
/* ==========================================================================
Assembly Syntax: Rdd32=or(Rss32,Rtt32)
C Intrinsic Prototype: Word64 Q6_P_or_PP(Word64 Rss, Word64 Rtt)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_or_PP __builtin_HEXAGON_A2_orp
/* ==========================================================================
Assembly Syntax: Rd32=round(Rss32):sat
C Intrinsic Prototype: Word32 Q6_R_round_P_sat(Word64 Rss)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_round_P_sat __builtin_HEXAGON_A2_roundsat
/* ==========================================================================
Assembly Syntax: Rd32=sat(Rss32)
C Intrinsic Prototype: Word32 Q6_R_sat_P(Word64 Rss)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_sat_P __builtin_HEXAGON_A2_sat
/* ==========================================================================
Assembly Syntax: Rd32=satb(Rs32)
C Intrinsic Prototype: Word32 Q6_R_satb_R(Word32 Rs)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_satb_R __builtin_HEXAGON_A2_satb
/* ==========================================================================
Assembly Syntax: Rd32=sath(Rs32)
C Intrinsic Prototype: Word32 Q6_R_sath_R(Word32 Rs)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_sath_R __builtin_HEXAGON_A2_sath
/* ==========================================================================
Assembly Syntax: Rd32=satub(Rs32)
C Intrinsic Prototype: Word32 Q6_R_satub_R(Word32 Rs)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_satub_R __builtin_HEXAGON_A2_satub
/* ==========================================================================
Assembly Syntax: Rd32=satuh(Rs32)
C Intrinsic Prototype: Word32 Q6_R_satuh_R(Word32 Rs)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_satuh_R __builtin_HEXAGON_A2_satuh
/* ==========================================================================
Assembly Syntax: Rd32=sub(Rt32,Rs32)
C Intrinsic Prototype: Word32 Q6_R_sub_RR(Word32 Rt, Word32 Rs)
Instruction Type: ALU32_3op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_R_sub_RR __builtin_HEXAGON_A2_sub
/* ==========================================================================
Assembly Syntax: Rd32=sub(Rt32.h,Rs32.h):<<16
C Intrinsic Prototype: Word32 Q6_R_sub_RhRh_s16(Word32 Rt, Word32 Rs)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_sub_RhRh_s16 __builtin_HEXAGON_A2_subh_h16_hh
/* ==========================================================================
Assembly Syntax: Rd32=sub(Rt32.h,Rs32.l):<<16
C Intrinsic Prototype: Word32 Q6_R_sub_RhRl_s16(Word32 Rt, Word32 Rs)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_sub_RhRl_s16 __builtin_HEXAGON_A2_subh_h16_hl
/* ==========================================================================
Assembly Syntax: Rd32=sub(Rt32.l,Rs32.h):<<16
C Intrinsic Prototype: Word32 Q6_R_sub_RlRh_s16(Word32 Rt, Word32 Rs)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_sub_RlRh_s16 __builtin_HEXAGON_A2_subh_h16_lh
/* ==========================================================================
Assembly Syntax: Rd32=sub(Rt32.l,Rs32.l):<<16
C Intrinsic Prototype: Word32 Q6_R_sub_RlRl_s16(Word32 Rt, Word32 Rs)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_sub_RlRl_s16 __builtin_HEXAGON_A2_subh_h16_ll
/* ==========================================================================
Assembly Syntax: Rd32=sub(Rt32.h,Rs32.h):sat:<<16
C Intrinsic Prototype: Word32 Q6_R_sub_RhRh_sat_s16(Word32 Rt, Word32 Rs)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_sub_RhRh_sat_s16 __builtin_HEXAGON_A2_subh_h16_sat_hh
/* ==========================================================================
Assembly Syntax: Rd32=sub(Rt32.h,Rs32.l):sat:<<16
C Intrinsic Prototype: Word32 Q6_R_sub_RhRl_sat_s16(Word32 Rt, Word32 Rs)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_sub_RhRl_sat_s16 __builtin_HEXAGON_A2_subh_h16_sat_hl
/* ==========================================================================
Assembly Syntax: Rd32=sub(Rt32.l,Rs32.h):sat:<<16
C Intrinsic Prototype: Word32 Q6_R_sub_RlRh_sat_s16(Word32 Rt, Word32 Rs)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_sub_RlRh_sat_s16 __builtin_HEXAGON_A2_subh_h16_sat_lh
/* ==========================================================================
Assembly Syntax: Rd32=sub(Rt32.l,Rs32.l):sat:<<16
C Intrinsic Prototype: Word32 Q6_R_sub_RlRl_sat_s16(Word32 Rt, Word32 Rs)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_sub_RlRl_sat_s16 __builtin_HEXAGON_A2_subh_h16_sat_ll
/* ==========================================================================
Assembly Syntax: Rd32=sub(Rt32.l,Rs32.h)
C Intrinsic Prototype: Word32 Q6_R_sub_RlRh(Word32 Rt, Word32 Rs)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_sub_RlRh __builtin_HEXAGON_A2_subh_l16_hl
/* ==========================================================================
Assembly Syntax: Rd32=sub(Rt32.l,Rs32.l)
C Intrinsic Prototype: Word32 Q6_R_sub_RlRl(Word32 Rt, Word32 Rs)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_sub_RlRl __builtin_HEXAGON_A2_subh_l16_ll
/* ==========================================================================
Assembly Syntax: Rd32=sub(Rt32.l,Rs32.h):sat
C Intrinsic Prototype: Word32 Q6_R_sub_RlRh_sat(Word32 Rt, Word32 Rs)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_sub_RlRh_sat __builtin_HEXAGON_A2_subh_l16_sat_hl
/* ==========================================================================
Assembly Syntax: Rd32=sub(Rt32.l,Rs32.l):sat
C Intrinsic Prototype: Word32 Q6_R_sub_RlRl_sat(Word32 Rt, Word32 Rs)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_sub_RlRl_sat __builtin_HEXAGON_A2_subh_l16_sat_ll
/* ==========================================================================
Assembly Syntax: Rdd32=sub(Rtt32,Rss32)
C Intrinsic Prototype: Word64 Q6_P_sub_PP(Word64 Rtt, Word64 Rss)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_sub_PP __builtin_HEXAGON_A2_subp
/* ==========================================================================
Assembly Syntax: Rd32=sub(#s10,Rs32)
C Intrinsic Prototype: Word32 Q6_R_sub_IR(Word32 Is10, Word32 Rs)
Instruction Type: ALU32_2op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_R_sub_IR __builtin_HEXAGON_A2_subri
/* ==========================================================================
Assembly Syntax: Rd32=sub(Rt32,Rs32):sat
C Intrinsic Prototype: Word32 Q6_R_sub_RR_sat(Word32 Rt, Word32 Rs)
Instruction Type: ALU32_3op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_R_sub_RR_sat __builtin_HEXAGON_A2_subsat
/* ==========================================================================
Assembly Syntax: Rd32=vaddh(Rs32,Rt32)
C Intrinsic Prototype: Word32 Q6_R_vaddh_RR(Word32 Rs, Word32 Rt)
Instruction Type: ALU32_3op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_R_vaddh_RR __builtin_HEXAGON_A2_svaddh
/* ==========================================================================
Assembly Syntax: Rd32=vaddh(Rs32,Rt32):sat
C Intrinsic Prototype: Word32 Q6_R_vaddh_RR_sat(Word32 Rs, Word32 Rt)
Instruction Type: ALU32_3op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_R_vaddh_RR_sat __builtin_HEXAGON_A2_svaddhs
/* ==========================================================================
Assembly Syntax: Rd32=vadduh(Rs32,Rt32):sat
C Intrinsic Prototype: Word32 Q6_R_vadduh_RR_sat(Word32 Rs, Word32 Rt)
Instruction Type: ALU32_3op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_R_vadduh_RR_sat __builtin_HEXAGON_A2_svadduhs
/* ==========================================================================
Assembly Syntax: Rd32=vavgh(Rs32,Rt32)
C Intrinsic Prototype: Word32 Q6_R_vavgh_RR(Word32 Rs, Word32 Rt)
Instruction Type: ALU32_3op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_R_vavgh_RR __builtin_HEXAGON_A2_svavgh
/* ==========================================================================
Assembly Syntax: Rd32=vavgh(Rs32,Rt32):rnd
C Intrinsic Prototype: Word32 Q6_R_vavgh_RR_rnd(Word32 Rs, Word32 Rt)
Instruction Type: ALU32_3op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_R_vavgh_RR_rnd __builtin_HEXAGON_A2_svavghs
/* ==========================================================================
Assembly Syntax: Rd32=vnavgh(Rt32,Rs32)
C Intrinsic Prototype: Word32 Q6_R_vnavgh_RR(Word32 Rt, Word32 Rs)
Instruction Type: ALU32_3op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_R_vnavgh_RR __builtin_HEXAGON_A2_svnavgh
/* ==========================================================================
Assembly Syntax: Rd32=vsubh(Rt32,Rs32)
C Intrinsic Prototype: Word32 Q6_R_vsubh_RR(Word32 Rt, Word32 Rs)
Instruction Type: ALU32_3op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_R_vsubh_RR __builtin_HEXAGON_A2_svsubh
/* ==========================================================================
Assembly Syntax: Rd32=vsubh(Rt32,Rs32):sat
C Intrinsic Prototype: Word32 Q6_R_vsubh_RR_sat(Word32 Rt, Word32 Rs)
Instruction Type: ALU32_3op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_R_vsubh_RR_sat __builtin_HEXAGON_A2_svsubhs
/* ==========================================================================
Assembly Syntax: Rd32=vsubuh(Rt32,Rs32):sat
C Intrinsic Prototype: Word32 Q6_R_vsubuh_RR_sat(Word32 Rt, Word32 Rs)
Instruction Type: ALU32_3op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_R_vsubuh_RR_sat __builtin_HEXAGON_A2_svsubuhs
/* ==========================================================================
Assembly Syntax: Rd32=swiz(Rs32)
C Intrinsic Prototype: Word32 Q6_R_swiz_R(Word32 Rs)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_swiz_R __builtin_HEXAGON_A2_swiz
/* ==========================================================================
Assembly Syntax: Rd32=sxtb(Rs32)
C Intrinsic Prototype: Word32 Q6_R_sxtb_R(Word32 Rs)
Instruction Type: ALU32_2op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_R_sxtb_R __builtin_HEXAGON_A2_sxtb
/* ==========================================================================
Assembly Syntax: Rd32=sxth(Rs32)
C Intrinsic Prototype: Word32 Q6_R_sxth_R(Word32 Rs)
Instruction Type: ALU32_2op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_R_sxth_R __builtin_HEXAGON_A2_sxth
/* ==========================================================================
Assembly Syntax: Rdd32=sxtw(Rs32)
C Intrinsic Prototype: Word64 Q6_P_sxtw_R(Word32 Rs)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_sxtw_R __builtin_HEXAGON_A2_sxtw
/* ==========================================================================
Assembly Syntax: Rd32=Rs32
C Intrinsic Prototype: Word32 Q6_R_equals_R(Word32 Rs)
Instruction Type: ALU32_2op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_R_equals_R __builtin_HEXAGON_A2_tfr
/* ==========================================================================
Assembly Syntax: Rx32.h=#u16
C Intrinsic Prototype: Word32 Q6_Rh_equals_I(Word32 Rx, Word32 Iu16)
Instruction Type: ALU32_2op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Rh_equals_I __builtin_HEXAGON_A2_tfrih
/* ==========================================================================
Assembly Syntax: Rx32.l=#u16
C Intrinsic Prototype: Word32 Q6_Rl_equals_I(Word32 Rx, Word32 Iu16)
Instruction Type: ALU32_2op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Rl_equals_I __builtin_HEXAGON_A2_tfril
/* ==========================================================================
Assembly Syntax: Rdd32=Rss32
C Intrinsic Prototype: Word64 Q6_P_equals_P(Word64 Rss)
Instruction Type: ALU32_2op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_P_equals_P __builtin_HEXAGON_A2_tfrp
/* ==========================================================================
Assembly Syntax: Rdd32=#s8
C Intrinsic Prototype: Word64 Q6_P_equals_I(Word32 Is8)
Instruction Type: ALU64
Execution Slots: SLOT0123
========================================================================== */
#define Q6_P_equals_I __builtin_HEXAGON_A2_tfrpi
/* ==========================================================================
Assembly Syntax: Rd32=#s16
C Intrinsic Prototype: Word32 Q6_R_equals_I(Word32 Is16)
Instruction Type: ALU32_2op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_R_equals_I __builtin_HEXAGON_A2_tfrsi
/* ==========================================================================
Assembly Syntax: Rdd32=vabsh(Rss32)
C Intrinsic Prototype: Word64 Q6_P_vabsh_P(Word64 Rss)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vabsh_P __builtin_HEXAGON_A2_vabsh
/* ==========================================================================
Assembly Syntax: Rdd32=vabsh(Rss32):sat
C Intrinsic Prototype: Word64 Q6_P_vabsh_P_sat(Word64 Rss)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vabsh_P_sat __builtin_HEXAGON_A2_vabshsat
/* ==========================================================================
Assembly Syntax: Rdd32=vabsw(Rss32)
C Intrinsic Prototype: Word64 Q6_P_vabsw_P(Word64 Rss)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vabsw_P __builtin_HEXAGON_A2_vabsw
/* ==========================================================================
Assembly Syntax: Rdd32=vabsw(Rss32):sat
C Intrinsic Prototype: Word64 Q6_P_vabsw_P_sat(Word64 Rss)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vabsw_P_sat __builtin_HEXAGON_A2_vabswsat
/* ==========================================================================
Assembly Syntax: Rdd32=vaddb(Rss32,Rtt32)
C Intrinsic Prototype: Word64 Q6_P_vaddb_PP(Word64 Rss, Word64 Rtt)
Instruction Type: MAPPING
Execution Slots: SLOT0123
========================================================================== */
#define Q6_P_vaddb_PP __builtin_HEXAGON_A2_vaddb_map
/* ==========================================================================
Assembly Syntax: Rdd32=vaddh(Rss32,Rtt32)
C Intrinsic Prototype: Word64 Q6_P_vaddh_PP(Word64 Rss, Word64 Rtt)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vaddh_PP __builtin_HEXAGON_A2_vaddh
/* ==========================================================================
Assembly Syntax: Rdd32=vaddh(Rss32,Rtt32):sat
C Intrinsic Prototype: Word64 Q6_P_vaddh_PP_sat(Word64 Rss, Word64 Rtt)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vaddh_PP_sat __builtin_HEXAGON_A2_vaddhs
/* ==========================================================================
Assembly Syntax: Rdd32=vaddub(Rss32,Rtt32)
C Intrinsic Prototype: Word64 Q6_P_vaddub_PP(Word64 Rss, Word64 Rtt)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vaddub_PP __builtin_HEXAGON_A2_vaddub
/* ==========================================================================
Assembly Syntax: Rdd32=vaddub(Rss32,Rtt32):sat
C Intrinsic Prototype: Word64 Q6_P_vaddub_PP_sat(Word64 Rss, Word64 Rtt)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vaddub_PP_sat __builtin_HEXAGON_A2_vaddubs
/* ==========================================================================
Assembly Syntax: Rdd32=vadduh(Rss32,Rtt32):sat
C Intrinsic Prototype: Word64 Q6_P_vadduh_PP_sat(Word64 Rss, Word64 Rtt)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vadduh_PP_sat __builtin_HEXAGON_A2_vadduhs
/* ==========================================================================
Assembly Syntax: Rdd32=vaddw(Rss32,Rtt32)
C Intrinsic Prototype: Word64 Q6_P_vaddw_PP(Word64 Rss, Word64 Rtt)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vaddw_PP __builtin_HEXAGON_A2_vaddw
/* ==========================================================================
Assembly Syntax: Rdd32=vaddw(Rss32,Rtt32):sat
C Intrinsic Prototype: Word64 Q6_P_vaddw_PP_sat(Word64 Rss, Word64 Rtt)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vaddw_PP_sat __builtin_HEXAGON_A2_vaddws
/* ==========================================================================
Assembly Syntax: Rdd32=vavgh(Rss32,Rtt32)
C Intrinsic Prototype: Word64 Q6_P_vavgh_PP(Word64 Rss, Word64 Rtt)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vavgh_PP __builtin_HEXAGON_A2_vavgh
/* ==========================================================================
Assembly Syntax: Rdd32=vavgh(Rss32,Rtt32):crnd
C Intrinsic Prototype: Word64 Q6_P_vavgh_PP_crnd(Word64 Rss, Word64 Rtt)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vavgh_PP_crnd __builtin_HEXAGON_A2_vavghcr
/* ==========================================================================
Assembly Syntax: Rdd32=vavgh(Rss32,Rtt32):rnd
C Intrinsic Prototype: Word64 Q6_P_vavgh_PP_rnd(Word64 Rss, Word64 Rtt)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vavgh_PP_rnd __builtin_HEXAGON_A2_vavghr
/* ==========================================================================
Assembly Syntax: Rdd32=vavgub(Rss32,Rtt32)
C Intrinsic Prototype: Word64 Q6_P_vavgub_PP(Word64 Rss, Word64 Rtt)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vavgub_PP __builtin_HEXAGON_A2_vavgub
/* ==========================================================================
Assembly Syntax: Rdd32=vavgub(Rss32,Rtt32):rnd
C Intrinsic Prototype: Word64 Q6_P_vavgub_PP_rnd(Word64 Rss, Word64 Rtt)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vavgub_PP_rnd __builtin_HEXAGON_A2_vavgubr
/* ==========================================================================
Assembly Syntax: Rdd32=vavguh(Rss32,Rtt32)
C Intrinsic Prototype: Word64 Q6_P_vavguh_PP(Word64 Rss, Word64 Rtt)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vavguh_PP __builtin_HEXAGON_A2_vavguh
/* ==========================================================================
Assembly Syntax: Rdd32=vavguh(Rss32,Rtt32):rnd
C Intrinsic Prototype: Word64 Q6_P_vavguh_PP_rnd(Word64 Rss, Word64 Rtt)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vavguh_PP_rnd __builtin_HEXAGON_A2_vavguhr
/* ==========================================================================
Assembly Syntax: Rdd32=vavguw(Rss32,Rtt32)
C Intrinsic Prototype: Word64 Q6_P_vavguw_PP(Word64 Rss, Word64 Rtt)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vavguw_PP __builtin_HEXAGON_A2_vavguw
/* ==========================================================================
Assembly Syntax: Rdd32=vavguw(Rss32,Rtt32):rnd
C Intrinsic Prototype: Word64 Q6_P_vavguw_PP_rnd(Word64 Rss, Word64 Rtt)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vavguw_PP_rnd __builtin_HEXAGON_A2_vavguwr
/* ==========================================================================
Assembly Syntax: Rdd32=vavgw(Rss32,Rtt32)
C Intrinsic Prototype: Word64 Q6_P_vavgw_PP(Word64 Rss, Word64 Rtt)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vavgw_PP __builtin_HEXAGON_A2_vavgw
/* ==========================================================================
Assembly Syntax: Rdd32=vavgw(Rss32,Rtt32):crnd
C Intrinsic Prototype: Word64 Q6_P_vavgw_PP_crnd(Word64 Rss, Word64 Rtt)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vavgw_PP_crnd __builtin_HEXAGON_A2_vavgwcr
/* ==========================================================================
Assembly Syntax: Rdd32=vavgw(Rss32,Rtt32):rnd
C Intrinsic Prototype: Word64 Q6_P_vavgw_PP_rnd(Word64 Rss, Word64 Rtt)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vavgw_PP_rnd __builtin_HEXAGON_A2_vavgwr
/* ==========================================================================
Assembly Syntax: Pd4=vcmpb.eq(Rss32,Rtt32)
C Intrinsic Prototype: Byte Q6_p_vcmpb_eq_PP(Word64 Rss, Word64 Rtt)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_vcmpb_eq_PP __builtin_HEXAGON_A2_vcmpbeq
/* ==========================================================================
Assembly Syntax: Pd4=vcmpb.gtu(Rss32,Rtt32)
C Intrinsic Prototype: Byte Q6_p_vcmpb_gtu_PP(Word64 Rss, Word64 Rtt)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_vcmpb_gtu_PP __builtin_HEXAGON_A2_vcmpbgtu
/* ==========================================================================
Assembly Syntax: Pd4=vcmph.eq(Rss32,Rtt32)
C Intrinsic Prototype: Byte Q6_p_vcmph_eq_PP(Word64 Rss, Word64 Rtt)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_vcmph_eq_PP __builtin_HEXAGON_A2_vcmpheq
/* ==========================================================================
Assembly Syntax: Pd4=vcmph.gt(Rss32,Rtt32)
C Intrinsic Prototype: Byte Q6_p_vcmph_gt_PP(Word64 Rss, Word64 Rtt)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_vcmph_gt_PP __builtin_HEXAGON_A2_vcmphgt
/* ==========================================================================
Assembly Syntax: Pd4=vcmph.gtu(Rss32,Rtt32)
C Intrinsic Prototype: Byte Q6_p_vcmph_gtu_PP(Word64 Rss, Word64 Rtt)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_vcmph_gtu_PP __builtin_HEXAGON_A2_vcmphgtu
/* ==========================================================================
Assembly Syntax: Pd4=vcmpw.eq(Rss32,Rtt32)
C Intrinsic Prototype: Byte Q6_p_vcmpw_eq_PP(Word64 Rss, Word64 Rtt)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_vcmpw_eq_PP __builtin_HEXAGON_A2_vcmpweq
/* ==========================================================================
Assembly Syntax: Pd4=vcmpw.gt(Rss32,Rtt32)
C Intrinsic Prototype: Byte Q6_p_vcmpw_gt_PP(Word64 Rss, Word64 Rtt)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_vcmpw_gt_PP __builtin_HEXAGON_A2_vcmpwgt
/* ==========================================================================
Assembly Syntax: Pd4=vcmpw.gtu(Rss32,Rtt32)
C Intrinsic Prototype: Byte Q6_p_vcmpw_gtu_PP(Word64 Rss, Word64 Rtt)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_vcmpw_gtu_PP __builtin_HEXAGON_A2_vcmpwgtu
/* ==========================================================================
Assembly Syntax: Rdd32=vconj(Rss32):sat
C Intrinsic Prototype: Word64 Q6_P_vconj_P_sat(Word64 Rss)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vconj_P_sat __builtin_HEXAGON_A2_vconj
/* ==========================================================================
Assembly Syntax: Rdd32=vmaxb(Rtt32,Rss32)
C Intrinsic Prototype: Word64 Q6_P_vmaxb_PP(Word64 Rtt, Word64 Rss)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vmaxb_PP __builtin_HEXAGON_A2_vmaxb
/* ==========================================================================
Assembly Syntax: Rdd32=vmaxh(Rtt32,Rss32)
C Intrinsic Prototype: Word64 Q6_P_vmaxh_PP(Word64 Rtt, Word64 Rss)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vmaxh_PP __builtin_HEXAGON_A2_vmaxh
/* ==========================================================================
Assembly Syntax: Rdd32=vmaxub(Rtt32,Rss32)
C Intrinsic Prototype: Word64 Q6_P_vmaxub_PP(Word64 Rtt, Word64 Rss)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vmaxub_PP __builtin_HEXAGON_A2_vmaxub
/* ==========================================================================
Assembly Syntax: Rdd32=vmaxuh(Rtt32,Rss32)
C Intrinsic Prototype: Word64 Q6_P_vmaxuh_PP(Word64 Rtt, Word64 Rss)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vmaxuh_PP __builtin_HEXAGON_A2_vmaxuh
/* ==========================================================================
Assembly Syntax: Rdd32=vmaxuw(Rtt32,Rss32)
C Intrinsic Prototype: Word64 Q6_P_vmaxuw_PP(Word64 Rtt, Word64 Rss)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vmaxuw_PP __builtin_HEXAGON_A2_vmaxuw
/* ==========================================================================
Assembly Syntax: Rdd32=vmaxw(Rtt32,Rss32)
C Intrinsic Prototype: Word64 Q6_P_vmaxw_PP(Word64 Rtt, Word64 Rss)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vmaxw_PP __builtin_HEXAGON_A2_vmaxw
/* ==========================================================================
Assembly Syntax: Rdd32=vminb(Rtt32,Rss32)
C Intrinsic Prototype: Word64 Q6_P_vminb_PP(Word64 Rtt, Word64 Rss)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vminb_PP __builtin_HEXAGON_A2_vminb
/* ==========================================================================
Assembly Syntax: Rdd32=vminh(Rtt32,Rss32)
C Intrinsic Prototype: Word64 Q6_P_vminh_PP(Word64 Rtt, Word64 Rss)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vminh_PP __builtin_HEXAGON_A2_vminh
/* ==========================================================================
Assembly Syntax: Rdd32=vminub(Rtt32,Rss32)
C Intrinsic Prototype: Word64 Q6_P_vminub_PP(Word64 Rtt, Word64 Rss)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vminub_PP __builtin_HEXAGON_A2_vminub
/* ==========================================================================
Assembly Syntax: Rdd32=vminuh(Rtt32,Rss32)
C Intrinsic Prototype: Word64 Q6_P_vminuh_PP(Word64 Rtt, Word64 Rss)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vminuh_PP __builtin_HEXAGON_A2_vminuh
/* ==========================================================================
Assembly Syntax: Rdd32=vminuw(Rtt32,Rss32)
C Intrinsic Prototype: Word64 Q6_P_vminuw_PP(Word64 Rtt, Word64 Rss)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vminuw_PP __builtin_HEXAGON_A2_vminuw
/* ==========================================================================
Assembly Syntax: Rdd32=vminw(Rtt32,Rss32)
C Intrinsic Prototype: Word64 Q6_P_vminw_PP(Word64 Rtt, Word64 Rss)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vminw_PP __builtin_HEXAGON_A2_vminw
/* ==========================================================================
Assembly Syntax: Rdd32=vnavgh(Rtt32,Rss32)
C Intrinsic Prototype: Word64 Q6_P_vnavgh_PP(Word64 Rtt, Word64 Rss)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vnavgh_PP __builtin_HEXAGON_A2_vnavgh
/* ==========================================================================
Assembly Syntax: Rdd32=vnavgh(Rtt32,Rss32):crnd:sat
C Intrinsic Prototype: Word64 Q6_P_vnavgh_PP_crnd_sat(Word64 Rtt, Word64 Rss)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vnavgh_PP_crnd_sat __builtin_HEXAGON_A2_vnavghcr
/* ==========================================================================
Assembly Syntax: Rdd32=vnavgh(Rtt32,Rss32):rnd:sat
C Intrinsic Prototype: Word64 Q6_P_vnavgh_PP_rnd_sat(Word64 Rtt, Word64 Rss)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vnavgh_PP_rnd_sat __builtin_HEXAGON_A2_vnavghr
/* ==========================================================================
Assembly Syntax: Rdd32=vnavgw(Rtt32,Rss32)
C Intrinsic Prototype: Word64 Q6_P_vnavgw_PP(Word64 Rtt, Word64 Rss)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vnavgw_PP __builtin_HEXAGON_A2_vnavgw
/* ==========================================================================
Assembly Syntax: Rdd32=vnavgw(Rtt32,Rss32):crnd:sat
C Intrinsic Prototype: Word64 Q6_P_vnavgw_PP_crnd_sat(Word64 Rtt, Word64 Rss)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vnavgw_PP_crnd_sat __builtin_HEXAGON_A2_vnavgwcr
/* ==========================================================================
Assembly Syntax: Rdd32=vnavgw(Rtt32,Rss32):rnd:sat
C Intrinsic Prototype: Word64 Q6_P_vnavgw_PP_rnd_sat(Word64 Rtt, Word64 Rss)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vnavgw_PP_rnd_sat __builtin_HEXAGON_A2_vnavgwr
/* ==========================================================================
Assembly Syntax: Rdd32=vraddub(Rss32,Rtt32)
C Intrinsic Prototype: Word64 Q6_P_vraddub_PP(Word64 Rss, Word64 Rtt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vraddub_PP __builtin_HEXAGON_A2_vraddub
/* ==========================================================================
Assembly Syntax: Rxx32+=vraddub(Rss32,Rtt32)
C Intrinsic Prototype: Word64 Q6_P_vraddubacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vraddubacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vraddubacc_PP(Word64 Rxx, Word64 Rss,
+   Word64 Rtt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_vraddubacc_PP…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vraddubacc_PP __builtin_HEXAGON_A2_vraddub_acc
/* ==========================================================================
Assembly Syntax: Rdd32=vrsadub(Rss32,Rtt32)
C Intrinsic Prototype: Word64 Q6_P_vrsadub_PP(Word64 Rss, Word64 Rtt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vrsadub_PP __builtin_HEXAGON_A2_vrsadub
/* ==========================================================================
Assembly Syntax: Rxx32+=vrsadub(Rss32,Rtt32)
C Intrinsic Prototype: Word64 Q6_P_vrsadubacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vrsadubacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vrsadubacc_PP(Word64 Rxx, Word64 Rss,
+   Word64 Rtt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_vrsadubacc_PP…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vrsadubacc_PP __builtin_HEXAGON_A2_vrsadub_acc
/* ==========================================================================
Assembly Syntax: Rdd32=vsubb(Rss32,Rtt32)
C Intrinsic Prototype: Word64 Q6_P_vsubb_PP(Word64 Rss, Word64 Rtt)
Instruction Type: MAPPING
Execution Slots: SLOT0123
========================================================================== */
#define Q6_P_vsubb_PP __builtin_HEXAGON_A2_vsubb_map
/* ==========================================================================
Assembly Syntax: Rdd32=vsubh(Rtt32,Rss32)
C Intrinsic Prototype: Word64 Q6_P_vsubh_PP(Word64 Rtt, Word64 Rss)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vsubh_PP __builtin_HEXAGON_A2_vsubh
/* ==========================================================================
Assembly Syntax: Rdd32=vsubh(Rtt32,Rss32):sat
C Intrinsic Prototype: Word64 Q6_P_vsubh_PP_sat(Word64 Rtt, Word64 Rss)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vsubh_PP_sat __builtin_HEXAGON_A2_vsubhs
/* ==========================================================================
Assembly Syntax: Rdd32=vsubub(Rtt32,Rss32)
C Intrinsic Prototype: Word64 Q6_P_vsubub_PP(Word64 Rtt, Word64 Rss)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vsubub_PP __builtin_HEXAGON_A2_vsubub
/* ==========================================================================
Assembly Syntax: Rdd32=vsubub(Rtt32,Rss32):sat
C Intrinsic Prototype: Word64 Q6_P_vsubub_PP_sat(Word64 Rtt, Word64 Rss)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vsubub_PP_sat __builtin_HEXAGON_A2_vsububs
/* ==========================================================================
Assembly Syntax: Rdd32=vsubuh(Rtt32,Rss32):sat
C Intrinsic Prototype: Word64 Q6_P_vsubuh_PP_sat(Word64 Rtt, Word64 Rss)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vsubuh_PP_sat __builtin_HEXAGON_A2_vsubuhs
/* ==========================================================================
Assembly Syntax: Rdd32=vsubw(Rtt32,Rss32)
C Intrinsic Prototype: Word64 Q6_P_vsubw_PP(Word64 Rtt, Word64 Rss)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vsubw_PP __builtin_HEXAGON_A2_vsubw
/* ==========================================================================
Assembly Syntax: Rdd32=vsubw(Rtt32,Rss32):sat
C Intrinsic Prototype: Word64 Q6_P_vsubw_PP_sat(Word64 Rtt, Word64 Rss)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vsubw_PP_sat __builtin_HEXAGON_A2_vsubws
/* ==========================================================================
Assembly Syntax: Rd32=xor(Rs32,Rt32)
C Intrinsic Prototype: Word32 Q6_R_xor_RR(Word32 Rs, Word32 Rt)
Instruction Type: ALU32_3op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_R_xor_RR __builtin_HEXAGON_A2_xor
/* ==========================================================================
Assembly Syntax: Rdd32=xor(Rss32,Rtt32)
C Intrinsic Prototype: Word64 Q6_P_xor_PP(Word64 Rss, Word64 Rtt)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_xor_PP __builtin_HEXAGON_A2_xorp
/* ==========================================================================
Assembly Syntax: Rd32=zxtb(Rs32)
C Intrinsic Prototype: Word32 Q6_R_zxtb_R(Word32 Rs)
Instruction Type: ALU32_2op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_R_zxtb_R __builtin_HEXAGON_A2_zxtb
/* ==========================================================================
Assembly Syntax: Rd32=zxth(Rs32)
C Intrinsic Prototype: Word32 Q6_R_zxth_R(Word32 Rs)
Instruction Type: ALU32_2op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_R_zxth_R __builtin_HEXAGON_A2_zxth
/* ==========================================================================
Assembly Syntax: Rd32=and(Rt32,~Rs32)
C Intrinsic Prototype: Word32 Q6_R_and_RnR(Word32 Rt, Word32 Rs)
Instruction Type: ALU32_3op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_R_and_RnR __builtin_HEXAGON_A4_andn
/* ==========================================================================
Assembly Syntax: Rdd32=and(Rtt32,~Rss32)
C Intrinsic Prototype: Word64 Q6_P_and_PnP(Word64 Rtt, Word64 Rss)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_and_PnP __builtin_HEXAGON_A4_andnp
/* ==========================================================================
Assembly Syntax: Rdd32=bitsplit(Rs32,Rt32)
C Intrinsic Prototype: Word64 Q6_P_bitsplit_RR(Word32 Rs, Word32 Rt)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_bitsplit_RR __builtin_HEXAGON_A4_bitsplit
/* ==========================================================================
Assembly Syntax: Rdd32=bitsplit(Rs32,#u5)
C Intrinsic Prototype: Word64 Q6_P_bitsplit_RI(Word32 Rs, Word32 Iu5)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_bitsplit_RI __builtin_HEXAGON_A4_bitspliti
/* ==========================================================================
Assembly Syntax: Pd4=boundscheck(Rs32,Rtt32)
C Intrinsic Prototype: Byte Q6_p_boundscheck_RP(Word32 Rs, Word64 Rtt)
Instruction Type: ALU64
Execution Slots: SLOT0123
========================================================================== */
#define Q6_p_boundscheck_RP __builtin_HEXAGON_A4_boundscheck
/* ==========================================================================
Assembly Syntax: Pd4=cmpb.eq(Rs32,Rt32)
C Intrinsic Prototype: Byte Q6_p_cmpb_eq_RR(Word32 Rs, Word32 Rt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_cmpb_eq_RR __builtin_HEXAGON_A4_cmpbeq
/* ==========================================================================
Assembly Syntax: Pd4=cmpb.eq(Rs32,#u8)
C Intrinsic Prototype: Byte Q6_p_cmpb_eq_RI(Word32 Rs, Word32 Iu8)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_cmpb_eq_RI __builtin_HEXAGON_A4_cmpbeqi
/* ==========================================================================
Assembly Syntax: Pd4=cmpb.gt(Rs32,Rt32)
C Intrinsic Prototype: Byte Q6_p_cmpb_gt_RR(Word32 Rs, Word32 Rt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_cmpb_gt_RR __builtin_HEXAGON_A4_cmpbgt
/* ==========================================================================
Assembly Syntax: Pd4=cmpb.gt(Rs32,#s8)
C Intrinsic Prototype: Byte Q6_p_cmpb_gt_RI(Word32 Rs, Word32 Is8)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_cmpb_gt_RI __builtin_HEXAGON_A4_cmpbgti
/* ==========================================================================
Assembly Syntax: Pd4=cmpb.gtu(Rs32,Rt32)
C Intrinsic Prototype: Byte Q6_p_cmpb_gtu_RR(Word32 Rs, Word32 Rt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_cmpb_gtu_RR __builtin_HEXAGON_A4_cmpbgtu
/* ==========================================================================
Assembly Syntax: Pd4=cmpb.gtu(Rs32,#u7)
C Intrinsic Prototype: Byte Q6_p_cmpb_gtu_RI(Word32 Rs, Word32 Iu7)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_cmpb_gtu_RI __builtin_HEXAGON_A4_cmpbgtui
/* ==========================================================================
Assembly Syntax: Pd4=cmph.eq(Rs32,Rt32)
C Intrinsic Prototype: Byte Q6_p_cmph_eq_RR(Word32 Rs, Word32 Rt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_cmph_eq_RR __builtin_HEXAGON_A4_cmpheq
/* ==========================================================================
Assembly Syntax: Pd4=cmph.eq(Rs32,#s8)
C Intrinsic Prototype: Byte Q6_p_cmph_eq_RI(Word32 Rs, Word32 Is8)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_cmph_eq_RI __builtin_HEXAGON_A4_cmpheqi
/* ==========================================================================
Assembly Syntax: Pd4=cmph.gt(Rs32,Rt32)
C Intrinsic Prototype: Byte Q6_p_cmph_gt_RR(Word32 Rs, Word32 Rt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_cmph_gt_RR __builtin_HEXAGON_A4_cmphgt
/* ==========================================================================
Assembly Syntax: Pd4=cmph.gt(Rs32,#s8)
C Intrinsic Prototype: Byte Q6_p_cmph_gt_RI(Word32 Rs, Word32 Is8)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_cmph_gt_RI __builtin_HEXAGON_A4_cmphgti
/* ==========================================================================
Assembly Syntax: Pd4=cmph.gtu(Rs32,Rt32)
C Intrinsic Prototype: Byte Q6_p_cmph_gtu_RR(Word32 Rs, Word32 Rt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_cmph_gtu_RR __builtin_HEXAGON_A4_cmphgtu
/* ==========================================================================
Assembly Syntax: Pd4=cmph.gtu(Rs32,#u7)
C Intrinsic Prototype: Byte Q6_p_cmph_gtu_RI(Word32 Rs, Word32 Iu7)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_cmph_gtu_RI __builtin_HEXAGON_A4_cmphgtui
/* ==========================================================================
Assembly Syntax: Rdd32=combine(#s8,Rs32)
C Intrinsic Prototype: Word64 Q6_P_combine_IR(Word32 Is8, Word32 Rs)
Instruction Type: ALU32_2op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_P_combine_IR __builtin_HEXAGON_A4_combineir
/* ==========================================================================
Assembly Syntax: Rdd32=combine(Rs32,#s8)
C Intrinsic Prototype: Word64 Q6_P_combine_RI(Word32 Rs, Word32 Is8)
Instruction Type: ALU32_2op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_P_combine_RI __builtin_HEXAGON_A4_combineri
/* ==========================================================================
Assembly Syntax: Rd32=cround(Rs32,#u5)
C Intrinsic Prototype: Word32 Q6_R_cround_RI(Word32 Rs, Word32 Iu5)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_cround_RI __builtin_HEXAGON_A4_cround_ri
/* ==========================================================================
Assembly Syntax: Rd32=cround(Rs32,Rt32)
C Intrinsic Prototype: Word32 Q6_R_cround_RR(Word32 Rs, Word32 Rt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_cround_RR __builtin_HEXAGON_A4_cround_rr
/* ==========================================================================
Assembly Syntax: Rd32=modwrap(Rs32,Rt32)
C Intrinsic Prototype: Word32 Q6_R_modwrap_RR(Word32 Rs, Word32 Rt)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_modwrap_RR __builtin_HEXAGON_A4_modwrapu
/* ==========================================================================
Assembly Syntax: Rd32=or(Rt32,~Rs32)
C Intrinsic Prototype: Word32 Q6_R_or_RnR(Word32 Rt, Word32 Rs)
Instruction Type: ALU32_3op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_R_or_RnR __builtin_HEXAGON_A4_orn
/* ==========================================================================
Assembly Syntax: Rdd32=or(Rtt32,~Rss32)
C Intrinsic Prototype: Word64 Q6_P_or_PnP(Word64 Rtt, Word64 Rss)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_or_PnP __builtin_HEXAGON_A4_ornp
/* ==========================================================================
Assembly Syntax: Rd32=cmp.eq(Rs32,Rt32)
C Intrinsic Prototype: Word32 Q6_R_cmp_eq_RR(Word32 Rs, Word32 Rt)
Instruction Type: ALU32_3op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_R_cmp_eq_RR __builtin_HEXAGON_A4_rcmpeq
/* ==========================================================================
Assembly Syntax: Rd32=cmp.eq(Rs32,#s8)
C Intrinsic Prototype: Word32 Q6_R_cmp_eq_RI(Word32 Rs, Word32 Is8)
Instruction Type: ALU32_2op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_R_cmp_eq_RI __builtin_HEXAGON_A4_rcmpeqi
/* ==========================================================================
Assembly Syntax: Rd32=!cmp.eq(Rs32,Rt32)
C Intrinsic Prototype: Word32 Q6_R_not_cmp_eq_RR(Word32 Rs, Word32 Rt)
Instruction Type: ALU32_3op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_R_not_cmp_eq_RR __builtin_HEXAGON_A4_rcmpneq
/* ==========================================================================
Assembly Syntax: Rd32=!cmp.eq(Rs32,#s8)
C Intrinsic Prototype: Word32 Q6_R_not_cmp_eq_RI(Word32 Rs, Word32 Is8)
Instruction Type: ALU32_2op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_R_not_cmp_eq_RI __builtin_HEXAGON_A4_rcmpneqi
/* ==========================================================================
Assembly Syntax: Rd32=round(Rs32,#u5)
C Intrinsic Prototype: Word32 Q6_R_round_RI(Word32 Rs, Word32 Iu5)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_round_RI __builtin_HEXAGON_A4_round_ri
/* ==========================================================================
Assembly Syntax: Rd32=round(Rs32,#u5):sat
C Intrinsic Prototype: Word32 Q6_R_round_RI_sat(Word32 Rs, Word32 Iu5)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_round_RI_sat __builtin_HEXAGON_A4_round_ri_sat
/* ==========================================================================
Assembly Syntax: Rd32=round(Rs32,Rt32)
C Intrinsic Prototype: Word32 Q6_R_round_RR(Word32 Rs, Word32 Rt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_round_RR __builtin_HEXAGON_A4_round_rr
/* ==========================================================================
Assembly Syntax: Rd32=round(Rs32,Rt32):sat
C Intrinsic Prototype: Word32 Q6_R_round_RR_sat(Word32 Rs, Word32 Rt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_round_RR_sat __builtin_HEXAGON_A4_round_rr_sat
/* ==========================================================================
Assembly Syntax: Pd4=tlbmatch(Rss32,Rt32)
C Intrinsic Prototype: Byte Q6_p_tlbmatch_PR(Word64 Rss, Word32 Rt)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_tlbmatch_PR __builtin_HEXAGON_A4_tlbmatch
/* ==========================================================================
Assembly Syntax: Pd4=any8(vcmpb.eq(Rss32,Rtt32))
C Intrinsic Prototype: Byte Q6_p_any8_vcmpb_eq_PP(Word64 Rss, Word64 Rtt)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_any8_vcmpb_eq_PP __builtin_HEXAGON_A4_vcmpbeq_any
/* ==========================================================================
Assembly Syntax: Pd4=vcmpb.eq(Rss32,#u8)
C Intrinsic Prototype: Byte Q6_p_vcmpb_eq_PI(Word64 Rss, Word32 Iu8)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_vcmpb_eq_PI __builtin_HEXAGON_A4_vcmpbeqi
/* ==========================================================================
Assembly Syntax: Pd4=vcmpb.gt(Rss32,Rtt32)
C Intrinsic Prototype: Byte Q6_p_vcmpb_gt_PP(Word64 Rss, Word64 Rtt)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_vcmpb_gt_PP __builtin_HEXAGON_A4_vcmpbgt
/* ==========================================================================
Assembly Syntax: Pd4=vcmpb.gt(Rss32,#s8)
C Intrinsic Prototype: Byte Q6_p_vcmpb_gt_PI(Word64 Rss, Word32 Is8)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_vcmpb_gt_PI __builtin_HEXAGON_A4_vcmpbgti
/* ==========================================================================
Assembly Syntax: Pd4=vcmpb.gtu(Rss32,#u7)
C Intrinsic Prototype: Byte Q6_p_vcmpb_gtu_PI(Word64 Rss, Word32 Iu7)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_vcmpb_gtu_PI __builtin_HEXAGON_A4_vcmpbgtui
/* ==========================================================================
Assembly Syntax: Pd4=vcmph.eq(Rss32,#s8)
C Intrinsic Prototype: Byte Q6_p_vcmph_eq_PI(Word64 Rss, Word32 Is8)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_vcmph_eq_PI __builtin_HEXAGON_A4_vcmpheqi
/* ==========================================================================
Assembly Syntax: Pd4=vcmph.gt(Rss32,#s8)
C Intrinsic Prototype: Byte Q6_p_vcmph_gt_PI(Word64 Rss, Word32 Is8)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_vcmph_gt_PI __builtin_HEXAGON_A4_vcmphgti
/* ==========================================================================
Assembly Syntax: Pd4=vcmph.gtu(Rss32,#u7)
C Intrinsic Prototype: Byte Q6_p_vcmph_gtu_PI(Word64 Rss, Word32 Iu7)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_vcmph_gtu_PI __builtin_HEXAGON_A4_vcmphgtui
/* ==========================================================================
Assembly Syntax: Pd4=vcmpw.eq(Rss32,#s8)
C Intrinsic Prototype: Byte Q6_p_vcmpw_eq_PI(Word64 Rss, Word32 Is8)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_vcmpw_eq_PI __builtin_HEXAGON_A4_vcmpweqi
/* ==========================================================================
Assembly Syntax: Pd4=vcmpw.gt(Rss32,#s8)
C Intrinsic Prototype: Byte Q6_p_vcmpw_gt_PI(Word64 Rss, Word32 Is8)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_vcmpw_gt_PI __builtin_HEXAGON_A4_vcmpwgti
/* ==========================================================================
Assembly Syntax: Pd4=vcmpw.gtu(Rss32,#u7)
C Intrinsic Prototype: Byte Q6_p_vcmpw_gtu_PI(Word64 Rss, Word32 Iu7)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_vcmpw_gtu_PI __builtin_HEXAGON_A4_vcmpwgtui
/* ==========================================================================
Assembly Syntax: Rxx32=vrmaxh(Rss32,Ru32)
C Intrinsic Prototype: Word64 Q6_P_vrmaxh_PR(Word64 Rxx, Word64 Rss, Word32 Ru)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vrmaxh_PR(Word64 Rxx, Word64 Rss, Word32 Ru)
-   Instruction Type:      S_3op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vrmaxh_PR(Word64 Rxx, Word64 Rss, Word32
+   Ru) Instruction Type:      S_3op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_vrmaxh_PR…
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vrmaxh_PR __builtin_HEXAGON_A4_vrmaxh
/* ==========================================================================
Assembly Syntax: Rxx32=vrmaxuh(Rss32,Ru32)
C Intrinsic Prototype: Word64 Q6_P_vrmaxuh_PR(Word64 Rxx, Word64 Rss, Word32 Ru)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vrmaxuh_PR(Word64 Rxx, Word64 Rss, Word32 Ru)
-   Instruction Type:      S_3op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vrmaxuh_PR(Word64 Rxx, Word64 Rss, Word32
+   Ru) Instruction Type:      S_3op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_vrmaxuh_PR…
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vrmaxuh_PR __builtin_HEXAGON_A4_vrmaxuh
/* ==========================================================================
Assembly Syntax: Rxx32=vrmaxuw(Rss32,Ru32)
C Intrinsic Prototype: Word64 Q6_P_vrmaxuw_PR(Word64 Rxx, Word64 Rss, Word32 Ru)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vrmaxuw_PR(Word64 Rxx, Word64 Rss, Word32 Ru)
-   Instruction Type:      S_3op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vrmaxuw_PR(Word64 Rxx, Word64 Rss, Word32
+   Ru) Instruction Type:      S_3op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_vrmaxuw_PR…
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vrmaxuw_PR __builtin_HEXAGON_A4_vrmaxuw
/* ==========================================================================
Assembly Syntax: Rxx32=vrmaxw(Rss32,Ru32)
C Intrinsic Prototype: Word64 Q6_P_vrmaxw_PR(Word64 Rxx, Word64 Rss, Word32 Ru)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vrmaxw_PR(Word64 Rxx, Word64 Rss, Word32 Ru)
-   Instruction Type:      S_3op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vrmaxw_PR(Word64 Rxx, Word64 Rss, Word32
+   Ru) Instruction Type:      S_3op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_vrmaxw_PR…
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vrmaxw_PR __builtin_HEXAGON_A4_vrmaxw
/* ==========================================================================
Assembly Syntax: Rxx32=vrminh(Rss32,Ru32)
C Intrinsic Prototype: Word64 Q6_P_vrminh_PR(Word64 Rxx, Word64 Rss, Word32 Ru)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vrminh_PR(Word64 Rxx, Word64 Rss, Word32 Ru)
-   Instruction Type:      S_3op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vrminh_PR(Word64 Rxx, Word64 Rss, Word32
+   Ru) Instruction Type:      S_3op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_vrminh_PR…
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vrminh_PR __builtin_HEXAGON_A4_vrminh
/* ==========================================================================
Assembly Syntax: Rxx32=vrminuh(Rss32,Ru32)
C Intrinsic Prototype: Word64 Q6_P_vrminuh_PR(Word64 Rxx, Word64 Rss, Word32 Ru)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vrminuh_PR(Word64 Rxx, Word64 Rss, Word32 Ru)
-   Instruction Type:      S_3op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vrminuh_PR(Word64 Rxx, Word64 Rss, Word32
+   Ru) Instruction Type:      S_3op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_vrminuh_PR…
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vrminuh_PR __builtin_HEXAGON_A4_vrminuh
/* ==========================================================================
Assembly Syntax: Rxx32=vrminuw(Rss32,Ru32)
C Intrinsic Prototype: Word64 Q6_P_vrminuw_PR(Word64 Rxx, Word64 Rss, Word32 Ru)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vrminuw_PR(Word64 Rxx, Word64 Rss, Word32 Ru)
-   Instruction Type:      S_3op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vrminuw_PR(Word64 Rxx, Word64 Rss, Word32
+   Ru) Instruction Type:      S_3op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_vrminuw_PR…
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vrminuw_PR __builtin_HEXAGON_A4_vrminuw
/* ==========================================================================
Assembly Syntax: Rxx32=vrminw(Rss32,Ru32)
C Intrinsic Prototype: Word64 Q6_P_vrminw_PR(Word64 Rxx, Word64 Rss, Word32 Ru)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vrminw_PR(Word64 Rxx, Word64 Rss, Word32 Ru)
-   Instruction Type:      S_3op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vrminw_PR(Word64 Rxx, Word64 Rss, Word32
+   Ru) Instruction Type:      S_3op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_vrminw_PR…
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vrminw_PR __builtin_HEXAGON_A4_vrminw
/* ==========================================================================
Assembly Syntax: Rd32=vaddhub(Rss32,Rtt32):sat
C Intrinsic Prototype: Word32 Q6_R_vaddhub_PP_sat(Word64 Rss, Word64 Rtt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_vaddhub_PP_sat __builtin_HEXAGON_A5_vaddhubs
/* ==========================================================================
Assembly Syntax: Pd4=all8(Ps4)
C Intrinsic Prototype: Byte Q6_p_all8_p(Byte Ps)
Instruction Type: CR
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_all8_p __builtin_HEXAGON_C2_all8
/* ==========================================================================
Assembly Syntax: Pd4=and(Pt4,Ps4)
C Intrinsic Prototype: Byte Q6_p_and_pp(Byte Pt, Byte Ps)
Instruction Type: CR
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_and_pp __builtin_HEXAGON_C2_and
/* ==========================================================================
Assembly Syntax: Pd4=and(Pt4,!Ps4)
C Intrinsic Prototype: Byte Q6_p_and_pnp(Byte Pt, Byte Ps)
Instruction Type: CR
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_and_pnp __builtin_HEXAGON_C2_andn
/* ==========================================================================
Assembly Syntax: Pd4=any8(Ps4)
C Intrinsic Prototype: Byte Q6_p_any8_p(Byte Ps)
Instruction Type: CR
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_any8_p __builtin_HEXAGON_C2_any8
/* ==========================================================================
Assembly Syntax: Pd4=bitsclr(Rs32,Rt32)
C Intrinsic Prototype: Byte Q6_p_bitsclr_RR(Word32 Rs, Word32 Rt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_bitsclr_RR __builtin_HEXAGON_C2_bitsclr
/* ==========================================================================
Assembly Syntax: Pd4=bitsclr(Rs32,#u6)
C Intrinsic Prototype: Byte Q6_p_bitsclr_RI(Word32 Rs, Word32 Iu6)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_bitsclr_RI __builtin_HEXAGON_C2_bitsclri
/* ==========================================================================
Assembly Syntax: Pd4=bitsset(Rs32,Rt32)
C Intrinsic Prototype: Byte Q6_p_bitsset_RR(Word32 Rs, Word32 Rt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_bitsset_RR __builtin_HEXAGON_C2_bitsset
/* ==========================================================================
Assembly Syntax: Pd4=cmp.eq(Rs32,Rt32)
C Intrinsic Prototype: Byte Q6_p_cmp_eq_RR(Word32 Rs, Word32 Rt)
Instruction Type: ALU32_3op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_p_cmp_eq_RR __builtin_HEXAGON_C2_cmpeq
/* ==========================================================================
Assembly Syntax: Pd4=cmp.eq(Rs32,#s10)
C Intrinsic Prototype: Byte Q6_p_cmp_eq_RI(Word32 Rs, Word32 Is10)
Instruction Type: ALU32_2op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_p_cmp_eq_RI __builtin_HEXAGON_C2_cmpeqi
/* ==========================================================================
Assembly Syntax: Pd4=cmp.eq(Rss32,Rtt32)
C Intrinsic Prototype: Byte Q6_p_cmp_eq_PP(Word64 Rss, Word64 Rtt)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_cmp_eq_PP __builtin_HEXAGON_C2_cmpeqp
/* ==========================================================================
Assembly Syntax: Pd4=cmp.ge(Rs32,#s8)
C Intrinsic Prototype: Byte Q6_p_cmp_ge_RI(Word32 Rs, Word32 Is8)
Instruction Type: ALU32_2op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_p_cmp_ge_RI __builtin_HEXAGON_C2_cmpgei
/* ==========================================================================
Assembly Syntax: Pd4=cmp.geu(Rs32,#u8)
C Intrinsic Prototype: Byte Q6_p_cmp_geu_RI(Word32 Rs, Word32 Iu8)
Instruction Type: ALU32_2op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_p_cmp_geu_RI __builtin_HEXAGON_C2_cmpgeui
/* ==========================================================================
Assembly Syntax: Pd4=cmp.gt(Rs32,Rt32)
C Intrinsic Prototype: Byte Q6_p_cmp_gt_RR(Word32 Rs, Word32 Rt)
Instruction Type: ALU32_3op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_p_cmp_gt_RR __builtin_HEXAGON_C2_cmpgt
/* ==========================================================================
Assembly Syntax: Pd4=cmp.gt(Rs32,#s10)
C Intrinsic Prototype: Byte Q6_p_cmp_gt_RI(Word32 Rs, Word32 Is10)
Instruction Type: ALU32_2op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_p_cmp_gt_RI __builtin_HEXAGON_C2_cmpgti
/* ==========================================================================
Assembly Syntax: Pd4=cmp.gt(Rss32,Rtt32)
C Intrinsic Prototype: Byte Q6_p_cmp_gt_PP(Word64 Rss, Word64 Rtt)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_cmp_gt_PP __builtin_HEXAGON_C2_cmpgtp
/* ==========================================================================
Assembly Syntax: Pd4=cmp.gtu(Rs32,Rt32)
C Intrinsic Prototype: Byte Q6_p_cmp_gtu_RR(Word32 Rs, Word32 Rt)
Instruction Type: ALU32_3op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_p_cmp_gtu_RR __builtin_HEXAGON_C2_cmpgtu
/* ==========================================================================
Assembly Syntax: Pd4=cmp.gtu(Rs32,#u9)
C Intrinsic Prototype: Byte Q6_p_cmp_gtu_RI(Word32 Rs, Word32 Iu9)
Instruction Type: ALU32_2op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_p_cmp_gtu_RI __builtin_HEXAGON_C2_cmpgtui
/* ==========================================================================
Assembly Syntax: Pd4=cmp.gtu(Rss32,Rtt32)
C Intrinsic Prototype: Byte Q6_p_cmp_gtu_PP(Word64 Rss, Word64 Rtt)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_cmp_gtu_PP __builtin_HEXAGON_C2_cmpgtup
/* ==========================================================================
Assembly Syntax: Pd4=cmp.lt(Rs32,Rt32)
C Intrinsic Prototype: Byte Q6_p_cmp_lt_RR(Word32 Rs, Word32 Rt)
Instruction Type: ALU32_3op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_p_cmp_lt_RR __builtin_HEXAGON_C2_cmplt
/* ==========================================================================
Assembly Syntax: Pd4=cmp.ltu(Rs32,Rt32)
C Intrinsic Prototype: Byte Q6_p_cmp_ltu_RR(Word32 Rs, Word32 Rt)
Instruction Type: ALU32_3op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_p_cmp_ltu_RR __builtin_HEXAGON_C2_cmpltu
/* ==========================================================================
Assembly Syntax: Rdd32=mask(Pt4)
C Intrinsic Prototype: Word64 Q6_P_mask_p(Byte Pt)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mask_p __builtin_HEXAGON_C2_mask
/* ==========================================================================
Assembly Syntax: Rd32=mux(Pu4,Rs32,Rt32)
C Intrinsic Prototype: Word32 Q6_R_mux_pRR(Byte Pu, Word32 Rs, Word32 Rt)
Instruction Type: ALU32_3op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_R_mux_pRR __builtin_HEXAGON_C2_mux
/* ==========================================================================
Assembly Syntax: Rd32=mux(Pu4,#s8,#S8)
C Intrinsic Prototype: Word32 Q6_R_mux_pII(Byte Pu, Word32 Is8, Word32 IS8)
Instruction Type: ALU32_2op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_R_mux_pII __builtin_HEXAGON_C2_muxii
/* ==========================================================================
Assembly Syntax: Rd32=mux(Pu4,Rs32,#s8)
C Intrinsic Prototype: Word32 Q6_R_mux_pRI(Byte Pu, Word32 Rs, Word32 Is8)
Instruction Type: ALU32_2op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_R_mux_pRI __builtin_HEXAGON_C2_muxir
/* ==========================================================================
Assembly Syntax: Rd32=mux(Pu4,#s8,Rs32)
C Intrinsic Prototype: Word32 Q6_R_mux_pIR(Byte Pu, Word32 Is8, Word32 Rs)
Instruction Type: ALU32_2op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_R_mux_pIR __builtin_HEXAGON_C2_muxri
/* ==========================================================================
Assembly Syntax: Pd4=not(Ps4)
C Intrinsic Prototype: Byte Q6_p_not_p(Byte Ps)
Instruction Type: CR
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_not_p __builtin_HEXAGON_C2_not
/* ==========================================================================
Assembly Syntax: Pd4=or(Pt4,Ps4)
C Intrinsic Prototype: Byte Q6_p_or_pp(Byte Pt, Byte Ps)
Instruction Type: CR
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_or_pp __builtin_HEXAGON_C2_or
/* ==========================================================================
Assembly Syntax: Pd4=or(Pt4,!Ps4)
C Intrinsic Prototype: Byte Q6_p_or_pnp(Byte Pt, Byte Ps)
Instruction Type: CR
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_or_pnp __builtin_HEXAGON_C2_orn
/* ==========================================================================
Assembly Syntax: Pd4=Ps4
C Intrinsic Prototype: Byte Q6_p_equals_p(Byte Ps)
Instruction Type: MAPPING
Execution Slots: SLOT0123
========================================================================== */
#define Q6_p_equals_p __builtin_HEXAGON_C2_pxfer_map
/* ==========================================================================
Assembly Syntax: Rd32=Ps4
C Intrinsic Prototype: Word32 Q6_R_equals_p(Byte Ps)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_equals_p __builtin_HEXAGON_C2_tfrpr
/* ==========================================================================
Assembly Syntax: Pd4=Rs32
C Intrinsic Prototype: Byte Q6_p_equals_R(Word32 Rs)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_equals_R __builtin_HEXAGON_C2_tfrrp
/* ==========================================================================
Assembly Syntax: Rd32=vitpack(Ps4,Pt4)
C Intrinsic Prototype: Word32 Q6_R_vitpack_pp(Byte Ps, Byte Pt)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_vitpack_pp __builtin_HEXAGON_C2_vitpack
/* ==========================================================================
Assembly Syntax: Rdd32=vmux(Pu4,Rss32,Rtt32)
C Intrinsic Prototype: Word64 Q6_P_vmux_pPP(Byte Pu, Word64 Rss, Word64 Rtt)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vmux_pPP __builtin_HEXAGON_C2_vmux
/* ==========================================================================
Assembly Syntax: Pd4=xor(Ps4,Pt4)
C Intrinsic Prototype: Byte Q6_p_xor_pp(Byte Ps, Byte Pt)
Instruction Type: CR
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_xor_pp __builtin_HEXAGON_C2_xor
/* ==========================================================================
Assembly Syntax: Pd4=and(Ps4,and(Pt4,Pu4))
C Intrinsic Prototype: Byte Q6_p_and_and_ppp(Byte Ps, Byte Pt, Byte Pu)
Instruction Type: CR
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_and_and_ppp __builtin_HEXAGON_C4_and_and
/* ==========================================================================
Assembly Syntax: Pd4=and(Ps4,and(Pt4,!Pu4))
C Intrinsic Prototype: Byte Q6_p_and_and_ppnp(Byte Ps, Byte Pt, Byte Pu)
Instruction Type: CR
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_and_and_ppnp __builtin_HEXAGON_C4_and_andn
/* ==========================================================================
Assembly Syntax: Pd4=and(Ps4,or(Pt4,Pu4))
C Intrinsic Prototype: Byte Q6_p_and_or_ppp(Byte Ps, Byte Pt, Byte Pu)
Instruction Type: CR
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_and_or_ppp __builtin_HEXAGON_C4_and_or
/* ==========================================================================
Assembly Syntax: Pd4=and(Ps4,or(Pt4,!Pu4))
C Intrinsic Prototype: Byte Q6_p_and_or_ppnp(Byte Ps, Byte Pt, Byte Pu)
Instruction Type: CR
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_and_or_ppnp __builtin_HEXAGON_C4_and_orn
/* ==========================================================================
Assembly Syntax: Pd4=!cmp.gt(Rs32,Rt32)
C Intrinsic Prototype: Byte Q6_p_not_cmp_gt_RR(Word32 Rs, Word32 Rt)
Instruction Type: ALU32_3op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_p_not_cmp_gt_RR __builtin_HEXAGON_C4_cmplte
/* ==========================================================================
Assembly Syntax: Pd4=!cmp.gt(Rs32,#s10)
C Intrinsic Prototype: Byte Q6_p_not_cmp_gt_RI(Word32 Rs, Word32 Is10)
Instruction Type: ALU32_2op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_p_not_cmp_gt_RI __builtin_HEXAGON_C4_cmpltei
/* ==========================================================================
Assembly Syntax: Pd4=!cmp.gtu(Rs32,Rt32)
C Intrinsic Prototype: Byte Q6_p_not_cmp_gtu_RR(Word32 Rs, Word32 Rt)
Instruction Type: ALU32_3op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_p_not_cmp_gtu_RR __builtin_HEXAGON_C4_cmplteu
/* ==========================================================================
Assembly Syntax: Pd4=!cmp.gtu(Rs32,#u9)
C Intrinsic Prototype: Byte Q6_p_not_cmp_gtu_RI(Word32 Rs, Word32 Iu9)
Instruction Type: ALU32_2op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_p_not_cmp_gtu_RI __builtin_HEXAGON_C4_cmplteui
/* ==========================================================================
Assembly Syntax: Pd4=!cmp.eq(Rs32,Rt32)
C Intrinsic Prototype: Byte Q6_p_not_cmp_eq_RR(Word32 Rs, Word32 Rt)
Instruction Type: ALU32_3op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_p_not_cmp_eq_RR __builtin_HEXAGON_C4_cmpneq
/* ==========================================================================
Assembly Syntax: Pd4=!cmp.eq(Rs32,#s10)
C Intrinsic Prototype: Byte Q6_p_not_cmp_eq_RI(Word32 Rs, Word32 Is10)
Instruction Type: ALU32_2op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_p_not_cmp_eq_RI __builtin_HEXAGON_C4_cmpneqi
/* ==========================================================================
Assembly Syntax: Pd4=fastcorner9(Ps4,Pt4)
C Intrinsic Prototype: Byte Q6_p_fastcorner9_pp(Byte Ps, Byte Pt)
Instruction Type: CR
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_fastcorner9_pp __builtin_HEXAGON_C4_fastcorner9
/* ==========================================================================
Assembly Syntax: Pd4=!fastcorner9(Ps4,Pt4)
C Intrinsic Prototype: Byte Q6_p_not_fastcorner9_pp(Byte Ps, Byte Pt)
Instruction Type: CR
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_not_fastcorner9_pp __builtin_HEXAGON_C4_fastcorner9_not
/* ==========================================================================
Assembly Syntax: Pd4=!bitsclr(Rs32,Rt32)
C Intrinsic Prototype: Byte Q6_p_not_bitsclr_RR(Word32 Rs, Word32 Rt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_not_bitsclr_RR __builtin_HEXAGON_C4_nbitsclr
/* ==========================================================================
Assembly Syntax: Pd4=!bitsclr(Rs32,#u6)
C Intrinsic Prototype: Byte Q6_p_not_bitsclr_RI(Word32 Rs, Word32 Iu6)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_not_bitsclr_RI __builtin_HEXAGON_C4_nbitsclri
/* ==========================================================================
Assembly Syntax: Pd4=!bitsset(Rs32,Rt32)
C Intrinsic Prototype: Byte Q6_p_not_bitsset_RR(Word32 Rs, Word32 Rt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_not_bitsset_RR __builtin_HEXAGON_C4_nbitsset
/* ==========================================================================
Assembly Syntax: Pd4=or(Ps4,and(Pt4,Pu4))
C Intrinsic Prototype: Byte Q6_p_or_and_ppp(Byte Ps, Byte Pt, Byte Pu)
Instruction Type: CR
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_or_and_ppp __builtin_HEXAGON_C4_or_and
/* ==========================================================================
Assembly Syntax: Pd4=or(Ps4,and(Pt4,!Pu4))
C Intrinsic Prototype: Byte Q6_p_or_and_ppnp(Byte Ps, Byte Pt, Byte Pu)
Instruction Type: CR
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_or_and_ppnp __builtin_HEXAGON_C4_or_andn
/* ==========================================================================
Assembly Syntax: Pd4=or(Ps4,or(Pt4,Pu4))
C Intrinsic Prototype: Byte Q6_p_or_or_ppp(Byte Ps, Byte Pt, Byte Pu)
Instruction Type: CR
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_or_or_ppp __builtin_HEXAGON_C4_or_or
/* ==========================================================================
Assembly Syntax: Pd4=or(Ps4,or(Pt4,!Pu4))
C Intrinsic Prototype: Byte Q6_p_or_or_ppnp(Byte Ps, Byte Pt, Byte Pu)
Instruction Type: CR
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_or_or_ppnp __builtin_HEXAGON_C4_or_orn
/* ==========================================================================
Assembly Syntax: Rdd32=convert_d2df(Rss32)
C Intrinsic Prototype: Float64 Q6_P_convert_d2df_P(Word64 Rss)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_convert_d2df_P __builtin_HEXAGON_F2_conv_d2df
/* ==========================================================================
Assembly Syntax: Rd32=convert_d2sf(Rss32)
C Intrinsic Prototype: Float32 Q6_R_convert_d2sf_P(Word64 Rss)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_convert_d2sf_P __builtin_HEXAGON_F2_conv_d2sf
/* ==========================================================================
Assembly Syntax: Rdd32=convert_df2d(Rss32)
C Intrinsic Prototype: Word64 Q6_P_convert_df2d_P(Float64 Rss)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_convert_df2d_P __builtin_HEXAGON_F2_conv_df2d
/* ==========================================================================
Assembly Syntax: Rdd32=convert_df2d(Rss32):chop
C Intrinsic Prototype: Word64 Q6_P_convert_df2d_P_chop(Float64 Rss)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_convert_df2d_P_chop __builtin_HEXAGON_F2_conv_df2d_chop
/* ==========================================================================
Assembly Syntax: Rd32=convert_df2sf(Rss32)
C Intrinsic Prototype: Float32 Q6_R_convert_df2sf_P(Float64 Rss)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_convert_df2sf_P __builtin_HEXAGON_F2_conv_df2sf
/* ==========================================================================
Assembly Syntax: Rdd32=convert_df2ud(Rss32)
C Intrinsic Prototype: Word64 Q6_P_convert_df2ud_P(Float64 Rss)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_convert_df2ud_P __builtin_HEXAGON_F2_conv_df2ud
/* ==========================================================================
Assembly Syntax: Rdd32=convert_df2ud(Rss32):chop
C Intrinsic Prototype: Word64 Q6_P_convert_df2ud_P_chop(Float64 Rss)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_convert_df2ud_P_chop __builtin_HEXAGON_F2_conv_df2ud_chop
/* ==========================================================================
Assembly Syntax: Rd32=convert_df2uw(Rss32)
C Intrinsic Prototype: Word32 Q6_R_convert_df2uw_P(Float64 Rss)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_convert_df2uw_P __builtin_HEXAGON_F2_conv_df2uw
/* ==========================================================================
Assembly Syntax: Rd32=convert_df2uw(Rss32):chop
C Intrinsic Prototype: Word32 Q6_R_convert_df2uw_P_chop(Float64 Rss)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_convert_df2uw_P_chop __builtin_HEXAGON_F2_conv_df2uw_chop
/* ==========================================================================
Assembly Syntax: Rd32=convert_df2w(Rss32)
C Intrinsic Prototype: Word32 Q6_R_convert_df2w_P(Float64 Rss)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_convert_df2w_P __builtin_HEXAGON_F2_conv_df2w
/* ==========================================================================
Assembly Syntax: Rd32=convert_df2w(Rss32):chop
C Intrinsic Prototype: Word32 Q6_R_convert_df2w_P_chop(Float64 Rss)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_convert_df2w_P_chop __builtin_HEXAGON_F2_conv_df2w_chop
/* ==========================================================================
Assembly Syntax: Rdd32=convert_sf2d(Rs32)
C Intrinsic Prototype: Word64 Q6_P_convert_sf2d_R(Float32 Rs)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_convert_sf2d_R __builtin_HEXAGON_F2_conv_sf2d
/* ==========================================================================
Assembly Syntax: Rdd32=convert_sf2d(Rs32):chop
C Intrinsic Prototype: Word64 Q6_P_convert_sf2d_R_chop(Float32 Rs)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_convert_sf2d_R_chop __builtin_HEXAGON_F2_conv_sf2d_chop
/* ==========================================================================
Assembly Syntax: Rdd32=convert_sf2df(Rs32)
C Intrinsic Prototype: Float64 Q6_P_convert_sf2df_R(Float32 Rs)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_convert_sf2df_R __builtin_HEXAGON_F2_conv_sf2df
/* ==========================================================================
Assembly Syntax: Rdd32=convert_sf2ud(Rs32)
C Intrinsic Prototype: Word64 Q6_P_convert_sf2ud_R(Float32 Rs)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_convert_sf2ud_R __builtin_HEXAGON_F2_conv_sf2ud
/* ==========================================================================
Assembly Syntax: Rdd32=convert_sf2ud(Rs32):chop
C Intrinsic Prototype: Word64 Q6_P_convert_sf2ud_R_chop(Float32 Rs)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_convert_sf2ud_R_chop __builtin_HEXAGON_F2_conv_sf2ud_chop
/* ==========================================================================
Assembly Syntax: Rd32=convert_sf2uw(Rs32)
C Intrinsic Prototype: Word32 Q6_R_convert_sf2uw_R(Float32 Rs)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_convert_sf2uw_R __builtin_HEXAGON_F2_conv_sf2uw
/* ==========================================================================
Assembly Syntax: Rd32=convert_sf2uw(Rs32):chop
C Intrinsic Prototype: Word32 Q6_R_convert_sf2uw_R_chop(Float32 Rs)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_convert_sf2uw_R_chop __builtin_HEXAGON_F2_conv_sf2uw_chop
/* ==========================================================================
Assembly Syntax: Rd32=convert_sf2w(Rs32)
C Intrinsic Prototype: Word32 Q6_R_convert_sf2w_R(Float32 Rs)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_convert_sf2w_R __builtin_HEXAGON_F2_conv_sf2w
/* ==========================================================================
Assembly Syntax: Rd32=convert_sf2w(Rs32):chop
C Intrinsic Prototype: Word32 Q6_R_convert_sf2w_R_chop(Float32 Rs)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_convert_sf2w_R_chop __builtin_HEXAGON_F2_conv_sf2w_chop
/* ==========================================================================
Assembly Syntax: Rdd32=convert_ud2df(Rss32)
C Intrinsic Prototype: Float64 Q6_P_convert_ud2df_P(Word64 Rss)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_convert_ud2df_P __builtin_HEXAGON_F2_conv_ud2df
/* ==========================================================================
Assembly Syntax: Rd32=convert_ud2sf(Rss32)
C Intrinsic Prototype: Float32 Q6_R_convert_ud2sf_P(Word64 Rss)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_convert_ud2sf_P __builtin_HEXAGON_F2_conv_ud2sf
/* ==========================================================================
Assembly Syntax: Rdd32=convert_uw2df(Rs32)
C Intrinsic Prototype: Float64 Q6_P_convert_uw2df_R(Word32 Rs)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_convert_uw2df_R __builtin_HEXAGON_F2_conv_uw2df
/* ==========================================================================
Assembly Syntax: Rd32=convert_uw2sf(Rs32)
C Intrinsic Prototype: Float32 Q6_R_convert_uw2sf_R(Word32 Rs)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_convert_uw2sf_R __builtin_HEXAGON_F2_conv_uw2sf
/* ==========================================================================
Assembly Syntax: Rdd32=convert_w2df(Rs32)
C Intrinsic Prototype: Float64 Q6_P_convert_w2df_R(Word32 Rs)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_convert_w2df_R __builtin_HEXAGON_F2_conv_w2df
/* ==========================================================================
Assembly Syntax: Rd32=convert_w2sf(Rs32)
C Intrinsic Prototype: Float32 Q6_R_convert_w2sf_R(Word32 Rs)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_convert_w2sf_R __builtin_HEXAGON_F2_conv_w2sf
/* ==========================================================================
Assembly Syntax: Pd4=dfclass(Rss32,#u5)
C Intrinsic Prototype: Byte Q6_p_dfclass_PI(Float64 Rss, Word32 Iu5)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_dfclass_PI __builtin_HEXAGON_F2_dfclass
/* ==========================================================================
Assembly Syntax: Pd4=dfcmp.eq(Rss32,Rtt32)
C Intrinsic Prototype: Byte Q6_p_dfcmp_eq_PP(Float64 Rss, Float64 Rtt)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_dfcmp_eq_PP __builtin_HEXAGON_F2_dfcmpeq
/* ==========================================================================
Assembly Syntax: Pd4=dfcmp.ge(Rss32,Rtt32)
C Intrinsic Prototype: Byte Q6_p_dfcmp_ge_PP(Float64 Rss, Float64 Rtt)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_dfcmp_ge_PP __builtin_HEXAGON_F2_dfcmpge
/* ==========================================================================
Assembly Syntax: Pd4=dfcmp.gt(Rss32,Rtt32)
C Intrinsic Prototype: Byte Q6_p_dfcmp_gt_PP(Float64 Rss, Float64 Rtt)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_dfcmp_gt_PP __builtin_HEXAGON_F2_dfcmpgt
/* ==========================================================================
Assembly Syntax: Pd4=dfcmp.uo(Rss32,Rtt32)
C Intrinsic Prototype: Byte Q6_p_dfcmp_uo_PP(Float64 Rss, Float64 Rtt)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_dfcmp_uo_PP __builtin_HEXAGON_F2_dfcmpuo
/* ==========================================================================
Assembly Syntax: Rdd32=dfmake(#u10):neg
C Intrinsic Prototype: Float64 Q6_P_dfmake_I_neg(Word32 Iu10)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_dfmake_I_neg __builtin_HEXAGON_F2_dfimm_n
/* ==========================================================================
Assembly Syntax: Rdd32=dfmake(#u10):pos
C Intrinsic Prototype: Float64 Q6_P_dfmake_I_pos(Word32 Iu10)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_dfmake_I_pos __builtin_HEXAGON_F2_dfimm_p
/* ==========================================================================
Assembly Syntax: Rd32=sfadd(Rs32,Rt32)
C Intrinsic Prototype: Float32 Q6_R_sfadd_RR(Float32 Rs, Float32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_sfadd_RR __builtin_HEXAGON_F2_sfadd
/* ==========================================================================
Assembly Syntax: Pd4=sfclass(Rs32,#u5)
C Intrinsic Prototype: Byte Q6_p_sfclass_RI(Float32 Rs, Word32 Iu5)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_sfclass_RI __builtin_HEXAGON_F2_sfclass
/* ==========================================================================
Assembly Syntax: Pd4=sfcmp.eq(Rs32,Rt32)
C Intrinsic Prototype: Byte Q6_p_sfcmp_eq_RR(Float32 Rs, Float32 Rt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_sfcmp_eq_RR __builtin_HEXAGON_F2_sfcmpeq
/* ==========================================================================
Assembly Syntax: Pd4=sfcmp.ge(Rs32,Rt32)
C Intrinsic Prototype: Byte Q6_p_sfcmp_ge_RR(Float32 Rs, Float32 Rt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_sfcmp_ge_RR __builtin_HEXAGON_F2_sfcmpge
/* ==========================================================================
Assembly Syntax: Pd4=sfcmp.gt(Rs32,Rt32)
C Intrinsic Prototype: Byte Q6_p_sfcmp_gt_RR(Float32 Rs, Float32 Rt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_sfcmp_gt_RR __builtin_HEXAGON_F2_sfcmpgt
/* ==========================================================================
Assembly Syntax: Pd4=sfcmp.uo(Rs32,Rt32)
C Intrinsic Prototype: Byte Q6_p_sfcmp_uo_RR(Float32 Rs, Float32 Rt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_sfcmp_uo_RR __builtin_HEXAGON_F2_sfcmpuo
/* ==========================================================================
Assembly Syntax: Rd32=sffixupd(Rs32,Rt32)
C Intrinsic Prototype: Float32 Q6_R_sffixupd_RR(Float32 Rs, Float32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_sffixupd_RR __builtin_HEXAGON_F2_sffixupd
/* ==========================================================================
Assembly Syntax: Rd32=sffixupn(Rs32,Rt32)
C Intrinsic Prototype: Float32 Q6_R_sffixupn_RR(Float32 Rs, Float32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_sffixupn_RR __builtin_HEXAGON_F2_sffixupn
/* ==========================================================================
Assembly Syntax: Rd32=sffixupr(Rs32)
C Intrinsic Prototype: Float32 Q6_R_sffixupr_R(Float32 Rs)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_sffixupr_R __builtin_HEXAGON_F2_sffixupr
/* ==========================================================================
Assembly Syntax: Rx32+=sfmpy(Rs32,Rt32)
C Intrinsic Prototype: Float32 Q6_R_sfmpyacc_RR(Float32 Rx, Float32 Rs, Float32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Float32 Q6_R_sfmpyacc_RR(Float32 Rx, Float32 Rs, Float32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Float32 Q6_R_sfmpyacc_RR(Float32 Rx, Float32 Rs,
+   Float32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Float32 Q6_R_sfmpyacc_RR…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_sfmpyacc_RR __builtin_HEXAGON_F2_sffma
/* ==========================================================================
Assembly Syntax: Rx32+=sfmpy(Rs32,Rt32):lib
C Intrinsic Prototype: Float32 Q6_R_sfmpyacc_RR_lib(Float32 Rx, Float32 Rs, Float32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Float32 Q6_R_sfmpyacc_RR_lib(Float32 Rx, Float32 Rs, Float32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Float32 Q6_R_sfmpyacc_RR_lib(Float32 Rx, Float32 Rs,
+   Float32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Float32…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_sfmpyacc_RR_lib __builtin_HEXAGON_F2_sffma_lib
/* ==========================================================================
Assembly Syntax: Rx32+=sfmpy(Rs32,Rt32,Pu4):scale
C Intrinsic Prototype: Float32 Q6_R_sfmpyacc_RRp_scale(Float32 Rx, Float32 Rs, Float32 Rt, Byte Pu)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Float32 Q6_R_sfmpyacc_RRp_scale(Float32 Rx, Float32 Rs, Float32 Rt, Byte Pu)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Float32 Q6_R_sfmpyacc_RRp_scale(Float32 Rx, Float32
+   Rs, Float32 Rt, Byte Pu) Instruction Type:      M Execution Slots: SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Float32…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_sfmpyacc_RRp_scale __builtin_HEXAGON_F2_sffma_sc
/* ==========================================================================
Assembly Syntax: Rx32-=sfmpy(Rs32,Rt32)
C Intrinsic Prototype: Float32 Q6_R_sfmpynac_RR(Float32 Rx, Float32 Rs, Float32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Float32 Q6_R_sfmpynac_RR(Float32 Rx, Float32 Rs, Float32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Float32 Q6_R_sfmpynac_RR(Float32 Rx, Float32 Rs,
+   Float32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Float32 Q6_R_sfmpynac_RR…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_sfmpynac_RR __builtin_HEXAGON_F2_sffms
/* ==========================================================================
Assembly Syntax: Rx32-=sfmpy(Rs32,Rt32):lib
C Intrinsic Prototype: Float32 Q6_R_sfmpynac_RR_lib(Float32 Rx, Float32 Rs, Float32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Float32 Q6_R_sfmpynac_RR_lib(Float32 Rx, Float32 Rs, Float32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Float32 Q6_R_sfmpynac_RR_lib(Float32 Rx, Float32 Rs,
+   Float32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Float32…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_sfmpynac_RR_lib __builtin_HEXAGON_F2_sffms_lib
/* ==========================================================================
Assembly Syntax: Rd32=sfmake(#u10):neg
C Intrinsic Prototype: Float32 Q6_R_sfmake_I_neg(Word32 Iu10)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_sfmake_I_neg __builtin_HEXAGON_F2_sfimm_n
/* ==========================================================================
Assembly Syntax: Rd32=sfmake(#u10):pos
C Intrinsic Prototype: Float32 Q6_R_sfmake_I_pos(Word32 Iu10)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_sfmake_I_pos __builtin_HEXAGON_F2_sfimm_p
/* ==========================================================================
Assembly Syntax: Rd32=sfmax(Rs32,Rt32)
C Intrinsic Prototype: Float32 Q6_R_sfmax_RR(Float32 Rs, Float32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_sfmax_RR __builtin_HEXAGON_F2_sfmax
/* ==========================================================================
Assembly Syntax: Rd32=sfmin(Rs32,Rt32)
C Intrinsic Prototype: Float32 Q6_R_sfmin_RR(Float32 Rs, Float32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_sfmin_RR __builtin_HEXAGON_F2_sfmin
/* ==========================================================================
Assembly Syntax: Rd32=sfmpy(Rs32,Rt32)
C Intrinsic Prototype: Float32 Q6_R_sfmpy_RR(Float32 Rs, Float32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_sfmpy_RR __builtin_HEXAGON_F2_sfmpy
/* ==========================================================================
Assembly Syntax: Rd32=sfsub(Rs32,Rt32)
C Intrinsic Prototype: Float32 Q6_R_sfsub_RR(Float32 Rs, Float32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_sfsub_RR __builtin_HEXAGON_F2_sfsub
/* ==========================================================================
Assembly Syntax: Rd32=memb(Rx32++#s4:0:circ(Mu2))
C Intrinsic Prototype: Word32 Q6_R_memb_IM_circ(void** Rx, Word32 Is4_0, Word32 Mu, void* BaseAddress)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_memb_IM_circ(void** Rx, Word32 Is4_0, Word32 Mu, void* BaseAddress)
-   Instruction Type:      LD
-   Execution Slots:       SLOT01
+   C Intrinsic Prototype: Word32 Q6_R_memb_IM_circ(void** Rx, Word32 Is4_0,
+   Word32 Mu, void* BaseAddress) Instruction Type:      LD Execution Slots:
+   SLOT01
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_memb_IM_circ…
Instruction Type: LD
Execution Slots: SLOT01
========================================================================== */
#define Q6_R_memb_IM_circ __builtin_HEXAGON_L2_loadrb_pci
/* ==========================================================================
Assembly Syntax: Rd32=memb(Rx32++I:circ(Mu2))
C Intrinsic Prototype: Word32 Q6_R_memb_M_circ(void** Rx, Word32 Mu, void* BaseAddress)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_memb_M_circ(void** Rx, Word32 Mu, void* BaseAddress)
-   Instruction Type:      LD
-   Execution Slots:       SLOT01
+   C Intrinsic Prototype: Word32 Q6_R_memb_M_circ(void** Rx, Word32 Mu, void*
+   BaseAddress) Instruction Type:      LD Execution Slots:       SLOT01
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_memb_M_circ…
Instruction Type: LD
Execution Slots: SLOT01
========================================================================== */
#define Q6_R_memb_M_circ __builtin_HEXAGON_L2_loadrb_pcr
/* ==========================================================================
Assembly Syntax: Rdd32=memd(Rx32++#s4:3:circ(Mu2))
C Intrinsic Prototype: Word64 Q6_P_memd_IM_circ(void** Rx, Word32 Is4_3, Word32 Mu, void* BaseAddress)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_memd_IM_circ(void** Rx, Word32 Is4_3, Word32 Mu, void* BaseAddress)
-   Instruction Type:      LD
-   Execution Slots:       SLOT01
+   C Intrinsic Prototype: Word64 Q6_P_memd_IM_circ(void** Rx, Word32 Is4_3,
+   Word32 Mu, void* BaseAddress) Instruction Type:      LD Execution Slots:
+   SLOT01
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_memd_IM_circ…
Instruction Type: LD
Execution Slots: SLOT01
========================================================================== */
#define Q6_P_memd_IM_circ __builtin_HEXAGON_L2_loadrd_pci
/* ==========================================================================
Assembly Syntax: Rdd32=memd(Rx32++I:circ(Mu2))
C Intrinsic Prototype: Word64 Q6_P_memd_M_circ(void** Rx, Word32 Mu, void* BaseAddress)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_memd_M_circ(void** Rx, Word32 Mu, void* BaseAddress)
-   Instruction Type:      LD
-   Execution Slots:       SLOT01
+   C Intrinsic Prototype: Word64 Q6_P_memd_M_circ(void** Rx, Word32 Mu, void*
+   BaseAddress) Instruction Type:      LD Execution Slots:       SLOT01
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_memd_M_circ…
Instruction Type: LD
Execution Slots: SLOT01
========================================================================== */
#define Q6_P_memd_M_circ __builtin_HEXAGON_L2_loadrd_pcr
/* ==========================================================================
Assembly Syntax: Rd32=memh(Rx32++#s4:1:circ(Mu2))
C Intrinsic Prototype: Word32 Q6_R_memh_IM_circ(void** Rx, Word32 Is4_1, Word32 Mu, void* BaseAddress)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_memh_IM_circ(void** Rx, Word32 Is4_1, Word32 Mu, void* BaseAddress)
-   Instruction Type:      LD
-   Execution Slots:       SLOT01
+   C Intrinsic Prototype: Word32 Q6_R_memh_IM_circ(void** Rx, Word32 Is4_1,
+   Word32 Mu, void* BaseAddress) Instruction Type:      LD Execution Slots:
+   SLOT01
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_memh_IM_circ…
Instruction Type: LD
Execution Slots: SLOT01
========================================================================== */
#define Q6_R_memh_IM_circ __builtin_HEXAGON_L2_loadrh_pci
/* ==========================================================================
Assembly Syntax: Rd32=memh(Rx32++I:circ(Mu2))
C Intrinsic Prototype: Word32 Q6_R_memh_M_circ(void** Rx, Word32 Mu, void* BaseAddress)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_memh_M_circ(void** Rx, Word32 Mu, void* BaseAddress)
-   Instruction Type:      LD
-   Execution Slots:       SLOT01
+   C Intrinsic Prototype: Word32 Q6_R_memh_M_circ(void** Rx, Word32 Mu, void*
+   BaseAddress) Instruction Type:      LD Execution Slots:       SLOT01
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_memh_M_circ…
Instruction Type: LD
Execution Slots: SLOT01
========================================================================== */
#define Q6_R_memh_M_circ __builtin_HEXAGON_L2_loadrh_pcr
/* ==========================================================================
Assembly Syntax: Rd32=memw(Rx32++#s4:2:circ(Mu2))
C Intrinsic Prototype: Word32 Q6_R_memw_IM_circ(void** Rx, Word32 Is4_2, Word32 Mu, void* BaseAddress)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_memw_IM_circ(void** Rx, Word32 Is4_2, Word32 Mu, void* BaseAddress)
-   Instruction Type:      LD
-   Execution Slots:       SLOT01
+   C Intrinsic Prototype: Word32 Q6_R_memw_IM_circ(void** Rx, Word32 Is4_2,
+   Word32 Mu, void* BaseAddress) Instruction Type:      LD Execution Slots:
+   SLOT01
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_memw_IM_circ…
Instruction Type: LD
Execution Slots: SLOT01
========================================================================== */
#define Q6_R_memw_IM_circ __builtin_HEXAGON_L2_loadri_pci
/* ==========================================================================
Assembly Syntax: Rd32=memw(Rx32++I:circ(Mu2))
C Intrinsic Prototype: Word32 Q6_R_memw_M_circ(void** Rx, Word32 Mu, void* BaseAddress)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_memw_M_circ(void** Rx, Word32 Mu, void* BaseAddress)
-   Instruction Type:      LD
-   Execution Slots:       SLOT01
+   C Intrinsic Prototype: Word32 Q6_R_memw_M_circ(void** Rx, Word32 Mu, void*
+   BaseAddress) Instruction Type:      LD Execution Slots:       SLOT01
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_memw_M_circ…
Instruction Type: LD
Execution Slots: SLOT01
========================================================================== */
#define Q6_R_memw_M_circ __builtin_HEXAGON_L2_loadri_pcr
/* ==========================================================================
Assembly Syntax: Rd32=memub(Rx32++#s4:0:circ(Mu2))
C Intrinsic Prototype: Word32 Q6_R_memub_IM_circ(void** Rx, Word32 Is4_0, Word32 Mu, void* BaseAddress)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_memub_IM_circ(void** Rx, Word32 Is4_0, Word32 Mu, void* BaseAddress)
-   Instruction Type:      LD
-   Execution Slots:       SLOT01
+   C Intrinsic Prototype: Word32 Q6_R_memub_IM_circ(void** Rx, Word32 Is4_0,
+   Word32 Mu, void* BaseAddress) Instruction Type:      LD Execution Slots:
+   SLOT01
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_memub_IM_circ…
Instruction Type: LD
Execution Slots: SLOT01
========================================================================== */
#define Q6_R_memub_IM_circ __builtin_HEXAGON_L2_loadrub_pci
/* ==========================================================================
Assembly Syntax: Rd32=memub(Rx32++I:circ(Mu2))
C Intrinsic Prototype: Word32 Q6_R_memub_M_circ(void** Rx, Word32 Mu, void* BaseAddress)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_memub_M_circ(void** Rx, Word32 Mu, void* BaseAddress)
-   Instruction Type:      LD
-   Execution Slots:       SLOT01
+   C Intrinsic Prototype: Word32 Q6_R_memub_M_circ(void** Rx, Word32 Mu, void*
+   BaseAddress) Instruction Type:      LD Execution Slots:       SLOT01
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_memub_M_circ…
Instruction Type: LD
Execution Slots: SLOT01
========================================================================== */
#define Q6_R_memub_M_circ __builtin_HEXAGON_L2_loadrub_pcr
/* ==========================================================================
Assembly Syntax: Rd32=memuh(Rx32++#s4:1:circ(Mu2))
C Intrinsic Prototype: Word32 Q6_R_memuh_IM_circ(void** Rx, Word32 Is4_1, Word32 Mu, void* BaseAddress)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_memuh_IM_circ(void** Rx, Word32 Is4_1, Word32 Mu, void* BaseAddress)
-   Instruction Type:      LD
-   Execution Slots:       SLOT01
+   C Intrinsic Prototype: Word32 Q6_R_memuh_IM_circ(void** Rx, Word32 Is4_1,
+   Word32 Mu, void* BaseAddress) Instruction Type:      LD Execution Slots:
+   SLOT01
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_memuh_IM_circ…
Instruction Type: LD
Execution Slots: SLOT01
========================================================================== */
#define Q6_R_memuh_IM_circ __builtin_HEXAGON_L2_loadruh_pci
/* ==========================================================================
Assembly Syntax: Rd32=memuh(Rx32++I:circ(Mu2))
C Intrinsic Prototype: Word32 Q6_R_memuh_M_circ(void** Rx, Word32 Mu, void* BaseAddress)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_memuh_M_circ(void** Rx, Word32 Mu, void* BaseAddress)
-   Instruction Type:      LD
-   Execution Slots:       SLOT01
+   C Intrinsic Prototype: Word32 Q6_R_memuh_M_circ(void** Rx, Word32 Mu, void*
+   BaseAddress) Instruction Type:      LD Execution Slots:       SLOT01
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_memuh_M_circ…
Instruction Type: LD
Execution Slots: SLOT01
========================================================================== */
#define Q6_R_memuh_M_circ __builtin_HEXAGON_L2_loadruh_pcr
/* ==========================================================================
Assembly Syntax: Rx32+=add(Rs32,Rt32)
C Intrinsic Prototype: Word32 Q6_R_addacc_RR(Word32 Rx, Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_addacc_RR __builtin_HEXAGON_M2_acci
/* ==========================================================================
Assembly Syntax: Rx32+=add(Rs32,#s8)
C Intrinsic Prototype: Word32 Q6_R_addacc_RI(Word32 Rx, Word32 Rs, Word32 Is8)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_addacc_RI(Word32 Rx, Word32 Rs, Word32 Is8)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_addacc_RI(Word32 Rx, Word32 Rs, Word32
+   Is8) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_addacc_RI…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_addacc_RI __builtin_HEXAGON_M2_accii
/* ==========================================================================
Assembly Syntax: Rxx32+=cmpyi(Rs32,Rt32)
C Intrinsic Prototype: Word64 Q6_P_cmpyiacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_cmpyiacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_cmpyiacc_RR(Word64 Rxx, Word32 Rs, Word32
+   Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_cmpyiacc_RR…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_cmpyiacc_RR __builtin_HEXAGON_M2_cmaci_s0
/* ==========================================================================
Assembly Syntax: Rxx32+=cmpyr(Rs32,Rt32)
C Intrinsic Prototype: Word64 Q6_P_cmpyracc_RR(Word64 Rxx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_cmpyracc_RR(Word64 Rxx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_cmpyracc_RR(Word64 Rxx, Word32 Rs, Word32
+   Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_cmpyracc_RR…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_cmpyracc_RR __builtin_HEXAGON_M2_cmacr_s0
/* ==========================================================================
Assembly Syntax: Rxx32+=cmpy(Rs32,Rt32):sat
C Intrinsic Prototype: Word64 Q6_P_cmpyacc_RR_sat(Word64 Rxx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_cmpyacc_RR_sat(Word64 Rxx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_cmpyacc_RR_sat(Word64 Rxx, Word32 Rs,
+   Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_cmpyacc_RR_sat __builtin_HEXAGON_M2_cmacs_s0
/* ==========================================================================
Assembly Syntax: Rxx32+=cmpy(Rs32,Rt32):<<1:sat
C Intrinsic Prototype: Word64 Q6_P_cmpyacc_RR_s1_sat(Word64 Rxx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_cmpyacc_RR_s1_sat(Word64 Rxx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_cmpyacc_RR_s1_sat(Word64 Rxx, Word32 Rs,
+   Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_cmpyacc_RR_s1_sat __builtin_HEXAGON_M2_cmacs_s1
/* ==========================================================================
Assembly Syntax: Rxx32+=cmpy(Rs32,Rt32*):sat
C Intrinsic Prototype: Word64 Q6_P_cmpyacc_RR_conj_sat(Word64 Rxx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_cmpyacc_RR_conj_sat(Word64 Rxx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_cmpyacc_RR_conj_sat(Word64 Rxx, Word32 Rs,
+   Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_cmpyacc_RR_conj_sat __builtin_HEXAGON_M2_cmacsc_s0
/* ==========================================================================
Assembly Syntax: Rxx32+=cmpy(Rs32,Rt32*):<<1:sat
C Intrinsic Prototype: Word64 Q6_P_cmpyacc_RR_conj_s1_sat(Word64 Rxx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_cmpyacc_RR_conj_s1_sat(Word64 Rxx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_cmpyacc_RR_conj_s1_sat(Word64 Rxx, Word32
+   Rs, Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_cmpyacc_RR_conj_s1_sat __builtin_HEXAGON_M2_cmacsc_s1
/* ==========================================================================
Assembly Syntax: Rdd32=cmpyi(Rs32,Rt32)
C Intrinsic Prototype: Word64 Q6_P_cmpyi_RR(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_cmpyi_RR __builtin_HEXAGON_M2_cmpyi_s0
/* ==========================================================================
Assembly Syntax: Rdd32=cmpyr(Rs32,Rt32)
C Intrinsic Prototype: Word64 Q6_P_cmpyr_RR(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_cmpyr_RR __builtin_HEXAGON_M2_cmpyr_s0
/* ==========================================================================
Assembly Syntax: Rd32=cmpy(Rs32,Rt32):rnd:sat
C Intrinsic Prototype: Word32 Q6_R_cmpy_RR_rnd_sat(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_cmpy_RR_rnd_sat __builtin_HEXAGON_M2_cmpyrs_s0
/* ==========================================================================
Assembly Syntax: Rd32=cmpy(Rs32,Rt32):<<1:rnd:sat
C Intrinsic Prototype: Word32 Q6_R_cmpy_RR_s1_rnd_sat(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_cmpy_RR_s1_rnd_sat __builtin_HEXAGON_M2_cmpyrs_s1
/* ==========================================================================
Assembly Syntax: Rd32=cmpy(Rs32,Rt32*):rnd:sat
C Intrinsic Prototype: Word32 Q6_R_cmpy_RR_conj_rnd_sat(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_cmpy_RR_conj_rnd_sat __builtin_HEXAGON_M2_cmpyrsc_s0
/* ==========================================================================
Assembly Syntax: Rd32=cmpy(Rs32,Rt32*):<<1:rnd:sat
C Intrinsic Prototype: Word32 Q6_R_cmpy_RR_conj_s1_rnd_sat(Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_cmpy_RR_conj_s1_rnd_sat(Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_cmpy_RR_conj_s1_rnd_sat(Word32 Rs, Word32
+   Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_cmpy_RR_conj_s1_rnd_sat __builtin_HEXAGON_M2_cmpyrsc_s1
/* ==========================================================================
Assembly Syntax: Rdd32=cmpy(Rs32,Rt32):sat
C Intrinsic Prototype: Word64 Q6_P_cmpy_RR_sat(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_cmpy_RR_sat __builtin_HEXAGON_M2_cmpys_s0
/* ==========================================================================
Assembly Syntax: Rdd32=cmpy(Rs32,Rt32):<<1:sat
C Intrinsic Prototype: Word64 Q6_P_cmpy_RR_s1_sat(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_cmpy_RR_s1_sat __builtin_HEXAGON_M2_cmpys_s1
/* ==========================================================================
Assembly Syntax: Rdd32=cmpy(Rs32,Rt32*):sat
C Intrinsic Prototype: Word64 Q6_P_cmpy_RR_conj_sat(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_cmpy_RR_conj_sat __builtin_HEXAGON_M2_cmpysc_s0
/* ==========================================================================
Assembly Syntax: Rdd32=cmpy(Rs32,Rt32*):<<1:sat
C Intrinsic Prototype: Word64 Q6_P_cmpy_RR_conj_s1_sat(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_cmpy_RR_conj_s1_sat __builtin_HEXAGON_M2_cmpysc_s1
/* ==========================================================================
Assembly Syntax: Rxx32-=cmpy(Rs32,Rt32):sat
C Intrinsic Prototype: Word64 Q6_P_cmpynac_RR_sat(Word64 Rxx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_cmpynac_RR_sat(Word64 Rxx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_cmpynac_RR_sat(Word64 Rxx, Word32 Rs,
+   Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_cmpynac_RR_sat __builtin_HEXAGON_M2_cnacs_s0
/* ==========================================================================
Assembly Syntax: Rxx32-=cmpy(Rs32,Rt32):<<1:sat
C Intrinsic Prototype: Word64 Q6_P_cmpynac_RR_s1_sat(Word64 Rxx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_cmpynac_RR_s1_sat(Word64 Rxx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_cmpynac_RR_s1_sat(Word64 Rxx, Word32 Rs,
+   Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_cmpynac_RR_s1_sat __builtin_HEXAGON_M2_cnacs_s1
/* ==========================================================================
Assembly Syntax: Rxx32-=cmpy(Rs32,Rt32*):sat
C Intrinsic Prototype: Word64 Q6_P_cmpynac_RR_conj_sat(Word64 Rxx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_cmpynac_RR_conj_sat(Word64 Rxx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_cmpynac_RR_conj_sat(Word64 Rxx, Word32 Rs,
+   Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_cmpynac_RR_conj_sat __builtin_HEXAGON_M2_cnacsc_s0
/* ==========================================================================
Assembly Syntax: Rxx32-=cmpy(Rs32,Rt32*):<<1:sat
C Intrinsic Prototype: Word64 Q6_P_cmpynac_RR_conj_s1_sat(Word64 Rxx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_cmpynac_RR_conj_s1_sat(Word64 Rxx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_cmpynac_RR_conj_s1_sat(Word64 Rxx, Word32
+   Rs, Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_cmpynac_RR_conj_s1_sat __builtin_HEXAGON_M2_cnacsc_s1
/* ==========================================================================
Assembly Syntax: Rxx32+=mpy(Rs32,Rt32)
C Intrinsic Prototype: Word64 Q6_P_mpyacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_mpyacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_mpyacc_RR(Word64 Rxx, Word32 Rs, Word32
+   Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_mpyacc_RR…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mpyacc_RR __builtin_HEXAGON_M2_dpmpyss_acc_s0
/* ==========================================================================
Assembly Syntax: Rxx32-=mpy(Rs32,Rt32)
C Intrinsic Prototype: Word64 Q6_P_mpynac_RR(Word64 Rxx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_mpynac_RR(Word64 Rxx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_mpynac_RR(Word64 Rxx, Word32 Rs, Word32
+   Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_mpynac_RR…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mpynac_RR __builtin_HEXAGON_M2_dpmpyss_nac_s0
/* ==========================================================================
Assembly Syntax: Rd32=mpy(Rs32,Rt32):rnd
C Intrinsic Prototype: Word32 Q6_R_mpy_RR_rnd(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpy_RR_rnd __builtin_HEXAGON_M2_dpmpyss_rnd_s0
/* ==========================================================================
Assembly Syntax: Rdd32=mpy(Rs32,Rt32)
C Intrinsic Prototype: Word64 Q6_P_mpy_RR(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mpy_RR __builtin_HEXAGON_M2_dpmpyss_s0
/* ==========================================================================
Assembly Syntax: Rxx32+=mpyu(Rs32,Rt32)
C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RR(Word64 Rxx, Word32 Rs, Word32
+   Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RR…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mpyuacc_RR __builtin_HEXAGON_M2_dpmpyuu_acc_s0
/* ==========================================================================
Assembly Syntax: Rxx32-=mpyu(Rs32,Rt32)
C Intrinsic Prototype: Word64 Q6_P_mpyunac_RR(Word64 Rxx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_mpyunac_RR(Word64 Rxx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_mpyunac_RR(Word64 Rxx, Word32 Rs, Word32
+   Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_mpyunac_RR…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mpyunac_RR __builtin_HEXAGON_M2_dpmpyuu_nac_s0
/* ==========================================================================
Assembly Syntax: Rdd32=mpyu(Rs32,Rt32)
C Intrinsic Prototype: UWord64 Q6_P_mpyu_RR(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mpyu_RR __builtin_HEXAGON_M2_dpmpyuu_s0
/* ==========================================================================
Assembly Syntax: Rd32=mpy(Rs32,Rt32.h):<<1:rnd:sat
C Intrinsic Prototype: Word32 Q6_R_mpy_RRh_s1_rnd_sat(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpy_RRh_s1_rnd_sat __builtin_HEXAGON_M2_hmmpyh_rs1
/* ==========================================================================
Assembly Syntax: Rd32=mpy(Rs32,Rt32.h):<<1:sat
C Intrinsic Prototype: Word32 Q6_R_mpy_RRh_s1_sat(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpy_RRh_s1_sat __builtin_HEXAGON_M2_hmmpyh_s1
/* ==========================================================================
Assembly Syntax: Rd32=mpy(Rs32,Rt32.l):<<1:rnd:sat
C Intrinsic Prototype: Word32 Q6_R_mpy_RRl_s1_rnd_sat(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpy_RRl_s1_rnd_sat __builtin_HEXAGON_M2_hmmpyl_rs1
/* ==========================================================================
Assembly Syntax: Rd32=mpy(Rs32,Rt32.l):<<1:sat
C Intrinsic Prototype: Word32 Q6_R_mpy_RRl_s1_sat(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpy_RRl_s1_sat __builtin_HEXAGON_M2_hmmpyl_s1
/* ==========================================================================
Assembly Syntax: Rx32+=mpyi(Rs32,Rt32)
C Intrinsic Prototype: Word32 Q6_R_mpyiacc_RR(Word32 Rx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_mpyiacc_RR(Word32 Rx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_mpyiacc_RR(Word32 Rx, Word32 Rs, Word32
+   Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_mpyiacc_RR…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpyiacc_RR __builtin_HEXAGON_M2_maci
/* ==========================================================================
Assembly Syntax: Rx32-=mpyi(Rs32,#u8)
C Intrinsic Prototype: Word32 Q6_R_mpyinac_RI(Word32 Rx, Word32 Rs, Word32 Iu8)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_mpyinac_RI(Word32 Rx, Word32 Rs, Word32 Iu8)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_mpyinac_RI(Word32 Rx, Word32 Rs, Word32
+   Iu8) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_mpyinac_RI…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpyinac_RI __builtin_HEXAGON_M2_macsin
/* ==========================================================================
Assembly Syntax: Rx32+=mpyi(Rs32,#u8)
C Intrinsic Prototype: Word32 Q6_R_mpyiacc_RI(Word32 Rx, Word32 Rs, Word32 Iu8)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_mpyiacc_RI(Word32 Rx, Word32 Rs, Word32 Iu8)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_mpyiacc_RI(Word32 Rx, Word32 Rs, Word32
+   Iu8) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_mpyiacc_RI…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpyiacc_RI __builtin_HEXAGON_M2_macsip
/* ==========================================================================
Assembly Syntax: Rxx32+=vmpywoh(Rss32,Rtt32):rnd:sat
C Intrinsic Prototype: Word64 Q6_P_vmpywohacc_PP_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vmpywohacc_PP_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vmpywohacc_PP_rnd_sat(Word64 Rxx, Word64
+   Rss, Word64 Rtt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vmpywohacc_PP_rnd_sat __builtin_HEXAGON_M2_mmachs_rs0
/* ==========================================================================
Assembly Syntax: Rxx32+=vmpywoh(Rss32,Rtt32):<<1:rnd:sat
C Intrinsic Prototype: Word64 Q6_P_vmpywohacc_PP_s1_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vmpywohacc_PP_s1_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vmpywohacc_PP_s1_rnd_sat(Word64 Rxx,
+   Word64 Rss, Word64 Rtt) Instruction Type:      M Execution Slots: SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vmpywohacc_PP_s1_rnd_sat __builtin_HEXAGON_M2_mmachs_rs1
/* ==========================================================================
Assembly Syntax: Rxx32+=vmpywoh(Rss32,Rtt32):sat
C Intrinsic Prototype: Word64 Q6_P_vmpywohacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vmpywohacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vmpywohacc_PP_sat(Word64 Rxx, Word64 Rss,
+   Word64 Rtt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vmpywohacc_PP_sat __builtin_HEXAGON_M2_mmachs_s0
/* ==========================================================================
Assembly Syntax: Rxx32+=vmpywoh(Rss32,Rtt32):<<1:sat
C Intrinsic Prototype: Word64 Q6_P_vmpywohacc_PP_s1_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vmpywohacc_PP_s1_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vmpywohacc_PP_s1_sat(Word64 Rxx, Word64
+   Rss, Word64 Rtt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vmpywohacc_PP_s1_sat __builtin_HEXAGON_M2_mmachs_s1
/* ==========================================================================
Assembly Syntax: Rxx32+=vmpyweh(Rss32,Rtt32):rnd:sat
C Intrinsic Prototype: Word64 Q6_P_vmpywehacc_PP_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vmpywehacc_PP_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vmpywehacc_PP_rnd_sat(Word64 Rxx, Word64
+   Rss, Word64 Rtt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vmpywehacc_PP_rnd_sat __builtin_HEXAGON_M2_mmacls_rs0
/* ==========================================================================
Assembly Syntax: Rxx32+=vmpyweh(Rss32,Rtt32):<<1:rnd:sat
C Intrinsic Prototype: Word64 Q6_P_vmpywehacc_PP_s1_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vmpywehacc_PP_s1_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vmpywehacc_PP_s1_rnd_sat(Word64 Rxx,
+   Word64 Rss, Word64 Rtt) Instruction Type:      M Execution Slots: SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vmpywehacc_PP_s1_rnd_sat __builtin_HEXAGON_M2_mmacls_rs1
/* ==========================================================================
Assembly Syntax: Rxx32+=vmpyweh(Rss32,Rtt32):sat
C Intrinsic Prototype: Word64 Q6_P_vmpywehacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vmpywehacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vmpywehacc_PP_sat(Word64 Rxx, Word64 Rss,
+   Word64 Rtt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vmpywehacc_PP_sat __builtin_HEXAGON_M2_mmacls_s0
/* ==========================================================================
Assembly Syntax: Rxx32+=vmpyweh(Rss32,Rtt32):<<1:sat
C Intrinsic Prototype: Word64 Q6_P_vmpywehacc_PP_s1_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vmpywehacc_PP_s1_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vmpywehacc_PP_s1_sat(Word64 Rxx, Word64
+   Rss, Word64 Rtt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vmpywehacc_PP_s1_sat __builtin_HEXAGON_M2_mmacls_s1
/* ==========================================================================
Assembly Syntax: Rxx32+=vmpywouh(Rss32,Rtt32):rnd:sat
C Intrinsic Prototype: Word64 Q6_P_vmpywouhacc_PP_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vmpywouhacc_PP_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vmpywouhacc_PP_rnd_sat(Word64 Rxx, Word64
+   Rss, Word64 Rtt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vmpywouhacc_PP_rnd_sat __builtin_HEXAGON_M2_mmacuhs_rs0
/* ==========================================================================
Assembly Syntax: Rxx32+=vmpywouh(Rss32,Rtt32):<<1:rnd:sat
C Intrinsic Prototype: Word64 Q6_P_vmpywouhacc_PP_s1_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vmpywouhacc_PP_s1_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vmpywouhacc_PP_s1_rnd_sat(Word64 Rxx,
+   Word64 Rss, Word64 Rtt) Instruction Type:      M Execution Slots: SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vmpywouhacc_PP_s1_rnd_sat __builtin_HEXAGON_M2_mmacuhs_rs1
/* ==========================================================================
Assembly Syntax: Rxx32+=vmpywouh(Rss32,Rtt32):sat
C Intrinsic Prototype: Word64 Q6_P_vmpywouhacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vmpywouhacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vmpywouhacc_PP_sat(Word64 Rxx, Word64 Rss,
+   Word64 Rtt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vmpywouhacc_PP_sat __builtin_HEXAGON_M2_mmacuhs_s0
/* ==========================================================================
Assembly Syntax: Rxx32+=vmpywouh(Rss32,Rtt32):<<1:sat
C Intrinsic Prototype: Word64 Q6_P_vmpywouhacc_PP_s1_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vmpywouhacc_PP_s1_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vmpywouhacc_PP_s1_sat(Word64 Rxx, Word64
+   Rss, Word64 Rtt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vmpywouhacc_PP_s1_sat __builtin_HEXAGON_M2_mmacuhs_s1
/* ==========================================================================
Assembly Syntax: Rxx32+=vmpyweuh(Rss32,Rtt32):rnd:sat
C Intrinsic Prototype: Word64 Q6_P_vmpyweuhacc_PP_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vmpyweuhacc_PP_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vmpyweuhacc_PP_rnd_sat(Word64 Rxx, Word64
+   Rss, Word64 Rtt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vmpyweuhacc_PP_rnd_sat __builtin_HEXAGON_M2_mmaculs_rs0
/* ==========================================================================
Assembly Syntax: Rxx32+=vmpyweuh(Rss32,Rtt32):<<1:rnd:sat
C Intrinsic Prototype: Word64 Q6_P_vmpyweuhacc_PP_s1_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vmpyweuhacc_PP_s1_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vmpyweuhacc_PP_s1_rnd_sat(Word64 Rxx,
+   Word64 Rss, Word64 Rtt) Instruction Type:      M Execution Slots: SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vmpyweuhacc_PP_s1_rnd_sat __builtin_HEXAGON_M2_mmaculs_rs1
/* ==========================================================================
Assembly Syntax: Rxx32+=vmpyweuh(Rss32,Rtt32):sat
C Intrinsic Prototype: Word64 Q6_P_vmpyweuhacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vmpyweuhacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vmpyweuhacc_PP_sat(Word64 Rxx, Word64 Rss,
+   Word64 Rtt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vmpyweuhacc_PP_sat __builtin_HEXAGON_M2_mmaculs_s0
/* ==========================================================================
Assembly Syntax: Rxx32+=vmpyweuh(Rss32,Rtt32):<<1:sat
C Intrinsic Prototype: Word64 Q6_P_vmpyweuhacc_PP_s1_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vmpyweuhacc_PP_s1_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vmpyweuhacc_PP_s1_sat(Word64 Rxx, Word64
+   Rss, Word64 Rtt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vmpyweuhacc_PP_s1_sat __builtin_HEXAGON_M2_mmaculs_s1
/* ==========================================================================
Assembly Syntax: Rdd32=vmpywoh(Rss32,Rtt32):rnd:sat
C Intrinsic Prototype: Word64 Q6_P_vmpywoh_PP_rnd_sat(Word64 Rss, Word64 Rtt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vmpywoh_PP_rnd_sat __builtin_HEXAGON_M2_mmpyh_rs0
/* ==========================================================================
Assembly Syntax: Rdd32=vmpywoh(Rss32,Rtt32):<<1:rnd:sat
C Intrinsic Prototype: Word64 Q6_P_vmpywoh_PP_s1_rnd_sat(Word64 Rss, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vmpywoh_PP_s1_rnd_sat(Word64 Rss, Word64 Rtt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vmpywoh_PP_s1_rnd_sat(Word64 Rss, Word64
+   Rtt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vmpywoh_PP_s1_rnd_sat __builtin_HEXAGON_M2_mmpyh_rs1
/* ==========================================================================
Assembly Syntax: Rdd32=vmpywoh(Rss32,Rtt32):sat
C Intrinsic Prototype: Word64 Q6_P_vmpywoh_PP_sat(Word64 Rss, Word64 Rtt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vmpywoh_PP_sat __builtin_HEXAGON_M2_mmpyh_s0
/* ==========================================================================
Assembly Syntax: Rdd32=vmpywoh(Rss32,Rtt32):<<1:sat
C Intrinsic Prototype: Word64 Q6_P_vmpywoh_PP_s1_sat(Word64 Rss, Word64 Rtt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vmpywoh_PP_s1_sat __builtin_HEXAGON_M2_mmpyh_s1
/* ==========================================================================
Assembly Syntax: Rdd32=vmpyweh(Rss32,Rtt32):rnd:sat
C Intrinsic Prototype: Word64 Q6_P_vmpyweh_PP_rnd_sat(Word64 Rss, Word64 Rtt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vmpyweh_PP_rnd_sat __builtin_HEXAGON_M2_mmpyl_rs0
/* ==========================================================================
Assembly Syntax: Rdd32=vmpyweh(Rss32,Rtt32):<<1:rnd:sat
C Intrinsic Prototype: Word64 Q6_P_vmpyweh_PP_s1_rnd_sat(Word64 Rss, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vmpyweh_PP_s1_rnd_sat(Word64 Rss, Word64 Rtt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vmpyweh_PP_s1_rnd_sat(Word64 Rss, Word64
+   Rtt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vmpyweh_PP_s1_rnd_sat __builtin_HEXAGON_M2_mmpyl_rs1
/* ==========================================================================
Assembly Syntax: Rdd32=vmpyweh(Rss32,Rtt32):sat
C Intrinsic Prototype: Word64 Q6_P_vmpyweh_PP_sat(Word64 Rss, Word64 Rtt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vmpyweh_PP_sat __builtin_HEXAGON_M2_mmpyl_s0
/* ==========================================================================
Assembly Syntax: Rdd32=vmpyweh(Rss32,Rtt32):<<1:sat
C Intrinsic Prototype: Word64 Q6_P_vmpyweh_PP_s1_sat(Word64 Rss, Word64 Rtt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vmpyweh_PP_s1_sat __builtin_HEXAGON_M2_mmpyl_s1
/* ==========================================================================
Assembly Syntax: Rdd32=vmpywouh(Rss32,Rtt32):rnd:sat
C Intrinsic Prototype: Word64 Q6_P_vmpywouh_PP_rnd_sat(Word64 Rss, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vmpywouh_PP_rnd_sat(Word64 Rss, Word64 Rtt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vmpywouh_PP_rnd_sat(Word64 Rss, Word64
+   Rtt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vmpywouh_PP_rnd_sat __builtin_HEXAGON_M2_mmpyuh_rs0
/* ==========================================================================
Assembly Syntax: Rdd32=vmpywouh(Rss32,Rtt32):<<1:rnd:sat
C Intrinsic Prototype: Word64 Q6_P_vmpywouh_PP_s1_rnd_sat(Word64 Rss, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vmpywouh_PP_s1_rnd_sat(Word64 Rss, Word64 Rtt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vmpywouh_PP_s1_rnd_sat(Word64 Rss, Word64
+   Rtt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vmpywouh_PP_s1_rnd_sat __builtin_HEXAGON_M2_mmpyuh_rs1
/* ==========================================================================
Assembly Syntax: Rdd32=vmpywouh(Rss32,Rtt32):sat
C Intrinsic Prototype: Word64 Q6_P_vmpywouh_PP_sat(Word64 Rss, Word64 Rtt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vmpywouh_PP_sat __builtin_HEXAGON_M2_mmpyuh_s0
/* ==========================================================================
Assembly Syntax: Rdd32=vmpywouh(Rss32,Rtt32):<<1:sat
C Intrinsic Prototype: Word64 Q6_P_vmpywouh_PP_s1_sat(Word64 Rss, Word64 Rtt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vmpywouh_PP_s1_sat __builtin_HEXAGON_M2_mmpyuh_s1
/* ==========================================================================
Assembly Syntax: Rdd32=vmpyweuh(Rss32,Rtt32):rnd:sat
C Intrinsic Prototype: Word64 Q6_P_vmpyweuh_PP_rnd_sat(Word64 Rss, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vmpyweuh_PP_rnd_sat(Word64 Rss, Word64 Rtt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vmpyweuh_PP_rnd_sat(Word64 Rss, Word64
+   Rtt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vmpyweuh_PP_rnd_sat __builtin_HEXAGON_M2_mmpyul_rs0
/* ==========================================================================
Assembly Syntax: Rdd32=vmpyweuh(Rss32,Rtt32):<<1:rnd:sat
C Intrinsic Prototype: Word64 Q6_P_vmpyweuh_PP_s1_rnd_sat(Word64 Rss, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vmpyweuh_PP_s1_rnd_sat(Word64 Rss, Word64 Rtt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vmpyweuh_PP_s1_rnd_sat(Word64 Rss, Word64
+   Rtt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vmpyweuh_PP_s1_rnd_sat __builtin_HEXAGON_M2_mmpyul_rs1
/* ==========================================================================
Assembly Syntax: Rdd32=vmpyweuh(Rss32,Rtt32):sat
C Intrinsic Prototype: Word64 Q6_P_vmpyweuh_PP_sat(Word64 Rss, Word64 Rtt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vmpyweuh_PP_sat __builtin_HEXAGON_M2_mmpyul_s0
/* ==========================================================================
Assembly Syntax: Rdd32=vmpyweuh(Rss32,Rtt32):<<1:sat
C Intrinsic Prototype: Word64 Q6_P_vmpyweuh_PP_s1_sat(Word64 Rss, Word64 Rtt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vmpyweuh_PP_s1_sat __builtin_HEXAGON_M2_mmpyul_s1
/* ==========================================================================
Assembly Syntax: Rx32+=mpy(Rs32.h,Rt32.h)
C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRh(Word32 Rx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRh(Word32 Rx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRh(Word32 Rx, Word32 Rs, Word32
+   Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRh…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpyacc_RhRh __builtin_HEXAGON_M2_mpy_acc_hh_s0
/* ==========================================================================
Assembly Syntax: Rx32+=mpy(Rs32.h,Rt32.h):<<1
C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRh_s1(Word32 Rx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRh_s1(Word32 Rx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRh_s1(Word32 Rx, Word32 Rs,
+   Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpyacc_RhRh_s1 __builtin_HEXAGON_M2_mpy_acc_hh_s1
/* ==========================================================================
Assembly Syntax: Rx32+=mpy(Rs32.h,Rt32.l)
C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRl(Word32 Rx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRl(Word32 Rx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRl(Word32 Rx, Word32 Rs, Word32
+   Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRl…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpyacc_RhRl __builtin_HEXAGON_M2_mpy_acc_hl_s0
/* ==========================================================================
Assembly Syntax: Rx32+=mpy(Rs32.h,Rt32.l):<<1
C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRl_s1(Word32 Rx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRl_s1(Word32 Rx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRl_s1(Word32 Rx, Word32 Rs,
+   Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpyacc_RhRl_s1 __builtin_HEXAGON_M2_mpy_acc_hl_s1
/* ==========================================================================
Assembly Syntax: Rx32+=mpy(Rs32.l,Rt32.h)
C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRh(Word32 Rx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRh(Word32 Rx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRh(Word32 Rx, Word32 Rs, Word32
+   Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRh…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpyacc_RlRh __builtin_HEXAGON_M2_mpy_acc_lh_s0
/* ==========================================================================
Assembly Syntax: Rx32+=mpy(Rs32.l,Rt32.h):<<1
C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRh_s1(Word32 Rx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRh_s1(Word32 Rx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRh_s1(Word32 Rx, Word32 Rs,
+   Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpyacc_RlRh_s1 __builtin_HEXAGON_M2_mpy_acc_lh_s1
/* ==========================================================================
Assembly Syntax: Rx32+=mpy(Rs32.l,Rt32.l)
C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRl(Word32 Rx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRl(Word32 Rx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRl(Word32 Rx, Word32 Rs, Word32
+   Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRl…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpyacc_RlRl __builtin_HEXAGON_M2_mpy_acc_ll_s0
/* ==========================================================================
Assembly Syntax: Rx32+=mpy(Rs32.l,Rt32.l):<<1
C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRl_s1(Word32 Rx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRl_s1(Word32 Rx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRl_s1(Word32 Rx, Word32 Rs,
+   Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpyacc_RlRl_s1 __builtin_HEXAGON_M2_mpy_acc_ll_s1
/* ==========================================================================
Assembly Syntax: Rx32+=mpy(Rs32.h,Rt32.h):sat
C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRh_sat(Word32 Rx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRh_sat(Word32 Rx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRh_sat(Word32 Rx, Word32 Rs,
+   Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpyacc_RhRh_sat __builtin_HEXAGON_M2_mpy_acc_sat_hh_s0
/* ==========================================================================
Assembly Syntax: Rx32+=mpy(Rs32.h,Rt32.h):<<1:sat
C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRh_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRh_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRh_s1_sat(Word32 Rx, Word32 Rs,
+   Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpyacc_RhRh_s1_sat __builtin_HEXAGON_M2_mpy_acc_sat_hh_s1
/* ==========================================================================
Assembly Syntax: Rx32+=mpy(Rs32.h,Rt32.l):sat
C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRl_sat(Word32 Rx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRl_sat(Word32 Rx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRl_sat(Word32 Rx, Word32 Rs,
+   Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpyacc_RhRl_sat __builtin_HEXAGON_M2_mpy_acc_sat_hl_s0
/* ==========================================================================
Assembly Syntax: Rx32+=mpy(Rs32.h,Rt32.l):<<1:sat
C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRl_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRl_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRl_s1_sat(Word32 Rx, Word32 Rs,
+   Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpyacc_RhRl_s1_sat __builtin_HEXAGON_M2_mpy_acc_sat_hl_s1
/* ==========================================================================
Assembly Syntax: Rx32+=mpy(Rs32.l,Rt32.h):sat
C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRh_sat(Word32 Rx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRh_sat(Word32 Rx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRh_sat(Word32 Rx, Word32 Rs,
+   Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpyacc_RlRh_sat __builtin_HEXAGON_M2_mpy_acc_sat_lh_s0
/* ==========================================================================
Assembly Syntax: Rx32+=mpy(Rs32.l,Rt32.h):<<1:sat
C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRh_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRh_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRh_s1_sat(Word32 Rx, Word32 Rs,
+   Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpyacc_RlRh_s1_sat __builtin_HEXAGON_M2_mpy_acc_sat_lh_s1
/* ==========================================================================
Assembly Syntax: Rx32+=mpy(Rs32.l,Rt32.l):sat
C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRl_sat(Word32 Rx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRl_sat(Word32 Rx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRl_sat(Word32 Rx, Word32 Rs,
+   Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpyacc_RlRl_sat __builtin_HEXAGON_M2_mpy_acc_sat_ll_s0
/* ==========================================================================
Assembly Syntax: Rx32+=mpy(Rs32.l,Rt32.l):<<1:sat
C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRl_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRl_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRl_s1_sat(Word32 Rx, Word32 Rs,
+   Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpyacc_RlRl_s1_sat __builtin_HEXAGON_M2_mpy_acc_sat_ll_s1
/* ==========================================================================
Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.h)
C Intrinsic Prototype: Word32 Q6_R_mpy_RhRh(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpy_RhRh __builtin_HEXAGON_M2_mpy_hh_s0
/* ==========================================================================
Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.h):<<1
C Intrinsic Prototype: Word32 Q6_R_mpy_RhRh_s1(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpy_RhRh_s1 __builtin_HEXAGON_M2_mpy_hh_s1
/* ==========================================================================
Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.l)
C Intrinsic Prototype: Word32 Q6_R_mpy_RhRl(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpy_RhRl __builtin_HEXAGON_M2_mpy_hl_s0
/* ==========================================================================
Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.l):<<1
C Intrinsic Prototype: Word32 Q6_R_mpy_RhRl_s1(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpy_RhRl_s1 __builtin_HEXAGON_M2_mpy_hl_s1
/* ==========================================================================
Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.h)
C Intrinsic Prototype: Word32 Q6_R_mpy_RlRh(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpy_RlRh __builtin_HEXAGON_M2_mpy_lh_s0
/* ==========================================================================
Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.h):<<1
C Intrinsic Prototype: Word32 Q6_R_mpy_RlRh_s1(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpy_RlRh_s1 __builtin_HEXAGON_M2_mpy_lh_s1
/* ==========================================================================
Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.l)
C Intrinsic Prototype: Word32 Q6_R_mpy_RlRl(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpy_RlRl __builtin_HEXAGON_M2_mpy_ll_s0
/* ==========================================================================
Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.l):<<1
C Intrinsic Prototype: Word32 Q6_R_mpy_RlRl_s1(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpy_RlRl_s1 __builtin_HEXAGON_M2_mpy_ll_s1
/* ==========================================================================
Assembly Syntax: Rx32-=mpy(Rs32.h,Rt32.h)
C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRh(Word32 Rx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRh(Word32 Rx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRh(Word32 Rx, Word32 Rs, Word32
+   Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRh…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpynac_RhRh __builtin_HEXAGON_M2_mpy_nac_hh_s0
/* ==========================================================================
Assembly Syntax: Rx32-=mpy(Rs32.h,Rt32.h):<<1
C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRh_s1(Word32 Rx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRh_s1(Word32 Rx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRh_s1(Word32 Rx, Word32 Rs,
+   Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpynac_RhRh_s1 __builtin_HEXAGON_M2_mpy_nac_hh_s1
/* ==========================================================================
Assembly Syntax: Rx32-=mpy(Rs32.h,Rt32.l)
C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRl(Word32 Rx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRl(Word32 Rx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRl(Word32 Rx, Word32 Rs, Word32
+   Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRl…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpynac_RhRl __builtin_HEXAGON_M2_mpy_nac_hl_s0
/* ==========================================================================
Assembly Syntax: Rx32-=mpy(Rs32.h,Rt32.l):<<1
C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRl_s1(Word32 Rx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRl_s1(Word32 Rx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRl_s1(Word32 Rx, Word32 Rs,
+   Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpynac_RhRl_s1 __builtin_HEXAGON_M2_mpy_nac_hl_s1
/* ==========================================================================
Assembly Syntax: Rx32-=mpy(Rs32.l,Rt32.h)
C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRh(Word32 Rx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRh(Word32 Rx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRh(Word32 Rx, Word32 Rs, Word32
+   Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRh…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpynac_RlRh __builtin_HEXAGON_M2_mpy_nac_lh_s0
/* ==========================================================================
Assembly Syntax: Rx32-=mpy(Rs32.l,Rt32.h):<<1
C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRh_s1(Word32 Rx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRh_s1(Word32 Rx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRh_s1(Word32 Rx, Word32 Rs,
+   Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpynac_RlRh_s1 __builtin_HEXAGON_M2_mpy_nac_lh_s1
/* ==========================================================================
Assembly Syntax: Rx32-=mpy(Rs32.l,Rt32.l)
C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRl(Word32 Rx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRl(Word32 Rx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRl(Word32 Rx, Word32 Rs, Word32
+   Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRl…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpynac_RlRl __builtin_HEXAGON_M2_mpy_nac_ll_s0
/* ==========================================================================
Assembly Syntax: Rx32-=mpy(Rs32.l,Rt32.l):<<1
C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRl_s1(Word32 Rx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRl_s1(Word32 Rx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRl_s1(Word32 Rx, Word32 Rs,
+   Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpynac_RlRl_s1 __builtin_HEXAGON_M2_mpy_nac_ll_s1
/* ==========================================================================
Assembly Syntax: Rx32-=mpy(Rs32.h,Rt32.h):sat
C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRh_sat(Word32 Rx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRh_sat(Word32 Rx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRh_sat(Word32 Rx, Word32 Rs,
+   Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpynac_RhRh_sat __builtin_HEXAGON_M2_mpy_nac_sat_hh_s0
/* ==========================================================================
Assembly Syntax: Rx32-=mpy(Rs32.h,Rt32.h):<<1:sat
C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRh_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRh_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRh_s1_sat(Word32 Rx, Word32 Rs,
+   Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpynac_RhRh_s1_sat __builtin_HEXAGON_M2_mpy_nac_sat_hh_s1
/* ==========================================================================
Assembly Syntax: Rx32-=mpy(Rs32.h,Rt32.l):sat
C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRl_sat(Word32 Rx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRl_sat(Word32 Rx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRl_sat(Word32 Rx, Word32 Rs,
+   Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpynac_RhRl_sat __builtin_HEXAGON_M2_mpy_nac_sat_hl_s0
/* ==========================================================================
Assembly Syntax: Rx32-=mpy(Rs32.h,Rt32.l):<<1:sat
C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRl_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRl_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRl_s1_sat(Word32 Rx, Word32 Rs,
+   Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpynac_RhRl_s1_sat __builtin_HEXAGON_M2_mpy_nac_sat_hl_s1
/* ==========================================================================
Assembly Syntax: Rx32-=mpy(Rs32.l,Rt32.h):sat
C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRh_sat(Word32 Rx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRh_sat(Word32 Rx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRh_sat(Word32 Rx, Word32 Rs,
+   Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpynac_RlRh_sat __builtin_HEXAGON_M2_mpy_nac_sat_lh_s0
/* ==========================================================================
Assembly Syntax: Rx32-=mpy(Rs32.l,Rt32.h):<<1:sat
C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRh_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRh_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRh_s1_sat(Word32 Rx, Word32 Rs,
+   Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpynac_RlRh_s1_sat __builtin_HEXAGON_M2_mpy_nac_sat_lh_s1
/* ==========================================================================
Assembly Syntax: Rx32-=mpy(Rs32.l,Rt32.l):sat
C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRl_sat(Word32 Rx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRl_sat(Word32 Rx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRl_sat(Word32 Rx, Word32 Rs,
+   Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpynac_RlRl_sat __builtin_HEXAGON_M2_mpy_nac_sat_ll_s0
/* ==========================================================================
Assembly Syntax: Rx32-=mpy(Rs32.l,Rt32.l):<<1:sat
C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRl_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRl_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRl_s1_sat(Word32 Rx, Word32 Rs,
+   Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpynac_RlRl_s1_sat __builtin_HEXAGON_M2_mpy_nac_sat_ll_s1
/* ==========================================================================
Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.h):rnd
C Intrinsic Prototype: Word32 Q6_R_mpy_RhRh_rnd(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpy_RhRh_rnd __builtin_HEXAGON_M2_mpy_rnd_hh_s0
/* ==========================================================================
Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.h):<<1:rnd
C Intrinsic Prototype: Word32 Q6_R_mpy_RhRh_s1_rnd(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpy_RhRh_s1_rnd __builtin_HEXAGON_M2_mpy_rnd_hh_s1
/* ==========================================================================
Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.l):rnd
C Intrinsic Prototype: Word32 Q6_R_mpy_RhRl_rnd(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpy_RhRl_rnd __builtin_HEXAGON_M2_mpy_rnd_hl_s0
/* ==========================================================================
Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.l):<<1:rnd
C Intrinsic Prototype: Word32 Q6_R_mpy_RhRl_s1_rnd(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpy_RhRl_s1_rnd __builtin_HEXAGON_M2_mpy_rnd_hl_s1
/* ==========================================================================
Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.h):rnd
C Intrinsic Prototype: Word32 Q6_R_mpy_RlRh_rnd(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpy_RlRh_rnd __builtin_HEXAGON_M2_mpy_rnd_lh_s0
/* ==========================================================================
Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.h):<<1:rnd
C Intrinsic Prototype: Word32 Q6_R_mpy_RlRh_s1_rnd(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpy_RlRh_s1_rnd __builtin_HEXAGON_M2_mpy_rnd_lh_s1
/* ==========================================================================
Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.l):rnd
C Intrinsic Prototype: Word32 Q6_R_mpy_RlRl_rnd(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpy_RlRl_rnd __builtin_HEXAGON_M2_mpy_rnd_ll_s0
/* ==========================================================================
Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.l):<<1:rnd
C Intrinsic Prototype: Word32 Q6_R_mpy_RlRl_s1_rnd(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpy_RlRl_s1_rnd __builtin_HEXAGON_M2_mpy_rnd_ll_s1
/* ==========================================================================
Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.h):sat
C Intrinsic Prototype: Word32 Q6_R_mpy_RhRh_sat(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpy_RhRh_sat __builtin_HEXAGON_M2_mpy_sat_hh_s0
/* ==========================================================================
Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.h):<<1:sat
C Intrinsic Prototype: Word32 Q6_R_mpy_RhRh_s1_sat(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpy_RhRh_s1_sat __builtin_HEXAGON_M2_mpy_sat_hh_s1
/* ==========================================================================
Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.l):sat
C Intrinsic Prototype: Word32 Q6_R_mpy_RhRl_sat(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpy_RhRl_sat __builtin_HEXAGON_M2_mpy_sat_hl_s0
/* ==========================================================================
Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.l):<<1:sat
C Intrinsic Prototype: Word32 Q6_R_mpy_RhRl_s1_sat(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpy_RhRl_s1_sat __builtin_HEXAGON_M2_mpy_sat_hl_s1
/* ==========================================================================
Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.h):sat
C Intrinsic Prototype: Word32 Q6_R_mpy_RlRh_sat(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpy_RlRh_sat __builtin_HEXAGON_M2_mpy_sat_lh_s0
/* ==========================================================================
Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.h):<<1:sat
C Intrinsic Prototype: Word32 Q6_R_mpy_RlRh_s1_sat(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpy_RlRh_s1_sat __builtin_HEXAGON_M2_mpy_sat_lh_s1
/* ==========================================================================
Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.l):sat
C Intrinsic Prototype: Word32 Q6_R_mpy_RlRl_sat(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpy_RlRl_sat __builtin_HEXAGON_M2_mpy_sat_ll_s0
/* ==========================================================================
Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.l):<<1:sat
C Intrinsic Prototype: Word32 Q6_R_mpy_RlRl_s1_sat(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpy_RlRl_s1_sat __builtin_HEXAGON_M2_mpy_sat_ll_s1
/* ==========================================================================
Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.h):rnd:sat
C Intrinsic Prototype: Word32 Q6_R_mpy_RhRh_rnd_sat(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpy_RhRh_rnd_sat __builtin_HEXAGON_M2_mpy_sat_rnd_hh_s0
/* ==========================================================================
Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.h):<<1:rnd:sat
C Intrinsic Prototype: Word32 Q6_R_mpy_RhRh_s1_rnd_sat(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpy_RhRh_s1_rnd_sat __builtin_HEXAGON_M2_mpy_sat_rnd_hh_s1
/* ==========================================================================
Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.l):rnd:sat
C Intrinsic Prototype: Word32 Q6_R_mpy_RhRl_rnd_sat(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpy_RhRl_rnd_sat __builtin_HEXAGON_M2_mpy_sat_rnd_hl_s0
/* ==========================================================================
Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.l):<<1:rnd:sat
C Intrinsic Prototype: Word32 Q6_R_mpy_RhRl_s1_rnd_sat(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpy_RhRl_s1_rnd_sat __builtin_HEXAGON_M2_mpy_sat_rnd_hl_s1
/* ==========================================================================
Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.h):rnd:sat
C Intrinsic Prototype: Word32 Q6_R_mpy_RlRh_rnd_sat(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpy_RlRh_rnd_sat __builtin_HEXAGON_M2_mpy_sat_rnd_lh_s0
/* ==========================================================================
Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.h):<<1:rnd:sat
C Intrinsic Prototype: Word32 Q6_R_mpy_RlRh_s1_rnd_sat(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpy_RlRh_s1_rnd_sat __builtin_HEXAGON_M2_mpy_sat_rnd_lh_s1
/* ==========================================================================
Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.l):rnd:sat
C Intrinsic Prototype: Word32 Q6_R_mpy_RlRl_rnd_sat(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpy_RlRl_rnd_sat __builtin_HEXAGON_M2_mpy_sat_rnd_ll_s0
/* ==========================================================================
Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.l):<<1:rnd:sat
C Intrinsic Prototype: Word32 Q6_R_mpy_RlRl_s1_rnd_sat(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpy_RlRl_s1_rnd_sat __builtin_HEXAGON_M2_mpy_sat_rnd_ll_s1
/* ==========================================================================
Assembly Syntax: Rd32=mpy(Rs32,Rt32)
C Intrinsic Prototype: Word32 Q6_R_mpy_RR(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpy_RR __builtin_HEXAGON_M2_mpy_up
/* ==========================================================================
Assembly Syntax: Rd32=mpy(Rs32,Rt32):<<1
C Intrinsic Prototype: Word32 Q6_R_mpy_RR_s1(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpy_RR_s1 __builtin_HEXAGON_M2_mpy_up_s1
/* ==========================================================================
Assembly Syntax: Rd32=mpy(Rs32,Rt32):<<1:sat
C Intrinsic Prototype: Word32 Q6_R_mpy_RR_s1_sat(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpy_RR_s1_sat __builtin_HEXAGON_M2_mpy_up_s1_sat
/* ==========================================================================
Assembly Syntax: Rxx32+=mpy(Rs32.h,Rt32.h)
C Intrinsic Prototype: Word64 Q6_P_mpyacc_RhRh(Word64 Rxx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_mpyacc_RhRh(Word64 Rxx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_mpyacc_RhRh(Word64 Rxx, Word32 Rs, Word32
+   Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_mpyacc_RhRh…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mpyacc_RhRh __builtin_HEXAGON_M2_mpyd_acc_hh_s0
/* ==========================================================================
Assembly Syntax: Rxx32+=mpy(Rs32.h,Rt32.h):<<1
C Intrinsic Prototype: Word64 Q6_P_mpyacc_RhRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_mpyacc_RhRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_mpyacc_RhRh_s1(Word64 Rxx, Word32 Rs,
+   Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mpyacc_RhRh_s1 __builtin_HEXAGON_M2_mpyd_acc_hh_s1
/* ==========================================================================
Assembly Syntax: Rxx32+=mpy(Rs32.h,Rt32.l)
C Intrinsic Prototype: Word64 Q6_P_mpyacc_RhRl(Word64 Rxx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_mpyacc_RhRl(Word64 Rxx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_mpyacc_RhRl(Word64 Rxx, Word32 Rs, Word32
+   Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_mpyacc_RhRl…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mpyacc_RhRl __builtin_HEXAGON_M2_mpyd_acc_hl_s0
/* ==========================================================================
Assembly Syntax: Rxx32+=mpy(Rs32.h,Rt32.l):<<1
C Intrinsic Prototype: Word64 Q6_P_mpyacc_RhRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_mpyacc_RhRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_mpyacc_RhRl_s1(Word64 Rxx, Word32 Rs,
+   Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mpyacc_RhRl_s1 __builtin_HEXAGON_M2_mpyd_acc_hl_s1
/* ==========================================================================
Assembly Syntax: Rxx32+=mpy(Rs32.l,Rt32.h)
C Intrinsic Prototype: Word64 Q6_P_mpyacc_RlRh(Word64 Rxx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_mpyacc_RlRh(Word64 Rxx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_mpyacc_RlRh(Word64 Rxx, Word32 Rs, Word32
+   Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_mpyacc_RlRh…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mpyacc_RlRh __builtin_HEXAGON_M2_mpyd_acc_lh_s0
/* ==========================================================================
Assembly Syntax: Rxx32+=mpy(Rs32.l,Rt32.h):<<1
C Intrinsic Prototype: Word64 Q6_P_mpyacc_RlRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_mpyacc_RlRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_mpyacc_RlRh_s1(Word64 Rxx, Word32 Rs,
+   Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mpyacc_RlRh_s1 __builtin_HEXAGON_M2_mpyd_acc_lh_s1
/* ==========================================================================
Assembly Syntax: Rxx32+=mpy(Rs32.l,Rt32.l)
C Intrinsic Prototype: Word64 Q6_P_mpyacc_RlRl(Word64 Rxx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_mpyacc_RlRl(Word64 Rxx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_mpyacc_RlRl(Word64 Rxx, Word32 Rs, Word32
+   Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_mpyacc_RlRl…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mpyacc_RlRl __builtin_HEXAGON_M2_mpyd_acc_ll_s0
/* ==========================================================================
Assembly Syntax: Rxx32+=mpy(Rs32.l,Rt32.l):<<1
C Intrinsic Prototype: Word64 Q6_P_mpyacc_RlRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_mpyacc_RlRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_mpyacc_RlRl_s1(Word64 Rxx, Word32 Rs,
+   Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mpyacc_RlRl_s1 __builtin_HEXAGON_M2_mpyd_acc_ll_s1
/* ==========================================================================
Assembly Syntax: Rdd32=mpy(Rs32.h,Rt32.h)
C Intrinsic Prototype: Word64 Q6_P_mpy_RhRh(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mpy_RhRh __builtin_HEXAGON_M2_mpyd_hh_s0
/* ==========================================================================
Assembly Syntax: Rdd32=mpy(Rs32.h,Rt32.h):<<1
C Intrinsic Prototype: Word64 Q6_P_mpy_RhRh_s1(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mpy_RhRh_s1 __builtin_HEXAGON_M2_mpyd_hh_s1
/* ==========================================================================
Assembly Syntax: Rdd32=mpy(Rs32.h,Rt32.l)
C Intrinsic Prototype: Word64 Q6_P_mpy_RhRl(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mpy_RhRl __builtin_HEXAGON_M2_mpyd_hl_s0
/* ==========================================================================
Assembly Syntax: Rdd32=mpy(Rs32.h,Rt32.l):<<1
C Intrinsic Prototype: Word64 Q6_P_mpy_RhRl_s1(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mpy_RhRl_s1 __builtin_HEXAGON_M2_mpyd_hl_s1
/* ==========================================================================
Assembly Syntax: Rdd32=mpy(Rs32.l,Rt32.h)
C Intrinsic Prototype: Word64 Q6_P_mpy_RlRh(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mpy_RlRh __builtin_HEXAGON_M2_mpyd_lh_s0
/* ==========================================================================
Assembly Syntax: Rdd32=mpy(Rs32.l,Rt32.h):<<1
C Intrinsic Prototype: Word64 Q6_P_mpy_RlRh_s1(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mpy_RlRh_s1 __builtin_HEXAGON_M2_mpyd_lh_s1
/* ==========================================================================
Assembly Syntax: Rdd32=mpy(Rs32.l,Rt32.l)
C Intrinsic Prototype: Word64 Q6_P_mpy_RlRl(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mpy_RlRl __builtin_HEXAGON_M2_mpyd_ll_s0
/* ==========================================================================
Assembly Syntax: Rdd32=mpy(Rs32.l,Rt32.l):<<1
C Intrinsic Prototype: Word64 Q6_P_mpy_RlRl_s1(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mpy_RlRl_s1 __builtin_HEXAGON_M2_mpyd_ll_s1
/* ==========================================================================
Assembly Syntax: Rxx32-=mpy(Rs32.h,Rt32.h)
C Intrinsic Prototype: Word64 Q6_P_mpynac_RhRh(Word64 Rxx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_mpynac_RhRh(Word64 Rxx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_mpynac_RhRh(Word64 Rxx, Word32 Rs, Word32
+   Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_mpynac_RhRh…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mpynac_RhRh __builtin_HEXAGON_M2_mpyd_nac_hh_s0
/* ==========================================================================
Assembly Syntax: Rxx32-=mpy(Rs32.h,Rt32.h):<<1
C Intrinsic Prototype: Word64 Q6_P_mpynac_RhRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_mpynac_RhRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_mpynac_RhRh_s1(Word64 Rxx, Word32 Rs,
+   Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mpynac_RhRh_s1 __builtin_HEXAGON_M2_mpyd_nac_hh_s1
/* ==========================================================================
Assembly Syntax: Rxx32-=mpy(Rs32.h,Rt32.l)
C Intrinsic Prototype: Word64 Q6_P_mpynac_RhRl(Word64 Rxx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_mpynac_RhRl(Word64 Rxx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_mpynac_RhRl(Word64 Rxx, Word32 Rs, Word32
+   Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_mpynac_RhRl…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mpynac_RhRl __builtin_HEXAGON_M2_mpyd_nac_hl_s0
/* ==========================================================================
Assembly Syntax: Rxx32-=mpy(Rs32.h,Rt32.l):<<1
C Intrinsic Prototype: Word64 Q6_P_mpynac_RhRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_mpynac_RhRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_mpynac_RhRl_s1(Word64 Rxx, Word32 Rs,
+   Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mpynac_RhRl_s1 __builtin_HEXAGON_M2_mpyd_nac_hl_s1
/* ==========================================================================
Assembly Syntax: Rxx32-=mpy(Rs32.l,Rt32.h)
C Intrinsic Prototype: Word64 Q6_P_mpynac_RlRh(Word64 Rxx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_mpynac_RlRh(Word64 Rxx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_mpynac_RlRh(Word64 Rxx, Word32 Rs, Word32
+   Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_mpynac_RlRh…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mpynac_RlRh __builtin_HEXAGON_M2_mpyd_nac_lh_s0
/* ==========================================================================
Assembly Syntax: Rxx32-=mpy(Rs32.l,Rt32.h):<<1
C Intrinsic Prototype: Word64 Q6_P_mpynac_RlRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_mpynac_RlRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_mpynac_RlRh_s1(Word64 Rxx, Word32 Rs,
+   Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mpynac_RlRh_s1 __builtin_HEXAGON_M2_mpyd_nac_lh_s1
/* ==========================================================================
Assembly Syntax: Rxx32-=mpy(Rs32.l,Rt32.l)
C Intrinsic Prototype: Word64 Q6_P_mpynac_RlRl(Word64 Rxx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_mpynac_RlRl(Word64 Rxx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_mpynac_RlRl(Word64 Rxx, Word32 Rs, Word32
+   Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_mpynac_RlRl…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mpynac_RlRl __builtin_HEXAGON_M2_mpyd_nac_ll_s0
/* ==========================================================================
Assembly Syntax: Rxx32-=mpy(Rs32.l,Rt32.l):<<1
C Intrinsic Prototype: Word64 Q6_P_mpynac_RlRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_mpynac_RlRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_mpynac_RlRl_s1(Word64 Rxx, Word32 Rs,
+   Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mpynac_RlRl_s1 __builtin_HEXAGON_M2_mpyd_nac_ll_s1
/* ==========================================================================
Assembly Syntax: Rdd32=mpy(Rs32.h,Rt32.h):rnd
C Intrinsic Prototype: Word64 Q6_P_mpy_RhRh_rnd(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mpy_RhRh_rnd __builtin_HEXAGON_M2_mpyd_rnd_hh_s0
/* ==========================================================================
Assembly Syntax: Rdd32=mpy(Rs32.h,Rt32.h):<<1:rnd
C Intrinsic Prototype: Word64 Q6_P_mpy_RhRh_s1_rnd(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mpy_RhRh_s1_rnd __builtin_HEXAGON_M2_mpyd_rnd_hh_s1
/* ==========================================================================
Assembly Syntax: Rdd32=mpy(Rs32.h,Rt32.l):rnd
C Intrinsic Prototype: Word64 Q6_P_mpy_RhRl_rnd(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mpy_RhRl_rnd __builtin_HEXAGON_M2_mpyd_rnd_hl_s0
/* ==========================================================================
Assembly Syntax: Rdd32=mpy(Rs32.h,Rt32.l):<<1:rnd
C Intrinsic Prototype: Word64 Q6_P_mpy_RhRl_s1_rnd(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mpy_RhRl_s1_rnd __builtin_HEXAGON_M2_mpyd_rnd_hl_s1
/* ==========================================================================
Assembly Syntax: Rdd32=mpy(Rs32.l,Rt32.h):rnd
C Intrinsic Prototype: Word64 Q6_P_mpy_RlRh_rnd(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mpy_RlRh_rnd __builtin_HEXAGON_M2_mpyd_rnd_lh_s0
/* ==========================================================================
Assembly Syntax: Rdd32=mpy(Rs32.l,Rt32.h):<<1:rnd
C Intrinsic Prototype: Word64 Q6_P_mpy_RlRh_s1_rnd(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mpy_RlRh_s1_rnd __builtin_HEXAGON_M2_mpyd_rnd_lh_s1
/* ==========================================================================
Assembly Syntax: Rdd32=mpy(Rs32.l,Rt32.l):rnd
C Intrinsic Prototype: Word64 Q6_P_mpy_RlRl_rnd(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mpy_RlRl_rnd __builtin_HEXAGON_M2_mpyd_rnd_ll_s0
/* ==========================================================================
Assembly Syntax: Rdd32=mpy(Rs32.l,Rt32.l):<<1:rnd
C Intrinsic Prototype: Word64 Q6_P_mpy_RlRl_s1_rnd(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mpy_RlRl_s1_rnd __builtin_HEXAGON_M2_mpyd_rnd_ll_s1
/* ==========================================================================
Assembly Syntax: Rd32=mpyi(Rs32,Rt32)
C Intrinsic Prototype: Word32 Q6_R_mpyi_RR(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpyi_RR __builtin_HEXAGON_M2_mpyi
/* ==========================================================================
Assembly Syntax: Rd32=mpyi(Rs32,#m9)
C Intrinsic Prototype: Word32 Q6_R_mpyi_RI(Word32 Rs, Word32 Im9)
Instruction Type: M
Execution Slots: SLOT0123
========================================================================== */
#define Q6_R_mpyi_RI __builtin_HEXAGON_M2_mpysmi
/* ==========================================================================
Assembly Syntax: Rd32=mpysu(Rs32,Rt32)
C Intrinsic Prototype: Word32 Q6_R_mpysu_RR(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpysu_RR __builtin_HEXAGON_M2_mpysu_up
/* ==========================================================================
Assembly Syntax: Rx32+=mpyu(Rs32.h,Rt32.h)
C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RhRh(Word32 Rx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RhRh(Word32 Rx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RhRh(Word32 Rx, Word32 Rs, Word32
+   Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RhRh…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpyuacc_RhRh __builtin_HEXAGON_M2_mpyu_acc_hh_s0
/* ==========================================================================
Assembly Syntax: Rx32+=mpyu(Rs32.h,Rt32.h):<<1
C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RhRh_s1(Word32 Rx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RhRh_s1(Word32 Rx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RhRh_s1(Word32 Rx, Word32 Rs,
+   Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpyuacc_RhRh_s1 __builtin_HEXAGON_M2_mpyu_acc_hh_s1
/* ==========================================================================
Assembly Syntax: Rx32+=mpyu(Rs32.h,Rt32.l)
C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RhRl(Word32 Rx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RhRl(Word32 Rx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RhRl(Word32 Rx, Word32 Rs, Word32
+   Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RhRl…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpyuacc_RhRl __builtin_HEXAGON_M2_mpyu_acc_hl_s0
/* ==========================================================================
Assembly Syntax: Rx32+=mpyu(Rs32.h,Rt32.l):<<1
C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RhRl_s1(Word32 Rx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RhRl_s1(Word32 Rx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RhRl_s1(Word32 Rx, Word32 Rs,
+   Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpyuacc_RhRl_s1 __builtin_HEXAGON_M2_mpyu_acc_hl_s1
/* ==========================================================================
Assembly Syntax: Rx32+=mpyu(Rs32.l,Rt32.h)
C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RlRh(Word32 Rx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RlRh(Word32 Rx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RlRh(Word32 Rx, Word32 Rs, Word32
+   Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RlRh…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpyuacc_RlRh __builtin_HEXAGON_M2_mpyu_acc_lh_s0
/* ==========================================================================
Assembly Syntax: Rx32+=mpyu(Rs32.l,Rt32.h):<<1
C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RlRh_s1(Word32 Rx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RlRh_s1(Word32 Rx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RlRh_s1(Word32 Rx, Word32 Rs,
+   Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpyuacc_RlRh_s1 __builtin_HEXAGON_M2_mpyu_acc_lh_s1
/* ==========================================================================
Assembly Syntax: Rx32+=mpyu(Rs32.l,Rt32.l)
C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RlRl(Word32 Rx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RlRl(Word32 Rx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RlRl(Word32 Rx, Word32 Rs, Word32
+   Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RlRl…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpyuacc_RlRl __builtin_HEXAGON_M2_mpyu_acc_ll_s0
/* ==========================================================================
Assembly Syntax: Rx32+=mpyu(Rs32.l,Rt32.l):<<1
C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RlRl_s1(Word32 Rx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RlRl_s1(Word32 Rx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RlRl_s1(Word32 Rx, Word32 Rs,
+   Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpyuacc_RlRl_s1 __builtin_HEXAGON_M2_mpyu_acc_ll_s1
/* ==========================================================================
Assembly Syntax: Rd32=mpyu(Rs32.h,Rt32.h)
C Intrinsic Prototype: UWord32 Q6_R_mpyu_RhRh(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpyu_RhRh __builtin_HEXAGON_M2_mpyu_hh_s0
/* ==========================================================================
Assembly Syntax: Rd32=mpyu(Rs32.h,Rt32.h):<<1
C Intrinsic Prototype: UWord32 Q6_R_mpyu_RhRh_s1(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpyu_RhRh_s1 __builtin_HEXAGON_M2_mpyu_hh_s1
/* ==========================================================================
Assembly Syntax: Rd32=mpyu(Rs32.h,Rt32.l)
C Intrinsic Prototype: UWord32 Q6_R_mpyu_RhRl(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpyu_RhRl __builtin_HEXAGON_M2_mpyu_hl_s0
/* ==========================================================================
Assembly Syntax: Rd32=mpyu(Rs32.h,Rt32.l):<<1
C Intrinsic Prototype: UWord32 Q6_R_mpyu_RhRl_s1(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpyu_RhRl_s1 __builtin_HEXAGON_M2_mpyu_hl_s1
/* ==========================================================================
Assembly Syntax: Rd32=mpyu(Rs32.l,Rt32.h)
C Intrinsic Prototype: UWord32 Q6_R_mpyu_RlRh(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpyu_RlRh __builtin_HEXAGON_M2_mpyu_lh_s0
/* ==========================================================================
Assembly Syntax: Rd32=mpyu(Rs32.l,Rt32.h):<<1
C Intrinsic Prototype: UWord32 Q6_R_mpyu_RlRh_s1(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpyu_RlRh_s1 __builtin_HEXAGON_M2_mpyu_lh_s1
/* ==========================================================================
Assembly Syntax: Rd32=mpyu(Rs32.l,Rt32.l)
C Intrinsic Prototype: UWord32 Q6_R_mpyu_RlRl(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpyu_RlRl __builtin_HEXAGON_M2_mpyu_ll_s0
/* ==========================================================================
Assembly Syntax: Rd32=mpyu(Rs32.l,Rt32.l):<<1
C Intrinsic Prototype: UWord32 Q6_R_mpyu_RlRl_s1(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpyu_RlRl_s1 __builtin_HEXAGON_M2_mpyu_ll_s1
/* ==========================================================================
Assembly Syntax: Rx32-=mpyu(Rs32.h,Rt32.h)
C Intrinsic Prototype: Word32 Q6_R_mpyunac_RhRh(Word32 Rx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_mpyunac_RhRh(Word32 Rx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_mpyunac_RhRh(Word32 Rx, Word32 Rs, Word32
+   Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_mpyunac_RhRh…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpyunac_RhRh __builtin_HEXAGON_M2_mpyu_nac_hh_s0
/* ==========================================================================
Assembly Syntax: Rx32-=mpyu(Rs32.h,Rt32.h):<<1
C Intrinsic Prototype: Word32 Q6_R_mpyunac_RhRh_s1(Word32 Rx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_mpyunac_RhRh_s1(Word32 Rx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_mpyunac_RhRh_s1(Word32 Rx, Word32 Rs,
+   Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpyunac_RhRh_s1 __builtin_HEXAGON_M2_mpyu_nac_hh_s1
/* ==========================================================================
Assembly Syntax: Rx32-=mpyu(Rs32.h,Rt32.l)
C Intrinsic Prototype: Word32 Q6_R_mpyunac_RhRl(Word32 Rx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_mpyunac_RhRl(Word32 Rx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_mpyunac_RhRl(Word32 Rx, Word32 Rs, Word32
+   Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_mpyunac_RhRl…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpyunac_RhRl __builtin_HEXAGON_M2_mpyu_nac_hl_s0
/* ==========================================================================
Assembly Syntax: Rx32-=mpyu(Rs32.h,Rt32.l):<<1
C Intrinsic Prototype: Word32 Q6_R_mpyunac_RhRl_s1(Word32 Rx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_mpyunac_RhRl_s1(Word32 Rx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_mpyunac_RhRl_s1(Word32 Rx, Word32 Rs,
+   Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpyunac_RhRl_s1 __builtin_HEXAGON_M2_mpyu_nac_hl_s1
/* ==========================================================================
Assembly Syntax: Rx32-=mpyu(Rs32.l,Rt32.h)
C Intrinsic Prototype: Word32 Q6_R_mpyunac_RlRh(Word32 Rx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_mpyunac_RlRh(Word32 Rx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_mpyunac_RlRh(Word32 Rx, Word32 Rs, Word32
+   Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_mpyunac_RlRh…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpyunac_RlRh __builtin_HEXAGON_M2_mpyu_nac_lh_s0
/* ==========================================================================
Assembly Syntax: Rx32-=mpyu(Rs32.l,Rt32.h):<<1
C Intrinsic Prototype: Word32 Q6_R_mpyunac_RlRh_s1(Word32 Rx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_mpyunac_RlRh_s1(Word32 Rx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_mpyunac_RlRh_s1(Word32 Rx, Word32 Rs,
+   Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpyunac_RlRh_s1 __builtin_HEXAGON_M2_mpyu_nac_lh_s1
/* ==========================================================================
Assembly Syntax: Rx32-=mpyu(Rs32.l,Rt32.l)
C Intrinsic Prototype: Word32 Q6_R_mpyunac_RlRl(Word32 Rx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_mpyunac_RlRl(Word32 Rx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_mpyunac_RlRl(Word32 Rx, Word32 Rs, Word32
+   Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_mpyunac_RlRl…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpyunac_RlRl __builtin_HEXAGON_M2_mpyu_nac_ll_s0
/* ==========================================================================
Assembly Syntax: Rx32-=mpyu(Rs32.l,Rt32.l):<<1
C Intrinsic Prototype: Word32 Q6_R_mpyunac_RlRl_s1(Word32 Rx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_mpyunac_RlRl_s1(Word32 Rx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_mpyunac_RlRl_s1(Word32 Rx, Word32 Rs,
+   Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpyunac_RlRl_s1 __builtin_HEXAGON_M2_mpyu_nac_ll_s1
/* ==========================================================================
Assembly Syntax: Rd32=mpyu(Rs32,Rt32)
C Intrinsic Prototype: UWord32 Q6_R_mpyu_RR(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpyu_RR __builtin_HEXAGON_M2_mpyu_up
/* ==========================================================================
Assembly Syntax: Rxx32+=mpyu(Rs32.h,Rt32.h)
C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RhRh(Word64 Rxx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RhRh(Word64 Rxx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RhRh(Word64 Rxx, Word32 Rs, Word32
+   Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RhRh…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mpyuacc_RhRh __builtin_HEXAGON_M2_mpyud_acc_hh_s0
/* ==========================================================================
Assembly Syntax: Rxx32+=mpyu(Rs32.h,Rt32.h):<<1
C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RhRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RhRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RhRh_s1(Word64 Rxx, Word32 Rs,
+   Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mpyuacc_RhRh_s1 __builtin_HEXAGON_M2_mpyud_acc_hh_s1
/* ==========================================================================
Assembly Syntax: Rxx32+=mpyu(Rs32.h,Rt32.l)
C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RhRl(Word64 Rxx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RhRl(Word64 Rxx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RhRl(Word64 Rxx, Word32 Rs, Word32
+   Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RhRl…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mpyuacc_RhRl __builtin_HEXAGON_M2_mpyud_acc_hl_s0
/* ==========================================================================
Assembly Syntax: Rxx32+=mpyu(Rs32.h,Rt32.l):<<1
C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RhRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RhRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RhRl_s1(Word64 Rxx, Word32 Rs,
+   Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mpyuacc_RhRl_s1 __builtin_HEXAGON_M2_mpyud_acc_hl_s1
/* ==========================================================================
Assembly Syntax: Rxx32+=mpyu(Rs32.l,Rt32.h)
C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RlRh(Word64 Rxx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RlRh(Word64 Rxx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RlRh(Word64 Rxx, Word32 Rs, Word32
+   Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RlRh…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mpyuacc_RlRh __builtin_HEXAGON_M2_mpyud_acc_lh_s0
/* ==========================================================================
Assembly Syntax: Rxx32+=mpyu(Rs32.l,Rt32.h):<<1
C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RlRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RlRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RlRh_s1(Word64 Rxx, Word32 Rs,
+   Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mpyuacc_RlRh_s1 __builtin_HEXAGON_M2_mpyud_acc_lh_s1
/* ==========================================================================
Assembly Syntax: Rxx32+=mpyu(Rs32.l,Rt32.l)
C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RlRl(Word64 Rxx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RlRl(Word64 Rxx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RlRl(Word64 Rxx, Word32 Rs, Word32
+   Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RlRl…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mpyuacc_RlRl __builtin_HEXAGON_M2_mpyud_acc_ll_s0
/* ==========================================================================
Assembly Syntax: Rxx32+=mpyu(Rs32.l,Rt32.l):<<1
C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RlRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RlRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RlRl_s1(Word64 Rxx, Word32 Rs,
+   Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mpyuacc_RlRl_s1 __builtin_HEXAGON_M2_mpyud_acc_ll_s1
/* ==========================================================================
Assembly Syntax: Rdd32=mpyu(Rs32.h,Rt32.h)
C Intrinsic Prototype: UWord64 Q6_P_mpyu_RhRh(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mpyu_RhRh __builtin_HEXAGON_M2_mpyud_hh_s0
/* ==========================================================================
Assembly Syntax: Rdd32=mpyu(Rs32.h,Rt32.h):<<1
C Intrinsic Prototype: UWord64 Q6_P_mpyu_RhRh_s1(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mpyu_RhRh_s1 __builtin_HEXAGON_M2_mpyud_hh_s1
/* ==========================================================================
Assembly Syntax: Rdd32=mpyu(Rs32.h,Rt32.l)
C Intrinsic Prototype: UWord64 Q6_P_mpyu_RhRl(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mpyu_RhRl __builtin_HEXAGON_M2_mpyud_hl_s0
/* ==========================================================================
Assembly Syntax: Rdd32=mpyu(Rs32.h,Rt32.l):<<1
C Intrinsic Prototype: UWord64 Q6_P_mpyu_RhRl_s1(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mpyu_RhRl_s1 __builtin_HEXAGON_M2_mpyud_hl_s1
/* ==========================================================================
Assembly Syntax: Rdd32=mpyu(Rs32.l,Rt32.h)
C Intrinsic Prototype: UWord64 Q6_P_mpyu_RlRh(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mpyu_RlRh __builtin_HEXAGON_M2_mpyud_lh_s0
/* ==========================================================================
Assembly Syntax: Rdd32=mpyu(Rs32.l,Rt32.h):<<1
C Intrinsic Prototype: UWord64 Q6_P_mpyu_RlRh_s1(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mpyu_RlRh_s1 __builtin_HEXAGON_M2_mpyud_lh_s1
/* ==========================================================================
Assembly Syntax: Rdd32=mpyu(Rs32.l,Rt32.l)
C Intrinsic Prototype: UWord64 Q6_P_mpyu_RlRl(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mpyu_RlRl __builtin_HEXAGON_M2_mpyud_ll_s0
/* ==========================================================================
Assembly Syntax: Rdd32=mpyu(Rs32.l,Rt32.l):<<1
C Intrinsic Prototype: UWord64 Q6_P_mpyu_RlRl_s1(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mpyu_RlRl_s1 __builtin_HEXAGON_M2_mpyud_ll_s1
/* ==========================================================================
Assembly Syntax: Rxx32-=mpyu(Rs32.h,Rt32.h)
C Intrinsic Prototype: Word64 Q6_P_mpyunac_RhRh(Word64 Rxx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_mpyunac_RhRh(Word64 Rxx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_mpyunac_RhRh(Word64 Rxx, Word32 Rs, Word32
+   Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_mpyunac_RhRh…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mpyunac_RhRh __builtin_HEXAGON_M2_mpyud_nac_hh_s0
/* ==========================================================================
Assembly Syntax: Rxx32-=mpyu(Rs32.h,Rt32.h):<<1
C Intrinsic Prototype: Word64 Q6_P_mpyunac_RhRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_mpyunac_RhRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_mpyunac_RhRh_s1(Word64 Rxx, Word32 Rs,
+   Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mpyunac_RhRh_s1 __builtin_HEXAGON_M2_mpyud_nac_hh_s1
/* ==========================================================================
Assembly Syntax: Rxx32-=mpyu(Rs32.h,Rt32.l)
C Intrinsic Prototype: Word64 Q6_P_mpyunac_RhRl(Word64 Rxx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_mpyunac_RhRl(Word64 Rxx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_mpyunac_RhRl(Word64 Rxx, Word32 Rs, Word32
+   Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_mpyunac_RhRl…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mpyunac_RhRl __builtin_HEXAGON_M2_mpyud_nac_hl_s0
/* ==========================================================================
Assembly Syntax: Rxx32-=mpyu(Rs32.h,Rt32.l):<<1
C Intrinsic Prototype: Word64 Q6_P_mpyunac_RhRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_mpyunac_RhRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_mpyunac_RhRl_s1(Word64 Rxx, Word32 Rs,
+   Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mpyunac_RhRl_s1 __builtin_HEXAGON_M2_mpyud_nac_hl_s1
/* ==========================================================================
Assembly Syntax: Rxx32-=mpyu(Rs32.l,Rt32.h)
C Intrinsic Prototype: Word64 Q6_P_mpyunac_RlRh(Word64 Rxx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_mpyunac_RlRh(Word64 Rxx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_mpyunac_RlRh(Word64 Rxx, Word32 Rs, Word32
+   Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_mpyunac_RlRh…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mpyunac_RlRh __builtin_HEXAGON_M2_mpyud_nac_lh_s0
/* ==========================================================================
Assembly Syntax: Rxx32-=mpyu(Rs32.l,Rt32.h):<<1
C Intrinsic Prototype: Word64 Q6_P_mpyunac_RlRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_mpyunac_RlRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_mpyunac_RlRh_s1(Word64 Rxx, Word32 Rs,
+   Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mpyunac_RlRh_s1 __builtin_HEXAGON_M2_mpyud_nac_lh_s1
/* ==========================================================================
Assembly Syntax: Rxx32-=mpyu(Rs32.l,Rt32.l)
C Intrinsic Prototype: Word64 Q6_P_mpyunac_RlRl(Word64 Rxx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_mpyunac_RlRl(Word64 Rxx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_mpyunac_RlRl(Word64 Rxx, Word32 Rs, Word32
+   Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_mpyunac_RlRl…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mpyunac_RlRl __builtin_HEXAGON_M2_mpyud_nac_ll_s0
/* ==========================================================================
Assembly Syntax: Rxx32-=mpyu(Rs32.l,Rt32.l):<<1
C Intrinsic Prototype: Word64 Q6_P_mpyunac_RlRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_mpyunac_RlRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_mpyunac_RlRl_s1(Word64 Rxx, Word32 Rs,
+   Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_mpyunac_RlRl_s1 __builtin_HEXAGON_M2_mpyud_nac_ll_s1
/* ==========================================================================
Assembly Syntax: Rd32=mpyui(Rs32,Rt32)
C Intrinsic Prototype: Word32 Q6_R_mpyui_RR(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT0123
========================================================================== */
#define Q6_R_mpyui_RR __builtin_HEXAGON_M2_mpyui
/* ==========================================================================
Assembly Syntax: Rx32-=add(Rs32,Rt32)
C Intrinsic Prototype: Word32 Q6_R_addnac_RR(Word32 Rx, Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_addnac_RR __builtin_HEXAGON_M2_nacci
/* ==========================================================================
Assembly Syntax: Rx32-=add(Rs32,#s8)
C Intrinsic Prototype: Word32 Q6_R_addnac_RI(Word32 Rx, Word32 Rs, Word32 Is8)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_addnac_RI(Word32 Rx, Word32 Rs, Word32 Is8)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_addnac_RI(Word32 Rx, Word32 Rs, Word32
+   Is8) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_addnac_RI…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_addnac_RI __builtin_HEXAGON_M2_naccii
/* ==========================================================================
Assembly Syntax: Rx32+=sub(Rt32,Rs32)
C Intrinsic Prototype: Word32 Q6_R_subacc_RR(Word32 Rx, Word32 Rt, Word32 Rs)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_subacc_RR __builtin_HEXAGON_M2_subacc
/* ==========================================================================
Assembly Syntax: Rdd32=vabsdiffh(Rtt32,Rss32)
C Intrinsic Prototype: Word64 Q6_P_vabsdiffh_PP(Word64 Rtt, Word64 Rss)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vabsdiffh_PP __builtin_HEXAGON_M2_vabsdiffh
/* ==========================================================================
Assembly Syntax: Rdd32=vabsdiffw(Rtt32,Rss32)
C Intrinsic Prototype: Word64 Q6_P_vabsdiffw_PP(Word64 Rtt, Word64 Rss)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vabsdiffw_PP __builtin_HEXAGON_M2_vabsdiffw
/* ==========================================================================
Assembly Syntax: Rxx32+=vcmpyi(Rss32,Rtt32):sat
C Intrinsic Prototype: Word64 Q6_P_vcmpyiacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vcmpyiacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vcmpyiacc_PP_sat(Word64 Rxx, Word64 Rss,
+   Word64 Rtt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vcmpyiacc_PP_sat __builtin_HEXAGON_M2_vcmac_s0_sat_i
/* ==========================================================================
Assembly Syntax: Rxx32+=vcmpyr(Rss32,Rtt32):sat
C Intrinsic Prototype: Word64 Q6_P_vcmpyracc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vcmpyracc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vcmpyracc_PP_sat(Word64 Rxx, Word64 Rss,
+   Word64 Rtt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vcmpyracc_PP_sat __builtin_HEXAGON_M2_vcmac_s0_sat_r
/* ==========================================================================
Assembly Syntax: Rdd32=vcmpyi(Rss32,Rtt32):sat
C Intrinsic Prototype: Word64 Q6_P_vcmpyi_PP_sat(Word64 Rss, Word64 Rtt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vcmpyi_PP_sat __builtin_HEXAGON_M2_vcmpy_s0_sat_i
/* ==========================================================================
Assembly Syntax: Rdd32=vcmpyr(Rss32,Rtt32):sat
C Intrinsic Prototype: Word64 Q6_P_vcmpyr_PP_sat(Word64 Rss, Word64 Rtt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vcmpyr_PP_sat __builtin_HEXAGON_M2_vcmpy_s0_sat_r
/* ==========================================================================
Assembly Syntax: Rdd32=vcmpyi(Rss32,Rtt32):<<1:sat
C Intrinsic Prototype: Word64 Q6_P_vcmpyi_PP_s1_sat(Word64 Rss, Word64 Rtt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vcmpyi_PP_s1_sat __builtin_HEXAGON_M2_vcmpy_s1_sat_i
/* ==========================================================================
Assembly Syntax: Rdd32=vcmpyr(Rss32,Rtt32):<<1:sat
C Intrinsic Prototype: Word64 Q6_P_vcmpyr_PP_s1_sat(Word64 Rss, Word64 Rtt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vcmpyr_PP_s1_sat __builtin_HEXAGON_M2_vcmpy_s1_sat_r
/* ==========================================================================
Assembly Syntax: Rxx32+=vdmpy(Rss32,Rtt32):sat
C Intrinsic Prototype: Word64 Q6_P_vdmpyacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vdmpyacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vdmpyacc_PP_sat(Word64 Rxx, Word64 Rss,
+   Word64 Rtt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vdmpyacc_PP_sat __builtin_HEXAGON_M2_vdmacs_s0
/* ==========================================================================
Assembly Syntax: Rxx32+=vdmpy(Rss32,Rtt32):<<1:sat
C Intrinsic Prototype: Word64 Q6_P_vdmpyacc_PP_s1_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vdmpyacc_PP_s1_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vdmpyacc_PP_s1_sat(Word64 Rxx, Word64 Rss,
+   Word64 Rtt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vdmpyacc_PP_s1_sat __builtin_HEXAGON_M2_vdmacs_s1
/* ==========================================================================
Assembly Syntax: Rd32=vdmpy(Rss32,Rtt32):rnd:sat
C Intrinsic Prototype: Word32 Q6_R_vdmpy_PP_rnd_sat(Word64 Rss, Word64 Rtt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_vdmpy_PP_rnd_sat __builtin_HEXAGON_M2_vdmpyrs_s0
/* ==========================================================================
Assembly Syntax: Rd32=vdmpy(Rss32,Rtt32):<<1:rnd:sat
C Intrinsic Prototype: Word32 Q6_R_vdmpy_PP_s1_rnd_sat(Word64 Rss, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_vdmpy_PP_s1_rnd_sat(Word64 Rss, Word64 Rtt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_vdmpy_PP_s1_rnd_sat(Word64 Rss, Word64
+   Rtt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_vdmpy_PP_s1_rnd_sat __builtin_HEXAGON_M2_vdmpyrs_s1
/* ==========================================================================
Assembly Syntax: Rdd32=vdmpy(Rss32,Rtt32):sat
C Intrinsic Prototype: Word64 Q6_P_vdmpy_PP_sat(Word64 Rss, Word64 Rtt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vdmpy_PP_sat __builtin_HEXAGON_M2_vdmpys_s0
/* ==========================================================================
Assembly Syntax: Rdd32=vdmpy(Rss32,Rtt32):<<1:sat
C Intrinsic Prototype: Word64 Q6_P_vdmpy_PP_s1_sat(Word64 Rss, Word64 Rtt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vdmpy_PP_s1_sat __builtin_HEXAGON_M2_vdmpys_s1
/* ==========================================================================
Assembly Syntax: Rxx32+=vmpyh(Rs32,Rt32)
C Intrinsic Prototype: Word64 Q6_P_vmpyhacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vmpyhacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vmpyhacc_RR(Word64 Rxx, Word32 Rs, Word32
+   Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_vmpyhacc_RR…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vmpyhacc_RR __builtin_HEXAGON_M2_vmac2
/* ==========================================================================
Assembly Syntax: Rxx32+=vmpyeh(Rss32,Rtt32)
C Intrinsic Prototype: Word64 Q6_P_vmpyehacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vmpyehacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vmpyehacc_PP(Word64 Rxx, Word64 Rss,
+   Word64 Rtt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_vmpyehacc_PP…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vmpyehacc_PP __builtin_HEXAGON_M2_vmac2es
/* ==========================================================================
Assembly Syntax: Rxx32+=vmpyeh(Rss32,Rtt32):sat
C Intrinsic Prototype: Word64 Q6_P_vmpyehacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vmpyehacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vmpyehacc_PP_sat(Word64 Rxx, Word64 Rss,
+   Word64 Rtt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vmpyehacc_PP_sat __builtin_HEXAGON_M2_vmac2es_s0
/* ==========================================================================
Assembly Syntax: Rxx32+=vmpyeh(Rss32,Rtt32):<<1:sat
C Intrinsic Prototype: Word64 Q6_P_vmpyehacc_PP_s1_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vmpyehacc_PP_s1_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vmpyehacc_PP_s1_sat(Word64 Rxx, Word64
+   Rss, Word64 Rtt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vmpyehacc_PP_s1_sat __builtin_HEXAGON_M2_vmac2es_s1
/* ==========================================================================
Assembly Syntax: Rxx32+=vmpyh(Rs32,Rt32):sat
C Intrinsic Prototype: Word64 Q6_P_vmpyhacc_RR_sat(Word64 Rxx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vmpyhacc_RR_sat(Word64 Rxx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vmpyhacc_RR_sat(Word64 Rxx, Word32 Rs,
+   Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vmpyhacc_RR_sat __builtin_HEXAGON_M2_vmac2s_s0
/* ==========================================================================
Assembly Syntax: Rxx32+=vmpyh(Rs32,Rt32):<<1:sat
C Intrinsic Prototype: Word64 Q6_P_vmpyhacc_RR_s1_sat(Word64 Rxx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vmpyhacc_RR_s1_sat(Word64 Rxx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vmpyhacc_RR_s1_sat(Word64 Rxx, Word32 Rs,
+   Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vmpyhacc_RR_s1_sat __builtin_HEXAGON_M2_vmac2s_s1
/* ==========================================================================
Assembly Syntax: Rxx32+=vmpyhsu(Rs32,Rt32):sat
C Intrinsic Prototype: Word64 Q6_P_vmpyhsuacc_RR_sat(Word64 Rxx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vmpyhsuacc_RR_sat(Word64 Rxx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vmpyhsuacc_RR_sat(Word64 Rxx, Word32 Rs,
+   Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vmpyhsuacc_RR_sat __builtin_HEXAGON_M2_vmac2su_s0
/* ==========================================================================
Assembly Syntax: Rxx32+=vmpyhsu(Rs32,Rt32):<<1:sat
C Intrinsic Prototype: Word64 Q6_P_vmpyhsuacc_RR_s1_sat(Word64 Rxx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vmpyhsuacc_RR_s1_sat(Word64 Rxx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vmpyhsuacc_RR_s1_sat(Word64 Rxx, Word32
+   Rs, Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vmpyhsuacc_RR_s1_sat __builtin_HEXAGON_M2_vmac2su_s1
/* ==========================================================================
Assembly Syntax: Rdd32=vmpyeh(Rss32,Rtt32):sat
C Intrinsic Prototype: Word64 Q6_P_vmpyeh_PP_sat(Word64 Rss, Word64 Rtt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vmpyeh_PP_sat __builtin_HEXAGON_M2_vmpy2es_s0
/* ==========================================================================
Assembly Syntax: Rdd32=vmpyeh(Rss32,Rtt32):<<1:sat
C Intrinsic Prototype: Word64 Q6_P_vmpyeh_PP_s1_sat(Word64 Rss, Word64 Rtt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vmpyeh_PP_s1_sat __builtin_HEXAGON_M2_vmpy2es_s1
/* ==========================================================================
Assembly Syntax: Rdd32=vmpyh(Rs32,Rt32):sat
C Intrinsic Prototype: Word64 Q6_P_vmpyh_RR_sat(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vmpyh_RR_sat __builtin_HEXAGON_M2_vmpy2s_s0
/* ==========================================================================
Assembly Syntax: Rd32=vmpyh(Rs32,Rt32):rnd:sat
C Intrinsic Prototype: Word32 Q6_R_vmpyh_RR_rnd_sat(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_vmpyh_RR_rnd_sat __builtin_HEXAGON_M2_vmpy2s_s0pack
/* ==========================================================================
Assembly Syntax: Rdd32=vmpyh(Rs32,Rt32):<<1:sat
C Intrinsic Prototype: Word64 Q6_P_vmpyh_RR_s1_sat(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vmpyh_RR_s1_sat __builtin_HEXAGON_M2_vmpy2s_s1
/* ==========================================================================
Assembly Syntax: Rd32=vmpyh(Rs32,Rt32):<<1:rnd:sat
C Intrinsic Prototype: Word32 Q6_R_vmpyh_RR_s1_rnd_sat(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_vmpyh_RR_s1_rnd_sat __builtin_HEXAGON_M2_vmpy2s_s1pack
/* ==========================================================================
Assembly Syntax: Rdd32=vmpyhsu(Rs32,Rt32):sat
C Intrinsic Prototype: Word64 Q6_P_vmpyhsu_RR_sat(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vmpyhsu_RR_sat __builtin_HEXAGON_M2_vmpy2su_s0
/* ==========================================================================
Assembly Syntax: Rdd32=vmpyhsu(Rs32,Rt32):<<1:sat
C Intrinsic Prototype: Word64 Q6_P_vmpyhsu_RR_s1_sat(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vmpyhsu_RR_s1_sat __builtin_HEXAGON_M2_vmpy2su_s1
/* ==========================================================================
Assembly Syntax: Rd32=vraddh(Rss32,Rtt32)
C Intrinsic Prototype: Word32 Q6_R_vraddh_PP(Word64 Rss, Word64 Rtt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_vraddh_PP __builtin_HEXAGON_M2_vraddh
/* ==========================================================================
Assembly Syntax: Rd32=vradduh(Rss32,Rtt32)
C Intrinsic Prototype: Word32 Q6_R_vradduh_PP(Word64 Rss, Word64 Rtt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_vradduh_PP __builtin_HEXAGON_M2_vradduh
/* ==========================================================================
Assembly Syntax: Rxx32+=vrcmpyi(Rss32,Rtt32)
C Intrinsic Prototype: Word64 Q6_P_vrcmpyiacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vrcmpyiacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vrcmpyiacc_PP(Word64 Rxx, Word64 Rss,
+   Word64 Rtt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_vrcmpyiacc_PP…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vrcmpyiacc_PP __builtin_HEXAGON_M2_vrcmaci_s0
/* ==========================================================================
Assembly Syntax: Rxx32+=vrcmpyi(Rss32,Rtt32*)
C Intrinsic Prototype: Word64 Q6_P_vrcmpyiacc_PP_conj(Word64 Rxx, Word64 Rss, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vrcmpyiacc_PP_conj(Word64 Rxx, Word64 Rss, Word64 Rtt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vrcmpyiacc_PP_conj(Word64 Rxx, Word64 Rss,
+   Word64 Rtt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vrcmpyiacc_PP_conj __builtin_HEXAGON_M2_vrcmaci_s0c
/* ==========================================================================
Assembly Syntax: Rxx32+=vrcmpyr(Rss32,Rtt32)
C Intrinsic Prototype: Word64 Q6_P_vrcmpyracc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vrcmpyracc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vrcmpyracc_PP(Word64 Rxx, Word64 Rss,
+   Word64 Rtt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_vrcmpyracc_PP…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vrcmpyracc_PP __builtin_HEXAGON_M2_vrcmacr_s0
/* ==========================================================================
Assembly Syntax: Rxx32+=vrcmpyr(Rss32,Rtt32*)
C Intrinsic Prototype: Word64 Q6_P_vrcmpyracc_PP_conj(Word64 Rxx, Word64 Rss, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vrcmpyracc_PP_conj(Word64 Rxx, Word64 Rss, Word64 Rtt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vrcmpyracc_PP_conj(Word64 Rxx, Word64 Rss,
+   Word64 Rtt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vrcmpyracc_PP_conj __builtin_HEXAGON_M2_vrcmacr_s0c
/* ==========================================================================
Assembly Syntax: Rdd32=vrcmpyi(Rss32,Rtt32)
C Intrinsic Prototype: Word64 Q6_P_vrcmpyi_PP(Word64 Rss, Word64 Rtt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vrcmpyi_PP __builtin_HEXAGON_M2_vrcmpyi_s0
/* ==========================================================================
Assembly Syntax: Rdd32=vrcmpyi(Rss32,Rtt32*)
C Intrinsic Prototype: Word64 Q6_P_vrcmpyi_PP_conj(Word64 Rss, Word64 Rtt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vrcmpyi_PP_conj __builtin_HEXAGON_M2_vrcmpyi_s0c
/* ==========================================================================
Assembly Syntax: Rdd32=vrcmpyr(Rss32,Rtt32)
C Intrinsic Prototype: Word64 Q6_P_vrcmpyr_PP(Word64 Rss, Word64 Rtt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vrcmpyr_PP __builtin_HEXAGON_M2_vrcmpyr_s0
/* ==========================================================================
Assembly Syntax: Rdd32=vrcmpyr(Rss32,Rtt32*)
C Intrinsic Prototype: Word64 Q6_P_vrcmpyr_PP_conj(Word64 Rss, Word64 Rtt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vrcmpyr_PP_conj __builtin_HEXAGON_M2_vrcmpyr_s0c
/* ==========================================================================
Assembly Syntax: Rxx32+=vrcmpys(Rss32,Rt32):<<1:sat
C Intrinsic Prototype: Word64 Q6_P_vrcmpysacc_PR_s1_sat(Word64 Rxx, Word64 Rss, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vrcmpysacc_PR_s1_sat(Word64 Rxx, Word64 Rss, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: Word64 Q6_P_vrcmpysacc_PR_s1_sat(Word64 Rxx, Word64
+   Rss, Word32 Rt) Instruction Type:      M Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT0123
========================================================================== */
#define Q6_P_vrcmpysacc_PR_s1_sat __builtin_HEXAGON_M2_vrcmpys_acc_s1
/* ==========================================================================
Assembly Syntax: Rdd32=vrcmpys(Rss32,Rt32):<<1:sat
C Intrinsic Prototype: Word64 Q6_P_vrcmpys_PR_s1_sat(Word64 Rss, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT0123
========================================================================== */
#define Q6_P_vrcmpys_PR_s1_sat __builtin_HEXAGON_M2_vrcmpys_s1
/* ==========================================================================
Assembly Syntax: Rd32=vrcmpys(Rss32,Rt32):<<1:rnd:sat
C Intrinsic Prototype: Word32 Q6_R_vrcmpys_PR_s1_rnd_sat(Word64 Rss, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_vrcmpys_PR_s1_rnd_sat(Word64 Rss, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: Word32 Q6_R_vrcmpys_PR_s1_rnd_sat(Word64 Rss, Word32
+   Rt) Instruction Type:      M Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32…
Instruction Type: M
Execution Slots: SLOT0123
========================================================================== */
#define Q6_R_vrcmpys_PR_s1_rnd_sat __builtin_HEXAGON_M2_vrcmpys_s1rp
/* ==========================================================================
Assembly Syntax: Rxx32+=vrmpyh(Rss32,Rtt32)
C Intrinsic Prototype: Word64 Q6_P_vrmpyhacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vrmpyhacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vrmpyhacc_PP(Word64 Rxx, Word64 Rss,
+   Word64 Rtt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_vrmpyhacc_PP…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vrmpyhacc_PP __builtin_HEXAGON_M2_vrmac_s0
/* ==========================================================================
Assembly Syntax: Rdd32=vrmpyh(Rss32,Rtt32)
C Intrinsic Prototype: Word64 Q6_P_vrmpyh_PP(Word64 Rss, Word64 Rtt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vrmpyh_PP __builtin_HEXAGON_M2_vrmpy_s0
/* ==========================================================================
Assembly Syntax: Rx32^=xor(Rs32,Rt32)
C Intrinsic Prototype: Word32 Q6_R_xorxacc_RR(Word32 Rx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_xorxacc_RR(Word32 Rx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_xorxacc_RR(Word32 Rx, Word32 Rs, Word32
+   Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_xorxacc_RR…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_xorxacc_RR __builtin_HEXAGON_M2_xor_xacc
/* ==========================================================================
Assembly Syntax: Rx32&=and(Rs32,Rt32)
C Intrinsic Prototype: Word32 Q6_R_andand_RR(Word32 Rx, Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_andand_RR __builtin_HEXAGON_M4_and_and
/* ==========================================================================
Assembly Syntax: Rx32&=and(Rs32,~Rt32)
C Intrinsic Prototype: Word32 Q6_R_andand_RnR(Word32 Rx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_andand_RnR(Word32 Rx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_andand_RnR(Word32 Rx, Word32 Rs, Word32
+   Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_andand_RnR…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_andand_RnR __builtin_HEXAGON_M4_and_andn
/* ==========================================================================
Assembly Syntax: Rx32&=or(Rs32,Rt32)
C Intrinsic Prototype: Word32 Q6_R_orand_RR(Word32 Rx, Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_orand_RR __builtin_HEXAGON_M4_and_or
/* ==========================================================================
Assembly Syntax: Rx32&=xor(Rs32,Rt32)
C Intrinsic Prototype: Word32 Q6_R_xorand_RR(Word32 Rx, Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_xorand_RR __builtin_HEXAGON_M4_and_xor
/* ==========================================================================
Assembly Syntax: Rd32=cmpyiwh(Rss32,Rt32):<<1:rnd:sat
C Intrinsic Prototype: Word32 Q6_R_cmpyiwh_PR_s1_rnd_sat(Word64 Rss, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_cmpyiwh_PR_s1_rnd_sat(Word64 Rss, Word32 Rt)
-   Instruction Type:      S_3op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_cmpyiwh_PR_s1_rnd_sat(Word64 Rss, Word32
+   Rt) Instruction Type:      S_3op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32…
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_cmpyiwh_PR_s1_rnd_sat __builtin_HEXAGON_M4_cmpyi_wh
/* ==========================================================================
Assembly Syntax: Rd32=cmpyiwh(Rss32,Rt32*):<<1:rnd:sat
C Intrinsic Prototype: Word32 Q6_R_cmpyiwh_PR_conj_s1_rnd_sat(Word64 Rss, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_cmpyiwh_PR_conj_s1_rnd_sat(Word64 Rss, Word32 Rt)
-   Instruction Type:      S_3op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_cmpyiwh_PR_conj_s1_rnd_sat(Word64 Rss,
+   Word32 Rt) Instruction Type:      S_3op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32…
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_cmpyiwh_PR_conj_s1_rnd_sat __builtin_HEXAGON_M4_cmpyi_whc
/* ==========================================================================
Assembly Syntax: Rd32=cmpyrwh(Rss32,Rt32):<<1:rnd:sat
C Intrinsic Prototype: Word32 Q6_R_cmpyrwh_PR_s1_rnd_sat(Word64 Rss, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_cmpyrwh_PR_s1_rnd_sat(Word64 Rss, Word32 Rt)
-   Instruction Type:      S_3op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_cmpyrwh_PR_s1_rnd_sat(Word64 Rss, Word32
+   Rt) Instruction Type:      S_3op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32…
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_cmpyrwh_PR_s1_rnd_sat __builtin_HEXAGON_M4_cmpyr_wh
/* ==========================================================================
Assembly Syntax: Rd32=cmpyrwh(Rss32,Rt32*):<<1:rnd:sat
C Intrinsic Prototype: Word32 Q6_R_cmpyrwh_PR_conj_s1_rnd_sat(Word64 Rss, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_cmpyrwh_PR_conj_s1_rnd_sat(Word64 Rss, Word32 Rt)
-   Instruction Type:      S_3op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_cmpyrwh_PR_conj_s1_rnd_sat(Word64 Rss,
+   Word32 Rt) Instruction Type:      S_3op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32…
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_cmpyrwh_PR_conj_s1_rnd_sat __builtin_HEXAGON_M4_cmpyr_whc
/* ==========================================================================
Assembly Syntax: Rx32+=mpy(Rs32,Rt32):<<1:sat
C Intrinsic Prototype: Word32 Q6_R_mpyacc_RR_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_mpyacc_RR_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_mpyacc_RR_s1_sat(Word32 Rx, Word32 Rs,
+   Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpyacc_RR_s1_sat __builtin_HEXAGON_M4_mac_up_s1_sat
/* ==========================================================================
Assembly Syntax: Rd32=add(#u6,mpyi(Rs32,#U6))
C Intrinsic Prototype: Word32 Q6_R_add_mpyi_IRI(Word32 Iu6, Word32 Rs, Word32 IU6)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_add_mpyi_IRI(Word32 Iu6, Word32 Rs, Word32 IU6)
-   Instruction Type:      ALU64
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_add_mpyi_IRI(Word32 Iu6, Word32 Rs, Word32
+   IU6) Instruction Type:      ALU64 Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_add_mpyi_IRI…
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_add_mpyi_IRI __builtin_HEXAGON_M4_mpyri_addi
/* ==========================================================================
Assembly Syntax: Rd32=add(Ru32,mpyi(Rs32,#u6))
C Intrinsic Prototype: Word32 Q6_R_add_mpyi_RRI(Word32 Ru, Word32 Rs, Word32 Iu6)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_add_mpyi_RRI(Word32 Ru, Word32 Rs, Word32 Iu6)
-   Instruction Type:      ALU64
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_add_mpyi_RRI(Word32 Ru, Word32 Rs, Word32
+   Iu6) Instruction Type:      ALU64 Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_add_mpyi_RRI…
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_add_mpyi_RRI __builtin_HEXAGON_M4_mpyri_addr
/* ==========================================================================
Assembly Syntax: Rd32=add(Ru32,mpyi(#u6:2,Rs32))
C Intrinsic Prototype: Word32 Q6_R_add_mpyi_RIR(Word32 Ru, Word32 Iu6_2, Word32 Rs)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_add_mpyi_RIR(Word32 Ru, Word32 Iu6_2, Word32 Rs)
-   Instruction Type:      ALU64
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_add_mpyi_RIR(Word32 Ru, Word32 Iu6_2,
+   Word32 Rs) Instruction Type:      ALU64 Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_add_mpyi_RIR…
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_add_mpyi_RIR __builtin_HEXAGON_M4_mpyri_addr_u2
/* ==========================================================================
Assembly Syntax: Rd32=add(#u6,mpyi(Rs32,Rt32))
C Intrinsic Prototype: Word32 Q6_R_add_mpyi_IRR(Word32 Iu6, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_add_mpyi_IRR(Word32 Iu6, Word32 Rs, Word32 Rt)
-   Instruction Type:      ALU64
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_add_mpyi_IRR(Word32 Iu6, Word32 Rs, Word32
+   Rt) Instruction Type:      ALU64 Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_add_mpyi_IRR…
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_add_mpyi_IRR __builtin_HEXAGON_M4_mpyrr_addi
/* ==========================================================================
Assembly Syntax: Ry32=add(Ru32,mpyi(Ry32,Rs32))
C Intrinsic Prototype: Word32 Q6_R_add_mpyi_RRR(Word32 Ru, Word32 Ry, Word32 Rs)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_add_mpyi_RRR(Word32 Ru, Word32 Ry, Word32 Rs)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_add_mpyi_RRR(Word32 Ru, Word32 Ry, Word32
+   Rs) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_add_mpyi_RRR…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_add_mpyi_RRR __builtin_HEXAGON_M4_mpyrr_addr
/* ==========================================================================
Assembly Syntax: Rx32-=mpy(Rs32,Rt32):<<1:sat
C Intrinsic Prototype: Word32 Q6_R_mpynac_RR_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_mpynac_RR_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_mpynac_RR_s1_sat(Word32 Rx, Word32 Rs,
+   Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpynac_RR_s1_sat __builtin_HEXAGON_M4_nac_up_s1_sat
/* ==========================================================================
Assembly Syntax: Rx32|=and(Rs32,Rt32)
C Intrinsic Prototype: Word32 Q6_R_andor_RR(Word32 Rx, Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_andor_RR __builtin_HEXAGON_M4_or_and
/* ==========================================================================
Assembly Syntax: Rx32|=and(Rs32,~Rt32)
C Intrinsic Prototype: Word32 Q6_R_andor_RnR(Word32 Rx, Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_andor_RnR __builtin_HEXAGON_M4_or_andn
/* ==========================================================================
Assembly Syntax: Rx32|=or(Rs32,Rt32)
C Intrinsic Prototype: Word32 Q6_R_oror_RR(Word32 Rx, Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_oror_RR __builtin_HEXAGON_M4_or_or
/* ==========================================================================
Assembly Syntax: Rx32|=xor(Rs32,Rt32)
C Intrinsic Prototype: Word32 Q6_R_xoror_RR(Word32 Rx, Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_xoror_RR __builtin_HEXAGON_M4_or_xor
/* ==========================================================================
Assembly Syntax: Rdd32=pmpyw(Rs32,Rt32)
C Intrinsic Prototype: Word64 Q6_P_pmpyw_RR(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_pmpyw_RR __builtin_HEXAGON_M4_pmpyw
/* ==========================================================================
Assembly Syntax: Rxx32^=pmpyw(Rs32,Rt32)
C Intrinsic Prototype: Word64 Q6_P_pmpywxacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_pmpywxacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_pmpywxacc_RR(Word64 Rxx, Word32 Rs, Word32
+   Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_pmpywxacc_RR…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_pmpywxacc_RR __builtin_HEXAGON_M4_pmpyw_acc
/* ==========================================================================
Assembly Syntax: Rdd32=vpmpyh(Rs32,Rt32)
C Intrinsic Prototype: Word64 Q6_P_vpmpyh_RR(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vpmpyh_RR __builtin_HEXAGON_M4_vpmpyh
/* ==========================================================================
Assembly Syntax: Rxx32^=vpmpyh(Rs32,Rt32)
C Intrinsic Prototype: Word64 Q6_P_vpmpyhxacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vpmpyhxacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vpmpyhxacc_RR(Word64 Rxx, Word32 Rs,
+   Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_vpmpyhxacc_RR…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vpmpyhxacc_RR __builtin_HEXAGON_M4_vpmpyh_acc
/* ==========================================================================
Assembly Syntax: Rxx32+=vrmpyweh(Rss32,Rtt32)
C Intrinsic Prototype: Word64 Q6_P_vrmpywehacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vrmpywehacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vrmpywehacc_PP(Word64 Rxx, Word64 Rss,
+   Word64 Rtt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vrmpywehacc_PP __builtin_HEXAGON_M4_vrmpyeh_acc_s0
/* ==========================================================================
Assembly Syntax: Rxx32+=vrmpyweh(Rss32,Rtt32):<<1
C Intrinsic Prototype: Word64 Q6_P_vrmpywehacc_PP_s1(Word64 Rxx, Word64 Rss, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vrmpywehacc_PP_s1(Word64 Rxx, Word64 Rss, Word64 Rtt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vrmpywehacc_PP_s1(Word64 Rxx, Word64 Rss,
+   Word64 Rtt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vrmpywehacc_PP_s1 __builtin_HEXAGON_M4_vrmpyeh_acc_s1
/* ==========================================================================
Assembly Syntax: Rdd32=vrmpyweh(Rss32,Rtt32)
C Intrinsic Prototype: Word64 Q6_P_vrmpyweh_PP(Word64 Rss, Word64 Rtt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vrmpyweh_PP __builtin_HEXAGON_M4_vrmpyeh_s0
/* ==========================================================================
Assembly Syntax: Rdd32=vrmpyweh(Rss32,Rtt32):<<1
C Intrinsic Prototype: Word64 Q6_P_vrmpyweh_PP_s1(Word64 Rss, Word64 Rtt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vrmpyweh_PP_s1 __builtin_HEXAGON_M4_vrmpyeh_s1
/* ==========================================================================
Assembly Syntax: Rxx32+=vrmpywoh(Rss32,Rtt32)
C Intrinsic Prototype: Word64 Q6_P_vrmpywohacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vrmpywohacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vrmpywohacc_PP(Word64 Rxx, Word64 Rss,
+   Word64 Rtt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vrmpywohacc_PP __builtin_HEXAGON_M4_vrmpyoh_acc_s0
/* ==========================================================================
Assembly Syntax: Rxx32+=vrmpywoh(Rss32,Rtt32):<<1
C Intrinsic Prototype: Word64 Q6_P_vrmpywohacc_PP_s1(Word64 Rxx, Word64 Rss, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vrmpywohacc_PP_s1(Word64 Rxx, Word64 Rss, Word64 Rtt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vrmpywohacc_PP_s1(Word64 Rxx, Word64 Rss,
+   Word64 Rtt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vrmpywohacc_PP_s1 __builtin_HEXAGON_M4_vrmpyoh_acc_s1
/* ==========================================================================
Assembly Syntax: Rdd32=vrmpywoh(Rss32,Rtt32)
C Intrinsic Prototype: Word64 Q6_P_vrmpywoh_PP(Word64 Rss, Word64 Rtt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vrmpywoh_PP __builtin_HEXAGON_M4_vrmpyoh_s0
/* ==========================================================================
Assembly Syntax: Rdd32=vrmpywoh(Rss32,Rtt32):<<1
C Intrinsic Prototype: Word64 Q6_P_vrmpywoh_PP_s1(Word64 Rss, Word64 Rtt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vrmpywoh_PP_s1 __builtin_HEXAGON_M4_vrmpyoh_s1
/* ==========================================================================
Assembly Syntax: Rx32^=and(Rs32,Rt32)
C Intrinsic Prototype: Word32 Q6_R_andxacc_RR(Word32 Rx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_andxacc_RR(Word32 Rx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_andxacc_RR(Word32 Rx, Word32 Rs, Word32
+   Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_andxacc_RR…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_andxacc_RR __builtin_HEXAGON_M4_xor_and
/* ==========================================================================
Assembly Syntax: Rx32^=and(Rs32,~Rt32)
C Intrinsic Prototype: Word32 Q6_R_andxacc_RnR(Word32 Rx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_andxacc_RnR(Word32 Rx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_andxacc_RnR(Word32 Rx, Word32 Rs, Word32
+   Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_andxacc_RnR…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_andxacc_RnR __builtin_HEXAGON_M4_xor_andn
/* ==========================================================================
Assembly Syntax: Rx32^=or(Rs32,Rt32)
C Intrinsic Prototype: Word32 Q6_R_orxacc_RR(Word32 Rx, Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_orxacc_RR __builtin_HEXAGON_M4_xor_or
/* ==========================================================================
Assembly Syntax: Rxx32^=xor(Rss32,Rtt32)
C Intrinsic Prototype: Word64 Q6_P_xorxacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_xorxacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
-   Instruction Type:      S_3op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_xorxacc_PP(Word64 Rxx, Word64 Rss, Word64
+   Rtt) Instruction Type:      S_3op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_xorxacc_PP…
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_xorxacc_PP __builtin_HEXAGON_M4_xor_xacc
/* ==========================================================================
Assembly Syntax: Rxx32+=vdmpybsu(Rss32,Rtt32):sat
C Intrinsic Prototype: Word64 Q6_P_vdmpybsuacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vdmpybsuacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vdmpybsuacc_PP_sat(Word64 Rxx, Word64 Rss,
+   Word64 Rtt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vdmpybsuacc_PP_sat __builtin_HEXAGON_M5_vdmacbsu
/* ==========================================================================
Assembly Syntax: Rdd32=vdmpybsu(Rss32,Rtt32):sat
C Intrinsic Prototype: Word64 Q6_P_vdmpybsu_PP_sat(Word64 Rss, Word64 Rtt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vdmpybsu_PP_sat __builtin_HEXAGON_M5_vdmpybsu
/* ==========================================================================
Assembly Syntax: Rxx32+=vmpybsu(Rs32,Rt32)
C Intrinsic Prototype: Word64 Q6_P_vmpybsuacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vmpybsuacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vmpybsuacc_RR(Word64 Rxx, Word32 Rs,
+   Word32 Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_vmpybsuacc_RR…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vmpybsuacc_RR __builtin_HEXAGON_M5_vmacbsu
/* ==========================================================================
Assembly Syntax: Rxx32+=vmpybu(Rs32,Rt32)
C Intrinsic Prototype: Word64 Q6_P_vmpybuacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vmpybuacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vmpybuacc_RR(Word64 Rxx, Word32 Rs, Word32
+   Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_vmpybuacc_RR…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vmpybuacc_RR __builtin_HEXAGON_M5_vmacbuu
/* ==========================================================================
Assembly Syntax: Rdd32=vmpybsu(Rs32,Rt32)
C Intrinsic Prototype: Word64 Q6_P_vmpybsu_RR(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vmpybsu_RR __builtin_HEXAGON_M5_vmpybsu
/* ==========================================================================
Assembly Syntax: Rdd32=vmpybu(Rs32,Rt32)
C Intrinsic Prototype: Word64 Q6_P_vmpybu_RR(Word32 Rs, Word32 Rt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vmpybu_RR __builtin_HEXAGON_M5_vmpybuu
/* ==========================================================================
Assembly Syntax: Rxx32+=vrmpybsu(Rss32,Rtt32)
C Intrinsic Prototype: Word64 Q6_P_vrmpybsuacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vrmpybsuacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vrmpybsuacc_PP(Word64 Rxx, Word64 Rss,
+   Word64 Rtt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vrmpybsuacc_PP __builtin_HEXAGON_M5_vrmacbsu
/* ==========================================================================
Assembly Syntax: Rxx32+=vrmpybu(Rss32,Rtt32)
C Intrinsic Prototype: Word64 Q6_P_vrmpybuacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vrmpybuacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vrmpybuacc_PP(Word64 Rxx, Word64 Rss,
+   Word64 Rtt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_vrmpybuacc_PP…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vrmpybuacc_PP __builtin_HEXAGON_M5_vrmacbuu
/* ==========================================================================
Assembly Syntax: Rdd32=vrmpybsu(Rss32,Rtt32)
C Intrinsic Prototype: Word64 Q6_P_vrmpybsu_PP(Word64 Rss, Word64 Rtt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vrmpybsu_PP __builtin_HEXAGON_M5_vrmpybsu
/* ==========================================================================
Assembly Syntax: Rdd32=vrmpybu(Rss32,Rtt32)
C Intrinsic Prototype: Word64 Q6_P_vrmpybu_PP(Word64 Rss, Word64 Rtt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vrmpybu_PP __builtin_HEXAGON_M5_vrmpybuu
/* ==========================================================================
Assembly Syntax: Rd32=addasl(Rt32,Rs32,#u3)
C Intrinsic Prototype: Word32 Q6_R_addasl_RRI(Word32 Rt, Word32 Rs, Word32 Iu3)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_addasl_RRI(Word32 Rt, Word32 Rs, Word32 Iu3)
-   Instruction Type:      S_3op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_addasl_RRI(Word32 Rt, Word32 Rs, Word32
+   Iu3) Instruction Type:      S_3op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_addasl_RRI…
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_addasl_RRI __builtin_HEXAGON_S2_addasl_rrri
/* ==========================================================================
Assembly Syntax: Rdd32=asl(Rss32,#u6)
C Intrinsic Prototype: Word64 Q6_P_asl_PI(Word64 Rss, Word32 Iu6)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_asl_PI __builtin_HEXAGON_S2_asl_i_p
/* ==========================================================================
Assembly Syntax: Rxx32+=asl(Rss32,#u6)
C Intrinsic Prototype: Word64 Q6_P_aslacc_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_aslacc_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
-   Instruction Type:      S_2op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_aslacc_PI(Word64 Rxx, Word64 Rss, Word32
+   Iu6) Instruction Type:      S_2op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_aslacc_PI…
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_aslacc_PI __builtin_HEXAGON_S2_asl_i_p_acc
/* ==========================================================================
Assembly Syntax: Rxx32&=asl(Rss32,#u6)
C Intrinsic Prototype: Word64 Q6_P_asland_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_asland_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
-   Instruction Type:      S_2op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_asland_PI(Word64 Rxx, Word64 Rss, Word32
+   Iu6) Instruction Type:      S_2op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_asland_PI…
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_asland_PI __builtin_HEXAGON_S2_asl_i_p_and
/* ==========================================================================
Assembly Syntax: Rxx32-=asl(Rss32,#u6)
C Intrinsic Prototype: Word64 Q6_P_aslnac_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_aslnac_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
-   Instruction Type:      S_2op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_aslnac_PI(Word64 Rxx, Word64 Rss, Word32
+   Iu6) Instruction Type:      S_2op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_aslnac_PI…
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_aslnac_PI __builtin_HEXAGON_S2_asl_i_p_nac
/* ==========================================================================
Assembly Syntax: Rxx32|=asl(Rss32,#u6)
C Intrinsic Prototype: Word64 Q6_P_aslor_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_aslor_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
-   Instruction Type:      S_2op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_aslor_PI(Word64 Rxx, Word64 Rss, Word32
+   Iu6) Instruction Type:      S_2op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_aslor_PI…
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_aslor_PI __builtin_HEXAGON_S2_asl_i_p_or
/* ==========================================================================
Assembly Syntax: Rxx32^=asl(Rss32,#u6)
C Intrinsic Prototype: Word64 Q6_P_aslxacc_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_aslxacc_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
-   Instruction Type:      S_2op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_aslxacc_PI(Word64 Rxx, Word64 Rss, Word32
+   Iu6) Instruction Type:      S_2op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_aslxacc_PI…
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_aslxacc_PI __builtin_HEXAGON_S2_asl_i_p_xacc
/* ==========================================================================
Assembly Syntax: Rd32=asl(Rs32,#u5)
C Intrinsic Prototype: Word32 Q6_R_asl_RI(Word32 Rs, Word32 Iu5)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_asl_RI __builtin_HEXAGON_S2_asl_i_r
/* ==========================================================================
Assembly Syntax: Rx32+=asl(Rs32,#u5)
C Intrinsic Prototype: Word32 Q6_R_aslacc_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_aslacc_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
-   Instruction Type:      S_2op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_aslacc_RI(Word32 Rx, Word32 Rs, Word32
+   Iu5) Instruction Type:      S_2op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_aslacc_RI…
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_aslacc_RI __builtin_HEXAGON_S2_asl_i_r_acc
/* ==========================================================================
Assembly Syntax: Rx32&=asl(Rs32,#u5)
C Intrinsic Prototype: Word32 Q6_R_asland_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_asland_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
-   Instruction Type:      S_2op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_asland_RI(Word32 Rx, Word32 Rs, Word32
+   Iu5) Instruction Type:      S_2op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_asland_RI…
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_asland_RI __builtin_HEXAGON_S2_asl_i_r_and
/* ==========================================================================
Assembly Syntax: Rx32-=asl(Rs32,#u5)
C Intrinsic Prototype: Word32 Q6_R_aslnac_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_aslnac_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
-   Instruction Type:      S_2op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_aslnac_RI(Word32 Rx, Word32 Rs, Word32
+   Iu5) Instruction Type:      S_2op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_aslnac_RI…
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_aslnac_RI __builtin_HEXAGON_S2_asl_i_r_nac
/* ==========================================================================
Assembly Syntax: Rx32|=asl(Rs32,#u5)
C Intrinsic Prototype: Word32 Q6_R_aslor_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_aslor_RI __builtin_HEXAGON_S2_asl_i_r_or
/* ==========================================================================
Assembly Syntax: Rd32=asl(Rs32,#u5):sat
C Intrinsic Prototype: Word32 Q6_R_asl_RI_sat(Word32 Rs, Word32 Iu5)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_asl_RI_sat __builtin_HEXAGON_S2_asl_i_r_sat
/* ==========================================================================
Assembly Syntax: Rx32^=asl(Rs32,#u5)
C Intrinsic Prototype: Word32 Q6_R_aslxacc_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_aslxacc_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
-   Instruction Type:      S_2op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_aslxacc_RI(Word32 Rx, Word32 Rs, Word32
+   Iu5) Instruction Type:      S_2op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_aslxacc_RI…
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_aslxacc_RI __builtin_HEXAGON_S2_asl_i_r_xacc
/* ==========================================================================
Assembly Syntax: Rdd32=vaslh(Rss32,#u4)
C Intrinsic Prototype: Word64 Q6_P_vaslh_PI(Word64 Rss, Word32 Iu4)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vaslh_PI __builtin_HEXAGON_S2_asl_i_vh
/* ==========================================================================
Assembly Syntax: Rdd32=vaslw(Rss32,#u5)
C Intrinsic Prototype: Word64 Q6_P_vaslw_PI(Word64 Rss, Word32 Iu5)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vaslw_PI __builtin_HEXAGON_S2_asl_i_vw
/* ==========================================================================
Assembly Syntax: Rdd32=asl(Rss32,Rt32)
C Intrinsic Prototype: Word64 Q6_P_asl_PR(Word64 Rss, Word32 Rt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_asl_PR __builtin_HEXAGON_S2_asl_r_p
/* ==========================================================================
Assembly Syntax: Rxx32+=asl(Rss32,Rt32)
C Intrinsic Prototype: Word64 Q6_P_aslacc_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_aslacc_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
-   Instruction Type:      S_3op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_aslacc_PR(Word64 Rxx, Word64 Rss, Word32
+   Rt) Instruction Type:      S_3op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_aslacc_PR…
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_aslacc_PR __builtin_HEXAGON_S2_asl_r_p_acc
/* ==========================================================================
Assembly Syntax: Rxx32&=asl(Rss32,Rt32)
C Intrinsic Prototype: Word64 Q6_P_asland_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_asland_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
-   Instruction Type:      S_3op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_asland_PR(Word64 Rxx, Word64 Rss, Word32
+   Rt) Instruction Type:      S_3op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_asland_PR…
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_asland_PR __builtin_HEXAGON_S2_asl_r_p_and
/* ==========================================================================
Assembly Syntax: Rxx32-=asl(Rss32,Rt32)
C Intrinsic Prototype: Word64 Q6_P_aslnac_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_aslnac_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
-   Instruction Type:      S_3op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_aslnac_PR(Word64 Rxx, Word64 Rss, Word32
+   Rt) Instruction Type:      S_3op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_aslnac_PR…
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_aslnac_PR __builtin_HEXAGON_S2_asl_r_p_nac
/* ==========================================================================
Assembly Syntax: Rxx32|=asl(Rss32,Rt32)
C Intrinsic Prototype: Word64 Q6_P_aslor_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_aslor_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
-   Instruction Type:      S_3op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_aslor_PR(Word64 Rxx, Word64 Rss, Word32
+   Rt) Instruction Type:      S_3op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_aslor_PR…
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_aslor_PR __builtin_HEXAGON_S2_asl_r_p_or
/* ==========================================================================
Assembly Syntax: Rxx32^=asl(Rss32,Rt32)
C Intrinsic Prototype: Word64 Q6_P_aslxacc_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_aslxacc_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
-   Instruction Type:      S_3op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_aslxacc_PR(Word64 Rxx, Word64 Rss, Word32
+   Rt) Instruction Type:      S_3op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_aslxacc_PR…
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_aslxacc_PR __builtin_HEXAGON_S2_asl_r_p_xor
/* ==========================================================================
Assembly Syntax: Rd32=asl(Rs32,Rt32)
C Intrinsic Prototype: Word32 Q6_R_asl_RR(Word32 Rs, Word32 Rt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_asl_RR __builtin_HEXAGON_S2_asl_r_r
/* ==========================================================================
Assembly Syntax: Rx32+=asl(Rs32,Rt32)
C Intrinsic Prototype: Word32 Q6_R_aslacc_RR(Word32 Rx, Word32 Rs, Word32 Rt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_aslacc_RR __builtin_HEXAGON_S2_asl_r_r_acc
/* ==========================================================================
Assembly Syntax: Rx32&=asl(Rs32,Rt32)
C Intrinsic Prototype: Word32 Q6_R_asland_RR(Word32 Rx, Word32 Rs, Word32 Rt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_asland_RR __builtin_HEXAGON_S2_asl_r_r_and
/* ==========================================================================
Assembly Syntax: Rx32-=asl(Rs32,Rt32)
C Intrinsic Prototype: Word32 Q6_R_aslnac_RR(Word32 Rx, Word32 Rs, Word32 Rt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_aslnac_RR __builtin_HEXAGON_S2_asl_r_r_nac
/* ==========================================================================
Assembly Syntax: Rx32|=asl(Rs32,Rt32)
C Intrinsic Prototype: Word32 Q6_R_aslor_RR(Word32 Rx, Word32 Rs, Word32 Rt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_aslor_RR __builtin_HEXAGON_S2_asl_r_r_or
/* ==========================================================================
Assembly Syntax: Rd32=asl(Rs32,Rt32):sat
C Intrinsic Prototype: Word32 Q6_R_asl_RR_sat(Word32 Rs, Word32 Rt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_asl_RR_sat __builtin_HEXAGON_S2_asl_r_r_sat
/* ==========================================================================
Assembly Syntax: Rdd32=vaslh(Rss32,Rt32)
C Intrinsic Prototype: Word64 Q6_P_vaslh_PR(Word64 Rss, Word32 Rt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vaslh_PR __builtin_HEXAGON_S2_asl_r_vh
/* ==========================================================================
Assembly Syntax: Rdd32=vaslw(Rss32,Rt32)
C Intrinsic Prototype: Word64 Q6_P_vaslw_PR(Word64 Rss, Word32 Rt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vaslw_PR __builtin_HEXAGON_S2_asl_r_vw
/* ==========================================================================
Assembly Syntax: Rdd32=asr(Rss32,#u6)
C Intrinsic Prototype: Word64 Q6_P_asr_PI(Word64 Rss, Word32 Iu6)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_asr_PI __builtin_HEXAGON_S2_asr_i_p
/* ==========================================================================
Assembly Syntax: Rxx32+=asr(Rss32,#u6)
C Intrinsic Prototype: Word64 Q6_P_asracc_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_asracc_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
-   Instruction Type:      S_2op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_asracc_PI(Word64 Rxx, Word64 Rss, Word32
+   Iu6) Instruction Type:      S_2op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_asracc_PI…
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_asracc_PI __builtin_HEXAGON_S2_asr_i_p_acc
/* ==========================================================================
Assembly Syntax: Rxx32&=asr(Rss32,#u6)
C Intrinsic Prototype: Word64 Q6_P_asrand_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_asrand_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
-   Instruction Type:      S_2op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_asrand_PI(Word64 Rxx, Word64 Rss, Word32
+   Iu6) Instruction Type:      S_2op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_asrand_PI…
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_asrand_PI __builtin_HEXAGON_S2_asr_i_p_and
/* ==========================================================================
Assembly Syntax: Rxx32-=asr(Rss32,#u6)
C Intrinsic Prototype: Word64 Q6_P_asrnac_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_asrnac_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
-   Instruction Type:      S_2op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_asrnac_PI(Word64 Rxx, Word64 Rss, Word32
+   Iu6) Instruction Type:      S_2op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_asrnac_PI…
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_asrnac_PI __builtin_HEXAGON_S2_asr_i_p_nac
/* ==========================================================================
Assembly Syntax: Rxx32|=asr(Rss32,#u6)
C Intrinsic Prototype: Word64 Q6_P_asror_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_asror_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
-   Instruction Type:      S_2op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_asror_PI(Word64 Rxx, Word64 Rss, Word32
+   Iu6) Instruction Type:      S_2op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_asror_PI…
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_asror_PI __builtin_HEXAGON_S2_asr_i_p_or
/* ==========================================================================
Assembly Syntax: Rdd32=asr(Rss32,#u6):rnd
C Intrinsic Prototype: Word64 Q6_P_asr_PI_rnd(Word64 Rss, Word32 Iu6)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_asr_PI_rnd __builtin_HEXAGON_S2_asr_i_p_rnd
/* ==========================================================================
Assembly Syntax: Rdd32=asrrnd(Rss32,#u6)
C Intrinsic Prototype: Word64 Q6_P_asrrnd_PI(Word64 Rss, Word32 Iu6)
Instruction Type: S_2op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_P_asrrnd_PI __builtin_HEXAGON_S2_asr_i_p_rnd_goodsyntax
/* ==========================================================================
Assembly Syntax: Rd32=asr(Rs32,#u5)
C Intrinsic Prototype: Word32 Q6_R_asr_RI(Word32 Rs, Word32 Iu5)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_asr_RI __builtin_HEXAGON_S2_asr_i_r
/* ==========================================================================
Assembly Syntax: Rx32+=asr(Rs32,#u5)
C Intrinsic Prototype: Word32 Q6_R_asracc_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_asracc_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
-   Instruction Type:      S_2op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_asracc_RI(Word32 Rx, Word32 Rs, Word32
+   Iu5) Instruction Type:      S_2op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_asracc_RI…
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_asracc_RI __builtin_HEXAGON_S2_asr_i_r_acc
/* ==========================================================================
Assembly Syntax: Rx32&=asr(Rs32,#u5)
C Intrinsic Prototype: Word32 Q6_R_asrand_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_asrand_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
-   Instruction Type:      S_2op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_asrand_RI(Word32 Rx, Word32 Rs, Word32
+   Iu5) Instruction Type:      S_2op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_asrand_RI…
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_asrand_RI __builtin_HEXAGON_S2_asr_i_r_and
/* ==========================================================================
Assembly Syntax: Rx32-=asr(Rs32,#u5)
C Intrinsic Prototype: Word32 Q6_R_asrnac_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_asrnac_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
-   Instruction Type:      S_2op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_asrnac_RI(Word32 Rx, Word32 Rs, Word32
+   Iu5) Instruction Type:      S_2op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_asrnac_RI…
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_asrnac_RI __builtin_HEXAGON_S2_asr_i_r_nac
/* ==========================================================================
Assembly Syntax: Rx32|=asr(Rs32,#u5)
C Intrinsic Prototype: Word32 Q6_R_asror_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_asror_RI __builtin_HEXAGON_S2_asr_i_r_or
/* ==========================================================================
Assembly Syntax: Rd32=asr(Rs32,#u5):rnd
C Intrinsic Prototype: Word32 Q6_R_asr_RI_rnd(Word32 Rs, Word32 Iu5)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_asr_RI_rnd __builtin_HEXAGON_S2_asr_i_r_rnd
/* ==========================================================================
Assembly Syntax: Rd32=asrrnd(Rs32,#u5)
C Intrinsic Prototype: Word32 Q6_R_asrrnd_RI(Word32 Rs, Word32 Iu5)
Instruction Type: S_2op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_R_asrrnd_RI __builtin_HEXAGON_S2_asr_i_r_rnd_goodsyntax
/* ==========================================================================
Assembly Syntax: Rd32=vasrw(Rss32,#u5)
C Intrinsic Prototype: Word32 Q6_R_vasrw_PI(Word64 Rss, Word32 Iu5)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_vasrw_PI __builtin_HEXAGON_S2_asr_i_svw_trun
/* ==========================================================================
Assembly Syntax: Rdd32=vasrh(Rss32,#u4)
C Intrinsic Prototype: Word64 Q6_P_vasrh_PI(Word64 Rss, Word32 Iu4)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vasrh_PI __builtin_HEXAGON_S2_asr_i_vh
/* ==========================================================================
Assembly Syntax: Rdd32=vasrw(Rss32,#u5)
C Intrinsic Prototype: Word64 Q6_P_vasrw_PI(Word64 Rss, Word32 Iu5)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vasrw_PI __builtin_HEXAGON_S2_asr_i_vw
/* ==========================================================================
Assembly Syntax: Rdd32=asr(Rss32,Rt32)
C Intrinsic Prototype: Word64 Q6_P_asr_PR(Word64 Rss, Word32 Rt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_asr_PR __builtin_HEXAGON_S2_asr_r_p
/* ==========================================================================
Assembly Syntax: Rxx32+=asr(Rss32,Rt32)
C Intrinsic Prototype: Word64 Q6_P_asracc_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_asracc_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
-   Instruction Type:      S_3op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_asracc_PR(Word64 Rxx, Word64 Rss, Word32
+   Rt) Instruction Type:      S_3op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_asracc_PR…
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_asracc_PR __builtin_HEXAGON_S2_asr_r_p_acc
/* ==========================================================================
Assembly Syntax: Rxx32&=asr(Rss32,Rt32)
C Intrinsic Prototype: Word64 Q6_P_asrand_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_asrand_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
-   Instruction Type:      S_3op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_asrand_PR(Word64 Rxx, Word64 Rss, Word32
+   Rt) Instruction Type:      S_3op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_asrand_PR…
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_asrand_PR __builtin_HEXAGON_S2_asr_r_p_and
/* ==========================================================================
Assembly Syntax: Rxx32-=asr(Rss32,Rt32)
C Intrinsic Prototype: Word64 Q6_P_asrnac_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_asrnac_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
-   Instruction Type:      S_3op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_asrnac_PR(Word64 Rxx, Word64 Rss, Word32
+   Rt) Instruction Type:      S_3op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_asrnac_PR…
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_asrnac_PR __builtin_HEXAGON_S2_asr_r_p_nac
/* ==========================================================================
Assembly Syntax: Rxx32|=asr(Rss32,Rt32)
C Intrinsic Prototype: Word64 Q6_P_asror_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_asror_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
-   Instruction Type:      S_3op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_asror_PR(Word64 Rxx, Word64 Rss, Word32
+   Rt) Instruction Type:      S_3op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_asror_PR…
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_asror_PR __builtin_HEXAGON_S2_asr_r_p_or
/* ==========================================================================
Assembly Syntax: Rxx32^=asr(Rss32,Rt32)
C Intrinsic Prototype: Word64 Q6_P_asrxacc_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_asrxacc_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
-   Instruction Type:      S_3op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_asrxacc_PR(Word64 Rxx, Word64 Rss, Word32
+   Rt) Instruction Type:      S_3op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_asrxacc_PR…
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_asrxacc_PR __builtin_HEXAGON_S2_asr_r_p_xor
/* ==========================================================================
Assembly Syntax: Rd32=asr(Rs32,Rt32)
C Intrinsic Prototype: Word32 Q6_R_asr_RR(Word32 Rs, Word32 Rt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_asr_RR __builtin_HEXAGON_S2_asr_r_r
/* ==========================================================================
Assembly Syntax: Rx32+=asr(Rs32,Rt32)
C Intrinsic Prototype: Word32 Q6_R_asracc_RR(Word32 Rx, Word32 Rs, Word32 Rt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_asracc_RR __builtin_HEXAGON_S2_asr_r_r_acc
/* ==========================================================================
Assembly Syntax: Rx32&=asr(Rs32,Rt32)
C Intrinsic Prototype: Word32 Q6_R_asrand_RR(Word32 Rx, Word32 Rs, Word32 Rt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_asrand_RR __builtin_HEXAGON_S2_asr_r_r_and
/* ==========================================================================
Assembly Syntax: Rx32-=asr(Rs32,Rt32)
C Intrinsic Prototype: Word32 Q6_R_asrnac_RR(Word32 Rx, Word32 Rs, Word32 Rt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_asrnac_RR __builtin_HEXAGON_S2_asr_r_r_nac
/* ==========================================================================
Assembly Syntax: Rx32|=asr(Rs32,Rt32)
C Intrinsic Prototype: Word32 Q6_R_asror_RR(Word32 Rx, Word32 Rs, Word32 Rt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_asror_RR __builtin_HEXAGON_S2_asr_r_r_or
/* ==========================================================================
Assembly Syntax: Rd32=asr(Rs32,Rt32):sat
C Intrinsic Prototype: Word32 Q6_R_asr_RR_sat(Word32 Rs, Word32 Rt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_asr_RR_sat __builtin_HEXAGON_S2_asr_r_r_sat
/* ==========================================================================
Assembly Syntax: Rd32=vasrw(Rss32,Rt32)
C Intrinsic Prototype: Word32 Q6_R_vasrw_PR(Word64 Rss, Word32 Rt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_vasrw_PR __builtin_HEXAGON_S2_asr_r_svw_trun
/* ==========================================================================
Assembly Syntax: Rdd32=vasrh(Rss32,Rt32)
C Intrinsic Prototype: Word64 Q6_P_vasrh_PR(Word64 Rss, Word32 Rt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vasrh_PR __builtin_HEXAGON_S2_asr_r_vh
/* ==========================================================================
Assembly Syntax: Rdd32=vasrw(Rss32,Rt32)
C Intrinsic Prototype: Word64 Q6_P_vasrw_PR(Word64 Rss, Word32 Rt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vasrw_PR __builtin_HEXAGON_S2_asr_r_vw
/* ==========================================================================
Assembly Syntax: Rd32=brev(Rs32)
C Intrinsic Prototype: Word32 Q6_R_brev_R(Word32 Rs)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_brev_R __builtin_HEXAGON_S2_brev
/* ==========================================================================
Assembly Syntax: Rdd32=brev(Rss32)
C Intrinsic Prototype: Word64 Q6_P_brev_P(Word64 Rss)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_brev_P __builtin_HEXAGON_S2_brevp
/* ==========================================================================
Assembly Syntax: Rd32=cl0(Rs32)
C Intrinsic Prototype: Word32 Q6_R_cl0_R(Word32 Rs)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_cl0_R __builtin_HEXAGON_S2_cl0
/* ==========================================================================
Assembly Syntax: Rd32=cl0(Rss32)
C Intrinsic Prototype: Word32 Q6_R_cl0_P(Word64 Rss)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_cl0_P __builtin_HEXAGON_S2_cl0p
/* ==========================================================================
Assembly Syntax: Rd32=cl1(Rs32)
C Intrinsic Prototype: Word32 Q6_R_cl1_R(Word32 Rs)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_cl1_R __builtin_HEXAGON_S2_cl1
/* ==========================================================================
Assembly Syntax: Rd32=cl1(Rss32)
C Intrinsic Prototype: Word32 Q6_R_cl1_P(Word64 Rss)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_cl1_P __builtin_HEXAGON_S2_cl1p
/* ==========================================================================
Assembly Syntax: Rd32=clb(Rs32)
C Intrinsic Prototype: Word32 Q6_R_clb_R(Word32 Rs)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_clb_R __builtin_HEXAGON_S2_clb
/* ==========================================================================
Assembly Syntax: Rd32=normamt(Rs32)
C Intrinsic Prototype: Word32 Q6_R_normamt_R(Word32 Rs)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_normamt_R __builtin_HEXAGON_S2_clbnorm
/* ==========================================================================
Assembly Syntax: Rd32=clb(Rss32)
C Intrinsic Prototype: Word32 Q6_R_clb_P(Word64 Rss)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_clb_P __builtin_HEXAGON_S2_clbp
/* ==========================================================================
Assembly Syntax: Rd32=clrbit(Rs32,#u5)
C Intrinsic Prototype: Word32 Q6_R_clrbit_RI(Word32 Rs, Word32 Iu5)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_clrbit_RI __builtin_HEXAGON_S2_clrbit_i
/* ==========================================================================
Assembly Syntax: Rd32=clrbit(Rs32,Rt32)
C Intrinsic Prototype: Word32 Q6_R_clrbit_RR(Word32 Rs, Word32 Rt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_clrbit_RR __builtin_HEXAGON_S2_clrbit_r
/* ==========================================================================
Assembly Syntax: Rd32=ct0(Rs32)
C Intrinsic Prototype: Word32 Q6_R_ct0_R(Word32 Rs)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_ct0_R __builtin_HEXAGON_S2_ct0
/* ==========================================================================
Assembly Syntax: Rd32=ct0(Rss32)
C Intrinsic Prototype: Word32 Q6_R_ct0_P(Word64 Rss)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_ct0_P __builtin_HEXAGON_S2_ct0p
/* ==========================================================================
Assembly Syntax: Rd32=ct1(Rs32)
C Intrinsic Prototype: Word32 Q6_R_ct1_R(Word32 Rs)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_ct1_R __builtin_HEXAGON_S2_ct1
/* ==========================================================================
Assembly Syntax: Rd32=ct1(Rss32)
C Intrinsic Prototype: Word32 Q6_R_ct1_P(Word64 Rss)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_ct1_P __builtin_HEXAGON_S2_ct1p
/* ==========================================================================
Assembly Syntax: Rdd32=deinterleave(Rss32)
C Intrinsic Prototype: Word64 Q6_P_deinterleave_P(Word64 Rss)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_deinterleave_P __builtin_HEXAGON_S2_deinterleave
/* ==========================================================================
Assembly Syntax: Rd32=extractu(Rs32,#u5,#U5)
C Intrinsic Prototype: Word32 Q6_R_extractu_RII(Word32 Rs, Word32 Iu5, Word32 IU5)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_extractu_RII(Word32 Rs, Word32 Iu5, Word32 IU5)
-   Instruction Type:      S_2op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_extractu_RII(Word32 Rs, Word32 Iu5, Word32
+   IU5) Instruction Type:      S_2op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_extractu_RII…
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_extractu_RII __builtin_HEXAGON_S2_extractu
/* ==========================================================================
Assembly Syntax: Rd32=extractu(Rs32,Rtt32)
C Intrinsic Prototype: Word32 Q6_R_extractu_RP(Word32 Rs, Word64 Rtt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_extractu_RP __builtin_HEXAGON_S2_extractu_rp
/* ==========================================================================
Assembly Syntax: Rdd32=extractu(Rss32,#u6,#U6)
C Intrinsic Prototype: Word64 Q6_P_extractu_PII(Word64 Rss, Word32 Iu6, Word32 IU6)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_extractu_PII(Word64 Rss, Word32 Iu6, Word32 IU6)
-   Instruction Type:      S_2op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_extractu_PII(Word64 Rss, Word32 Iu6,
+   Word32 IU6) Instruction Type:      S_2op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_extractu_PII…
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_extractu_PII __builtin_HEXAGON_S2_extractup
/* ==========================================================================
Assembly Syntax: Rdd32=extractu(Rss32,Rtt32)
C Intrinsic Prototype: Word64 Q6_P_extractu_PP(Word64 Rss, Word64 Rtt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_extractu_PP __builtin_HEXAGON_S2_extractup_rp
/* ==========================================================================
Assembly Syntax: Rx32=insert(Rs32,#u5,#U5)
C Intrinsic Prototype: Word32 Q6_R_insert_RII(Word32 Rx, Word32 Rs, Word32 Iu5, Word32 IU5)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_insert_RII(Word32 Rx, Word32 Rs, Word32 Iu5, Word32 IU5)
-   Instruction Type:      S_2op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_insert_RII(Word32 Rx, Word32 Rs, Word32
+   Iu5, Word32 IU5) Instruction Type:      S_2op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_insert_RII…
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_insert_RII __builtin_HEXAGON_S2_insert
/* ==========================================================================
Assembly Syntax: Rx32=insert(Rs32,Rtt32)
C Intrinsic Prototype: Word32 Q6_R_insert_RP(Word32 Rx, Word32 Rs, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_insert_RP(Word32 Rx, Word32 Rs, Word64 Rtt)
-   Instruction Type:      S_3op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_insert_RP(Word32 Rx, Word32 Rs, Word64
+   Rtt) Instruction Type:      S_3op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_insert_RP…
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_insert_RP __builtin_HEXAGON_S2_insert_rp
/* ==========================================================================
Assembly Syntax: Rxx32=insert(Rss32,#u6,#U6)
C Intrinsic Prototype: Word64 Q6_P_insert_PII(Word64 Rxx, Word64 Rss, Word32 Iu6, Word32 IU6)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_insert_PII(Word64 Rxx, Word64 Rss, Word32 Iu6, Word32 IU6)
-   Instruction Type:      S_2op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_insert_PII(Word64 Rxx, Word64 Rss, Word32
+   Iu6, Word32 IU6) Instruction Type:      S_2op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_insert_PII…
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_insert_PII __builtin_HEXAGON_S2_insertp
/* ==========================================================================
Assembly Syntax: Rxx32=insert(Rss32,Rtt32)
C Intrinsic Prototype: Word64 Q6_P_insert_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_insert_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
-   Instruction Type:      S_3op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_insert_PP(Word64 Rxx, Word64 Rss, Word64
+   Rtt) Instruction Type:      S_3op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_insert_PP…
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_insert_PP __builtin_HEXAGON_S2_insertp_rp
/* ==========================================================================
Assembly Syntax: Rdd32=interleave(Rss32)
C Intrinsic Prototype: Word64 Q6_P_interleave_P(Word64 Rss)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_interleave_P __builtin_HEXAGON_S2_interleave
/* ==========================================================================
Assembly Syntax: Rdd32=lfs(Rss32,Rtt32)
C Intrinsic Prototype: Word64 Q6_P_lfs_PP(Word64 Rss, Word64 Rtt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_lfs_PP __builtin_HEXAGON_S2_lfsp
/* ==========================================================================
Assembly Syntax: Rdd32=lsl(Rss32,Rt32)
C Intrinsic Prototype: Word64 Q6_P_lsl_PR(Word64 Rss, Word32 Rt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_lsl_PR __builtin_HEXAGON_S2_lsl_r_p
/* ==========================================================================
Assembly Syntax: Rxx32+=lsl(Rss32,Rt32)
C Intrinsic Prototype: Word64 Q6_P_lslacc_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_lslacc_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
-   Instruction Type:      S_3op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_lslacc_PR(Word64 Rxx, Word64 Rss, Word32
+   Rt) Instruction Type:      S_3op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_lslacc_PR…
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_lslacc_PR __builtin_HEXAGON_S2_lsl_r_p_acc
/* ==========================================================================
Assembly Syntax: Rxx32&=lsl(Rss32,Rt32)
C Intrinsic Prototype: Word64 Q6_P_lsland_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_lsland_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
-   Instruction Type:      S_3op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_lsland_PR(Word64 Rxx, Word64 Rss, Word32
+   Rt) Instruction Type:      S_3op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_lsland_PR…
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_lsland_PR __builtin_HEXAGON_S2_lsl_r_p_and
/* ==========================================================================
Assembly Syntax: Rxx32-=lsl(Rss32,Rt32)
C Intrinsic Prototype: Word64 Q6_P_lslnac_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_lslnac_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
-   Instruction Type:      S_3op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_lslnac_PR(Word64 Rxx, Word64 Rss, Word32
+   Rt) Instruction Type:      S_3op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_lslnac_PR…
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_lslnac_PR __builtin_HEXAGON_S2_lsl_r_p_nac
/* ==========================================================================
Assembly Syntax: Rxx32|=lsl(Rss32,Rt32)
C Intrinsic Prototype: Word64 Q6_P_lslor_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_lslor_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
-   Instruction Type:      S_3op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_lslor_PR(Word64 Rxx, Word64 Rss, Word32
+   Rt) Instruction Type:      S_3op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_lslor_PR…
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_lslor_PR __builtin_HEXAGON_S2_lsl_r_p_or
/* ==========================================================================
Assembly Syntax: Rxx32^=lsl(Rss32,Rt32)
C Intrinsic Prototype: Word64 Q6_P_lslxacc_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_lslxacc_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
-   Instruction Type:      S_3op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_lslxacc_PR(Word64 Rxx, Word64 Rss, Word32
+   Rt) Instruction Type:      S_3op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_lslxacc_PR…
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_lslxacc_PR __builtin_HEXAGON_S2_lsl_r_p_xor
/* ==========================================================================
Assembly Syntax: Rd32=lsl(Rs32,Rt32)
C Intrinsic Prototype: Word32 Q6_R_lsl_RR(Word32 Rs, Word32 Rt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_lsl_RR __builtin_HEXAGON_S2_lsl_r_r
/* ==========================================================================
Assembly Syntax: Rx32+=lsl(Rs32,Rt32)
C Intrinsic Prototype: Word32 Q6_R_lslacc_RR(Word32 Rx, Word32 Rs, Word32 Rt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_lslacc_RR __builtin_HEXAGON_S2_lsl_r_r_acc
/* ==========================================================================
Assembly Syntax: Rx32&=lsl(Rs32,Rt32)
C Intrinsic Prototype: Word32 Q6_R_lsland_RR(Word32 Rx, Word32 Rs, Word32 Rt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_lsland_RR __builtin_HEXAGON_S2_lsl_r_r_and
/* ==========================================================================
Assembly Syntax: Rx32-=lsl(Rs32,Rt32)
C Intrinsic Prototype: Word32 Q6_R_lslnac_RR(Word32 Rx, Word32 Rs, Word32 Rt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_lslnac_RR __builtin_HEXAGON_S2_lsl_r_r_nac
/* ==========================================================================
Assembly Syntax: Rx32|=lsl(Rs32,Rt32)
C Intrinsic Prototype: Word32 Q6_R_lslor_RR(Word32 Rx, Word32 Rs, Word32 Rt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_lslor_RR __builtin_HEXAGON_S2_lsl_r_r_or
/* ==========================================================================
Assembly Syntax: Rdd32=vlslh(Rss32,Rt32)
C Intrinsic Prototype: Word64 Q6_P_vlslh_PR(Word64 Rss, Word32 Rt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vlslh_PR __builtin_HEXAGON_S2_lsl_r_vh
/* ==========================================================================
Assembly Syntax: Rdd32=vlslw(Rss32,Rt32)
C Intrinsic Prototype: Word64 Q6_P_vlslw_PR(Word64 Rss, Word32 Rt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vlslw_PR __builtin_HEXAGON_S2_lsl_r_vw
/* ==========================================================================
Assembly Syntax: Rdd32=lsr(Rss32,#u6)
C Intrinsic Prototype: Word64 Q6_P_lsr_PI(Word64 Rss, Word32 Iu6)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_lsr_PI __builtin_HEXAGON_S2_lsr_i_p
/* ==========================================================================
Assembly Syntax: Rxx32+=lsr(Rss32,#u6)
C Intrinsic Prototype: Word64 Q6_P_lsracc_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_lsracc_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
-   Instruction Type:      S_2op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_lsracc_PI(Word64 Rxx, Word64 Rss, Word32
+   Iu6) Instruction Type:      S_2op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_lsracc_PI…
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_lsracc_PI __builtin_HEXAGON_S2_lsr_i_p_acc
/* ==========================================================================
Assembly Syntax: Rxx32&=lsr(Rss32,#u6)
C Intrinsic Prototype: Word64 Q6_P_lsrand_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_lsrand_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
-   Instruction Type:      S_2op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_lsrand_PI(Word64 Rxx, Word64 Rss, Word32
+   Iu6) Instruction Type:      S_2op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_lsrand_PI…
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_lsrand_PI __builtin_HEXAGON_S2_lsr_i_p_and
/* ==========================================================================
Assembly Syntax: Rxx32-=lsr(Rss32,#u6)
C Intrinsic Prototype: Word64 Q6_P_lsrnac_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_lsrnac_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
-   Instruction Type:      S_2op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_lsrnac_PI(Word64 Rxx, Word64 Rss, Word32
+   Iu6) Instruction Type:      S_2op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_lsrnac_PI…
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_lsrnac_PI __builtin_HEXAGON_S2_lsr_i_p_nac
/* ==========================================================================
Assembly Syntax: Rxx32|=lsr(Rss32,#u6)
C Intrinsic Prototype: Word64 Q6_P_lsror_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_lsror_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
-   Instruction Type:      S_2op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_lsror_PI(Word64 Rxx, Word64 Rss, Word32
+   Iu6) Instruction Type:      S_2op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_lsror_PI…
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_lsror_PI __builtin_HEXAGON_S2_lsr_i_p_or
/* ==========================================================================
Assembly Syntax: Rxx32^=lsr(Rss32,#u6)
C Intrinsic Prototype: Word64 Q6_P_lsrxacc_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_lsrxacc_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
-   Instruction Type:      S_2op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_lsrxacc_PI(Word64 Rxx, Word64 Rss, Word32
+   Iu6) Instruction Type:      S_2op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_lsrxacc_PI…
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_lsrxacc_PI __builtin_HEXAGON_S2_lsr_i_p_xacc
/* ==========================================================================
Assembly Syntax: Rd32=lsr(Rs32,#u5)
C Intrinsic Prototype: Word32 Q6_R_lsr_RI(Word32 Rs, Word32 Iu5)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_lsr_RI __builtin_HEXAGON_S2_lsr_i_r
/* ==========================================================================
Assembly Syntax: Rx32+=lsr(Rs32,#u5)
C Intrinsic Prototype: Word32 Q6_R_lsracc_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_lsracc_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
-   Instruction Type:      S_2op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_lsracc_RI(Word32 Rx, Word32 Rs, Word32
+   Iu5) Instruction Type:      S_2op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_lsracc_RI…
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_lsracc_RI __builtin_HEXAGON_S2_lsr_i_r_acc
/* ==========================================================================
Assembly Syntax: Rx32&=lsr(Rs32,#u5)
C Intrinsic Prototype: Word32 Q6_R_lsrand_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_lsrand_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
-   Instruction Type:      S_2op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_lsrand_RI(Word32 Rx, Word32 Rs, Word32
+   Iu5) Instruction Type:      S_2op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_lsrand_RI…
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_lsrand_RI __builtin_HEXAGON_S2_lsr_i_r_and
/* ==========================================================================
Assembly Syntax: Rx32-=lsr(Rs32,#u5)
C Intrinsic Prototype: Word32 Q6_R_lsrnac_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_lsrnac_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
-   Instruction Type:      S_2op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_lsrnac_RI(Word32 Rx, Word32 Rs, Word32
+   Iu5) Instruction Type:      S_2op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_lsrnac_RI…
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_lsrnac_RI __builtin_HEXAGON_S2_lsr_i_r_nac
/* ==========================================================================
Assembly Syntax: Rx32|=lsr(Rs32,#u5)
C Intrinsic Prototype: Word32 Q6_R_lsror_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_lsror_RI __builtin_HEXAGON_S2_lsr_i_r_or
/* ==========================================================================
Assembly Syntax: Rx32^=lsr(Rs32,#u5)
C Intrinsic Prototype: Word32 Q6_R_lsrxacc_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_lsrxacc_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
-   Instruction Type:      S_2op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_lsrxacc_RI(Word32 Rx, Word32 Rs, Word32
+   Iu5) Instruction Type:      S_2op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_lsrxacc_RI…
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_lsrxacc_RI __builtin_HEXAGON_S2_lsr_i_r_xacc
/* ==========================================================================
Assembly Syntax: Rdd32=vlsrh(Rss32,#u4)
C Intrinsic Prototype: Word64 Q6_P_vlsrh_PI(Word64 Rss, Word32 Iu4)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vlsrh_PI __builtin_HEXAGON_S2_lsr_i_vh
/* ==========================================================================
Assembly Syntax: Rdd32=vlsrw(Rss32,#u5)
C Intrinsic Prototype: Word64 Q6_P_vlsrw_PI(Word64 Rss, Word32 Iu5)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vlsrw_PI __builtin_HEXAGON_S2_lsr_i_vw
/* ==========================================================================
Assembly Syntax: Rdd32=lsr(Rss32,Rt32)
C Intrinsic Prototype: Word64 Q6_P_lsr_PR(Word64 Rss, Word32 Rt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_lsr_PR __builtin_HEXAGON_S2_lsr_r_p
/* ==========================================================================
Assembly Syntax: Rxx32+=lsr(Rss32,Rt32)
C Intrinsic Prototype: Word64 Q6_P_lsracc_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_lsracc_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
-   Instruction Type:      S_3op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_lsracc_PR(Word64 Rxx, Word64 Rss, Word32
+   Rt) Instruction Type:      S_3op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_lsracc_PR…
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_lsracc_PR __builtin_HEXAGON_S2_lsr_r_p_acc
/* ==========================================================================
Assembly Syntax: Rxx32&=lsr(Rss32,Rt32)
C Intrinsic Prototype: Word64 Q6_P_lsrand_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_lsrand_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
-   Instruction Type:      S_3op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_lsrand_PR(Word64 Rxx, Word64 Rss, Word32
+   Rt) Instruction Type:      S_3op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_lsrand_PR…
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_lsrand_PR __builtin_HEXAGON_S2_lsr_r_p_and
/* ==========================================================================
Assembly Syntax: Rxx32-=lsr(Rss32,Rt32)
C Intrinsic Prototype: Word64 Q6_P_lsrnac_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_lsrnac_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
-   Instruction Type:      S_3op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_lsrnac_PR(Word64 Rxx, Word64 Rss, Word32
+   Rt) Instruction Type:      S_3op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_lsrnac_PR…
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_lsrnac_PR __builtin_HEXAGON_S2_lsr_r_p_nac
/* ==========================================================================
Assembly Syntax: Rxx32|=lsr(Rss32,Rt32)
C Intrinsic Prototype: Word64 Q6_P_lsror_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_lsror_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
-   Instruction Type:      S_3op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_lsror_PR(Word64 Rxx, Word64 Rss, Word32
+   Rt) Instruction Type:      S_3op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_lsror_PR…
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_lsror_PR __builtin_HEXAGON_S2_lsr_r_p_or
/* ==========================================================================
Assembly Syntax: Rxx32^=lsr(Rss32,Rt32)
C Intrinsic Prototype: Word64 Q6_P_lsrxacc_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_lsrxacc_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
-   Instruction Type:      S_3op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_lsrxacc_PR(Word64 Rxx, Word64 Rss, Word32
+   Rt) Instruction Type:      S_3op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_lsrxacc_PR…
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_lsrxacc_PR __builtin_HEXAGON_S2_lsr_r_p_xor
/* ==========================================================================
Assembly Syntax: Rd32=lsr(Rs32,Rt32)
C Intrinsic Prototype: Word32 Q6_R_lsr_RR(Word32 Rs, Word32 Rt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_lsr_RR __builtin_HEXAGON_S2_lsr_r_r
/* ==========================================================================
Assembly Syntax: Rx32+=lsr(Rs32,Rt32)
C Intrinsic Prototype: Word32 Q6_R_lsracc_RR(Word32 Rx, Word32 Rs, Word32 Rt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_lsracc_RR __builtin_HEXAGON_S2_lsr_r_r_acc
/* ==========================================================================
Assembly Syntax: Rx32&=lsr(Rs32,Rt32)
C Intrinsic Prototype: Word32 Q6_R_lsrand_RR(Word32 Rx, Word32 Rs, Word32 Rt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_lsrand_RR __builtin_HEXAGON_S2_lsr_r_r_and
/* ==========================================================================
Assembly Syntax: Rx32-=lsr(Rs32,Rt32)
C Intrinsic Prototype: Word32 Q6_R_lsrnac_RR(Word32 Rx, Word32 Rs, Word32 Rt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_lsrnac_RR __builtin_HEXAGON_S2_lsr_r_r_nac
/* ==========================================================================
Assembly Syntax: Rx32|=lsr(Rs32,Rt32)
C Intrinsic Prototype: Word32 Q6_R_lsror_RR(Word32 Rx, Word32 Rs, Word32 Rt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_lsror_RR __builtin_HEXAGON_S2_lsr_r_r_or
/* ==========================================================================
Assembly Syntax: Rdd32=vlsrh(Rss32,Rt32)
C Intrinsic Prototype: Word64 Q6_P_vlsrh_PR(Word64 Rss, Word32 Rt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vlsrh_PR __builtin_HEXAGON_S2_lsr_r_vh
/* ==========================================================================
Assembly Syntax: Rdd32=vlsrw(Rss32,Rt32)
C Intrinsic Prototype: Word64 Q6_P_vlsrw_PR(Word64 Rss, Word32 Rt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vlsrw_PR __builtin_HEXAGON_S2_lsr_r_vw
/* ==========================================================================
Assembly Syntax: Rdd32=packhl(Rs32,Rt32)
C Intrinsic Prototype: Word64 Q6_P_packhl_RR(Word32 Rs, Word32 Rt)
Instruction Type: ALU32_3op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_P_packhl_RR __builtin_HEXAGON_S2_packhl
/* ==========================================================================
Assembly Syntax: Rd32=parity(Rss32,Rtt32)
C Intrinsic Prototype: Word32 Q6_R_parity_PP(Word64 Rss, Word64 Rtt)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_parity_PP __builtin_HEXAGON_S2_parityp
/* ==========================================================================
Assembly Syntax: Rd32=setbit(Rs32,#u5)
C Intrinsic Prototype: Word32 Q6_R_setbit_RI(Word32 Rs, Word32 Iu5)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_setbit_RI __builtin_HEXAGON_S2_setbit_i
/* ==========================================================================
Assembly Syntax: Rd32=setbit(Rs32,Rt32)
C Intrinsic Prototype: Word32 Q6_R_setbit_RR(Word32 Rs, Word32 Rt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_setbit_RR __builtin_HEXAGON_S2_setbit_r
/* ==========================================================================
Assembly Syntax: Rdd32=shuffeb(Rss32,Rtt32)
C Intrinsic Prototype: Word64 Q6_P_shuffeb_PP(Word64 Rss, Word64 Rtt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_shuffeb_PP __builtin_HEXAGON_S2_shuffeb
/* ==========================================================================
Assembly Syntax: Rdd32=shuffeh(Rss32,Rtt32)
C Intrinsic Prototype: Word64 Q6_P_shuffeh_PP(Word64 Rss, Word64 Rtt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_shuffeh_PP __builtin_HEXAGON_S2_shuffeh
/* ==========================================================================
Assembly Syntax: Rdd32=shuffob(Rtt32,Rss32)
C Intrinsic Prototype: Word64 Q6_P_shuffob_PP(Word64 Rtt, Word64 Rss)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_shuffob_PP __builtin_HEXAGON_S2_shuffob
/* ==========================================================================
Assembly Syntax: Rdd32=shuffoh(Rtt32,Rss32)
C Intrinsic Prototype: Word64 Q6_P_shuffoh_PP(Word64 Rtt, Word64 Rss)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_shuffoh_PP __builtin_HEXAGON_S2_shuffoh
/* ==========================================================================
Assembly Syntax: memb(Rx32++#s4:0:circ(Mu2))=Rt32
C Intrinsic Prototype: void Q6_memb_IMR_circ(void** Rx, Word32 Is4_0, Word32 Mu, Word32 Rt, void* BaseAddress)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: void Q6_memb_IMR_circ(void** Rx, Word32 Is4_0, Word32 Mu, Word32 Rt, void* BaseAddress)
-   Instruction Type:      ST
-   Execution Slots:       SLOT01
+   C Intrinsic Prototype: void Q6_memb_IMR_circ(void** Rx, Word32 Is4_0, Word32
+   Mu, Word32 Rt, void* BaseAddress) Instruction Type:      ST Execution Slots:
+   SLOT01
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: void Q6_memb_IMR_circ…
Instruction Type: ST
Execution Slots: SLOT01
========================================================================== */
#define Q6_memb_IMR_circ __builtin_HEXAGON_S2_storerb_pci
/* ==========================================================================
Assembly Syntax: memb(Rx32++I:circ(Mu2))=Rt32
C Intrinsic Prototype: void Q6_memb_MR_circ(void** Rx, Word32 Mu, Word32 Rt, void* BaseAddress)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: void Q6_memb_MR_circ(void** Rx, Word32 Mu, Word32 Rt, void* BaseAddress)
-   Instruction Type:      ST
-   Execution Slots:       SLOT01
+   C Intrinsic Prototype: void Q6_memb_MR_circ(void** Rx, Word32 Mu, Word32 Rt,
+   void* BaseAddress) Instruction Type:      ST Execution Slots:       SLOT01
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: void Q6_memb_MR_circ…
Instruction Type: ST
Execution Slots: SLOT01
========================================================================== */
#define Q6_memb_MR_circ __builtin_HEXAGON_S2_storerb_pcr
/* ==========================================================================
Assembly Syntax: memd(Rx32++#s4:3:circ(Mu2))=Rtt32
C Intrinsic Prototype: void Q6_memd_IMP_circ(void** Rx, Word32 Is4_3, Word32 Mu, Word64 Rtt, void* BaseAddress)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: void Q6_memd_IMP_circ(void** Rx, Word32 Is4_3, Word32 Mu, Word64 Rtt, void* BaseAddress)
-   Instruction Type:      ST
-   Execution Slots:       SLOT01
+   C Intrinsic Prototype: void Q6_memd_IMP_circ(void** Rx, Word32 Is4_3, Word32
+   Mu, Word64 Rtt, void* BaseAddress) Instruction Type:      ST Execution Slots:
+   SLOT01
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: void Q6_memd_IMP_circ…
Instruction Type: ST
Execution Slots: SLOT01
========================================================================== */
#define Q6_memd_IMP_circ __builtin_HEXAGON_S2_storerd_pci
/* ==========================================================================
Assembly Syntax: memd(Rx32++I:circ(Mu2))=Rtt32
C Intrinsic Prototype: void Q6_memd_MP_circ(void** Rx, Word32 Mu, Word64 Rtt, void* BaseAddress)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: void Q6_memd_MP_circ(void** Rx, Word32 Mu, Word64 Rtt, void* BaseAddress)
-   Instruction Type:      ST
-   Execution Slots:       SLOT01
+   C Intrinsic Prototype: void Q6_memd_MP_circ(void** Rx, Word32 Mu, Word64 Rtt,
+   void* BaseAddress) Instruction Type:      ST Execution Slots:       SLOT01
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: void Q6_memd_MP_circ…
Instruction Type: ST
Execution Slots: SLOT01
========================================================================== */
#define Q6_memd_MP_circ __builtin_HEXAGON_S2_storerd_pcr
/* ==========================================================================
Assembly Syntax: memh(Rx32++#s4:1:circ(Mu2))=Rt32.h
C Intrinsic Prototype: void Q6_memh_IMRh_circ(void** Rx, Word32 Is4_1, Word32 Mu, Word32 Rt, void* BaseAddress)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: void Q6_memh_IMRh_circ(void** Rx, Word32 Is4_1, Word32 Mu, Word32 Rt, void* BaseAddress)
-   Instruction Type:      ST
-   Execution Slots:       SLOT01
+   C Intrinsic Prototype: void Q6_memh_IMRh_circ(void** Rx, Word32 Is4_1, Word32
+   Mu, Word32 Rt, void* BaseAddress) Instruction Type:      ST Execution Slots:
+   SLOT01
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: void Q6_memh_IMRh_circ…
Instruction Type: ST
Execution Slots: SLOT01
========================================================================== */
#define Q6_memh_IMRh_circ __builtin_HEXAGON_S2_storerf_pci
/* ==========================================================================
Assembly Syntax: memh(Rx32++I:circ(Mu2))=Rt32.h
C Intrinsic Prototype: void Q6_memh_MRh_circ(void** Rx, Word32 Mu, Word32 Rt, void* BaseAddress)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: void Q6_memh_MRh_circ(void** Rx, Word32 Mu, Word32 Rt, void* BaseAddress)
-   Instruction Type:      ST
-   Execution Slots:       SLOT01
+   C Intrinsic Prototype: void Q6_memh_MRh_circ(void** Rx, Word32 Mu, Word32 Rt,
+   void* BaseAddress) Instruction Type:      ST Execution Slots:       SLOT01
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: void Q6_memh_MRh_circ…
Instruction Type: ST
Execution Slots: SLOT01
========================================================================== */
#define Q6_memh_MRh_circ __builtin_HEXAGON_S2_storerf_pcr
/* ==========================================================================
Assembly Syntax: memh(Rx32++#s4:1:circ(Mu2))=Rt32
C Intrinsic Prototype: void Q6_memh_IMR_circ(void** Rx, Word32 Is4_1, Word32 Mu, Word32 Rt, void* BaseAddress)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: void Q6_memh_IMR_circ(void** Rx, Word32 Is4_1, Word32 Mu, Word32 Rt, void* BaseAddress)
-   Instruction Type:      ST
-   Execution Slots:       SLOT01
+   C Intrinsic Prototype: void Q6_memh_IMR_circ(void** Rx, Word32 Is4_1, Word32
+   Mu, Word32 Rt, void* BaseAddress) Instruction Type:      ST Execution Slots:
+   SLOT01
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: void Q6_memh_IMR_circ…
Instruction Type: ST
Execution Slots: SLOT01
========================================================================== */
#define Q6_memh_IMR_circ __builtin_HEXAGON_S2_storerh_pci
/* ==========================================================================
Assembly Syntax: memh(Rx32++I:circ(Mu2))=Rt32
C Intrinsic Prototype: void Q6_memh_MR_circ(void** Rx, Word32 Mu, Word32 Rt, void* BaseAddress)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: void Q6_memh_MR_circ(void** Rx, Word32 Mu, Word32 Rt, void* BaseAddress)
-   Instruction Type:      ST
-   Execution Slots:       SLOT01
+   C Intrinsic Prototype: void Q6_memh_MR_circ(void** Rx, Word32 Mu, Word32 Rt,
+   void* BaseAddress) Instruction Type:      ST Execution Slots:       SLOT01
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: void Q6_memh_MR_circ…
Instruction Type: ST
Execution Slots: SLOT01
========================================================================== */
#define Q6_memh_MR_circ __builtin_HEXAGON_S2_storerh_pcr
/* ==========================================================================
Assembly Syntax: memw(Rx32++#s4:2:circ(Mu2))=Rt32
C Intrinsic Prototype: void Q6_memw_IMR_circ(void** Rx, Word32 Is4_2, Word32 Mu, Word32 Rt, void* BaseAddress)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: void Q6_memw_IMR_circ(void** Rx, Word32 Is4_2, Word32 Mu, Word32 Rt, void* BaseAddress)
-   Instruction Type:      ST
-   Execution Slots:       SLOT01
+   C Intrinsic Prototype: void Q6_memw_IMR_circ(void** Rx, Word32 Is4_2, Word32
+   Mu, Word32 Rt, void* BaseAddress) Instruction Type:      ST Execution Slots:
+   SLOT01
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: void Q6_memw_IMR_circ…
Instruction Type: ST
Execution Slots: SLOT01
========================================================================== */
#define Q6_memw_IMR_circ __builtin_HEXAGON_S2_storeri_pci
/* ==========================================================================
Assembly Syntax: memw(Rx32++I:circ(Mu2))=Rt32
C Intrinsic Prototype: void Q6_memw_MR_circ(void** Rx, Word32 Mu, Word32 Rt, void* BaseAddress)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: void Q6_memw_MR_circ(void** Rx, Word32 Mu, Word32 Rt, void* BaseAddress)
-   Instruction Type:      ST
-   Execution Slots:       SLOT01
+   C Intrinsic Prototype: void Q6_memw_MR_circ(void** Rx, Word32 Mu, Word32 Rt,
+   void* BaseAddress) Instruction Type:      ST Execution Slots:       SLOT01
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: void Q6_memw_MR_circ…
Instruction Type: ST
Execution Slots: SLOT01
========================================================================== */
#define Q6_memw_MR_circ __builtin_HEXAGON_S2_storeri_pcr
/* ==========================================================================
Assembly Syntax: Rd32=vsathb(Rs32)
C Intrinsic Prototype: Word32 Q6_R_vsathb_R(Word32 Rs)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_vsathb_R __builtin_HEXAGON_S2_svsathb
/* ==========================================================================
Assembly Syntax: Rd32=vsathub(Rs32)
C Intrinsic Prototype: Word32 Q6_R_vsathub_R(Word32 Rs)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_vsathub_R __builtin_HEXAGON_S2_svsathub
/* ==========================================================================
Assembly Syntax: Rx32=tableidxb(Rs32,#u4,#U5)
C Intrinsic Prototype: Word32 Q6_R_tableidxb_RII(Word32 Rx, Word32 Rs, Word32 Iu4, Word32 IU5)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_tableidxb_RII(Word32 Rx, Word32 Rs, Word32 Iu4, Word32 IU5)
-   Instruction Type:      S_2op
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: Word32 Q6_R_tableidxb_RII(Word32 Rx, Word32 Rs, Word32
+   Iu4, Word32 IU5) Instruction Type:      S_2op Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_tableidxb_RII…
Instruction Type: S_2op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_R_tableidxb_RII __builtin_HEXAGON_S2_tableidxb_goodsyntax
/* ==========================================================================
Assembly Syntax: Rx32=tableidxd(Rs32,#u4,#U5)
C Intrinsic Prototype: Word32 Q6_R_tableidxd_RII(Word32 Rx, Word32 Rs, Word32 Iu4, Word32 IU5)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_tableidxd_RII(Word32 Rx, Word32 Rs, Word32 Iu4, Word32 IU5)
-   Instruction Type:      S_2op
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: Word32 Q6_R_tableidxd_RII(Word32 Rx, Word32 Rs, Word32
+   Iu4, Word32 IU5) Instruction Type:      S_2op Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_tableidxd_RII…
Instruction Type: S_2op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_R_tableidxd_RII __builtin_HEXAGON_S2_tableidxd_goodsyntax
/* ==========================================================================
Assembly Syntax: Rx32=tableidxh(Rs32,#u4,#U5)
C Intrinsic Prototype: Word32 Q6_R_tableidxh_RII(Word32 Rx, Word32 Rs, Word32 Iu4, Word32 IU5)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_tableidxh_RII(Word32 Rx, Word32 Rs, Word32 Iu4, Word32 IU5)
-   Instruction Type:      S_2op
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: Word32 Q6_R_tableidxh_RII(Word32 Rx, Word32 Rs, Word32
+   Iu4, Word32 IU5) Instruction Type:      S_2op Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_tableidxh_RII…
Instruction Type: S_2op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_R_tableidxh_RII __builtin_HEXAGON_S2_tableidxh_goodsyntax
/* ==========================================================================
Assembly Syntax: Rx32=tableidxw(Rs32,#u4,#U5)
C Intrinsic Prototype: Word32 Q6_R_tableidxw_RII(Word32 Rx, Word32 Rs, Word32 Iu4, Word32 IU5)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_tableidxw_RII(Word32 Rx, Word32 Rs, Word32 Iu4, Word32 IU5)
-   Instruction Type:      S_2op
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: Word32 Q6_R_tableidxw_RII(Word32 Rx, Word32 Rs, Word32
+   Iu4, Word32 IU5) Instruction Type:      S_2op Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_tableidxw_RII…
Instruction Type: S_2op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_R_tableidxw_RII __builtin_HEXAGON_S2_tableidxw_goodsyntax
/* ==========================================================================
Assembly Syntax: Rd32=togglebit(Rs32,#u5)
C Intrinsic Prototype: Word32 Q6_R_togglebit_RI(Word32 Rs, Word32 Iu5)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_togglebit_RI __builtin_HEXAGON_S2_togglebit_i
/* ==========================================================================
Assembly Syntax: Rd32=togglebit(Rs32,Rt32)
C Intrinsic Prototype: Word32 Q6_R_togglebit_RR(Word32 Rs, Word32 Rt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_togglebit_RR __builtin_HEXAGON_S2_togglebit_r
/* ==========================================================================
Assembly Syntax: Pd4=tstbit(Rs32,#u5)
C Intrinsic Prototype: Byte Q6_p_tstbit_RI(Word32 Rs, Word32 Iu5)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_tstbit_RI __builtin_HEXAGON_S2_tstbit_i
/* ==========================================================================
Assembly Syntax: Pd4=tstbit(Rs32,Rt32)
C Intrinsic Prototype: Byte Q6_p_tstbit_RR(Word32 Rs, Word32 Rt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_tstbit_RR __builtin_HEXAGON_S2_tstbit_r
/* ==========================================================================
Assembly Syntax: Rdd32=valignb(Rtt32,Rss32,#u3)
C Intrinsic Prototype: Word64 Q6_P_valignb_PPI(Word64 Rtt, Word64 Rss, Word32 Iu3)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_valignb_PPI(Word64 Rtt, Word64 Rss, Word32 Iu3)
-   Instruction Type:      S_3op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_valignb_PPI(Word64 Rtt, Word64 Rss, Word32
+   Iu3) Instruction Type:      S_3op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_valignb_PPI…
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_valignb_PPI __builtin_HEXAGON_S2_valignib
/* ==========================================================================
Assembly Syntax: Rdd32=valignb(Rtt32,Rss32,Pu4)
C Intrinsic Prototype: Word64 Q6_P_valignb_PPp(Word64 Rtt, Word64 Rss, Byte Pu)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_valignb_PPp(Word64 Rtt, Word64 Rss, Byte Pu)
-   Instruction Type:      S_3op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_valignb_PPp(Word64 Rtt, Word64 Rss, Byte
+   Pu) Instruction Type:      S_3op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_valignb_PPp…
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_valignb_PPp __builtin_HEXAGON_S2_valignrb
/* ==========================================================================
Assembly Syntax: Rdd32=vcnegh(Rss32,Rt32)
C Intrinsic Prototype: Word64 Q6_P_vcnegh_PR(Word64 Rss, Word32 Rt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vcnegh_PR __builtin_HEXAGON_S2_vcnegh
/* ==========================================================================
Assembly Syntax: Rdd32=vcrotate(Rss32,Rt32)
C Intrinsic Prototype: Word64 Q6_P_vcrotate_PR(Word64 Rss, Word32 Rt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vcrotate_PR __builtin_HEXAGON_S2_vcrotate
/* ==========================================================================
Assembly Syntax: Rxx32+=vrcnegh(Rss32,Rt32)
C Intrinsic Prototype: Word64 Q6_P_vrcneghacc_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vrcneghacc_PR(Word64 Rxx, Word64 Rss, Word32 Rt)
-   Instruction Type:      S_3op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vrcneghacc_PR(Word64 Rxx, Word64 Rss,
+   Word32 Rt) Instruction Type:      S_3op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_vrcneghacc_PR…
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vrcneghacc_PR __builtin_HEXAGON_S2_vrcnegh
/* ==========================================================================
Assembly Syntax: Rd32=vrndwh(Rss32)
C Intrinsic Prototype: Word32 Q6_R_vrndwh_P(Word64 Rss)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_vrndwh_P __builtin_HEXAGON_S2_vrndpackwh
/* ==========================================================================
Assembly Syntax: Rd32=vrndwh(Rss32):sat
C Intrinsic Prototype: Word32 Q6_R_vrndwh_P_sat(Word64 Rss)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_vrndwh_P_sat __builtin_HEXAGON_S2_vrndpackwhs
/* ==========================================================================
Assembly Syntax: Rd32=vsathb(Rss32)
C Intrinsic Prototype: Word32 Q6_R_vsathb_P(Word64 Rss)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_vsathb_P __builtin_HEXAGON_S2_vsathb
/* ==========================================================================
Assembly Syntax: Rdd32=vsathb(Rss32)
C Intrinsic Prototype: Word64 Q6_P_vsathb_P(Word64 Rss)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vsathb_P __builtin_HEXAGON_S2_vsathb_nopack
/* ==========================================================================
Assembly Syntax: Rd32=vsathub(Rss32)
C Intrinsic Prototype: Word32 Q6_R_vsathub_P(Word64 Rss)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_vsathub_P __builtin_HEXAGON_S2_vsathub
/* ==========================================================================
Assembly Syntax: Rdd32=vsathub(Rss32)
C Intrinsic Prototype: Word64 Q6_P_vsathub_P(Word64 Rss)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vsathub_P __builtin_HEXAGON_S2_vsathub_nopack
/* ==========================================================================
Assembly Syntax: Rd32=vsatwh(Rss32)
C Intrinsic Prototype: Word32 Q6_R_vsatwh_P(Word64 Rss)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_vsatwh_P __builtin_HEXAGON_S2_vsatwh
/* ==========================================================================
Assembly Syntax: Rdd32=vsatwh(Rss32)
C Intrinsic Prototype: Word64 Q6_P_vsatwh_P(Word64 Rss)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vsatwh_P __builtin_HEXAGON_S2_vsatwh_nopack
/* ==========================================================================
Assembly Syntax: Rd32=vsatwuh(Rss32)
C Intrinsic Prototype: Word32 Q6_R_vsatwuh_P(Word64 Rss)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_vsatwuh_P __builtin_HEXAGON_S2_vsatwuh
/* ==========================================================================
Assembly Syntax: Rdd32=vsatwuh(Rss32)
C Intrinsic Prototype: Word64 Q6_P_vsatwuh_P(Word64 Rss)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vsatwuh_P __builtin_HEXAGON_S2_vsatwuh_nopack
/* ==========================================================================
Assembly Syntax: Rd32=vsplatb(Rs32)
C Intrinsic Prototype: Word32 Q6_R_vsplatb_R(Word32 Rs)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_vsplatb_R __builtin_HEXAGON_S2_vsplatrb
/* ==========================================================================
Assembly Syntax: Rdd32=vsplath(Rs32)
C Intrinsic Prototype: Word64 Q6_P_vsplath_R(Word32 Rs)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vsplath_R __builtin_HEXAGON_S2_vsplatrh
/* ==========================================================================
Assembly Syntax: Rdd32=vspliceb(Rss32,Rtt32,#u3)
C Intrinsic Prototype: Word64 Q6_P_vspliceb_PPI(Word64 Rss, Word64 Rtt, Word32 Iu3)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vspliceb_PPI(Word64 Rss, Word64 Rtt, Word32 Iu3)
-   Instruction Type:      S_3op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vspliceb_PPI(Word64 Rss, Word64 Rtt,
+   Word32 Iu3) Instruction Type:      S_3op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_vspliceb_PPI…
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vspliceb_PPI __builtin_HEXAGON_S2_vspliceib
/* ==========================================================================
Assembly Syntax: Rdd32=vspliceb(Rss32,Rtt32,Pu4)
C Intrinsic Prototype: Word64 Q6_P_vspliceb_PPp(Word64 Rss, Word64 Rtt, Byte Pu)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vspliceb_PPp(Word64 Rss, Word64 Rtt, Byte Pu)
-   Instruction Type:      S_3op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vspliceb_PPp(Word64 Rss, Word64 Rtt, Byte
+   Pu) Instruction Type:      S_3op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_vspliceb_PPp…
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vspliceb_PPp __builtin_HEXAGON_S2_vsplicerb
/* ==========================================================================
Assembly Syntax: Rdd32=vsxtbh(Rs32)
C Intrinsic Prototype: Word64 Q6_P_vsxtbh_R(Word32 Rs)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vsxtbh_R __builtin_HEXAGON_S2_vsxtbh
/* ==========================================================================
Assembly Syntax: Rdd32=vsxthw(Rs32)
C Intrinsic Prototype: Word64 Q6_P_vsxthw_R(Word32 Rs)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vsxthw_R __builtin_HEXAGON_S2_vsxthw
/* ==========================================================================
Assembly Syntax: Rd32=vtrunehb(Rss32)
C Intrinsic Prototype: Word32 Q6_R_vtrunehb_P(Word64 Rss)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_vtrunehb_P __builtin_HEXAGON_S2_vtrunehb
/* ==========================================================================
Assembly Syntax: Rdd32=vtrunewh(Rss32,Rtt32)
C Intrinsic Prototype: Word64 Q6_P_vtrunewh_PP(Word64 Rss, Word64 Rtt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vtrunewh_PP __builtin_HEXAGON_S2_vtrunewh
/* ==========================================================================
Assembly Syntax: Rd32=vtrunohb(Rss32)
C Intrinsic Prototype: Word32 Q6_R_vtrunohb_P(Word64 Rss)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_vtrunohb_P __builtin_HEXAGON_S2_vtrunohb
/* ==========================================================================
Assembly Syntax: Rdd32=vtrunowh(Rss32,Rtt32)
C Intrinsic Prototype: Word64 Q6_P_vtrunowh_PP(Word64 Rss, Word64 Rtt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vtrunowh_PP __builtin_HEXAGON_S2_vtrunowh
/* ==========================================================================
Assembly Syntax: Rdd32=vzxtbh(Rs32)
C Intrinsic Prototype: Word64 Q6_P_vzxtbh_R(Word32 Rs)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vzxtbh_R __builtin_HEXAGON_S2_vzxtbh
/* ==========================================================================
Assembly Syntax: Rdd32=vzxthw(Rs32)
C Intrinsic Prototype: Word64 Q6_P_vzxthw_R(Word32 Rs)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vzxthw_R __builtin_HEXAGON_S2_vzxthw
/* ==========================================================================
Assembly Syntax: Rd32=add(Rs32,add(Ru32,#s6))
C Intrinsic Prototype: Word32 Q6_R_add_add_RRI(Word32 Rs, Word32 Ru, Word32 Is6)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_add_add_RRI(Word32 Rs, Word32 Ru, Word32 Is6)
-   Instruction Type:      ALU64
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_add_add_RRI(Word32 Rs, Word32 Ru, Word32
+   Is6) Instruction Type:      ALU64 Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_add_add_RRI…
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_add_add_RRI __builtin_HEXAGON_S4_addaddi
/* ==========================================================================
Assembly Syntax: Rx32=add(#u8,asl(Rx32,#U5))
C Intrinsic Prototype: Word32 Q6_R_add_asl_IRI(Word32 Iu8, Word32 Rx, Word32 IU5)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_add_asl_IRI(Word32 Iu8, Word32 Rx, Word32 IU5)
-   Instruction Type:      ALU64
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_add_asl_IRI(Word32 Iu8, Word32 Rx, Word32
+   IU5) Instruction Type:      ALU64 Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_add_asl_IRI…
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_add_asl_IRI __builtin_HEXAGON_S4_addi_asl_ri
/* ==========================================================================
Assembly Syntax: Rx32=add(#u8,lsr(Rx32,#U5))
C Intrinsic Prototype: Word32 Q6_R_add_lsr_IRI(Word32 Iu8, Word32 Rx, Word32 IU5)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_add_lsr_IRI(Word32 Iu8, Word32 Rx, Word32 IU5)
-   Instruction Type:      ALU64
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_add_lsr_IRI(Word32 Iu8, Word32 Rx, Word32
+   IU5) Instruction Type:      ALU64 Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_add_lsr_IRI…
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_add_lsr_IRI __builtin_HEXAGON_S4_addi_lsr_ri
/* ==========================================================================
Assembly Syntax: Rx32=and(#u8,asl(Rx32,#U5))
C Intrinsic Prototype: Word32 Q6_R_and_asl_IRI(Word32 Iu8, Word32 Rx, Word32 IU5)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_and_asl_IRI(Word32 Iu8, Word32 Rx, Word32 IU5)
-   Instruction Type:      ALU64
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_and_asl_IRI(Word32 Iu8, Word32 Rx, Word32
+   IU5) Instruction Type:      ALU64 Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_and_asl_IRI…
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_and_asl_IRI __builtin_HEXAGON_S4_andi_asl_ri
/* ==========================================================================
Assembly Syntax: Rx32=and(#u8,lsr(Rx32,#U5))
C Intrinsic Prototype: Word32 Q6_R_and_lsr_IRI(Word32 Iu8, Word32 Rx, Word32 IU5)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_and_lsr_IRI(Word32 Iu8, Word32 Rx, Word32 IU5)
-   Instruction Type:      ALU64
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_and_lsr_IRI(Word32 Iu8, Word32 Rx, Word32
+   IU5) Instruction Type:      ALU64 Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_and_lsr_IRI…
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_and_lsr_IRI __builtin_HEXAGON_S4_andi_lsr_ri
/* ==========================================================================
Assembly Syntax: Rd32=add(clb(Rs32),#s6)
C Intrinsic Prototype: Word32 Q6_R_add_clb_RI(Word32 Rs, Word32 Is6)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_add_clb_RI __builtin_HEXAGON_S4_clbaddi
/* ==========================================================================
Assembly Syntax: Rd32=add(clb(Rss32),#s6)
C Intrinsic Prototype: Word32 Q6_R_add_clb_PI(Word64 Rss, Word32 Is6)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_add_clb_PI __builtin_HEXAGON_S4_clbpaddi
/* ==========================================================================
Assembly Syntax: Rd32=normamt(Rss32)
C Intrinsic Prototype: Word32 Q6_R_normamt_P(Word64 Rss)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_normamt_P __builtin_HEXAGON_S4_clbpnorm
/* ==========================================================================
Assembly Syntax: Rd32=extract(Rs32,#u5,#U5)
C Intrinsic Prototype: Word32 Q6_R_extract_RII(Word32 Rs, Word32 Iu5, Word32 IU5)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_extract_RII(Word32 Rs, Word32 Iu5, Word32 IU5)
-   Instruction Type:      S_2op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_extract_RII(Word32 Rs, Word32 Iu5, Word32
+   IU5) Instruction Type:      S_2op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_extract_RII…
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_extract_RII __builtin_HEXAGON_S4_extract
/* ==========================================================================
Assembly Syntax: Rd32=extract(Rs32,Rtt32)
C Intrinsic Prototype: Word32 Q6_R_extract_RP(Word32 Rs, Word64 Rtt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_extract_RP __builtin_HEXAGON_S4_extract_rp
/* ==========================================================================
Assembly Syntax: Rdd32=extract(Rss32,#u6,#U6)
C Intrinsic Prototype: Word64 Q6_P_extract_PII(Word64 Rss, Word32 Iu6, Word32 IU6)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_extract_PII(Word64 Rss, Word32 Iu6, Word32 IU6)
-   Instruction Type:      S_2op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_extract_PII(Word64 Rss, Word32 Iu6, Word32
+   IU6) Instruction Type:      S_2op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_extract_PII…
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_extract_PII __builtin_HEXAGON_S4_extractp
/* ==========================================================================
Assembly Syntax: Rdd32=extract(Rss32,Rtt32)
C Intrinsic Prototype: Word64 Q6_P_extract_PP(Word64 Rss, Word64 Rtt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_extract_PP __builtin_HEXAGON_S4_extractp_rp
/* ==========================================================================
Assembly Syntax: Rd32=lsl(#s6,Rt32)
C Intrinsic Prototype: Word32 Q6_R_lsl_IR(Word32 Is6, Word32 Rt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_lsl_IR __builtin_HEXAGON_S4_lsli
/* ==========================================================================
Assembly Syntax: Pd4=!tstbit(Rs32,#u5)
C Intrinsic Prototype: Byte Q6_p_not_tstbit_RI(Word32 Rs, Word32 Iu5)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_not_tstbit_RI __builtin_HEXAGON_S4_ntstbit_i
/* ==========================================================================
Assembly Syntax: Pd4=!tstbit(Rs32,Rt32)
C Intrinsic Prototype: Byte Q6_p_not_tstbit_RR(Word32 Rs, Word32 Rt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_not_tstbit_RR __builtin_HEXAGON_S4_ntstbit_r
/* ==========================================================================
Assembly Syntax: Rx32|=and(Rs32,#s10)
C Intrinsic Prototype: Word32 Q6_R_andor_RI(Word32 Rx, Word32 Rs, Word32 Is10)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_andor_RI(Word32 Rx, Word32 Rs, Word32 Is10)
-   Instruction Type:      ALU64
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_andor_RI(Word32 Rx, Word32 Rs, Word32
+   Is10) Instruction Type:      ALU64 Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_andor_RI…
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_andor_RI __builtin_HEXAGON_S4_or_andi
/* ==========================================================================
Assembly Syntax: Rx32=or(Ru32,and(Rx32,#s10))
C Intrinsic Prototype: Word32 Q6_R_or_and_RRI(Word32 Ru, Word32 Rx, Word32 Is10)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_or_and_RRI(Word32 Ru, Word32 Rx, Word32 Is10)
-   Instruction Type:      ALU64
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_or_and_RRI(Word32 Ru, Word32 Rx, Word32
+   Is10) Instruction Type:      ALU64 Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_or_and_RRI…
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_or_and_RRI __builtin_HEXAGON_S4_or_andix
/* ==========================================================================
Assembly Syntax: Rx32|=or(Rs32,#s10)
C Intrinsic Prototype: Word32 Q6_R_oror_RI(Word32 Rx, Word32 Rs, Word32 Is10)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_oror_RI __builtin_HEXAGON_S4_or_ori
/* ==========================================================================
Assembly Syntax: Rx32=or(#u8,asl(Rx32,#U5))
C Intrinsic Prototype: Word32 Q6_R_or_asl_IRI(Word32 Iu8, Word32 Rx, Word32 IU5)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_or_asl_IRI(Word32 Iu8, Word32 Rx, Word32 IU5)
-   Instruction Type:      ALU64
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_or_asl_IRI(Word32 Iu8, Word32 Rx, Word32
+   IU5) Instruction Type:      ALU64 Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_or_asl_IRI…
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_or_asl_IRI __builtin_HEXAGON_S4_ori_asl_ri
/* ==========================================================================
Assembly Syntax: Rx32=or(#u8,lsr(Rx32,#U5))
C Intrinsic Prototype: Word32 Q6_R_or_lsr_IRI(Word32 Iu8, Word32 Rx, Word32 IU5)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_or_lsr_IRI(Word32 Iu8, Word32 Rx, Word32 IU5)
-   Instruction Type:      ALU64
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_or_lsr_IRI(Word32 Iu8, Word32 Rx, Word32
+   IU5) Instruction Type:      ALU64 Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_or_lsr_IRI…
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_or_lsr_IRI __builtin_HEXAGON_S4_ori_lsr_ri
/* ==========================================================================
Assembly Syntax: Rd32=parity(Rs32,Rt32)
C Intrinsic Prototype: Word32 Q6_R_parity_RR(Word32 Rs, Word32 Rt)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_parity_RR __builtin_HEXAGON_S4_parity
/* ==========================================================================
Assembly Syntax: Rd32=add(Rs32,sub(#s6,Ru32))
C Intrinsic Prototype: Word32 Q6_R_add_sub_RIR(Word32 Rs, Word32 Is6, Word32 Ru)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_add_sub_RIR(Word32 Rs, Word32 Is6, Word32 Ru)
-   Instruction Type:      ALU64
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_add_sub_RIR(Word32 Rs, Word32 Is6, Word32
+   Ru) Instruction Type:      ALU64 Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_add_sub_RIR…
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_add_sub_RIR __builtin_HEXAGON_S4_subaddi
/* ==========================================================================
Assembly Syntax: Rx32=sub(#u8,asl(Rx32,#U5))
C Intrinsic Prototype: Word32 Q6_R_sub_asl_IRI(Word32 Iu8, Word32 Rx, Word32 IU5)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_sub_asl_IRI(Word32 Iu8, Word32 Rx, Word32 IU5)
-   Instruction Type:      ALU64
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_sub_asl_IRI(Word32 Iu8, Word32 Rx, Word32
+   IU5) Instruction Type:      ALU64 Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_sub_asl_IRI…
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_sub_asl_IRI __builtin_HEXAGON_S4_subi_asl_ri
/* ==========================================================================
Assembly Syntax: Rx32=sub(#u8,lsr(Rx32,#U5))
C Intrinsic Prototype: Word32 Q6_R_sub_lsr_IRI(Word32 Iu8, Word32 Rx, Word32 IU5)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_sub_lsr_IRI(Word32 Iu8, Word32 Rx, Word32 IU5)
-   Instruction Type:      ALU64
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_sub_lsr_IRI(Word32 Iu8, Word32 Rx, Word32
+   IU5) Instruction Type:      ALU64 Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_sub_lsr_IRI…
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_sub_lsr_IRI __builtin_HEXAGON_S4_subi_lsr_ri
/* ==========================================================================
Assembly Syntax: Rdd32=vrcrotate(Rss32,Rt32,#u2)
C Intrinsic Prototype: Word64 Q6_P_vrcrotate_PRI(Word64 Rss, Word32 Rt, Word32 Iu2)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vrcrotate_PRI(Word64 Rss, Word32 Rt, Word32 Iu2)
-   Instruction Type:      S_3op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vrcrotate_PRI(Word64 Rss, Word32 Rt,
+   Word32 Iu2) Instruction Type:      S_3op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_vrcrotate_PRI…
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vrcrotate_PRI __builtin_HEXAGON_S4_vrcrotate
/* ==========================================================================
Assembly Syntax: Rxx32+=vrcrotate(Rss32,Rt32,#u2)
C Intrinsic Prototype: Word64 Q6_P_vrcrotateacc_PRI(Word64 Rxx, Word64 Rss, Word32 Rt, Word32 Iu2)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vrcrotateacc_PRI(Word64 Rxx, Word64 Rss, Word32 Rt, Word32 Iu2)
-   Instruction Type:      S_3op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vrcrotateacc_PRI(Word64 Rxx, Word64 Rss,
+   Word32 Rt, Word32 Iu2) Instruction Type:      S_3op Execution Slots: SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vrcrotateacc_PRI __builtin_HEXAGON_S4_vrcrotate_acc
/* ==========================================================================
Assembly Syntax: Rdd32=vxaddsubh(Rss32,Rtt32):sat
C Intrinsic Prototype: Word64 Q6_P_vxaddsubh_PP_sat(Word64 Rss, Word64 Rtt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vxaddsubh_PP_sat __builtin_HEXAGON_S4_vxaddsubh
/* ==========================================================================
Assembly Syntax: Rdd32=vxaddsubh(Rss32,Rtt32):rnd:>>1:sat
C Intrinsic Prototype: Word64 Q6_P_vxaddsubh_PP_rnd_rs1_sat(Word64 Rss, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vxaddsubh_PP_rnd_rs1_sat(Word64 Rss, Word64 Rtt)
-   Instruction Type:      S_3op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vxaddsubh_PP_rnd_rs1_sat(Word64 Rss,
+   Word64 Rtt) Instruction Type:      S_3op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vxaddsubh_PP_rnd_rs1_sat __builtin_HEXAGON_S4_vxaddsubhr
/* ==========================================================================
Assembly Syntax: Rdd32=vxaddsubw(Rss32,Rtt32):sat
C Intrinsic Prototype: Word64 Q6_P_vxaddsubw_PP_sat(Word64 Rss, Word64 Rtt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vxaddsubw_PP_sat __builtin_HEXAGON_S4_vxaddsubw
/* ==========================================================================
Assembly Syntax: Rdd32=vxsubaddh(Rss32,Rtt32):sat
C Intrinsic Prototype: Word64 Q6_P_vxsubaddh_PP_sat(Word64 Rss, Word64 Rtt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vxsubaddh_PP_sat __builtin_HEXAGON_S4_vxsubaddh
/* ==========================================================================
Assembly Syntax: Rdd32=vxsubaddh(Rss32,Rtt32):rnd:>>1:sat
C Intrinsic Prototype: Word64 Q6_P_vxsubaddh_PP_rnd_rs1_sat(Word64 Rss, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vxsubaddh_PP_rnd_rs1_sat(Word64 Rss, Word64 Rtt)
-   Instruction Type:      S_3op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_vxsubaddh_PP_rnd_rs1_sat(Word64 Rss,
+   Word64 Rtt) Instruction Type:      S_3op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vxsubaddh_PP_rnd_rs1_sat __builtin_HEXAGON_S4_vxsubaddhr
/* ==========================================================================
Assembly Syntax: Rdd32=vxsubaddw(Rss32,Rtt32):sat
C Intrinsic Prototype: Word64 Q6_P_vxsubaddw_PP_sat(Word64 Rss, Word64 Rtt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vxsubaddw_PP_sat __builtin_HEXAGON_S4_vxsubaddw
/* ==========================================================================
Assembly Syntax: Rd32=vasrhub(Rss32,#u4):rnd:sat
C Intrinsic Prototype: Word32 Q6_R_vasrhub_PI_rnd_sat(Word64 Rss, Word32 Iu4)
Instruction Type: S_2op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_R_vasrhub_PI_rnd_sat __builtin_HEXAGON_S5_asrhub_rnd_sat_goodsyntax
/* ==========================================================================
Assembly Syntax: Rd32=vasrhub(Rss32,#u4):sat
C Intrinsic Prototype: Word32 Q6_R_vasrhub_PI_sat(Word64 Rss, Word32 Iu4)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_vasrhub_PI_sat __builtin_HEXAGON_S5_asrhub_sat
/* ==========================================================================
Assembly Syntax: Rd32=popcount(Rss32)
C Intrinsic Prototype: Word32 Q6_R_popcount_P(Word64 Rss)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_popcount_P __builtin_HEXAGON_S5_popcountp
/* ==========================================================================
Assembly Syntax: Rdd32=vasrh(Rss32,#u4):rnd
C Intrinsic Prototype: Word64 Q6_P_vasrh_PI_rnd(Word64 Rss, Word32 Iu4)
Instruction Type: S_2op
Execution Slots: SLOT0123
========================================================================== */
#define Q6_P_vasrh_PI_rnd __builtin_HEXAGON_S5_vasrhrnd_goodsyntax
/* ==========================================================================
Assembly Syntax: dccleana(Rs32)
C Intrinsic Prototype: void Q6_dccleana_A(Address Rs)
Instruction Type: ST
Execution Slots: SLOT0
========================================================================== */
#define Q6_dccleana_A __builtin_HEXAGON_Y2_dccleana
/* ==========================================================================
Assembly Syntax: dccleaninva(Rs32)
C Intrinsic Prototype: void Q6_dccleaninva_A(Address Rs)
Instruction Type: ST
Execution Slots: SLOT0
========================================================================== */
#define Q6_dccleaninva_A __builtin_HEXAGON_Y2_dccleaninva
/* ==========================================================================
Assembly Syntax: dcfetch(Rs32)
C Intrinsic Prototype: void Q6_dcfetch_A(Address Rs)
Instruction Type: MAPPING
Execution Slots: SLOT0123
========================================================================== */
#define Q6_dcfetch_A __builtin_HEXAGON_Y2_dcfetch
/* ==========================================================================
Assembly Syntax: dcinva(Rs32)
C Intrinsic Prototype: void Q6_dcinva_A(Address Rs)
Instruction Type: ST
Execution Slots: SLOT0
========================================================================== */
#define Q6_dcinva_A __builtin_HEXAGON_Y2_dcinva
/* ==========================================================================
Assembly Syntax: dczeroa(Rs32)
C Intrinsic Prototype: void Q6_dczeroa_A(Address Rs)
Instruction Type: ST
Execution Slots: SLOT0
========================================================================== */
#define Q6_dczeroa_A __builtin_HEXAGON_Y2_dczeroa
/* ==========================================================================
Assembly Syntax: l2fetch(Rs32,Rt32)
C Intrinsic Prototype: void Q6_l2fetch_AR(Address Rs, Word32 Rt)
Instruction Type: ST
Execution Slots: SLOT0
========================================================================== */
#define Q6_l2fetch_AR __builtin_HEXAGON_Y4_l2fetch
/* ==========================================================================
Assembly Syntax: l2fetch(Rs32,Rtt32)
C Intrinsic Prototype: void Q6_l2fetch_AP(Address Rs, Word64 Rtt)
Instruction Type: ST
Execution Slots: SLOT0
========================================================================== */
#define Q6_l2fetch_AP __builtin_HEXAGON_Y5_l2fetch
#if __HEXAGON_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Rdd32=rol(Rss32,#u6)
C Intrinsic Prototype: Word64 Q6_P_rol_PI(Word64 Rss, Word32 Iu6)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_rol_PI __builtin_HEXAGON_S6_rol_i_p
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HEXAGON_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Rxx32+=rol(Rss32,#u6)
C Intrinsic Prototype: Word64 Q6_P_rolacc_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_rolacc_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
-   Instruction Type:      S_2op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_rolacc_PI(Word64 Rxx, Word64 Rss, Word32
+   Iu6) Instruction Type:      S_2op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_rolacc_PI…
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_rolacc_PI __builtin_HEXAGON_S6_rol_i_p_acc
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HEXAGON_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Rxx32&=rol(Rss32,#u6)
C Intrinsic Prototype: Word64 Q6_P_roland_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_roland_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
-   Instruction Type:      S_2op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_roland_PI(Word64 Rxx, Word64 Rss, Word32
+   Iu6) Instruction Type:      S_2op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_roland_PI…
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_roland_PI __builtin_HEXAGON_S6_rol_i_p_and
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HEXAGON_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Rxx32-=rol(Rss32,#u6)
C Intrinsic Prototype: Word64 Q6_P_rolnac_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_rolnac_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
-   Instruction Type:      S_2op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_rolnac_PI(Word64 Rxx, Word64 Rss, Word32
+   Iu6) Instruction Type:      S_2op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_rolnac_PI…
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_rolnac_PI __builtin_HEXAGON_S6_rol_i_p_nac
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HEXAGON_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Rxx32|=rol(Rss32,#u6)
C Intrinsic Prototype: Word64 Q6_P_rolor_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_rolor_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
-   Instruction Type:      S_2op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_rolor_PI(Word64 Rxx, Word64 Rss, Word32
+   Iu6) Instruction Type:      S_2op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_rolor_PI…
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_rolor_PI __builtin_HEXAGON_S6_rol_i_p_or
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HEXAGON_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Rxx32^=rol(Rss32,#u6)
C Intrinsic Prototype: Word64 Q6_P_rolxacc_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_rolxacc_PI(Word64 Rxx, Word64 Rss, Word32 Iu6)
-   Instruction Type:      S_2op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word64 Q6_P_rolxacc_PI(Word64 Rxx, Word64 Rss, Word32
+   Iu6) Instruction Type:      S_2op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_rolxacc_PI…
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_rolxacc_PI __builtin_HEXAGON_S6_rol_i_p_xacc
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HEXAGON_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Rd32=rol(Rs32,#u5)
C Intrinsic Prototype: Word32 Q6_R_rol_RI(Word32 Rs, Word32 Iu5)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_rol_RI __builtin_HEXAGON_S6_rol_i_r
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HEXAGON_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Rx32+=rol(Rs32,#u5)
C Intrinsic Prototype: Word32 Q6_R_rolacc_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_rolacc_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
-   Instruction Type:      S_2op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_rolacc_RI(Word32 Rx, Word32 Rs, Word32
+   Iu5) Instruction Type:      S_2op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_rolacc_RI…
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_rolacc_RI __builtin_HEXAGON_S6_rol_i_r_acc
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HEXAGON_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Rx32&=rol(Rs32,#u5)
C Intrinsic Prototype: Word32 Q6_R_roland_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_roland_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
-   Instruction Type:      S_2op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_roland_RI(Word32 Rx, Word32 Rs, Word32
+   Iu5) Instruction Type:      S_2op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_roland_RI…
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_roland_RI __builtin_HEXAGON_S6_rol_i_r_and
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HEXAGON_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Rx32-=rol(Rs32,#u5)
C Intrinsic Prototype: Word32 Q6_R_rolnac_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_rolnac_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
-   Instruction Type:      S_2op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_rolnac_RI(Word32 Rx, Word32 Rs, Word32
+   Iu5) Instruction Type:      S_2op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_rolnac_RI…
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_rolnac_RI __builtin_HEXAGON_S6_rol_i_r_nac
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HEXAGON_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Rx32|=rol(Rs32,#u5)
C Intrinsic Prototype: Word32 Q6_R_rolor_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_rolor_RI __builtin_HEXAGON_S6_rol_i_r_or
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HEXAGON_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Rx32^=rol(Rs32,#u5)
C Intrinsic Prototype: Word32 Q6_R_rolxacc_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_rolxacc_RI(Word32 Rx, Word32 Rs, Word32 Iu5)
-   Instruction Type:      S_2op
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_rolxacc_RI(Word32 Rx, Word32 Rs, Word32
+   Iu5) Instruction Type:      S_2op Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_rolxacc_RI…
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_rolxacc_RI __builtin_HEXAGON_S6_rol_i_r_xacc
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HEXAGON_ARCH__ >= 62
/* ==========================================================================
Assembly Syntax: Rdd32=vabsdiffb(Rtt32,Rss32)
C Intrinsic Prototype: Word64 Q6_P_vabsdiffb_PP(Word64 Rtt, Word64 Rss)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vabsdiffb_PP __builtin_HEXAGON_M6_vabsdiffb
#endif /* __HEXAGON_ARCH___ >= 62 */
#if __HEXAGON_ARCH__ >= 62
/* ==========================================================================
Assembly Syntax: Rdd32=vabsdiffub(Rtt32,Rss32)
C Intrinsic Prototype: Word64 Q6_P_vabsdiffub_PP(Word64 Rtt, Word64 Rss)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vabsdiffub_PP __builtin_HEXAGON_M6_vabsdiffub
#endif /* __HEXAGON_ARCH___ >= 62 */
#if __HEXAGON_ARCH__ >= 62
/* ==========================================================================
Assembly Syntax: Rdd32=vsplatb(Rs32)
C Intrinsic Prototype: Word64 Q6_P_vsplatb_R(Word32 Rs)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vsplatb_R __builtin_HEXAGON_S6_vsplatrbp
#endif /* __HEXAGON_ARCH___ >= 62 */
#if __HEXAGON_ARCH__ >= 62
/* ==========================================================================
Assembly Syntax: Rdd32=vtrunehb(Rss32,Rtt32)
C Intrinsic Prototype: Word64 Q6_P_vtrunehb_PP(Word64 Rss, Word64 Rtt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vtrunehb_PP __builtin_HEXAGON_S6_vtrunehb_ppp
#endif /* __HEXAGON_ARCH___ >= 62 */
#if __HEXAGON_ARCH__ >= 62
/* ==========================================================================
Assembly Syntax: Rdd32=vtrunohb(Rss32,Rtt32)
C Intrinsic Prototype: Word64 Q6_P_vtrunohb_PP(Word64 Rss, Word64 Rtt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vtrunohb_PP __builtin_HEXAGON_S6_vtrunohb_ppp
#endif /* __HEXAGON_ARCH___ >= 62 */
#if __HEXAGON_ARCH__ >= 62
/* ==========================================================================
Assembly Syntax: Vd32=vmem(Rt32):nt
C Intrinsic Prototype: HVX_Vector Q6_V_vmem_R_nt(Word32 Rt)
Instruction Type: MAPPING
Execution Slots: SLOT0123
========================================================================== */
#define Q6_V_vmem_R_nt __builtin_HEXAGON_V6_ldntnt0
#endif /* __HEXAGON_ARCH___ >= 62 */
#if __HEXAGON_ARCH__ >= 65
/* ==========================================================================
Assembly Syntax: Pd4=!any8(vcmpb.eq(Rss32,Rtt32))
C Intrinsic Prototype: Byte Q6_p_not_any8_vcmpb_eq_PP(Word64 Rss, Word64 Rtt)
Instruction Type: ALU64
Execution Slots: SLOT23
========================================================================== */
#define Q6_p_not_any8_vcmpb_eq_PP __builtin_HEXAGON_A6_vcmpbeq_notany
#endif /* __HEXAGON_ARCH___ >= 65 */
#if __HEXAGON_ARCH__ >= 66
/* ==========================================================================
Assembly Syntax: Rdd32=dfadd(Rss32,Rtt32)
C Intrinsic Prototype: Float64 Q6_P_dfadd_PP(Float64 Rss, Float64 Rtt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_dfadd_PP __builtin_HEXAGON_F2_dfadd
#endif /* __HEXAGON_ARCH___ >= 66 */
#if __HEXAGON_ARCH__ >= 66
/* ==========================================================================
Assembly Syntax: Rdd32=dfsub(Rss32,Rtt32)
C Intrinsic Prototype: Float64 Q6_P_dfsub_PP(Float64 Rss, Float64 Rtt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_dfsub_PP __builtin_HEXAGON_F2_dfsub
#endif /* __HEXAGON_ARCH___ >= 66 */
#if __HEXAGON_ARCH__ >= 66
/* ==========================================================================
Assembly Syntax: Rx32-=mpyi(Rs32,Rt32)
C Intrinsic Prototype: Word32 Q6_R_mpyinac_RR(Word32 Rx, Word32 Rs, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_mpyinac_RR(Word32 Rx, Word32 Rs, Word32 Rt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Word32 Q6_R_mpyinac_RR(Word32 Rx, Word32 Rs, Word32
+   Rt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32 Q6_R_mpyinac_RR…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mpyinac_RR __builtin_HEXAGON_M2_mnaci
#endif /* __HEXAGON_ARCH___ >= 66 */
#if __HEXAGON_ARCH__ >= 66
/* ==========================================================================
Assembly Syntax: Rd32=mask(#u5,#U5)
C Intrinsic Prototype: Word32 Q6_R_mask_II(Word32 Iu5, Word32 IU5)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_mask_II __builtin_HEXAGON_S2_mask
#endif /* __HEXAGON_ARCH___ >= 66 */
#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
/* ==========================================================================
Assembly Syntax: Rd32=clip(Rs32,#u5)
C Intrinsic Prototype: Word32 Q6_R_clip_RI(Word32 Rs, Word32 Iu5)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_R_clip_RI __builtin_HEXAGON_A7_clip
#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/
#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
/* ==========================================================================
Assembly Syntax: Rdd32=cround(Rss32,#u6)
C Intrinsic Prototype: Word64 Q6_P_cround_PI(Word64 Rss, Word32 Iu6)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_cround_PI __builtin_HEXAGON_A7_croundd_ri
#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/
#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
/* ==========================================================================
Assembly Syntax: Rdd32=cround(Rss32,Rt32)
C Intrinsic Prototype: Word64 Q6_P_cround_PR(Word64 Rss, Word32 Rt)
Instruction Type: S_3op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_cround_PR __builtin_HEXAGON_A7_croundd_rr
#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/
#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
/* ==========================================================================
Assembly Syntax: Rdd32=vclip(Rss32,#u5)
C Intrinsic Prototype: Word64 Q6_P_vclip_PI(Word64 Rss, Word32 Iu5)
Instruction Type: S_2op
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_vclip_PI __builtin_HEXAGON_A7_vclip
#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/
#if __HEXAGON_ARCH__ >= 67
/* ==========================================================================
Assembly Syntax: Rdd32=dfmax(Rss32,Rtt32)
C Intrinsic Prototype: Float64 Q6_P_dfmax_PP(Float64 Rss, Float64 Rtt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_dfmax_PP __builtin_HEXAGON_F2_dfmax
#endif /* __HEXAGON_ARCH___ >= 67 */
#if __HEXAGON_ARCH__ >= 67
/* ==========================================================================
Assembly Syntax: Rdd32=dfmin(Rss32,Rtt32)
C Intrinsic Prototype: Float64 Q6_P_dfmin_PP(Float64 Rss, Float64 Rtt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_dfmin_PP __builtin_HEXAGON_F2_dfmin
#endif /* __HEXAGON_ARCH___ >= 67 */
#if __HEXAGON_ARCH__ >= 67
/* ==========================================================================
Assembly Syntax: Rdd32=dfmpyfix(Rss32,Rtt32)
C Intrinsic Prototype: Float64 Q6_P_dfmpyfix_PP(Float64 Rss, Float64 Rtt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_dfmpyfix_PP __builtin_HEXAGON_F2_dfmpyfix
#endif /* __HEXAGON_ARCH___ >= 67 */
#if __HEXAGON_ARCH__ >= 67
/* ==========================================================================
Assembly Syntax: Rxx32+=dfmpyhh(Rss32,Rtt32)
C Intrinsic Prototype: Float64 Q6_P_dfmpyhhacc_PP(Float64 Rxx, Float64 Rss, Float64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Float64 Q6_P_dfmpyhhacc_PP(Float64 Rxx, Float64 Rss, Float64 Rtt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Float64 Q6_P_dfmpyhhacc_PP(Float64 Rxx, Float64 Rss,
+   Float64 Rtt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Float64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_dfmpyhhacc_PP __builtin_HEXAGON_F2_dfmpyhh
#endif /* __HEXAGON_ARCH___ >= 67 */
#if __HEXAGON_ARCH__ >= 67
/* ==========================================================================
Assembly Syntax: Rxx32+=dfmpylh(Rss32,Rtt32)
C Intrinsic Prototype: Float64 Q6_P_dfmpylhacc_PP(Float64 Rxx, Float64 Rss, Float64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Float64 Q6_P_dfmpylhacc_PP(Float64 Rxx, Float64 Rss, Float64 Rtt)
-   Instruction Type:      M
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: Float64 Q6_P_dfmpylhacc_PP(Float64 Rxx, Float64 Rss,
+   Float64 Rtt) Instruction Type:      M Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Float64…
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_dfmpylhacc_PP __builtin_HEXAGON_F2_dfmpylh
#endif /* __HEXAGON_ARCH___ >= 67 */
#if __HEXAGON_ARCH__ >= 67
/* ==========================================================================
Assembly Syntax: Rdd32=dfmpyll(Rss32,Rtt32)
C Intrinsic Prototype: Float64 Q6_P_dfmpyll_PP(Float64 Rss, Float64 Rtt)
Instruction Type: M
Execution Slots: SLOT23
========================================================================== */
#define Q6_P_dfmpyll_PP __builtin_HEXAGON_F2_dfmpyll
#endif /* __HEXAGON_ARCH___ >= 67 */
#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
/* ==========================================================================
Assembly Syntax: Rdd32=cmpyiw(Rss32,Rtt32)
C Intrinsic Prototype: Word64 Q6_P_cmpyiw_PP(Word64 Rss, Word64 Rtt)
Instruction Type: M
Execution Slots: SLOT3
========================================================================== */
#define Q6_P_cmpyiw_PP __builtin_HEXAGON_M7_dcmpyiw
#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/
#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
/* ==========================================================================
Assembly Syntax: Rxx32+=cmpyiw(Rss32,Rtt32)
C Intrinsic Prototype: Word64 Q6_P_cmpyiwacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_cmpyiwacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
-   Instruction Type:      M
-   Execution Slots:       SLOT3
+   C Intrinsic Prototype: Word64 Q6_P_cmpyiwacc_PP(Word64 Rxx, Word64 Rss,
+   Word64 Rtt) Instruction Type:      M Execution Slots:       SLOT3
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_cmpyiwacc_PP…
Instruction Type: M
Execution Slots: SLOT3
========================================================================== */
#define Q6_P_cmpyiwacc_PP __builtin_HEXAGON_M7_dcmpyiw_acc
#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/
#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
/* ==========================================================================
Assembly Syntax: Rdd32=cmpyiw(Rss32,Rtt32*)
C Intrinsic Prototype: Word64 Q6_P_cmpyiw_PP_conj(Word64 Rss, Word64 Rtt)
Instruction Type: M
Execution Slots: SLOT3
========================================================================== */
#define Q6_P_cmpyiw_PP_conj __builtin_HEXAGON_M7_dcmpyiwc
#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/
#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
/* ==========================================================================
Assembly Syntax: Rxx32+=cmpyiw(Rss32,Rtt32*)
C Intrinsic Prototype: Word64 Q6_P_cmpyiwacc_PP_conj(Word64 Rxx, Word64 Rss, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_cmpyiwacc_PP_conj(Word64 Rxx, Word64 Rss, Word64 Rtt)
-   Instruction Type:      M
-   Execution Slots:       SLOT3
+   C Intrinsic Prototype: Word64 Q6_P_cmpyiwacc_PP_conj(Word64 Rxx, Word64 Rss,
+   Word64 Rtt) Instruction Type:      M Execution Slots:       SLOT3
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT3
========================================================================== */
#define Q6_P_cmpyiwacc_PP_conj __builtin_HEXAGON_M7_dcmpyiwc_acc
#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/
#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
/* ==========================================================================
Assembly Syntax: Rdd32=cmpyrw(Rss32,Rtt32)
C Intrinsic Prototype: Word64 Q6_P_cmpyrw_PP(Word64 Rss, Word64 Rtt)
Instruction Type: M
Execution Slots: SLOT3
========================================================================== */
#define Q6_P_cmpyrw_PP __builtin_HEXAGON_M7_dcmpyrw
#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/
#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
/* ==========================================================================
Assembly Syntax: Rxx32+=cmpyrw(Rss32,Rtt32)
C Intrinsic Prototype: Word64 Q6_P_cmpyrwacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_cmpyrwacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
-   Instruction Type:      M
-   Execution Slots:       SLOT3
+   C Intrinsic Prototype: Word64 Q6_P_cmpyrwacc_PP(Word64 Rxx, Word64 Rss,
+   Word64 Rtt) Instruction Type:      M Execution Slots:       SLOT3
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_cmpyrwacc_PP…
Instruction Type: M
Execution Slots: SLOT3
========================================================================== */
#define Q6_P_cmpyrwacc_PP __builtin_HEXAGON_M7_dcmpyrw_acc
#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/
#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
/* ==========================================================================
Assembly Syntax: Rdd32=cmpyrw(Rss32,Rtt32*)
C Intrinsic Prototype: Word64 Q6_P_cmpyrw_PP_conj(Word64 Rss, Word64 Rtt)
Instruction Type: M
Execution Slots: SLOT3
========================================================================== */
#define Q6_P_cmpyrw_PP_conj __builtin_HEXAGON_M7_dcmpyrwc
#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/
#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
/* ==========================================================================
Assembly Syntax: Rxx32+=cmpyrw(Rss32,Rtt32*)
C Intrinsic Prototype: Word64 Q6_P_cmpyrwacc_PP_conj(Word64 Rxx, Word64 Rss, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_cmpyrwacc_PP_conj(Word64 Rxx, Word64 Rss, Word64 Rtt)
-   Instruction Type:      M
-   Execution Slots:       SLOT3
+   C Intrinsic Prototype: Word64 Q6_P_cmpyrwacc_PP_conj(Word64 Rxx, Word64 Rss,
+   Word64 Rtt) Instruction Type:      M Execution Slots:       SLOT3
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64…
Instruction Type: M
Execution Slots: SLOT3
========================================================================== */
#define Q6_P_cmpyrwacc_PP_conj __builtin_HEXAGON_M7_dcmpyrwc_acc
#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/
#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
/* ==========================================================================
Assembly Syntax: Rdd32=vdmpyw(Rss32,Rtt32)
C Intrinsic Prototype: Word64 Q6_P_vdmpyw_PP(Word64 Rss, Word64 Rtt)
Instruction Type: M
Execution Slots: SLOT3
========================================================================== */
#define Q6_P_vdmpyw_PP __builtin_HEXAGON_M7_vdmpy
#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/
#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
/* ==========================================================================
Assembly Syntax: Rxx32+=vdmpyw(Rss32,Rtt32)
C Intrinsic Prototype: Word64 Q6_P_vdmpywacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word64 Q6_P_vdmpywacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt)
-   Instruction Type:      M
-   Execution Slots:       SLOT3
+   C Intrinsic Prototype: Word64 Q6_P_vdmpywacc_PP(Word64 Rxx, Word64 Rss,
+   Word64 Rtt) Instruction Type:      M Execution Slots:       SLOT3
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word64 Q6_P_vdmpywacc_PP…
Instruction Type: M
Execution Slots: SLOT3
========================================================================== */
#define Q6_P_vdmpywacc_PP __builtin_HEXAGON_M7_vdmpy_acc
#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/
#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
/* ==========================================================================
Assembly Syntax: Rd32=cmpyiw(Rss32,Rtt32):<<1:sat
C Intrinsic Prototype: Word32 Q6_R_cmpyiw_PP_s1_sat(Word64 Rss, Word64 Rtt)
Instruction Type: M
Execution Slots: SLOT3
========================================================================== */
#define Q6_R_cmpyiw_PP_s1_sat __builtin_HEXAGON_M7_wcmpyiw
#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/
#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
/* ==========================================================================
Assembly Syntax: Rd32=cmpyiw(Rss32,Rtt32):<<1:rnd:sat
C Intrinsic Prototype: Word32 Q6_R_cmpyiw_PP_s1_rnd_sat(Word64 Rss, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_cmpyiw_PP_s1_rnd_sat(Word64 Rss, Word64 Rtt)
-   Instruction Type:      M
-   Execution Slots:       SLOT3
+   C Intrinsic Prototype: Word32 Q6_R_cmpyiw_PP_s1_rnd_sat(Word64 Rss, Word64
+   Rtt) Instruction Type:      M Execution Slots:       SLOT3
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32…
Instruction Type: M
Execution Slots: SLOT3
========================================================================== */
#define Q6_R_cmpyiw_PP_s1_rnd_sat __builtin_HEXAGON_M7_wcmpyiw_rnd
#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/
#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
/* ==========================================================================
Assembly Syntax: Rd32=cmpyiw(Rss32,Rtt32*):<<1:sat
C Intrinsic Prototype: Word32 Q6_R_cmpyiw_PP_conj_s1_sat(Word64 Rss, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_cmpyiw_PP_conj_s1_sat(Word64 Rss, Word64 Rtt)
-   Instruction Type:      M
-   Execution Slots:       SLOT3
+   C Intrinsic Prototype: Word32 Q6_R_cmpyiw_PP_conj_s1_sat(Word64 Rss, Word64
+   Rtt) Instruction Type:      M Execution Slots:       SLOT3
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32…
Instruction Type: M
Execution Slots: SLOT3
========================================================================== */
#define Q6_R_cmpyiw_PP_conj_s1_sat __builtin_HEXAGON_M7_wcmpyiwc
#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/
#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
/* ==========================================================================
Assembly Syntax: Rd32=cmpyiw(Rss32,Rtt32*):<<1:rnd:sat
C Intrinsic Prototype: Word32 Q6_R_cmpyiw_PP_conj_s1_rnd_sat(Word64 Rss, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_cmpyiw_PP_conj_s1_rnd_sat(Word64 Rss, Word64 Rtt)
-   Instruction Type:      M
-   Execution Slots:       SLOT3
+   C Intrinsic Prototype: Word32 Q6_R_cmpyiw_PP_conj_s1_rnd_sat(Word64 Rss,
+   Word64 Rtt) Instruction Type:      M Execution Slots:       SLOT3
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32…
Instruction Type: M
Execution Slots: SLOT3
========================================================================== */
#define Q6_R_cmpyiw_PP_conj_s1_rnd_sat __builtin_HEXAGON_M7_wcmpyiwc_rnd
#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/
#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
/* ==========================================================================
Assembly Syntax: Rd32=cmpyrw(Rss32,Rtt32):<<1:sat
C Intrinsic Prototype: Word32 Q6_R_cmpyrw_PP_s1_sat(Word64 Rss, Word64 Rtt)
Instruction Type: M
Execution Slots: SLOT3
========================================================================== */
#define Q6_R_cmpyrw_PP_s1_sat __builtin_HEXAGON_M7_wcmpyrw
#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/
#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
/* ==========================================================================
Assembly Syntax: Rd32=cmpyrw(Rss32,Rtt32):<<1:rnd:sat
C Intrinsic Prototype: Word32 Q6_R_cmpyrw_PP_s1_rnd_sat(Word64 Rss, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_cmpyrw_PP_s1_rnd_sat(Word64 Rss, Word64 Rtt)
-   Instruction Type:      M
-   Execution Slots:       SLOT3
+   C Intrinsic Prototype: Word32 Q6_R_cmpyrw_PP_s1_rnd_sat(Word64 Rss, Word64
+   Rtt) Instruction Type:      M Execution Slots:       SLOT3
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32…
Instruction Type: M
Execution Slots: SLOT3
========================================================================== */
#define Q6_R_cmpyrw_PP_s1_rnd_sat __builtin_HEXAGON_M7_wcmpyrw_rnd
#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/
#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
/* ==========================================================================
Assembly Syntax: Rd32=cmpyrw(Rss32,Rtt32*):<<1:sat
C Intrinsic Prototype: Word32 Q6_R_cmpyrw_PP_conj_s1_sat(Word64 Rss, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_cmpyrw_PP_conj_s1_sat(Word64 Rss, Word64 Rtt)
-   Instruction Type:      M
-   Execution Slots:       SLOT3
+   C Intrinsic Prototype: Word32 Q6_R_cmpyrw_PP_conj_s1_sat(Word64 Rss, Word64
+   Rtt) Instruction Type:      M Execution Slots:       SLOT3
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32…
Instruction Type: M
Execution Slots: SLOT3
========================================================================== */
#define Q6_R_cmpyrw_PP_conj_s1_sat __builtin_HEXAGON_M7_wcmpyrwc
#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/
#if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__
/* ==========================================================================
Assembly Syntax: Rd32=cmpyrw(Rss32,Rtt32*):<<1:rnd:sat
C Intrinsic Prototype: Word32 Q6_R_cmpyrw_PP_conj_s1_rnd_sat(Word64 Rss, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: Word32 Q6_R_cmpyrw_PP_conj_s1_rnd_sat(Word64 Rss, Word64 Rtt)
-   Instruction Type:      M
-   Execution Slots:       SLOT3
+   C Intrinsic Prototype: Word32 Q6_R_cmpyrw_PP_conj_s1_rnd_sat(Word64 Rss,
+   Word64 Rtt) Instruction Type:      M Execution Slots:       SLOT3
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: Word32…
Instruction Type: M
Execution Slots: SLOT3
========================================================================== */
#define Q6_R_cmpyrw_PP_conj_s1_rnd_sat __builtin_HEXAGON_M7_wcmpyrwc_rnd
#endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/
#if __HEXAGON_ARCH__ >= 68
/* ==========================================================================
Assembly Syntax: dmlink(Rs32,Rt32)
C Intrinsic Prototype: void Q6_dmlink_AA(Address Rs, Address Rt)
Instruction Type: ST
Execution Slots: SLOT0
========================================================================== */
#define Q6_dmlink_AA __builtin_HEXAGON_Y6_dmlink
#endif /* __HEXAGON_ARCH___ >= 68 */
#if __HEXAGON_ARCH__ >= 68
/* ==========================================================================
Assembly Syntax: Rd32=dmpause
C Intrinsic Prototype: Word32 Q6_R_dmpause()
Instruction Type: ST
Execution Slots: SLOT0
========================================================================== */
#define Q6_R_dmpause __builtin_HEXAGON_Y6_dmpause
#endif /* __HEXAGON_ARCH___ >= 68 */
#if __HEXAGON_ARCH__ >= 68
/* ==========================================================================
Assembly Syntax: Rd32=dmpoll
C Intrinsic Prototype: Word32 Q6_R_dmpoll()
Instruction Type: ST
Execution Slots: SLOT0
========================================================================== */
#define Q6_R_dmpoll __builtin_HEXAGON_Y6_dmpoll
#endif /* __HEXAGON_ARCH___ >= 68 */
#if __HEXAGON_ARCH__ >= 68
/* ==========================================================================
Assembly Syntax: dmresume(Rs32)
C Intrinsic Prototype: void Q6_dmresume_A(Address Rs)
Instruction Type: ST
Execution Slots: SLOT0
========================================================================== */
#define Q6_dmresume_A __builtin_HEXAGON_Y6_dmresume
#endif /* __HEXAGON_ARCH___ >= 68 */
#if __HEXAGON_ARCH__ >= 68
/* ==========================================================================
Assembly Syntax: dmstart(Rs32)
C Intrinsic Prototype: void Q6_dmstart_A(Address Rs)
Instruction Type: ST
Execution Slots: SLOT0
========================================================================== */
#define Q6_dmstart_A __builtin_HEXAGON_Y6_dmstart
#endif /* __HEXAGON_ARCH___ >= 68 */
#if __HEXAGON_ARCH__ >= 68
/* ==========================================================================
Assembly Syntax: Rd32=dmwait
C Intrinsic Prototype: Word32 Q6_R_dmwait()
Instruction Type: ST
Execution Slots: SLOT0
========================================================================== */
#define Q6_R_dmwait __builtin_HEXAGON_Y6_dmwait
#endif /* __HEXAGON_ARCH___ >= 68 */
#include <hexagon_circ_brev_intrinsics.h>
Lint: Pre-merge checks
Inline Actions

clang-tidy: error: 'hexagon_circ_brev_intrinsics.h' file not found with <angled> include; use "quotes" instead [clang-diagnostic-error]
not useful
clang-tidy: error: 'hexagon_circ_brev_intrinsics.h' file not found with <angled> include; use "quotes" instead [clang-diagnostic-error]
not useful
clang-tidy: error: 'hexagon_circ_brev_intrinsics.h' file not found with <angled> include; use "quotes" instead [clang-diagnostic-error]
not useful

Lint: Pre-merge checks: clang-tidy: error: 'hexagon_circ_brev_intrinsics.h' file not found with <angled> include; use…
#ifdef __HVX__
#include <hvx_hexagon_protos.h>
#endif /* __HVX__ */
#endif

clang/lib/Headers/hexagon_types.h

  • This file was added.
/******************************************************************************/
/* (c) 2020 Qualcomm Innovation Center, Inc. All rights reserved. */
/* */
/******************************************************************************/
#ifndef HEXAGON_TYPES_H
Lint: Pre-merge checks
Inline Actions

clang-tidy: warning: header guard does not follow preferred style [llvm-header-guard]
not useful

Lint: Pre-merge checks: clang-tidy: warning: header guard does not follow preferred style [llvm-header-guard] [[https…
#define HEXAGON_TYPES_H
#include <hexagon_protos.h>
Lint: Pre-merge checks
Inline Actions

clang-tidy: error: 'hexagon_protos.h' file not found with <angled> include; use "quotes" instead [clang-diagnostic-error]
not useful

Lint: Pre-merge checks: clang-tidy: error: 'hexagon_protos.h' file not found with <angled> include; use "quotes"…
/* Hexagon names */
#define HEXAGON_Vect HEXAGON_Vect64
#define HEXAGON_V_GET_D HEXAGON_V64_GET_D
#define HEXAGON_V_GET_UD HEXAGON_V64_GET_UD
#define HEXAGON_V_GET_W0 HEXAGON_V64_GET_W0
#define HEXAGON_V_GET_W1 HEXAGON_V64_GET_W1
#define HEXAGON_V_GET_UW0 HEXAGON_V64_GET_UW0
#define HEXAGON_V_GET_UW1 HEXAGON_V64_GET_UW1
#define HEXAGON_V_GET_H0 HEXAGON_V64_GET_H0
#define HEXAGON_V_GET_H1 HEXAGON_V64_GET_H1
#define HEXAGON_V_GET_H2 HEXAGON_V64_GET_H2
#define HEXAGON_V_GET_H3 HEXAGON_V64_GET_H3
#define HEXAGON_V_GET_UH0 HEXAGON_V64_GET_UH0
#define HEXAGON_V_GET_UH1 HEXAGON_V64_GET_UH1
#define HEXAGON_V_GET_UH2 HEXAGON_V64_GET_UH2
#define HEXAGON_V_GET_UH3 HEXAGON_V64_GET_UH3
#define HEXAGON_V_GET_B0 HEXAGON_V64_GET_B0
#define HEXAGON_V_GET_B1 HEXAGON_V64_GET_B1
#define HEXAGON_V_GET_B2 HEXAGON_V64_GET_B2
#define HEXAGON_V_GET_B3 HEXAGON_V64_GET_B3
#define HEXAGON_V_GET_B4 HEXAGON_V64_GET_B4
#define HEXAGON_V_GET_B5 HEXAGON_V64_GET_B5
#define HEXAGON_V_GET_B6 HEXAGON_V64_GET_B6
#define HEXAGON_V_GET_B7 HEXAGON_V64_GET_B7
#define HEXAGON_V_GET_UB0 HEXAGON_V64_GET_UB0
#define HEXAGON_V_GET_UB1 HEXAGON_V64_GET_UB1
#define HEXAGON_V_GET_UB2 HEXAGON_V64_GET_UB2
#define HEXAGON_V_GET_UB3 HEXAGON_V64_GET_UB3
#define HEXAGON_V_GET_UB4 HEXAGON_V64_GET_UB4
#define HEXAGON_V_GET_UB5 HEXAGON_V64_GET_UB5
#define HEXAGON_V_GET_UB6 HEXAGON_V64_GET_UB6
#define HEXAGON_V_GET_UB7 HEXAGON_V64_GET_UB7
#define HEXAGON_V_PUT_D HEXAGON_V64_PUT_D
#define HEXAGON_V_PUT_W0 HEXAGON_V64_PUT_W0
#define HEXAGON_V_PUT_W1 HEXAGON_V64_PUT_W1
#define HEXAGON_V_PUT_H0 HEXAGON_V64_PUT_H0
#define HEXAGON_V_PUT_H1 HEXAGON_V64_PUT_H1
#define HEXAGON_V_PUT_H2 HEXAGON_V64_PUT_H2
#define HEXAGON_V_PUT_H3 HEXAGON_V64_PUT_H3
#define HEXAGON_V_PUT_B0 HEXAGON_V64_PUT_B0
#define HEXAGON_V_PUT_B1 HEXAGON_V64_PUT_B1
#define HEXAGON_V_PUT_B2 HEXAGON_V64_PUT_B2
#define HEXAGON_V_PUT_B3 HEXAGON_V64_PUT_B3
#define HEXAGON_V_PUT_B4 HEXAGON_V64_PUT_B4
#define HEXAGON_V_PUT_B5 HEXAGON_V64_PUT_B5
#define HEXAGON_V_PUT_B6 HEXAGON_V64_PUT_B6
#define HEXAGON_V_PUT_B7 HEXAGON_V64_PUT_B7
#define HEXAGON_V_CREATE_D HEXAGON_V64_CREATE_D
#define HEXAGON_V_CREATE_W HEXAGON_V64_CREATE_W
#define HEXAGON_V_CREATE_H HEXAGON_V64_CREATE_H
#define HEXAGON_V_CREATE_B HEXAGON_V64_CREATE_B
#ifdef __cplusplus
#define HEXAGON_VectC HEXAGON_Vect64C
#endif /* __cplusplus */
/* 64 Bit Vectors */
typedef long long __attribute__((__may_alias__)) HEXAGON_Vect64;
/* Extract doubleword macros */
#define HEXAGON_V64_GET_D(v) (v)
#define HEXAGON_V64_GET_UD(v) ((unsigned long long)(v))
/* Extract word macros */
#define HEXAGON_V64_GET_W0(v) \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define HEXAGON_V64_GET_W0(v)                                                        \
+#define HEXAGON_V64_GET_W0(v)                                                  \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V64_GET_W0(v)…
__extension__({ \
union { \
long long d; \
int w[2]; \
} _HEXAGON_V64_internal_union; \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    } _HEXAGON_V64_internal_union;                                                   \
-    _HEXAGON_V64_internal_union.d = (v);                                             \
-    _HEXAGON_V64_internal_union.w[0];                                                \
+    } _HEXAGON_V64_internal_union;                                             \
+    _HEXAGON_V64_internal_union.d = (v);                                       \
+    _HEXAGON_V64_internal_union.w[0];                                          \
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V64_internal_union…
_HEXAGON_V64_internal_union.d = (v); \
_HEXAGON_V64_internal_union.w[0]; \
})
#define HEXAGON_V64_GET_W1(v) \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define HEXAGON_V64_GET_W1(v)                                                        \
+#define HEXAGON_V64_GET_W1(v)                                                  \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V64_GET_W1(v)…
__extension__({ \
union { \
long long d; \
int w[2]; \
} _HEXAGON_V64_internal_union; \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    } _HEXAGON_V64_internal_union;                                                   \
-    _HEXAGON_V64_internal_union.d = (v);                                             \
-    _HEXAGON_V64_internal_union.w[1];                                                \
+    } _HEXAGON_V64_internal_union;                                             \
+    _HEXAGON_V64_internal_union.d = (v);                                       \
+    _HEXAGON_V64_internal_union.w[1];                                          \
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V64_internal_union…
_HEXAGON_V64_internal_union.d = (v); \
_HEXAGON_V64_internal_union.w[1]; \
})
#define HEXAGON_V64_GET_UW0(v) \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define HEXAGON_V64_GET_UW0(v)                                                       \
+#define HEXAGON_V64_GET_UW0(v)                                                 \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V64_GET_UW0(v)…
__extension__({ \
union { \
long long d; \
unsigned int uw[2]; \
} _HEXAGON_V64_internal_union; \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    } _HEXAGON_V64_internal_union;                                                   \
-    _HEXAGON_V64_internal_union.d = (v);                                             \
-    _HEXAGON_V64_internal_union.uw[0];                                               \
+    } _HEXAGON_V64_internal_union;                                             \
+    _HEXAGON_V64_internal_union.d = (v);                                       \
+    _HEXAGON_V64_internal_union.uw[0];                                         \
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V64_internal_union…
_HEXAGON_V64_internal_union.d = (v); \
_HEXAGON_V64_internal_union.uw[0]; \
})
#define HEXAGON_V64_GET_UW1(v) \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define HEXAGON_V64_GET_UW1(v)                                                       \
+#define HEXAGON_V64_GET_UW1(v)                                                 \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V64_GET_UW1(v)…
__extension__({ \
union { \
long long d; \
unsigned int uw[2]; \
} _HEXAGON_V64_internal_union; \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    } _HEXAGON_V64_internal_union;                                                   \
-    _HEXAGON_V64_internal_union.d = (v);                                             \
-    _HEXAGON_V64_internal_union.uw[1];                                               \
+    } _HEXAGON_V64_internal_union;                                             \
+    _HEXAGON_V64_internal_union.d = (v);                                       \
+    _HEXAGON_V64_internal_union.uw[1];                                         \
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V64_internal_union…
_HEXAGON_V64_internal_union.d = (v); \
_HEXAGON_V64_internal_union.uw[1]; \
})
/* Extract half word macros */
#define HEXAGON_V64_GET_H0(v) \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define HEXAGON_V64_GET_H0(v)                                                        \
+#define HEXAGON_V64_GET_H0(v)                                                  \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V64_GET_H0(v)…
__extension__({ \
union { \
long long d; \
short h[4]; \
} _HEXAGON_V64_internal_union; \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    } _HEXAGON_V64_internal_union;                                                   \
-    _HEXAGON_V64_internal_union.d = (v);                                             \
-    _HEXAGON_V64_internal_union.h[0];                                                \
+    } _HEXAGON_V64_internal_union;                                             \
+    _HEXAGON_V64_internal_union.d = (v);                                       \
+    _HEXAGON_V64_internal_union.h[0];                                          \
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V64_internal_union…
_HEXAGON_V64_internal_union.d = (v); \
_HEXAGON_V64_internal_union.h[0]; \
})
#define HEXAGON_V64_GET_H1(v) \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define HEXAGON_V64_GET_H1(v)                                                        \
+#define HEXAGON_V64_GET_H1(v)                                                  \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V64_GET_H1(v)…
__extension__({ \
union { \
long long d; \
short h[4]; \
} _HEXAGON_V64_internal_union; \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    } _HEXAGON_V64_internal_union;                                                   \
-    _HEXAGON_V64_internal_union.d = (v);                                             \
-    _HEXAGON_V64_internal_union.h[1];                                                \
+    } _HEXAGON_V64_internal_union;                                             \
+    _HEXAGON_V64_internal_union.d = (v);                                       \
+    _HEXAGON_V64_internal_union.h[1];                                          \
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V64_internal_union…
_HEXAGON_V64_internal_union.d = (v); \
_HEXAGON_V64_internal_union.h[1]; \
})
#define HEXAGON_V64_GET_H2(v) \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define HEXAGON_V64_GET_H2(v)                                                        \
+#define HEXAGON_V64_GET_H2(v)                                                  \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V64_GET_H2(v)…
__extension__({ \
union { \
long long d; \
short h[4]; \
} _HEXAGON_V64_internal_union; \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    } _HEXAGON_V64_internal_union;                                                   \
-    _HEXAGON_V64_internal_union.d = (v);                                             \
-    _HEXAGON_V64_internal_union.h[2];                                                \
+    } _HEXAGON_V64_internal_union;                                             \
+    _HEXAGON_V64_internal_union.d = (v);                                       \
+    _HEXAGON_V64_internal_union.h[2];                                          \
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V64_internal_union…
_HEXAGON_V64_internal_union.d = (v); \
_HEXAGON_V64_internal_union.h[2]; \
})
#define HEXAGON_V64_GET_H3(v) \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define HEXAGON_V64_GET_H3(v)                                                        \
+#define HEXAGON_V64_GET_H3(v)                                                  \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V64_GET_H3(v)…
__extension__({ \
union { \
long long d; \
short h[4]; \
} _HEXAGON_V64_internal_union; \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    } _HEXAGON_V64_internal_union;                                                   \
-    _HEXAGON_V64_internal_union.d = (v);                                             \
-    _HEXAGON_V64_internal_union.h[3];                                                \
+    } _HEXAGON_V64_internal_union;                                             \
+    _HEXAGON_V64_internal_union.d = (v);                                       \
+    _HEXAGON_V64_internal_union.h[3];                                          \
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V64_internal_union…
_HEXAGON_V64_internal_union.d = (v); \
_HEXAGON_V64_internal_union.h[3]; \
})
#define HEXAGON_V64_GET_UH0(v) \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define HEXAGON_V64_GET_UH0(v)                                                       \
+#define HEXAGON_V64_GET_UH0(v)                                                 \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V64_GET_UH0(v)…
__extension__({ \
union { \
long long d; \
unsigned short uh[4]; \
} _HEXAGON_V64_internal_union; \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    } _HEXAGON_V64_internal_union;                                                   \
-    _HEXAGON_V64_internal_union.d = (v);                                             \
-    _HEXAGON_V64_internal_union.uh[0];                                               \
+    } _HEXAGON_V64_internal_union;                                             \
+    _HEXAGON_V64_internal_union.d = (v);                                       \
+    _HEXAGON_V64_internal_union.uh[0];                                         \
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V64_internal_union…
_HEXAGON_V64_internal_union.d = (v); \
_HEXAGON_V64_internal_union.uh[0]; \
})
#define HEXAGON_V64_GET_UH1(v) \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define HEXAGON_V64_GET_UH1(v)                                                       \
+#define HEXAGON_V64_GET_UH1(v)                                                 \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V64_GET_UH1(v)…
__extension__({ \
union { \
long long d; \
unsigned short uh[4]; \
} _HEXAGON_V64_internal_union; \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    } _HEXAGON_V64_internal_union;                                                   \
-    _HEXAGON_V64_internal_union.d = (v);                                             \
-    _HEXAGON_V64_internal_union.uh[1];                                               \
+    } _HEXAGON_V64_internal_union;                                             \
+    _HEXAGON_V64_internal_union.d = (v);                                       \
+    _HEXAGON_V64_internal_union.uh[1];                                         \
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V64_internal_union…
_HEXAGON_V64_internal_union.d = (v); \
_HEXAGON_V64_internal_union.uh[1]; \
})
#define HEXAGON_V64_GET_UH2(v) \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define HEXAGON_V64_GET_UH2(v)                                                       \
+#define HEXAGON_V64_GET_UH2(v)                                                 \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V64_GET_UH2(v)…
__extension__({ \
union { \
long long d; \
unsigned short uh[4]; \
} _HEXAGON_V64_internal_union; \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    } _HEXAGON_V64_internal_union;                                                   \
-    _HEXAGON_V64_internal_union.d = (v);                                             \
-    _HEXAGON_V64_internal_union.uh[2];                                               \
+    } _HEXAGON_V64_internal_union;                                             \
+    _HEXAGON_V64_internal_union.d = (v);                                       \
+    _HEXAGON_V64_internal_union.uh[2];                                         \
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V64_internal_union…
_HEXAGON_V64_internal_union.d = (v); \
_HEXAGON_V64_internal_union.uh[2]; \
})
#define HEXAGON_V64_GET_UH3(v) \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define HEXAGON_V64_GET_UH3(v)                                                       \
+#define HEXAGON_V64_GET_UH3(v)                                                 \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V64_GET_UH3(v)…
__extension__({ \
union { \
long long d; \
unsigned short uh[4]; \
} _HEXAGON_V64_internal_union; \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    } _HEXAGON_V64_internal_union;                                                   \
-    _HEXAGON_V64_internal_union.d = (v);                                             \
-    _HEXAGON_V64_internal_union.uh[3];                                               \
+    } _HEXAGON_V64_internal_union;                                             \
+    _HEXAGON_V64_internal_union.d = (v);                                       \
+    _HEXAGON_V64_internal_union.uh[3];                                         \
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V64_internal_union…
_HEXAGON_V64_internal_union.d = (v); \
_HEXAGON_V64_internal_union.uh[3]; \
})
/* Extract byte macros */
#define HEXAGON_V64_GET_B0(v) \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define HEXAGON_V64_GET_B0(v)                                                        \
+#define HEXAGON_V64_GET_B0(v)                                                  \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V64_GET_B0(v)…
__extension__({ \
union { \
long long d; \
signed char b[8]; \
} _HEXAGON_V64_internal_union; \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    } _HEXAGON_V64_internal_union;                                                   \
-    _HEXAGON_V64_internal_union.d = (v);                                             \
-    _HEXAGON_V64_internal_union.b[0];                                                \
+    } _HEXAGON_V64_internal_union;                                             \
+    _HEXAGON_V64_internal_union.d = (v);                                       \
+    _HEXAGON_V64_internal_union.b[0];                                          \
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V64_internal_union…
_HEXAGON_V64_internal_union.d = (v); \
_HEXAGON_V64_internal_union.b[0]; \
})
#define HEXAGON_V64_GET_B1(v) \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define HEXAGON_V64_GET_B1(v)                                                        \
+#define HEXAGON_V64_GET_B1(v)                                                  \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V64_GET_B1(v)…
__extension__({ \
union { \
long long d; \
signed char b[8]; \
} _HEXAGON_V64_internal_union; \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    } _HEXAGON_V64_internal_union;                                                   \
-    _HEXAGON_V64_internal_union.d = (v);                                             \
-    _HEXAGON_V64_internal_union.b[1];                                                \
+    } _HEXAGON_V64_internal_union;                                             \
+    _HEXAGON_V64_internal_union.d = (v);                                       \
+    _HEXAGON_V64_internal_union.b[1];                                          \
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V64_internal_union…
_HEXAGON_V64_internal_union.d = (v); \
_HEXAGON_V64_internal_union.b[1]; \
})
#define HEXAGON_V64_GET_B2(v) \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define HEXAGON_V64_GET_B2(v)                                                        \
+#define HEXAGON_V64_GET_B2(v)                                                  \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V64_GET_B2(v)…
__extension__({ \
union { \
long long d; \
signed char b[8]; \
} _HEXAGON_V64_internal_union; \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    } _HEXAGON_V64_internal_union;                                                   \
-    _HEXAGON_V64_internal_union.d = (v);                                             \
-    _HEXAGON_V64_internal_union.b[2];                                                \
+    } _HEXAGON_V64_internal_union;                                             \
+    _HEXAGON_V64_internal_union.d = (v);                                       \
+    _HEXAGON_V64_internal_union.b[2];                                          \
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V64_internal_union…
_HEXAGON_V64_internal_union.d = (v); \
_HEXAGON_V64_internal_union.b[2]; \
})
#define HEXAGON_V64_GET_B3(v) \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define HEXAGON_V64_GET_B3(v)                                                        \
+#define HEXAGON_V64_GET_B3(v)                                                  \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V64_GET_B3(v)…
__extension__({ \
union { \
long long d; \
signed char b[8]; \
} _HEXAGON_V64_internal_union; \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    } _HEXAGON_V64_internal_union;                                                   \
-    _HEXAGON_V64_internal_union.d = (v);                                             \
-    _HEXAGON_V64_internal_union.b[3];                                                \
+    } _HEXAGON_V64_internal_union;                                             \
+    _HEXAGON_V64_internal_union.d = (v);                                       \
+    _HEXAGON_V64_internal_union.b[3];                                          \
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V64_internal_union…
_HEXAGON_V64_internal_union.d = (v); \
_HEXAGON_V64_internal_union.b[3]; \
})
#define HEXAGON_V64_GET_B4(v) \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define HEXAGON_V64_GET_B4(v)                                                        \
+#define HEXAGON_V64_GET_B4(v)                                                  \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V64_GET_B4(v)…
__extension__({ \
union { \
long long d; \
signed char b[8]; \
} _HEXAGON_V64_internal_union; \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    } _HEXAGON_V64_internal_union;                                                   \
-    _HEXAGON_V64_internal_union.d = (v);                                             \
-    _HEXAGON_V64_internal_union.b[4];                                                \
+    } _HEXAGON_V64_internal_union;                                             \
+    _HEXAGON_V64_internal_union.d = (v);                                       \
+    _HEXAGON_V64_internal_union.b[4];                                          \
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V64_internal_union…
_HEXAGON_V64_internal_union.d = (v); \
_HEXAGON_V64_internal_union.b[4]; \
})
#define HEXAGON_V64_GET_B5(v) \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define HEXAGON_V64_GET_B5(v)                                                        \
+#define HEXAGON_V64_GET_B5(v)                                                  \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V64_GET_B5(v)…
__extension__({ \
union { \
long long d; \
signed char b[8]; \
} _HEXAGON_V64_internal_union; \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    } _HEXAGON_V64_internal_union;                                                   \
-    _HEXAGON_V64_internal_union.d = (v);                                             \
-    _HEXAGON_V64_internal_union.b[5];                                                \
+    } _HEXAGON_V64_internal_union;                                             \
+    _HEXAGON_V64_internal_union.d = (v);                                       \
+    _HEXAGON_V64_internal_union.b[5];                                          \
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V64_internal_union…
_HEXAGON_V64_internal_union.d = (v); \
_HEXAGON_V64_internal_union.b[5]; \
})
#define HEXAGON_V64_GET_B6(v) \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define HEXAGON_V64_GET_B6(v)                                                        \
+#define HEXAGON_V64_GET_B6(v)                                                  \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V64_GET_B6(v)…
__extension__({ \
union { \
long long d; \
signed char b[8]; \
} _HEXAGON_V64_internal_union; \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    } _HEXAGON_V64_internal_union;                                                   \
-    _HEXAGON_V64_internal_union.d = (v);                                             \
-    _HEXAGON_V64_internal_union.b[6];                                                \
+    } _HEXAGON_V64_internal_union;                                             \
+    _HEXAGON_V64_internal_union.d = (v);                                       \
+    _HEXAGON_V64_internal_union.b[6];                                          \
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V64_internal_union…
_HEXAGON_V64_internal_union.d = (v); \
_HEXAGON_V64_internal_union.b[6]; \
})
#define HEXAGON_V64_GET_B7(v) \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define HEXAGON_V64_GET_B7(v)                                                        \
+#define HEXAGON_V64_GET_B7(v)                                                  \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V64_GET_B7(v)…
__extension__({ \
union { \
long long d; \
signed char b[8]; \
} _HEXAGON_V64_internal_union; \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    } _HEXAGON_V64_internal_union;                                                   \
-    _HEXAGON_V64_internal_union.d = (v);                                             \
-    _HEXAGON_V64_internal_union.b[7];                                                \
+    } _HEXAGON_V64_internal_union;                                             \
+    _HEXAGON_V64_internal_union.d = (v);                                       \
+    _HEXAGON_V64_internal_union.b[7];                                          \
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V64_internal_union…
_HEXAGON_V64_internal_union.d = (v); \
_HEXAGON_V64_internal_union.b[7]; \
})
#define HEXAGON_V64_GET_UB0(v) \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define HEXAGON_V64_GET_UB0(v)                                                       \
+#define HEXAGON_V64_GET_UB0(v)                                                 \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V64_GET_UB0(v)…
__extension__({ \
union { \
long long d; \
unsigned char ub[8]; \
} _HEXAGON_V64_internal_union; \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    } _HEXAGON_V64_internal_union;                                                   \
-    _HEXAGON_V64_internal_union.d = (v);                                             \
-    _HEXAGON_V64_internal_union.ub[0];                                               \
+    } _HEXAGON_V64_internal_union;                                             \
+    _HEXAGON_V64_internal_union.d = (v);                                       \
+    _HEXAGON_V64_internal_union.ub[0];                                         \
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V64_internal_union…
_HEXAGON_V64_internal_union.d = (v); \
_HEXAGON_V64_internal_union.ub[0]; \
})
#define HEXAGON_V64_GET_UB1(v) \
Lint: Pre-merge checks
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clang-format: please reformat the code

-#define HEXAGON_V64_GET_UB1(v)                                                       \
+#define HEXAGON_V64_GET_UB1(v)                                                 \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V64_GET_UB1(v)…
__extension__({ \
union { \
long long d; \
unsigned char ub[8]; \
} _HEXAGON_V64_internal_union; \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    } _HEXAGON_V64_internal_union;                                                   \
-    _HEXAGON_V64_internal_union.d = (v);                                             \
-    _HEXAGON_V64_internal_union.ub[1];                                               \
+    } _HEXAGON_V64_internal_union;                                             \
+    _HEXAGON_V64_internal_union.d = (v);                                       \
+    _HEXAGON_V64_internal_union.ub[1];                                         \
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V64_internal_union…
_HEXAGON_V64_internal_union.d = (v); \
_HEXAGON_V64_internal_union.ub[1]; \
})
#define HEXAGON_V64_GET_UB2(v) \
Lint: Pre-merge checks
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clang-format: please reformat the code

-#define HEXAGON_V64_GET_UB2(v)                                                       \
+#define HEXAGON_V64_GET_UB2(v)                                                 \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V64_GET_UB2(v)…
__extension__({ \
union { \
long long d; \
unsigned char ub[8]; \
} _HEXAGON_V64_internal_union; \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    } _HEXAGON_V64_internal_union;                                                   \
-    _HEXAGON_V64_internal_union.d = (v);                                             \
-    _HEXAGON_V64_internal_union.ub[2];                                               \
+    } _HEXAGON_V64_internal_union;                                             \
+    _HEXAGON_V64_internal_union.d = (v);                                       \
+    _HEXAGON_V64_internal_union.ub[2];                                         \
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V64_internal_union…
_HEXAGON_V64_internal_union.d = (v); \
_HEXAGON_V64_internal_union.ub[2]; \
})
#define HEXAGON_V64_GET_UB3(v) \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define HEXAGON_V64_GET_UB3(v)                                                       \
+#define HEXAGON_V64_GET_UB3(v)                                                 \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V64_GET_UB3(v)…
__extension__({ \
union { \
long long d; \
unsigned char ub[8]; \
} _HEXAGON_V64_internal_union; \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    } _HEXAGON_V64_internal_union;                                                   \
-    _HEXAGON_V64_internal_union.d = (v);                                             \
-    _HEXAGON_V64_internal_union.ub[3];                                               \
+    } _HEXAGON_V64_internal_union;                                             \
+    _HEXAGON_V64_internal_union.d = (v);                                       \
+    _HEXAGON_V64_internal_union.ub[3];                                         \
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V64_internal_union…
_HEXAGON_V64_internal_union.d = (v); \
_HEXAGON_V64_internal_union.ub[3]; \
})
#define HEXAGON_V64_GET_UB4(v) \
Lint: Pre-merge checks
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clang-format: please reformat the code

-#define HEXAGON_V64_GET_UB4(v)                                                       \
+#define HEXAGON_V64_GET_UB4(v)                                                 \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V64_GET_UB4(v)…
__extension__({ \
union { \
long long d; \
unsigned char ub[8]; \
} _HEXAGON_V64_internal_union; \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    } _HEXAGON_V64_internal_union;                                                   \
-    _HEXAGON_V64_internal_union.d = (v);                                             \
-    _HEXAGON_V64_internal_union.ub[4];                                               \
+    } _HEXAGON_V64_internal_union;                                             \
+    _HEXAGON_V64_internal_union.d = (v);                                       \
+    _HEXAGON_V64_internal_union.ub[4];                                         \
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V64_internal_union…
_HEXAGON_V64_internal_union.d = (v); \
_HEXAGON_V64_internal_union.ub[4]; \
})
#define HEXAGON_V64_GET_UB5(v) \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define HEXAGON_V64_GET_UB5(v)                                                       \
+#define HEXAGON_V64_GET_UB5(v)                                                 \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V64_GET_UB5(v)…
__extension__({ \
union { \
long long d; \
unsigned char ub[8]; \
} _HEXAGON_V64_internal_union; \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    } _HEXAGON_V64_internal_union;                                                   \
-    _HEXAGON_V64_internal_union.d = (v);                                             \
-    _HEXAGON_V64_internal_union.ub[5];                                               \
+    } _HEXAGON_V64_internal_union;                                             \
+    _HEXAGON_V64_internal_union.d = (v);                                       \
+    _HEXAGON_V64_internal_union.ub[5];                                         \
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V64_internal_union…
_HEXAGON_V64_internal_union.d = (v); \
_HEXAGON_V64_internal_union.ub[5]; \
})
#define HEXAGON_V64_GET_UB6(v) \
Lint: Pre-merge checks
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clang-format: please reformat the code

-#define HEXAGON_V64_GET_UB6(v)                                                       \
+#define HEXAGON_V64_GET_UB6(v)                                                 \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V64_GET_UB6(v)…
__extension__({ \
union { \
long long d; \
unsigned char ub[8]; \
} _HEXAGON_V64_internal_union; \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    } _HEXAGON_V64_internal_union;                                                   \
-    _HEXAGON_V64_internal_union.d = (v);                                             \
-    _HEXAGON_V64_internal_union.ub[6];                                               \
+    } _HEXAGON_V64_internal_union;                                             \
+    _HEXAGON_V64_internal_union.d = (v);                                       \
+    _HEXAGON_V64_internal_union.ub[6];                                         \
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V64_internal_union…
_HEXAGON_V64_internal_union.d = (v); \
_HEXAGON_V64_internal_union.ub[6]; \
})
#define HEXAGON_V64_GET_UB7(v) \
Lint: Pre-merge checks
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clang-format: please reformat the code

-#define HEXAGON_V64_GET_UB7(v)                                                       \
+#define HEXAGON_V64_GET_UB7(v)                                                 \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V64_GET_UB7(v)…
__extension__({ \
union { \
long long d; \
unsigned char ub[8]; \
} _HEXAGON_V64_internal_union; \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    } _HEXAGON_V64_internal_union;                                                   \
-    _HEXAGON_V64_internal_union.d = (v);                                             \
-    _HEXAGON_V64_internal_union.ub[7];                                               \
+    } _HEXAGON_V64_internal_union;                                             \
+    _HEXAGON_V64_internal_union.d = (v);                                       \
+    _HEXAGON_V64_internal_union.ub[7];                                         \
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V64_internal_union…
_HEXAGON_V64_internal_union.d = (v); \
_HEXAGON_V64_internal_union.ub[7]; \
})
/* NOTE: All set macros return a HEXAGON_Vect64 type */
/* Set doubleword macro */
#define HEXAGON_V64_PUT_D(v, new) (new)
/* Set word macros */
#ifdef __hexagon__
#define HEXAGON_V64_PUT_W0(v, new) \
Lint: Pre-merge checks
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clang-format: please reformat the code

-#define HEXAGON_V64_PUT_W0(v, new)                                                   \
+#define HEXAGON_V64_PUT_W0(v, new)                                             \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V64_PUT_W0(v, new)…
__extension__({ \
union { \
long long d; \
int w[2]; \
} _HEXAGON_V64_internal_union; \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    } _HEXAGON_V64_internal_union;                                                   \
-    _HEXAGON_V64_internal_union.d = (v);                                             \
-    _HEXAGON_V64_internal_union.w[0] = (new);                                        \
-    _HEXAGON_V64_internal_union.d;                                                   \
+    } _HEXAGON_V64_internal_union;                                             \
+    _HEXAGON_V64_internal_union.d = (v);                                       \
+    _HEXAGON_V64_internal_union.w[0] = (new);                                  \
+    _HEXAGON_V64_internal_union.d;                                             \
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V64_internal_union…
_HEXAGON_V64_internal_union.d = (v); \
_HEXAGON_V64_internal_union.w[0] = (new); \
_HEXAGON_V64_internal_union.d; \
})
#define HEXAGON_V64_PUT_W1(v, new) \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define HEXAGON_V64_PUT_W1(v, new)                                                   \
+#define HEXAGON_V64_PUT_W1(v, new)                                             \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V64_PUT_W1(v, new)…
__extension__({ \
union { \
long long d; \
int w[2]; \
} _HEXAGON_V64_internal_union; \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    } _HEXAGON_V64_internal_union;                                                   \
-    _HEXAGON_V64_internal_union.d = (v);                                             \
-    _HEXAGON_V64_internal_union.w[1] = (new);                                        \
-    _HEXAGON_V64_internal_union.d;                                                   \
+    } _HEXAGON_V64_internal_union;                                             \
+    _HEXAGON_V64_internal_union.d = (v);                                       \
+    _HEXAGON_V64_internal_union.w[1] = (new);                                  \
+    _HEXAGON_V64_internal_union.d;                                             \
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V64_internal_union…
_HEXAGON_V64_internal_union.d = (v); \
_HEXAGON_V64_internal_union.w[1] = (new); \
_HEXAGON_V64_internal_union.d; \
})
#else /* !__hexagon__ */
#define HEXAGON_V64_PUT_W0(v, new) \
Lint: Pre-merge checks
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clang-format: please reformat the code

-#define HEXAGON_V64_PUT_W0(v, new)                                                   \
-  (((v) & 0xffffffff00000000LL) | ((HEXAGON_Vect64)((unsigned int)(new))))
-#define HEXAGON_V64_PUT_W1(v, new)                                                   \
-  (((v) & 0x00000000ffffffffLL) | (((HEXAGON_Vect64)(new)) << 32LL))
+#define HEXAGON_V64_PUT_W0(v, new)                                             \
+  (((v)&0xffffffff00000000LL) | ((HEXAGON_Vect64)((unsigned int)(new))))
+#define HEXAGON_V64_PUT_W1(v, new)                                             \
+  (((v)&0x00000000ffffffffLL) | (((HEXAGON_Vect64)(new)) << 32LL))
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V64_PUT_W0(v, new)…
(((v) & 0xffffffff00000000LL) | ((HEXAGON_Vect64)((unsigned int)(new))))
#define HEXAGON_V64_PUT_W1(v, new) \
(((v) & 0x00000000ffffffffLL) | (((HEXAGON_Vect64)(new)) << 32LL))
#endif /* !__hexagon__ */
/* Set half word macros */
#ifdef __hexagon__
#define HEXAGON_V64_PUT_H0(v, new) \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define HEXAGON_V64_PUT_H0(v, new)                                                   \
+#define HEXAGON_V64_PUT_H0(v, new)                                             \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V64_PUT_H0(v, new)…
__extension__({ \
union { \
long long d; \
short h[4]; \
} _HEXAGON_V64_internal_union; \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    } _HEXAGON_V64_internal_union;                                                   \
-    _HEXAGON_V64_internal_union.d = (v);                                             \
-    _HEXAGON_V64_internal_union.h[0] = (new);                                        \
-    _HEXAGON_V64_internal_union.d;                                                   \
+    } _HEXAGON_V64_internal_union;                                             \
+    _HEXAGON_V64_internal_union.d = (v);                                       \
+    _HEXAGON_V64_internal_union.h[0] = (new);                                  \
+    _HEXAGON_V64_internal_union.d;                                             \
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V64_internal_union…
_HEXAGON_V64_internal_union.d = (v); \
_HEXAGON_V64_internal_union.h[0] = (new); \
_HEXAGON_V64_internal_union.d; \
})
#define HEXAGON_V64_PUT_H1(v, new) \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define HEXAGON_V64_PUT_H1(v, new)                                                   \
+#define HEXAGON_V64_PUT_H1(v, new)                                             \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V64_PUT_H1(v, new)…
__extension__({ \
union { \
long long d; \
short h[4]; \
} _HEXAGON_V64_internal_union; \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    } _HEXAGON_V64_internal_union;                                                   \
-    _HEXAGON_V64_internal_union.d = (v);                                             \
-    _HEXAGON_V64_internal_union.h[1] = (new);                                        \
-    _HEXAGON_V64_internal_union.d;                                                   \
+    } _HEXAGON_V64_internal_union;                                             \
+    _HEXAGON_V64_internal_union.d = (v);                                       \
+    _HEXAGON_V64_internal_union.h[1] = (new);                                  \
+    _HEXAGON_V64_internal_union.d;                                             \
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V64_internal_union…
_HEXAGON_V64_internal_union.d = (v); \
_HEXAGON_V64_internal_union.h[1] = (new); \
_HEXAGON_V64_internal_union.d; \
})
#define HEXAGON_V64_PUT_H2(v, new) \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define HEXAGON_V64_PUT_H2(v, new)                                                   \
+#define HEXAGON_V64_PUT_H2(v, new)                                             \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V64_PUT_H2(v, new)…
__extension__({ \
union { \
long long d; \
short h[4]; \
} _HEXAGON_V64_internal_union; \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    } _HEXAGON_V64_internal_union;                                                   \
-    _HEXAGON_V64_internal_union.d = (v);                                             \
-    _HEXAGON_V64_internal_union.h[2] = (new);                                        \
-    _HEXAGON_V64_internal_union.d;                                                   \
+    } _HEXAGON_V64_internal_union;                                             \
+    _HEXAGON_V64_internal_union.d = (v);                                       \
+    _HEXAGON_V64_internal_union.h[2] = (new);                                  \
+    _HEXAGON_V64_internal_union.d;                                             \
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V64_internal_union…
_HEXAGON_V64_internal_union.d = (v); \
_HEXAGON_V64_internal_union.h[2] = (new); \
_HEXAGON_V64_internal_union.d; \
})
#define HEXAGON_V64_PUT_H3(v, new) \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define HEXAGON_V64_PUT_H3(v, new)                                                   \
+#define HEXAGON_V64_PUT_H3(v, new)                                             \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V64_PUT_H3(v, new)…
__extension__({ \
union { \
long long d; \
short h[4]; \
} _HEXAGON_V64_internal_union; \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    } _HEXAGON_V64_internal_union;                                                   \
-    _HEXAGON_V64_internal_union.d = (v);                                             \
-    _HEXAGON_V64_internal_union.h[3] = (new);                                        \
-    _HEXAGON_V64_internal_union.d;                                                   \
+    } _HEXAGON_V64_internal_union;                                             \
+    _HEXAGON_V64_internal_union.d = (v);                                       \
+    _HEXAGON_V64_internal_union.h[3] = (new);                                  \
+    _HEXAGON_V64_internal_union.d;                                             \
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V64_internal_union…
_HEXAGON_V64_internal_union.d = (v); \
_HEXAGON_V64_internal_union.h[3] = (new); \
_HEXAGON_V64_internal_union.d; \
})
#else /* !__hexagon__ */
#define HEXAGON_V64_PUT_H0(v, new) \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define HEXAGON_V64_PUT_H0(v, new)                                                   \
-  (((v) & 0xffffffffffff0000LL) | ((HEXAGON_Vect64)((unsigned short)(new))))
-#define HEXAGON_V64_PUT_H1(v, new)                                                   \
-  (((v) & 0xffffffff0000ffffLL) | (((HEXAGON_Vect64)((unsigned short)(new))) << 16LL))
-#define HEXAGON_V64_PUT_H2(v, new)                                                   \
-  (((v) & 0xffff0000ffffffffLL) | (((HEXAGON_Vect64)((unsigned short)(new))) << 32LL))
-#define HEXAGON_V64_PUT_H3(v, new)                                                   \
-  (((v) & 0x0000ffffffffffffLL) | (((HEXAGON_Vect64)(new)) << 48LL))
+#define HEXAGON_V64_PUT_H0(v, new)                                             \
+  (((v)&0xffffffffffff0000LL) | ((HEXAGON_Vect64)((unsigned short)(new))))

8 diff lines are omitted. See full path.

Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V64_PUT_H0(v, new)…
(((v) & 0xffffffffffff0000LL) | ((HEXAGON_Vect64)((unsigned short)(new))))
#define HEXAGON_V64_PUT_H1(v, new) \
(((v) & 0xffffffff0000ffffLL) | (((HEXAGON_Vect64)((unsigned short)(new))) << 16LL))
#define HEXAGON_V64_PUT_H2(v, new) \
(((v) & 0xffff0000ffffffffLL) | (((HEXAGON_Vect64)((unsigned short)(new))) << 32LL))
#define HEXAGON_V64_PUT_H3(v, new) \
(((v) & 0x0000ffffffffffffLL) | (((HEXAGON_Vect64)(new)) << 48LL))
#endif /* !__hexagon__ */
/* Set byte macros */
#ifdef __hexagon__
#define HEXAGON_V64_PUT_B0(v, new) \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define HEXAGON_V64_PUT_B0(v, new)                                                   \
+#define HEXAGON_V64_PUT_B0(v, new)                                             \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V64_PUT_B0(v, new)…
__extension__({ \
union { \
long long d; \
char b[8]; \
} _HEXAGON_V64_internal_union; \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    } _HEXAGON_V64_internal_union;                                                   \
-    _HEXAGON_V64_internal_union.d = (v);                                             \
-    _HEXAGON_V64_internal_union.b[0] = (new);                                        \
-    _HEXAGON_V64_internal_union.d;                                                   \
+    } _HEXAGON_V64_internal_union;                                             \
+    _HEXAGON_V64_internal_union.d = (v);                                       \
+    _HEXAGON_V64_internal_union.b[0] = (new);                                  \
+    _HEXAGON_V64_internal_union.d;                                             \
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V64_internal_union…
_HEXAGON_V64_internal_union.d = (v); \
_HEXAGON_V64_internal_union.b[0] = (new); \
_HEXAGON_V64_internal_union.d; \
})
#define HEXAGON_V64_PUT_B1(v, new) \
Lint: Pre-merge checks
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clang-format: please reformat the code

-#define HEXAGON_V64_PUT_B1(v, new)                                                   \
+#define HEXAGON_V64_PUT_B1(v, new)                                             \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V64_PUT_B1(v, new)…
__extension__({ \
union { \
long long d; \
char b[8]; \
} _HEXAGON_V64_internal_union; \
Lint: Pre-merge checks
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clang-format: please reformat the code

-    } _HEXAGON_V64_internal_union;                                                   \
-    _HEXAGON_V64_internal_union.d = (v);                                             \
-    _HEXAGON_V64_internal_union.b[1] = (new);                                        \
-    _HEXAGON_V64_internal_union.d;                                                   \
+    } _HEXAGON_V64_internal_union;                                             \
+    _HEXAGON_V64_internal_union.d = (v);                                       \
+    _HEXAGON_V64_internal_union.b[1] = (new);                                  \
+    _HEXAGON_V64_internal_union.d;                                             \
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V64_internal_union…
_HEXAGON_V64_internal_union.d = (v); \
_HEXAGON_V64_internal_union.b[1] = (new); \
_HEXAGON_V64_internal_union.d; \
})
#define HEXAGON_V64_PUT_B2(v, new) \
Lint: Pre-merge checks
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clang-format: please reformat the code

-#define HEXAGON_V64_PUT_B2(v, new)                                                   \
+#define HEXAGON_V64_PUT_B2(v, new)                                             \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V64_PUT_B2(v, new)…
__extension__({ \
union { \
long long d; \
char b[8]; \
} _HEXAGON_V64_internal_union; \
Lint: Pre-merge checks
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clang-format: please reformat the code

-    } _HEXAGON_V64_internal_union;                                                   \
-    _HEXAGON_V64_internal_union.d = (v);                                             \
-    _HEXAGON_V64_internal_union.b[2] = (new);                                        \
-    _HEXAGON_V64_internal_union.d;                                                   \
+    } _HEXAGON_V64_internal_union;                                             \
+    _HEXAGON_V64_internal_union.d = (v);                                       \
+    _HEXAGON_V64_internal_union.b[2] = (new);                                  \
+    _HEXAGON_V64_internal_union.d;                                             \
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V64_internal_union…
_HEXAGON_V64_internal_union.d = (v); \
_HEXAGON_V64_internal_union.b[2] = (new); \
_HEXAGON_V64_internal_union.d; \
})
#define HEXAGON_V64_PUT_B3(v, new) \
Lint: Pre-merge checks
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clang-format: please reformat the code

-#define HEXAGON_V64_PUT_B3(v, new)                                                   \
+#define HEXAGON_V64_PUT_B3(v, new)                                             \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V64_PUT_B3(v, new)…
__extension__({ \
union { \
long long d; \
char b[8]; \
} _HEXAGON_V64_internal_union; \
Lint: Pre-merge checks
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clang-format: please reformat the code

-    } _HEXAGON_V64_internal_union;                                                   \
-    _HEXAGON_V64_internal_union.d = (v);                                             \
-    _HEXAGON_V64_internal_union.b[3] = (new);                                        \
-    _HEXAGON_V64_internal_union.d;                                                   \
+    } _HEXAGON_V64_internal_union;                                             \
+    _HEXAGON_V64_internal_union.d = (v);                                       \
+    _HEXAGON_V64_internal_union.b[3] = (new);                                  \
+    _HEXAGON_V64_internal_union.d;                                             \
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V64_internal_union…
_HEXAGON_V64_internal_union.d = (v); \
_HEXAGON_V64_internal_union.b[3] = (new); \
_HEXAGON_V64_internal_union.d; \
})
#define HEXAGON_V64_PUT_B4(v, new) \
Lint: Pre-merge checks
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clang-format: please reformat the code

-#define HEXAGON_V64_PUT_B4(v, new)                                                   \
+#define HEXAGON_V64_PUT_B4(v, new)                                             \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V64_PUT_B4(v, new)…
__extension__({ \
union { \
long long d; \
char b[8]; \
} _HEXAGON_V64_internal_union; \
Lint: Pre-merge checks
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clang-format: please reformat the code

-    } _HEXAGON_V64_internal_union;                                                   \
-    _HEXAGON_V64_internal_union.d = (v);                                             \
-    _HEXAGON_V64_internal_union.b[4] = (new);                                        \
-    _HEXAGON_V64_internal_union.d;                                                   \
+    } _HEXAGON_V64_internal_union;                                             \
+    _HEXAGON_V64_internal_union.d = (v);                                       \
+    _HEXAGON_V64_internal_union.b[4] = (new);                                  \
+    _HEXAGON_V64_internal_union.d;                                             \
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V64_internal_union…
_HEXAGON_V64_internal_union.d = (v); \
_HEXAGON_V64_internal_union.b[4] = (new); \
_HEXAGON_V64_internal_union.d; \
})
#define HEXAGON_V64_PUT_B5(v, new) \
Lint: Pre-merge checks
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clang-format: please reformat the code

-#define HEXAGON_V64_PUT_B5(v, new)                                                   \
+#define HEXAGON_V64_PUT_B5(v, new)                                             \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V64_PUT_B5(v, new)…
__extension__({ \
union { \
long long d; \
char b[8]; \
} _HEXAGON_V64_internal_union; \
Lint: Pre-merge checks
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clang-format: please reformat the code

-    } _HEXAGON_V64_internal_union;                                                   \
-    _HEXAGON_V64_internal_union.d = (v);                                             \
-    _HEXAGON_V64_internal_union.b[5] = (new);                                        \
-    _HEXAGON_V64_internal_union.d;                                                   \
+    } _HEXAGON_V64_internal_union;                                             \
+    _HEXAGON_V64_internal_union.d = (v);                                       \
+    _HEXAGON_V64_internal_union.b[5] = (new);                                  \
+    _HEXAGON_V64_internal_union.d;                                             \
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V64_internal_union…
_HEXAGON_V64_internal_union.d = (v); \
_HEXAGON_V64_internal_union.b[5] = (new); \
_HEXAGON_V64_internal_union.d; \
})
#define HEXAGON_V64_PUT_B6(v, new) \
Lint: Pre-merge checks
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clang-format: please reformat the code

-#define HEXAGON_V64_PUT_B6(v, new)                                                   \
+#define HEXAGON_V64_PUT_B6(v, new)                                             \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V64_PUT_B6(v, new)…
__extension__({ \
union { \
long long d; \
char b[8]; \
} _HEXAGON_V64_internal_union; \
Lint: Pre-merge checks
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clang-format: please reformat the code

-    } _HEXAGON_V64_internal_union;                                                   \
-    _HEXAGON_V64_internal_union.d = (v);                                             \
-    _HEXAGON_V64_internal_union.b[6] = (new);                                        \
-    _HEXAGON_V64_internal_union.d;                                                   \
+    } _HEXAGON_V64_internal_union;                                             \
+    _HEXAGON_V64_internal_union.d = (v);                                       \
+    _HEXAGON_V64_internal_union.b[6] = (new);                                  \
+    _HEXAGON_V64_internal_union.d;                                             \
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V64_internal_union…
_HEXAGON_V64_internal_union.d = (v); \
_HEXAGON_V64_internal_union.b[6] = (new); \
_HEXAGON_V64_internal_union.d; \
})
#define HEXAGON_V64_PUT_B7(v, new) \
Lint: Pre-merge checks
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clang-format: please reformat the code

-#define HEXAGON_V64_PUT_B7(v, new)                                                   \
+#define HEXAGON_V64_PUT_B7(v, new)                                             \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V64_PUT_B7(v, new)…
__extension__({ \
union { \
long long d; \
char b[8]; \
} _HEXAGON_V64_internal_union; \
Lint: Pre-merge checks
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clang-format: please reformat the code

-    } _HEXAGON_V64_internal_union;                                                   \
-    _HEXAGON_V64_internal_union.d = (v);                                             \
-    _HEXAGON_V64_internal_union.b[7] = (new);                                        \
-    _HEXAGON_V64_internal_union.d;                                                   \
+    } _HEXAGON_V64_internal_union;                                             \
+    _HEXAGON_V64_internal_union.d = (v);                                       \
+    _HEXAGON_V64_internal_union.b[7] = (new);                                  \
+    _HEXAGON_V64_internal_union.d;                                             \
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V64_internal_union…
_HEXAGON_V64_internal_union.d = (v); \
_HEXAGON_V64_internal_union.b[7] = (new); \
_HEXAGON_V64_internal_union.d; \
})
#else /* !__hexagon__ */
#define HEXAGON_V64_PUT_B0(v, new) \
Lint: Pre-merge checks
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clang-format: please reformat the code

-#define HEXAGON_V64_PUT_B0(v, new)                                                   \
-  (((v) & 0xffffffffffffff00LL) | ((HEXAGON_Vect64)((unsigned char)(new))))
-#define HEXAGON_V64_PUT_B1(v, new)                                                   \
-  (((v) & 0xffffffffffff00ffLL) | (((HEXAGON_Vect64)((unsigned char)(new))) << 8LL))
-#define HEXAGON_V64_PUT_B2(v, new)                                                   \
-  (((v) & 0xffffffffff00ffffLL) | (((HEXAGON_Vect64)((unsigned char)(new))) << 16LL))
-#define HEXAGON_V64_PUT_B3(v, new)                                                   \
-  (((v) & 0xffffffff00ffffffLL) | (((HEXAGON_Vect64)((unsigned char)(new))) << 24LL))
-#define HEXAGON_V64_PUT_B4(v, new)                                                   \
-  (((v) & 0xffffff00ffffffffLL) | (((HEXAGON_Vect64)((unsigned char)(new))) << 32LL))

28 diff lines are omitted. See full path.

Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V64_PUT_B0(v, new)…
(((v) & 0xffffffffffffff00LL) | ((HEXAGON_Vect64)((unsigned char)(new))))
#define HEXAGON_V64_PUT_B1(v, new) \
(((v) & 0xffffffffffff00ffLL) | (((HEXAGON_Vect64)((unsigned char)(new))) << 8LL))
#define HEXAGON_V64_PUT_B2(v, new) \
(((v) & 0xffffffffff00ffffLL) | (((HEXAGON_Vect64)((unsigned char)(new))) << 16LL))
#define HEXAGON_V64_PUT_B3(v, new) \
(((v) & 0xffffffff00ffffffLL) | (((HEXAGON_Vect64)((unsigned char)(new))) << 24LL))
#define HEXAGON_V64_PUT_B4(v, new) \
(((v) & 0xffffff00ffffffffLL) | (((HEXAGON_Vect64)((unsigned char)(new))) << 32LL))
#define HEXAGON_V64_PUT_B5(v, new) \
(((v) & 0xffff00ffffffffffLL) | (((HEXAGON_Vect64)((unsigned char)(new))) << 40LL))
#define HEXAGON_V64_PUT_B6(v, new) \
(((v) & 0xff00ffffffffffffLL) | (((HEXAGON_Vect64)((unsigned char)(new))) << 48LL))
#define HEXAGON_V64_PUT_B7(v, new) \
(((v) & 0x00ffffffffffffffLL) | (((HEXAGON_Vect64)(new)) << 56LL))
#endif /* !__hexagon__ */
/* NOTE: All create macros return a HEXAGON_Vect64 type */
/* Create from a doubleword */
#define HEXAGON_V64_CREATE_D(d) (d)
/* Create from words */
#ifdef __hexagon__
#define HEXAGON_V64_CREATE_W(w1, w0) \
Lint: Pre-merge checks
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clang-format: please reformat the code

-#define HEXAGON_V64_CREATE_W(w1, w0)                                                 \
+#define HEXAGON_V64_CREATE_W(w1, w0)                                           \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V64_CREATE_W(w1, w0)…
__extension__({ \
union { \
long long d; \
int w[2]; \
} _HEXAGON_V64_internal_union; \
Lint: Pre-merge checks
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clang-format: please reformat the code

-    } _HEXAGON_V64_internal_union;                                                   \
-    _HEXAGON_V64_internal_union.w[0] = (w0);                                         \
-    _HEXAGON_V64_internal_union.w[1] = (w1);                                         \
-    _HEXAGON_V64_internal_union.d;                                                   \
+    } _HEXAGON_V64_internal_union;                                             \
+    _HEXAGON_V64_internal_union.w[0] = (w0);                                   \
+    _HEXAGON_V64_internal_union.w[1] = (w1);                                   \
+    _HEXAGON_V64_internal_union.d;                                             \
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V64_internal_union…
_HEXAGON_V64_internal_union.w[0] = (w0); \
_HEXAGON_V64_internal_union.w[1] = (w1); \
_HEXAGON_V64_internal_union.d; \
})
#else /* !__hexagon__ */
#define HEXAGON_V64_CREATE_W(w1, w0) \
Lint: Pre-merge checks
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clang-format: please reformat the code

-#define HEXAGON_V64_CREATE_W(w1, w0)                                                 \
-  ((((HEXAGON_Vect64)(w1)) << 32LL) | ((HEXAGON_Vect64)((w0) & 0xffffffff)))
+#define HEXAGON_V64_CREATE_W(w1, w0)                                           \
+  ((((HEXAGON_Vect64)(w1)) << 32LL) | ((HEXAGON_Vect64)((w0)&0xffffffff)))
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V64_CREATE_W(w1, w0)…
((((HEXAGON_Vect64)(w1)) << 32LL) | ((HEXAGON_Vect64)((w0) & 0xffffffff)))
#endif /* !__hexagon__ */
/* Create from half words */
#ifdef __hexagon__
#define HEXAGON_V64_CREATE_H(h3, h2, h1, h0) \
Lint: Pre-merge checks
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clang-format: please reformat the code

-#define HEXAGON_V64_CREATE_H(h3, h2, h1, h0)                                         \
+#define HEXAGON_V64_CREATE_H(h3, h2, h1, h0)                                   \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V64_CREATE_H(h3, h2, h1, h0)…
__extension__({ \
union { \
long long d; \
short h[4]; \
} _HEXAGON_V64_internal_union; \
Lint: Pre-merge checks
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clang-format: please reformat the code

-    } _HEXAGON_V64_internal_union;                                                   \
-    _HEXAGON_V64_internal_union.h[0] = (h0);                                         \
-    _HEXAGON_V64_internal_union.h[1] = (h1);                                         \
-    _HEXAGON_V64_internal_union.h[2] = (h2);                                         \
-    _HEXAGON_V64_internal_union.h[3] = (h3);                                         \
-    _HEXAGON_V64_internal_union.d;                                                   \
+    } _HEXAGON_V64_internal_union;                                             \
+    _HEXAGON_V64_internal_union.h[0] = (h0);                                   \
+    _HEXAGON_V64_internal_union.h[1] = (h1);                                   \
+    _HEXAGON_V64_internal_union.h[2] = (h2);                                   \

2 diff lines are omitted. See full path.

Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V64_internal_union…
_HEXAGON_V64_internal_union.h[0] = (h0); \
_HEXAGON_V64_internal_union.h[1] = (h1); \
_HEXAGON_V64_internal_union.h[2] = (h2); \
_HEXAGON_V64_internal_union.h[3] = (h3); \
_HEXAGON_V64_internal_union.d; \
})
#else /* !__hexagon__ */
#define HEXAGON_V64_CREATE_H(h3, h2, h1, h0) \
Lint: Pre-merge checks
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clang-format: please reformat the code

-#define HEXAGON_V64_CREATE_H(h3, h2, h1, h0)                                         \
-  ((((HEXAGON_Vect64)(h3)) << 48LL) | (((HEXAGON_Vect64)((h2) & 0xffff)) << 32LL) |        \
-   (((HEXAGON_Vect64)((h1) & 0xffff)) << 16LL) | ((HEXAGON_Vect64)((h0) & 0xffff)))
+#define HEXAGON_V64_CREATE_H(h3, h2, h1, h0)                                   \
+  ((((HEXAGON_Vect64)(h3)) << 48LL) |                                          \
+   (((HEXAGON_Vect64)((h2)&0xffff)) << 32LL) |                                 \
+   (((HEXAGON_Vect64)((h1)&0xffff)) << 16LL) |                                 \
+   ((HEXAGON_Vect64)((h0)&0xffff)))
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V64_CREATE_H(h3, h2, h1, h0)…
((((HEXAGON_Vect64)(h3)) << 48LL) | (((HEXAGON_Vect64)((h2) & 0xffff)) << 32LL) | \
(((HEXAGON_Vect64)((h1) & 0xffff)) << 16LL) | ((HEXAGON_Vect64)((h0) & 0xffff)))
#endif /* !__hexagon__ */
/* Create from bytes */
#ifdef __hexagon__
#define HEXAGON_V64_CREATE_B(b7, b6, b5, b4, b3, b2, b1, b0) \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define HEXAGON_V64_CREATE_B(b7, b6, b5, b4, b3, b2, b1, b0)                         \
+#define HEXAGON_V64_CREATE_B(b7, b6, b5, b4, b3, b2, b1, b0)                   \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V64_CREATE_B(b7, b6, b5, b4, b3, b2…
__extension__({ \
union { \
long long d; \
char b[8]; \
} _HEXAGON_V64_internal_union; \
Lint: Pre-merge checks
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clang-format: please reformat the code

-    } _HEXAGON_V64_internal_union;                                                   \
-    _HEXAGON_V64_internal_union.b[0] = (b0);                                         \
-    _HEXAGON_V64_internal_union.b[1] = (b1);                                         \
-    _HEXAGON_V64_internal_union.b[2] = (b2);                                         \
-    _HEXAGON_V64_internal_union.b[3] = (b3);                                         \
-    _HEXAGON_V64_internal_union.b[4] = (b4);                                         \
-    _HEXAGON_V64_internal_union.b[5] = (b5);                                         \
-    _HEXAGON_V64_internal_union.b[6] = (b6);                                         \
-    _HEXAGON_V64_internal_union.b[7] = (b7);                                         \
-    _HEXAGON_V64_internal_union.d;                                                   \

10 diff lines are omitted. See full path.

Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V64_internal_union…
_HEXAGON_V64_internal_union.b[0] = (b0); \
_HEXAGON_V64_internal_union.b[1] = (b1); \
_HEXAGON_V64_internal_union.b[2] = (b2); \
_HEXAGON_V64_internal_union.b[3] = (b3); \
_HEXAGON_V64_internal_union.b[4] = (b4); \
_HEXAGON_V64_internal_union.b[5] = (b5); \
_HEXAGON_V64_internal_union.b[6] = (b6); \
_HEXAGON_V64_internal_union.b[7] = (b7); \
_HEXAGON_V64_internal_union.d; \
})
#else /* !__hexagon__ */
#define HEXAGON_V64_CREATE_B(b7, b6, b5, b4, b3, b2, b1, b0) \
Lint: Pre-merge checks
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clang-format: please reformat the code

-#define HEXAGON_V64_CREATE_B(b7, b6, b5, b4, b3, b2, b1, b0)                         \
-  ((((HEXAGON_Vect64)(b7)) << 56LL) | (((HEXAGON_Vect64)((b6) & 0xff)) << 48LL) |          \
-   (((HEXAGON_Vect64)((b5) & 0xff)) << 40LL) | (((HEXAGON_Vect64)((b4) & 0xff)) << 32LL) | \
-   (((HEXAGON_Vect64)((b3) & 0xff)) << 24LL) | (((HEXAGON_Vect64)((b2) & 0xff)) << 16LL) | \
-   (((HEXAGON_Vect64)((b1) & 0xff)) << 8LL) | ((HEXAGON_Vect64)((b0) & 0xff)))
+#define HEXAGON_V64_CREATE_B(b7, b6, b5, b4, b3, b2, b1, b0)                   \
+  ((((HEXAGON_Vect64)(b7)) << 56LL) |                                          \
+   (((HEXAGON_Vect64)((b6)&0xff)) << 48LL) |                                   \
+   (((HEXAGON_Vect64)((b5)&0xff)) << 40LL) |                                   \
+   (((HEXAGON_Vect64)((b4)&0xff)) << 32LL) |                                   \

3 diff lines are omitted. See full path.

Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V64_CREATE_B(b7, b6, b5, b4, b3, b2…
((((HEXAGON_Vect64)(b7)) << 56LL) | (((HEXAGON_Vect64)((b6) & 0xff)) << 48LL) | \
(((HEXAGON_Vect64)((b5) & 0xff)) << 40LL) | (((HEXAGON_Vect64)((b4) & 0xff)) << 32LL) | \
(((HEXAGON_Vect64)((b3) & 0xff)) << 24LL) | (((HEXAGON_Vect64)((b2) & 0xff)) << 16LL) | \
(((HEXAGON_Vect64)((b1) & 0xff)) << 8LL) | ((HEXAGON_Vect64)((b0) & 0xff)))
#endif /* !__hexagon__ */
#ifdef __cplusplus
class HEXAGON_Vect64C {
public:
// Constructors
HEXAGON_Vect64C(long long d = 0) : data(d) {};
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clang-format: please reformat the code

-  HEXAGON_Vect64C(long long d = 0) : data(d) {};
-  HEXAGON_Vect64C(int w1, int w0) : data(HEXAGON_V64_CREATE_W(w1, w0)) {};
+  HEXAGON_Vect64C(long long d = 0) : data(d){};
+  HEXAGON_Vect64C(int w1, int w0) : data(HEXAGON_V64_CREATE_W(w1, w0)){};
Lint: Pre-merge checks: clang-format: please reformat the code ``` - HEXAGON_Vect64C(long long d = 0) : data(d) {}…
HEXAGON_Vect64C(int w1, int w0) : data(HEXAGON_V64_CREATE_W(w1, w0)) {};
HEXAGON_Vect64C(short h3, short h2, short h1, short h0)
: data(HEXAGON_V64_CREATE_H(h3, h2, h1, h0)) {};
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clang-format: please reformat the code

-      : data(HEXAGON_V64_CREATE_H(h3, h2, h1, h0)) {};
-  HEXAGON_Vect64C(signed char b7, signed char b6, signed char b5, signed char b4,
-            signed char b3, signed char b2, signed char b1, signed char b0)
-      : data(HEXAGON_V64_CREATE_B(b7, b6, b5, b4, b3, b2, b1, b0)) {};
-  HEXAGON_Vect64C(const HEXAGON_Vect64C &v) : data(v.data) {};
+      : data(HEXAGON_V64_CREATE_H(h3, h2, h1, h0)){};
+  HEXAGON_Vect64C(signed char b7, signed char b6, signed char b5,
+                  signed char b4, signed char b3, signed char b2,
+                  signed char b1, signed char b0)
+      : data(HEXAGON_V64_CREATE_B(b7, b6, b5, b4, b3, b2, b1, b0)){};
+  HEXAGON_Vect64C(const HEXAGON_Vect64C &v) : data(v.data){};
Lint: Pre-merge checks: clang-format: please reformat the code ``` - : data(HEXAGON_V64_CREATE_H(h3, h2, h1, h0))…
HEXAGON_Vect64C(signed char b7, signed char b6, signed char b5, signed char b4,
signed char b3, signed char b2, signed char b1, signed char b0)
: data(HEXAGON_V64_CREATE_B(b7, b6, b5, b4, b3, b2, b1, b0)) {};
HEXAGON_Vect64C(const HEXAGON_Vect64C &v) : data(v.data) {};
HEXAGON_Vect64C &operator=(const HEXAGON_Vect64C &v) {
data = v.data;
return *this;
};
operator long long() {
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clang-format: please reformat the code

-  operator long long() {
-    return data;
-  };
+  operator long long() { return data; };
Lint: Pre-merge checks: clang-format: please reformat the code ``` - operator long long() { - return data; - }; +…
return data;
};
// Extract doubleword methods
long long D(void) {
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clang-format: please reformat the code

-  long long D(void) {
-    return HEXAGON_V64_GET_D(data);
-  };
-  unsigned long long UD(void) {
-    return HEXAGON_V64_GET_UD(data);
-  };
+  long long D(void) { return HEXAGON_V64_GET_D(data); };
+  unsigned long long UD(void) { return HEXAGON_V64_GET_UD(data); };
Lint: Pre-merge checks: clang-format: please reformat the code ``` - long long D(void) { - return HEXAGON_V64_GET_D…
return HEXAGON_V64_GET_D(data);
};
unsigned long long UD(void) {
return HEXAGON_V64_GET_UD(data);
};
// Extract word methods
int W0(void) {
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clang-format: please reformat the code

-  int W0(void) {
-    return HEXAGON_V64_GET_W0(data);
-  };
-  int W1(void) {
-    return HEXAGON_V64_GET_W1(data);
-  };
-  unsigned int UW0(void) {
-    return HEXAGON_V64_GET_UW0(data);
-  };
-  unsigned int UW1(void) {

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Lint: Pre-merge checks: clang-format: please reformat the code ``` - int W0(void) { - return HEXAGON_V64_GET_W0…
return HEXAGON_V64_GET_W0(data);
};
int W1(void) {
return HEXAGON_V64_GET_W1(data);
};
unsigned int UW0(void) {
return HEXAGON_V64_GET_UW0(data);
};
unsigned int UW1(void) {
return HEXAGON_V64_GET_UW1(data);
};
// Extract half word methods
short H0(void) {
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clang-format: please reformat the code

-  short H0(void) {
-    return HEXAGON_V64_GET_H0(data);
-  };
-  short H1(void) {
-    return HEXAGON_V64_GET_H1(data);
-  };
-  short H2(void) {
-    return HEXAGON_V64_GET_H2(data);
-  };
-  short H3(void) {

22 diff lines are omitted. See full path.

Lint: Pre-merge checks: clang-format: please reformat the code ``` - short H0(void) { - return HEXAGON_V64_GET_H0…
return HEXAGON_V64_GET_H0(data);
};
short H1(void) {
return HEXAGON_V64_GET_H1(data);
};
short H2(void) {
return HEXAGON_V64_GET_H2(data);
};
short H3(void) {
return HEXAGON_V64_GET_H3(data);
};
unsigned short UH0(void) {
return HEXAGON_V64_GET_UH0(data);
};
unsigned short UH1(void) {
return HEXAGON_V64_GET_UH1(data);
};
unsigned short UH2(void) {
return HEXAGON_V64_GET_UH2(data);
};
unsigned short UH3(void) {
return HEXAGON_V64_GET_UH3(data);
};
// Extract byte methods
signed char B0(void) {
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clang-format: please reformat the code

-  signed char B0(void) {
-    return HEXAGON_V64_GET_B0(data);
-  };
-  signed char B1(void) {
-    return HEXAGON_V64_GET_B1(data);
-  };
-  signed char B2(void) {
-    return HEXAGON_V64_GET_B2(data);
-  };
-  signed char B3(void) {

54 diff lines are omitted. See full path.

Lint: Pre-merge checks: clang-format: please reformat the code ``` - signed char B0(void) { - return…
return HEXAGON_V64_GET_B0(data);
};
signed char B1(void) {
return HEXAGON_V64_GET_B1(data);
};
signed char B2(void) {
return HEXAGON_V64_GET_B2(data);
};
signed char B3(void) {
return HEXAGON_V64_GET_B3(data);
};
signed char B4(void) {
return HEXAGON_V64_GET_B4(data);
};
signed char B5(void) {
return HEXAGON_V64_GET_B5(data);
};
signed char B6(void) {
return HEXAGON_V64_GET_B6(data);
};
signed char B7(void) {
return HEXAGON_V64_GET_B7(data);
};
unsigned char UB0(void) {
return HEXAGON_V64_GET_UB0(data);
};
unsigned char UB1(void) {
return HEXAGON_V64_GET_UB1(data);
};
unsigned char UB2(void) {
return HEXAGON_V64_GET_UB2(data);
};
unsigned char UB3(void) {
return HEXAGON_V64_GET_UB3(data);
};
unsigned char UB4(void) {
return HEXAGON_V64_GET_UB4(data);
};
unsigned char UB5(void) {
return HEXAGON_V64_GET_UB5(data);
};
unsigned char UB6(void) {
return HEXAGON_V64_GET_UB6(data);
};
unsigned char UB7(void) {
return HEXAGON_V64_GET_UB7(data);
};
// NOTE: All set methods return a HEXAGON_Vect64C type
// Set doubleword method
HEXAGON_Vect64C D(long long d) {
return HEXAGON_Vect64C(HEXAGON_V64_PUT_D(data, d));
};
// Set word methods
HEXAGON_Vect64C W0(int w) {
return HEXAGON_Vect64C(HEXAGON_V64_PUT_W0(data, w));
};
HEXAGON_Vect64C W1(int w) {
return HEXAGON_Vect64C(HEXAGON_V64_PUT_W1(data, w));
};
// Set half word methods
HEXAGON_Vect64C H0(short h) {
return HEXAGON_Vect64C(HEXAGON_V64_PUT_H0(data, h));
};
HEXAGON_Vect64C H1(short h) {
return HEXAGON_Vect64C(HEXAGON_V64_PUT_H1(data, h));
};
HEXAGON_Vect64C H2(short h) {
return HEXAGON_Vect64C(HEXAGON_V64_PUT_H2(data, h));
};
HEXAGON_Vect64C H3(short h) {
return HEXAGON_Vect64C(HEXAGON_V64_PUT_H3(data, h));
};
// Set byte methods
HEXAGON_Vect64C B0(signed char b) {
return HEXAGON_Vect64C(HEXAGON_V64_PUT_B0(data, b));
};
HEXAGON_Vect64C B1(signed char b) {
return HEXAGON_Vect64C(HEXAGON_V64_PUT_B1(data, b));
};
HEXAGON_Vect64C B2(signed char b) {
return HEXAGON_Vect64C(HEXAGON_V64_PUT_B2(data, b));
};
HEXAGON_Vect64C B3(signed char b) {
return HEXAGON_Vect64C(HEXAGON_V64_PUT_B3(data, b));
};
HEXAGON_Vect64C B4(signed char b) {
return HEXAGON_Vect64C(HEXAGON_V64_PUT_B4(data, b));
};
HEXAGON_Vect64C B5(signed char b) {
return HEXAGON_Vect64C(HEXAGON_V64_PUT_B5(data, b));
};
HEXAGON_Vect64C B6(signed char b) {
return HEXAGON_Vect64C(HEXAGON_V64_PUT_B6(data, b));
};
HEXAGON_Vect64C B7(signed char b) {
return HEXAGON_Vect64C(HEXAGON_V64_PUT_B7(data, b));
};
private:
long long data;
};
#endif /* __cplusplus */
/* 32 Bit Vectors */
typedef int HEXAGON_Vect32;
/* Extract word macros */
#define HEXAGON_V32_GET_W(v) (v)
#define HEXAGON_V32_GET_UW(v) ((unsigned int)(v))
/* Extract half word macros */
#define HEXAGON_V32_GET_H0(v) \
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clang-format: please reformat the code

-#define HEXAGON_V32_GET_H0(v)                                                        \
+#define HEXAGON_V32_GET_H0(v)                                                  \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V32_GET_H0(v)…
__extension__({ \
union { \
int w; \
short h[2]; \
} _HEXAGON_V32_internal_union; \
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clang-format: please reformat the code

-    } _HEXAGON_V32_internal_union;                                                   \
-    _HEXAGON_V32_internal_union.w = (v);                                             \
-    _HEXAGON_V32_internal_union.h[0];                                                \
+    } _HEXAGON_V32_internal_union;                                             \
+    _HEXAGON_V32_internal_union.w = (v);                                       \
+    _HEXAGON_V32_internal_union.h[0];                                          \
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V32_internal_union…
_HEXAGON_V32_internal_union.w = (v); \
_HEXAGON_V32_internal_union.h[0]; \
})
#define HEXAGON_V32_GET_H1(v) \
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clang-format: please reformat the code

-#define HEXAGON_V32_GET_H1(v)                                                        \
+#define HEXAGON_V32_GET_H1(v)                                                  \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V32_GET_H1(v)…
__extension__({ \
union { \
int w; \
short h[2]; \
} _HEXAGON_V32_internal_union; \
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clang-format: please reformat the code

-    } _HEXAGON_V32_internal_union;                                                   \
-    _HEXAGON_V32_internal_union.w = (v);                                             \
-    _HEXAGON_V32_internal_union.h[1];                                                \
+    } _HEXAGON_V32_internal_union;                                             \
+    _HEXAGON_V32_internal_union.w = (v);                                       \
+    _HEXAGON_V32_internal_union.h[1];                                          \
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V32_internal_union…
_HEXAGON_V32_internal_union.w = (v); \
_HEXAGON_V32_internal_union.h[1]; \
})
#define HEXAGON_V32_GET_UH0(v) \
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clang-format: please reformat the code

-#define HEXAGON_V32_GET_UH0(v)                                                       \
+#define HEXAGON_V32_GET_UH0(v)                                                 \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V32_GET_UH0(v)…
__extension__({ \
union { \
int w; \
unsigned short uh[2]; \
} _HEXAGON_V32_internal_union; \
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clang-format: please reformat the code

-    } _HEXAGON_V32_internal_union;                                                   \
-    _HEXAGON_V32_internal_union.w = (v);                                             \
-    _HEXAGON_V32_internal_union.uh[0];                                               \
+    } _HEXAGON_V32_internal_union;                                             \
+    _HEXAGON_V32_internal_union.w = (v);                                       \
+    _HEXAGON_V32_internal_union.uh[0];                                         \
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V32_internal_union…
_HEXAGON_V32_internal_union.w = (v); \
_HEXAGON_V32_internal_union.uh[0]; \
})
#define HEXAGON_V32_GET_UH1(v) \
Lint: Pre-merge checks
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clang-format: please reformat the code

-#define HEXAGON_V32_GET_UH1(v)                                                       \
+#define HEXAGON_V32_GET_UH1(v)                                                 \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V32_GET_UH1(v)…
__extension__({ \
union { \
int w; \
unsigned short uh[2]; \
} _HEXAGON_V32_internal_union; \
Lint: Pre-merge checks
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clang-format: please reformat the code

-    } _HEXAGON_V32_internal_union;                                                   \
-    _HEXAGON_V32_internal_union.w = (v);                                             \
-    _HEXAGON_V32_internal_union.uh[1];                                               \
+    } _HEXAGON_V32_internal_union;                                             \
+    _HEXAGON_V32_internal_union.w = (v);                                       \
+    _HEXAGON_V32_internal_union.uh[1];                                         \
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V32_internal_union…
_HEXAGON_V32_internal_union.w = (v); \
_HEXAGON_V32_internal_union.uh[1]; \
})
/* Extract byte macros */
#define HEXAGON_V32_GET_B0(v) \
Lint: Pre-merge checks
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clang-format: please reformat the code

-#define HEXAGON_V32_GET_B0(v)                                                        \
+#define HEXAGON_V32_GET_B0(v)                                                  \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V32_GET_B0(v)…
__extension__({ \
union { \
int w; \
signed char b[4]; \
} _HEXAGON_V32_internal_union; \
Lint: Pre-merge checks
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clang-format: please reformat the code

-    } _HEXAGON_V32_internal_union;                                                   \
-    _HEXAGON_V32_internal_union.w = (v);                                             \
-    _HEXAGON_V32_internal_union.b[0];                                                \
+    } _HEXAGON_V32_internal_union;                                             \
+    _HEXAGON_V32_internal_union.w = (v);                                       \
+    _HEXAGON_V32_internal_union.b[0];                                          \
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V32_internal_union…
_HEXAGON_V32_internal_union.w = (v); \
_HEXAGON_V32_internal_union.b[0]; \
})
#define HEXAGON_V32_GET_B1(v) \
Lint: Pre-merge checks
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clang-format: please reformat the code

-#define HEXAGON_V32_GET_B1(v)                                                        \
+#define HEXAGON_V32_GET_B1(v)                                                  \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V32_GET_B1(v)…
__extension__({ \
union { \
int w; \
signed char b[4]; \
} _HEXAGON_V32_internal_union; \
Lint: Pre-merge checks
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clang-format: please reformat the code

-    } _HEXAGON_V32_internal_union;                                                   \
-    _HEXAGON_V32_internal_union.w = (v);                                             \
-    _HEXAGON_V32_internal_union.b[1];                                                \
+    } _HEXAGON_V32_internal_union;                                             \
+    _HEXAGON_V32_internal_union.w = (v);                                       \
+    _HEXAGON_V32_internal_union.b[1];                                          \
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V32_internal_union…
_HEXAGON_V32_internal_union.w = (v); \
_HEXAGON_V32_internal_union.b[1]; \
})
#define HEXAGON_V32_GET_B2(v) \
Lint: Pre-merge checks
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clang-format: please reformat the code

-#define HEXAGON_V32_GET_B2(v)                                                        \
+#define HEXAGON_V32_GET_B2(v)                                                  \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V32_GET_B2(v)…
__extension__({ \
union { \
int w; \
signed char b[4]; \
} _HEXAGON_V32_internal_union; \
Lint: Pre-merge checks
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clang-format: please reformat the code

-    } _HEXAGON_V32_internal_union;                                                   \
-    _HEXAGON_V32_internal_union.w = (v);                                             \
-    _HEXAGON_V32_internal_union.b[2];                                                \
+    } _HEXAGON_V32_internal_union;                                             \
+    _HEXAGON_V32_internal_union.w = (v);                                       \
+    _HEXAGON_V32_internal_union.b[2];                                          \
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V32_internal_union…
_HEXAGON_V32_internal_union.w = (v); \
_HEXAGON_V32_internal_union.b[2]; \
})
#define HEXAGON_V32_GET_B3(v) \
Lint: Pre-merge checks
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clang-format: please reformat the code

-#define HEXAGON_V32_GET_B3(v)                                                        \
+#define HEXAGON_V32_GET_B3(v)                                                  \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V32_GET_B3(v)…
__extension__({ \
union { \
int w; \
signed char b[4]; \
} _HEXAGON_V32_internal_union; \
Lint: Pre-merge checks
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clang-format: please reformat the code

-    } _HEXAGON_V32_internal_union;                                                   \
-    _HEXAGON_V32_internal_union.w = (v);                                             \
-    _HEXAGON_V32_internal_union.b[3];                                                \
+    } _HEXAGON_V32_internal_union;                                             \
+    _HEXAGON_V32_internal_union.w = (v);                                       \
+    _HEXAGON_V32_internal_union.b[3];                                          \
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V32_internal_union…
_HEXAGON_V32_internal_union.w = (v); \
_HEXAGON_V32_internal_union.b[3]; \
})
#define HEXAGON_V32_GET_UB0(v) \
Lint: Pre-merge checks
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clang-format: please reformat the code

-#define HEXAGON_V32_GET_UB0(v)                                                       \
+#define HEXAGON_V32_GET_UB0(v)                                                 \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V32_GET_UB0(v)…
__extension__({ \
union { \
int w; \
unsigned char ub[4]; \
} _HEXAGON_V32_internal_union; \
Lint: Pre-merge checks
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clang-format: please reformat the code

-    } _HEXAGON_V32_internal_union;                                                   \
-    _HEXAGON_V32_internal_union.w = (v);                                             \
-    _HEXAGON_V32_internal_union.ub[0];                                               \
+    } _HEXAGON_V32_internal_union;                                             \
+    _HEXAGON_V32_internal_union.w = (v);                                       \
+    _HEXAGON_V32_internal_union.ub[0];                                         \
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V32_internal_union…
_HEXAGON_V32_internal_union.w = (v); \
_HEXAGON_V32_internal_union.ub[0]; \
})
#define HEXAGON_V32_GET_UB1(v) \
Lint: Pre-merge checks
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clang-format: please reformat the code

-#define HEXAGON_V32_GET_UB1(v)                                                       \
+#define HEXAGON_V32_GET_UB1(v)                                                 \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V32_GET_UB1(v)…
__extension__({ \
union { \
int w; \
unsigned char ub[4]; \
} _HEXAGON_V32_internal_union; \
Lint: Pre-merge checks
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clang-format: please reformat the code

-    } _HEXAGON_V32_internal_union;                                                   \
-    _HEXAGON_V32_internal_union.w = (v);                                             \
-    _HEXAGON_V32_internal_union.ub[1];                                               \
+    } _HEXAGON_V32_internal_union;                                             \
+    _HEXAGON_V32_internal_union.w = (v);                                       \
+    _HEXAGON_V32_internal_union.ub[1];                                         \
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V32_internal_union…
_HEXAGON_V32_internal_union.w = (v); \
_HEXAGON_V32_internal_union.ub[1]; \
})
#define HEXAGON_V32_GET_UB2(v) \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define HEXAGON_V32_GET_UB2(v)                                                       \
+#define HEXAGON_V32_GET_UB2(v)                                                 \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V32_GET_UB2(v)…
__extension__({ \
union { \
int w; \
unsigned char ub[4]; \
} _HEXAGON_V32_internal_union; \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    } _HEXAGON_V32_internal_union;                                                   \
-    _HEXAGON_V32_internal_union.w = (v);                                             \
-    _HEXAGON_V32_internal_union.ub[2];                                               \
+    } _HEXAGON_V32_internal_union;                                             \
+    _HEXAGON_V32_internal_union.w = (v);                                       \
+    _HEXAGON_V32_internal_union.ub[2];                                         \
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V32_internal_union…
_HEXAGON_V32_internal_union.w = (v); \
_HEXAGON_V32_internal_union.ub[2]; \
})
#define HEXAGON_V32_GET_UB3(v) \
Lint: Pre-merge checks
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clang-format: please reformat the code

-#define HEXAGON_V32_GET_UB3(v)                                                       \
+#define HEXAGON_V32_GET_UB3(v)                                                 \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V32_GET_UB3(v)…
__extension__({ \
union { \
int w; \
unsigned char ub[4]; \
} _HEXAGON_V32_internal_union; \
Lint: Pre-merge checks
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clang-format: please reformat the code

-    } _HEXAGON_V32_internal_union;                                                   \
-    _HEXAGON_V32_internal_union.w = (v);                                             \
-    _HEXAGON_V32_internal_union.ub[3];                                               \
+    } _HEXAGON_V32_internal_union;                                             \
+    _HEXAGON_V32_internal_union.w = (v);                                       \
+    _HEXAGON_V32_internal_union.ub[3];                                         \
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V32_internal_union…
_HEXAGON_V32_internal_union.w = (v); \
_HEXAGON_V32_internal_union.ub[3]; \
})
/* NOTE: All set macros return a HEXAGON_Vect32 type */
/* Set word macro */
#define HEXAGON_V32_PUT_W(v, new) (new)
/* Set half word macros */
#ifdef __hexagon__
#define HEXAGON_V32_PUT_H0(v, new) \
Lint: Pre-merge checks
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clang-format: please reformat the code

-#define HEXAGON_V32_PUT_H0(v, new)                                                   \
+#define HEXAGON_V32_PUT_H0(v, new)                                             \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V32_PUT_H0(v, new)…
__extension__({ \
union { \
int w; \
short h[2]; \
} _HEXAGON_V32_internal_union; \
Lint: Pre-merge checks
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clang-format: please reformat the code

-    } _HEXAGON_V32_internal_union;                                                   \
-    _HEXAGON_V32_internal_union.w = (v);                                             \
-    _HEXAGON_V32_internal_union.h[0] = (new);                                        \
-    _HEXAGON_V32_internal_union.w;                                                   \
+    } _HEXAGON_V32_internal_union;                                             \
+    _HEXAGON_V32_internal_union.w = (v);                                       \
+    _HEXAGON_V32_internal_union.h[0] = (new);                                  \
+    _HEXAGON_V32_internal_union.w;                                             \
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V32_internal_union…
_HEXAGON_V32_internal_union.w = (v); \
_HEXAGON_V32_internal_union.h[0] = (new); \
_HEXAGON_V32_internal_union.w; \
})
#define HEXAGON_V32_PUT_H1(v, new) \
Lint: Pre-merge checks
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clang-format: please reformat the code

-#define HEXAGON_V32_PUT_H1(v, new)                                                   \
+#define HEXAGON_V32_PUT_H1(v, new)                                             \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V32_PUT_H1(v, new)…
__extension__({ \
union { \
int w; \
short h[2]; \
} _HEXAGON_V32_internal_union; \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    } _HEXAGON_V32_internal_union;                                                   \
-    _HEXAGON_V32_internal_union.w = (v);                                             \
-    _HEXAGON_V32_internal_union.h[1] = (new);                                        \
-    _HEXAGON_V32_internal_union.w;                                                   \
+    } _HEXAGON_V32_internal_union;                                             \
+    _HEXAGON_V32_internal_union.w = (v);                                       \
+    _HEXAGON_V32_internal_union.h[1] = (new);                                  \
+    _HEXAGON_V32_internal_union.w;                                             \
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V32_internal_union…
_HEXAGON_V32_internal_union.w = (v); \
_HEXAGON_V32_internal_union.h[1] = (new); \
_HEXAGON_V32_internal_union.w; \
})
#else /* !__hexagon__ */
#define HEXAGON_V32_PUT_H0(v, new) \
Lint: Pre-merge checks
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clang-format: please reformat the code

-#define HEXAGON_V32_PUT_H0(v, new)                                                   \
-  (((v) & 0xffff0000) | ((HEXAGON_Vect32)((unsigned short)(new))))
-#define HEXAGON_V32_PUT_H1(v, new) (((v) & 0x0000ffff) | (((HEXAGON_Vect32)(new)) << 16))
+#define HEXAGON_V32_PUT_H0(v, new)                                             \
+  (((v)&0xffff0000) | ((HEXAGON_Vect32)((unsigned short)(new))))
+#define HEXAGON_V32_PUT_H1(v, new)                                             \
+  (((v)&0x0000ffff) | (((HEXAGON_Vect32)(new)) << 16))
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V32_PUT_H0(v, new)…
(((v) & 0xffff0000) | ((HEXAGON_Vect32)((unsigned short)(new))))
#define HEXAGON_V32_PUT_H1(v, new) (((v) & 0x0000ffff) | (((HEXAGON_Vect32)(new)) << 16))
#endif /* !__hexagon__ */
/* Set byte macros */
#ifdef __hexagon__
#define HEXAGON_V32_PUT_B0(v, new) \
Lint: Pre-merge checks
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clang-format: please reformat the code

-#define HEXAGON_V32_PUT_B0(v, new)                                                   \
+#define HEXAGON_V32_PUT_B0(v, new)                                             \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V32_PUT_B0(v, new)…
__extension__({ \
union { \
int w; \
char b[4]; \
} _HEXAGON_V32_internal_union; \
Lint: Pre-merge checks
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clang-format: please reformat the code

-    } _HEXAGON_V32_internal_union;                                                   \
-    _HEXAGON_V32_internal_union.w = (v);                                             \
-    _HEXAGON_V32_internal_union.b[0] = (new);                                        \
-    _HEXAGON_V32_internal_union.w;                                                   \
+    } _HEXAGON_V32_internal_union;                                             \
+    _HEXAGON_V32_internal_union.w = (v);                                       \
+    _HEXAGON_V32_internal_union.b[0] = (new);                                  \
+    _HEXAGON_V32_internal_union.w;                                             \
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V32_internal_union…
_HEXAGON_V32_internal_union.w = (v); \
_HEXAGON_V32_internal_union.b[0] = (new); \
_HEXAGON_V32_internal_union.w; \
})
#define HEXAGON_V32_PUT_B1(v, new) \
Lint: Pre-merge checks
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clang-format: please reformat the code

-#define HEXAGON_V32_PUT_B1(v, new)                                                   \
+#define HEXAGON_V32_PUT_B1(v, new)                                             \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V32_PUT_B1(v, new)…
__extension__({ \
union { \
int w; \
char b[4]; \
} _HEXAGON_V32_internal_union; \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    } _HEXAGON_V32_internal_union;                                                   \
-    _HEXAGON_V32_internal_union.w = (v);                                             \
-    _HEXAGON_V32_internal_union.b[1] = (new);                                        \
-    _HEXAGON_V32_internal_union.w;                                                   \
+    } _HEXAGON_V32_internal_union;                                             \
+    _HEXAGON_V32_internal_union.w = (v);                                       \
+    _HEXAGON_V32_internal_union.b[1] = (new);                                  \
+    _HEXAGON_V32_internal_union.w;                                             \
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V32_internal_union…
_HEXAGON_V32_internal_union.w = (v); \
_HEXAGON_V32_internal_union.b[1] = (new); \
_HEXAGON_V32_internal_union.w; \
})
#define HEXAGON_V32_PUT_B2(v, new) \
Lint: Pre-merge checks
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clang-format: please reformat the code

-#define HEXAGON_V32_PUT_B2(v, new)                                                   \
+#define HEXAGON_V32_PUT_B2(v, new)                                             \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V32_PUT_B2(v, new)…
__extension__({ \
union { \
int w; \
char b[4]; \
} _HEXAGON_V32_internal_union; \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    } _HEXAGON_V32_internal_union;                                                   \
-    _HEXAGON_V32_internal_union.w = (v);                                             \
-    _HEXAGON_V32_internal_union.b[2] = (new);                                        \
-    _HEXAGON_V32_internal_union.w;                                                   \
+    } _HEXAGON_V32_internal_union;                                             \
+    _HEXAGON_V32_internal_union.w = (v);                                       \
+    _HEXAGON_V32_internal_union.b[2] = (new);                                  \
+    _HEXAGON_V32_internal_union.w;                                             \
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V32_internal_union…
_HEXAGON_V32_internal_union.w = (v); \
_HEXAGON_V32_internal_union.b[2] = (new); \
_HEXAGON_V32_internal_union.w; \
})
#define HEXAGON_V32_PUT_B3(v, new) \
Lint: Pre-merge checks
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clang-format: please reformat the code

-#define HEXAGON_V32_PUT_B3(v, new)                                                   \
+#define HEXAGON_V32_PUT_B3(v, new)                                             \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V32_PUT_B3(v, new)…
__extension__({ \
union { \
int w; \
char b[4]; \
} _HEXAGON_V32_internal_union; \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    } _HEXAGON_V32_internal_union;                                                   \
-    _HEXAGON_V32_internal_union.w = (v);                                             \
-    _HEXAGON_V32_internal_union.b[3] = (new);                                        \
-    _HEXAGON_V32_internal_union.w;                                                   \
+    } _HEXAGON_V32_internal_union;                                             \
+    _HEXAGON_V32_internal_union.w = (v);                                       \
+    _HEXAGON_V32_internal_union.b[3] = (new);                                  \
+    _HEXAGON_V32_internal_union.w;                                             \
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V32_internal_union…
_HEXAGON_V32_internal_union.w = (v); \
_HEXAGON_V32_internal_union.b[3] = (new); \
_HEXAGON_V32_internal_union.w; \
})
#else /* !__hexagon__ */
#define HEXAGON_V32_PUT_B0(v, new) \
Lint: Pre-merge checks
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clang-format: please reformat the code

-#define HEXAGON_V32_PUT_B0(v, new)                                                   \
-  (((v) & 0xffffff00) | ((HEXAGON_Vect32)((unsigned char)(new))))
-#define HEXAGON_V32_PUT_B1(v, new)                                                   \
-  (((v) & 0xffff00ff) | (((HEXAGON_Vect32)((unsigned char)(new))) << 8))
-#define HEXAGON_V32_PUT_B2(v, new)                                                   \
-  (((v) & 0xff00ffff) | (((HEXAGON_Vect32)((unsigned char)(new))) << 16))
-#define HEXAGON_V32_PUT_B3(v, new) (((v) & 0x00ffffff) | (((HEXAGON_Vect32)(new)) << 24))
+#define HEXAGON_V32_PUT_B0(v, new)                                             \
+  (((v)&0xffffff00) | ((HEXAGON_Vect32)((unsigned char)(new))))
+#define HEXAGON_V32_PUT_B1(v, new)                                             \

5 diff lines are omitted. See full path.

Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V32_PUT_B0(v, new)…
(((v) & 0xffffff00) | ((HEXAGON_Vect32)((unsigned char)(new))))
#define HEXAGON_V32_PUT_B1(v, new) \
(((v) & 0xffff00ff) | (((HEXAGON_Vect32)((unsigned char)(new))) << 8))
#define HEXAGON_V32_PUT_B2(v, new) \
(((v) & 0xff00ffff) | (((HEXAGON_Vect32)((unsigned char)(new))) << 16))
#define HEXAGON_V32_PUT_B3(v, new) (((v) & 0x00ffffff) | (((HEXAGON_Vect32)(new)) << 24))
#endif /* !__hexagon__ */
/* NOTE: All create macros return a HEXAGON_Vect32 type */
/* Create from a word */
#define HEXAGON_V32_CREATE_W(w) (w)
/* Create from half words */
#ifdef __hexagon__
#define HEXAGON_V32_CREATE_H(h1, h0) \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define HEXAGON_V32_CREATE_H(h1, h0)                                                 \
+#define HEXAGON_V32_CREATE_H(h1, h0)                                           \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V32_CREATE_H(h1, h0)…
__extension__({ \
union { \
long long d; \
short h[2]; \
} _HEXAGON_V32_internal_union; \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    } _HEXAGON_V32_internal_union;                                                   \
-    _HEXAGON_V32_internal_union.h[0] = (h0);                                         \
-    _HEXAGON_V32_internal_union.h[1] = (h1);                                         \
-    _HEXAGON_V32_internal_union.d;                                                   \
+    } _HEXAGON_V32_internal_union;                                             \
+    _HEXAGON_V32_internal_union.h[0] = (h0);                                   \
+    _HEXAGON_V32_internal_union.h[1] = (h1);                                   \
+    _HEXAGON_V32_internal_union.d;                                             \
Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V32_internal_union…
_HEXAGON_V32_internal_union.h[0] = (h0); \
_HEXAGON_V32_internal_union.h[1] = (h1); \
_HEXAGON_V32_internal_union.d; \
})
#else /* !__hexagon__ */
#define HEXAGON_V32_CREATE_H(h1, h0) \
Lint: Pre-merge checks
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clang-format: please reformat the code

-#define HEXAGON_V32_CREATE_H(h1, h0)                                                 \
-  ((((HEXAGON_Vect32)(h1)) << 16) | ((HEXAGON_Vect32)((h0) & 0xffff)))
+#define HEXAGON_V32_CREATE_H(h1, h0)                                           \
+  ((((HEXAGON_Vect32)(h1)) << 16) | ((HEXAGON_Vect32)((h0)&0xffff)))
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V32_CREATE_H(h1, h0)…
((((HEXAGON_Vect32)(h1)) << 16) | ((HEXAGON_Vect32)((h0) & 0xffff)))
#endif /* !__hexagon__ */
/* Create from bytes */
#ifdef __hexagon__
#define HEXAGON_V32_CREATE_B(b3, b2, b1, b0) \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define HEXAGON_V32_CREATE_B(b3, b2, b1, b0)                                         \
+#define HEXAGON_V32_CREATE_B(b3, b2, b1, b0)                                   \
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V32_CREATE_B(b3, b2, b1, b0)…
__extension__({ \
union { \
long long d; \
char b[4]; \
} _HEXAGON_V32_internal_union; \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-    } _HEXAGON_V32_internal_union;                                                   \
-    _HEXAGON_V32_internal_union.b[0] = (b0);                                         \
-    _HEXAGON_V32_internal_union.b[1] = (b1);                                         \
-    _HEXAGON_V32_internal_union.b[2] = (b2);                                         \
-    _HEXAGON_V32_internal_union.b[3] = (b3);                                         \
-    _HEXAGON_V32_internal_union.d;                                                   \
+    } _HEXAGON_V32_internal_union;                                             \
+    _HEXAGON_V32_internal_union.b[0] = (b0);                                   \
+    _HEXAGON_V32_internal_union.b[1] = (b1);                                   \
+    _HEXAGON_V32_internal_union.b[2] = (b2);                                   \

2 diff lines are omitted. See full path.

Lint: Pre-merge checks: clang-format: please reformat the code ``` - } _HEXAGON_V32_internal_union…
_HEXAGON_V32_internal_union.b[0] = (b0); \
_HEXAGON_V32_internal_union.b[1] = (b1); \
_HEXAGON_V32_internal_union.b[2] = (b2); \
_HEXAGON_V32_internal_union.b[3] = (b3); \
_HEXAGON_V32_internal_union.d; \
})
#else /* !__hexagon__ */
#define HEXAGON_V32_CREATE_B(b3, b2, b1, b0) \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define HEXAGON_V32_CREATE_B(b3, b2, b1, b0)                                         \
-  ((((HEXAGON_Vect32)(b3)) << 24) | (((HEXAGON_Vect32)((b2) & 0xff)) << 16) |              \
-   (((HEXAGON_Vect32)((b1) & 0xff)) << 8) | ((HEXAGON_Vect32)((b0) & 0xff)))
+#define HEXAGON_V32_CREATE_B(b3, b2, b1, b0)                                   \
+  ((((HEXAGON_Vect32)(b3)) << 24) | (((HEXAGON_Vect32)((b2)&0xff)) << 16) |    \
+   (((HEXAGON_Vect32)((b1)&0xff)) << 8) | ((HEXAGON_Vect32)((b0)&0xff)))
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_V32_CREATE_B(b3, b2, b1, b0)…
((((HEXAGON_Vect32)(b3)) << 24) | (((HEXAGON_Vect32)((b2) & 0xff)) << 16) | \
(((HEXAGON_Vect32)((b1) & 0xff)) << 8) | ((HEXAGON_Vect32)((b0) & 0xff)))
#endif /* !__hexagon__ */
#ifdef __cplusplus
class HEXAGON_Vect32C {
public:
// Constructors
HEXAGON_Vect32C(int w = 0) : data(w) {};
Lint: Pre-merge checks
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clang-format: please reformat the code

-  HEXAGON_Vect32C(int w = 0) : data(w) {};
-  HEXAGON_Vect32C(short h1, short h0) : data(HEXAGON_V32_CREATE_H(h1, h0)) {};
-  HEXAGON_Vect32C(signed char b3, signed char b2, signed char b1, signed char b0)
-      : data(HEXAGON_V32_CREATE_B(b3, b2, b1, b0)) {};
-  HEXAGON_Vect32C(const HEXAGON_Vect32C &v) : data(v.data) {};
+  HEXAGON_Vect32C(int w = 0) : data(w){};
+  HEXAGON_Vect32C(short h1, short h0) : data(HEXAGON_V32_CREATE_H(h1, h0)){};
+  HEXAGON_Vect32C(signed char b3, signed char b2, signed char b1,
+                  signed char b0)
+      : data(HEXAGON_V32_CREATE_B(b3, b2, b1, b0)){};
+  HEXAGON_Vect32C(const HEXAGON_Vect32C &v) : data(v.data){};
Lint: Pre-merge checks: clang-format: please reformat the code ``` - HEXAGON_Vect32C(int w = 0) : data(w) {}…
HEXAGON_Vect32C(short h1, short h0) : data(HEXAGON_V32_CREATE_H(h1, h0)) {};
HEXAGON_Vect32C(signed char b3, signed char b2, signed char b1, signed char b0)
: data(HEXAGON_V32_CREATE_B(b3, b2, b1, b0)) {};
HEXAGON_Vect32C(const HEXAGON_Vect32C &v) : data(v.data) {};
HEXAGON_Vect32C &operator=(const HEXAGON_Vect32C &v) {
data = v.data;
return *this;
};
operator int() {
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  operator int() {
-    return data;
-  };
+  operator int() { return data; };
Lint: Pre-merge checks: clang-format: please reformat the code ``` - operator int() { - return data; - }; +…
return data;
};
// Extract word methods
int W(void) {
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  int W(void) {
-    return HEXAGON_V32_GET_W(data);
-  };
-  unsigned int UW(void) {
-    return HEXAGON_V32_GET_UW(data);
-  };
+  int W(void) { return HEXAGON_V32_GET_W(data); };
+  unsigned int UW(void) { return HEXAGON_V32_GET_UW(data); };
Lint: Pre-merge checks: clang-format: please reformat the code ``` - int W(void) { - return HEXAGON_V32_GET_W(data)…
return HEXAGON_V32_GET_W(data);
};
unsigned int UW(void) {
return HEXAGON_V32_GET_UW(data);
};
// Extract half word methods
short H0(void) {
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clang-format: please reformat the code

-  short H0(void) {
-    return HEXAGON_V32_GET_H0(data);
-  };
-  short H1(void) {
-    return HEXAGON_V32_GET_H1(data);
-  };
-  unsigned short UH0(void) {
-    return HEXAGON_V32_GET_UH0(data);
-  };
-  unsigned short UH1(void) {

6 diff lines are omitted. See full path.

Lint: Pre-merge checks: clang-format: please reformat the code ``` - short H0(void) { - return HEXAGON_V32_GET_H0…
return HEXAGON_V32_GET_H0(data);
};
short H1(void) {
return HEXAGON_V32_GET_H1(data);
};
unsigned short UH0(void) {
return HEXAGON_V32_GET_UH0(data);
};
unsigned short UH1(void) {
return HEXAGON_V32_GET_UH1(data);
};
// Extract byte methods
signed char B0(void) {
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clang-format: please reformat the code

-  signed char B0(void) {
-    return HEXAGON_V32_GET_B0(data);
-  };
-  signed char B1(void) {
-    return HEXAGON_V32_GET_B1(data);
-  };
-  signed char B2(void) {
-    return HEXAGON_V32_GET_B2(data);
-  };
-  signed char B3(void) {

22 diff lines are omitted. See full path.

Lint: Pre-merge checks: clang-format: please reformat the code ``` - signed char B0(void) { - return…
return HEXAGON_V32_GET_B0(data);
};
signed char B1(void) {
return HEXAGON_V32_GET_B1(data);
};
signed char B2(void) {
return HEXAGON_V32_GET_B2(data);
};
signed char B3(void) {
return HEXAGON_V32_GET_B3(data);
};
unsigned char UB0(void) {
return HEXAGON_V32_GET_UB0(data);
};
unsigned char UB1(void) {
return HEXAGON_V32_GET_UB1(data);
};
unsigned char UB2(void) {
return HEXAGON_V32_GET_UB2(data);
};
unsigned char UB3(void) {
return HEXAGON_V32_GET_UB3(data);
};
// NOTE: All set methods return a HEXAGON_Vect32C type
// Set word method
HEXAGON_Vect32C W(int w) {
return HEXAGON_Vect32C(HEXAGON_V32_PUT_W(data, w));
};
// Set half word methods
HEXAGON_Vect32C H0(short h) {
return HEXAGON_Vect32C(HEXAGON_V32_PUT_H0(data, h));
};
HEXAGON_Vect32C H1(short h) {
return HEXAGON_Vect32C(HEXAGON_V32_PUT_H1(data, h));
};
// Set byte methods
HEXAGON_Vect32C B0(signed char b) {
return HEXAGON_Vect32C(HEXAGON_V32_PUT_B0(data, b));
};
HEXAGON_Vect32C B1(signed char b) {
return HEXAGON_Vect32C(HEXAGON_V32_PUT_B1(data, b));
};
HEXAGON_Vect32C B2(signed char b) {
return HEXAGON_Vect32C(HEXAGON_V32_PUT_B2(data, b));
};
HEXAGON_Vect32C B3(signed char b) {
return HEXAGON_Vect32C(HEXAGON_V32_PUT_B3(data, b));
};
private:
int data;
};
#endif /* __cplusplus */
// V65 Silver types
#if __Q6S_ARCH__ >= 65
// Silver vector types are 128 bytes, and pairs are 256. The vector predicate
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clang-format: please reformat the code

-  // Silver vector types are 128 bytes, and pairs are 256. The vector predicate
-  // types are 16 bytes and 32 bytes for pairs.
-  typedef long HEXAGON_VecPred128 __attribute__((__vector_size__(16)))
-    __attribute__((aligned(128)));
+// Silver vector types are 128 bytes, and pairs are 256. The vector predicate
+// types are 16 bytes and 32 bytes for pairs.
+typedef long HEXAGON_VecPred128 __attribute__((__vector_size__(16)))
+__attribute__((aligned(128)));
Lint: Pre-merge checks: clang-format: please reformat the code ``` - // Silver vector types are 128 bytes, and pairs…
// types are 16 bytes and 32 bytes for pairs.
typedef long HEXAGON_VecPred128 __attribute__((__vector_size__(16)))
__attribute__((aligned(128)));
typedef long HEXAGON_VecPred256 __attribute__((__vector_size__(32)))
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clang-format: please reformat the code

-  typedef long HEXAGON_VecPred256 __attribute__((__vector_size__(32)))
-    __attribute__((aligned(128)));
+typedef long HEXAGON_VecPred256 __attribute__((__vector_size__(32)))
+__attribute__((aligned(128)));
Lint: Pre-merge checks: clang-format: please reformat the code ``` - typedef long HEXAGON_VecPred256 __attribute__…
__attribute__((aligned(128)));
typedef long HEXAGON_Vect1024 __attribute__((__vector_size__(128)))
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clang-format: please reformat the code

-  typedef long HEXAGON_Vect1024 __attribute__((__vector_size__(128)))
-    __attribute__((aligned(128)));
+typedef long HEXAGON_Vect1024 __attribute__((__vector_size__(128)))
+__attribute__((aligned(128)));
Lint: Pre-merge checks: clang-format: please reformat the code ``` - typedef long HEXAGON_Vect1024 __attribute__…
__attribute__((aligned(128)));
typedef long HEXAGON_Vect2048 __attribute__((__vector_size__(256)))
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clang-format: please reformat the code

-  typedef long HEXAGON_Vect2048 __attribute__((__vector_size__(256)))
-    __attribute__((aligned(256)));
+typedef long HEXAGON_Vect2048 __attribute__((__vector_size__(256)))
+__attribute__((aligned(256)));
Lint: Pre-merge checks: clang-format: please reformat the code ``` - typedef long HEXAGON_Vect2048 __attribute__…
__attribute__((aligned(256)));
typedef long HEXAGON_UVect1024 __attribute__((__vector_size__(128)))
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clang-format: please reformat the code

-  typedef long HEXAGON_UVect1024 __attribute__((__vector_size__(128)))
-    __attribute__((aligned(4)));
+typedef long HEXAGON_UVect1024 __attribute__((__vector_size__(128)))
+__attribute__((aligned(4)));
Lint: Pre-merge checks: clang-format: please reformat the code ``` - typedef long HEXAGON_UVect1024 __attribute__…
__attribute__((aligned(4)));
typedef long HEXAGON_UVect2048 __attribute__((__vector_size__(256)))
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clang-format: please reformat the code

-  typedef long HEXAGON_UVect2048 __attribute__((__vector_size__(256)))
-    __attribute__((aligned(4)));
+typedef long HEXAGON_UVect2048 __attribute__((__vector_size__(256)))
+__attribute__((aligned(4)));
Lint: Pre-merge checks: clang-format: please reformat the code ``` - typedef long HEXAGON_UVect2048 __attribute__…
__attribute__((aligned(4)));
#define Q6S_VectorPredPair HEXAGON_VecPred256
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-  #define Q6S_VectorPredPair HEXAGON_VecPred256
-  #define Q6S_VectorPred     HEXAGON_VecPred128
-  #define Q6S_Vector         HEXAGON_Vect1024
-  #define Q6S_VectorPair     HEXAGON_Vect2048
-  #define Q6S_UVector        HEXAGON_UVect1024
-  #define Q6S_UVectorPair    HEXAGON_UVect2048
+#define Q6S_VectorPredPair HEXAGON_VecPred256
+#define Q6S_VectorPred HEXAGON_VecPred128
+#define Q6S_Vector HEXAGON_Vect1024
+#define Q6S_VectorPair HEXAGON_Vect2048

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Lint: Pre-merge checks: clang-format: please reformat the code ``` - #define Q6S_VectorPredPair HEXAGON_VecPred256…
#define Q6S_VectorPred HEXAGON_VecPred128
#define Q6S_Vector HEXAGON_Vect1024
#define Q6S_VectorPair HEXAGON_Vect2048
#define Q6S_UVector HEXAGON_UVect1024
#define Q6S_UVectorPair HEXAGON_UVect2048
#else /* __Q6S_ARCH__ >= 65 */
// V65 Vector types
#if __HVX_ARCH__ >= 65
#if defined __HVX__ && (__HVX_LENGTH__ == 128)
typedef long HEXAGON_VecPred128 __attribute__((__vector_size__(128)))
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clang-format: please reformat the code

-  typedef long HEXAGON_VecPred128 __attribute__((__vector_size__(128)))
-    __attribute__((aligned(128)));
+typedef long HEXAGON_VecPred128 __attribute__((__vector_size__(128)))
+__attribute__((aligned(128)));
Lint: Pre-merge checks: clang-format: please reformat the code ``` - typedef long HEXAGON_VecPred128 __attribute__…
__attribute__((aligned(128)));
typedef long HEXAGON_Vect1024 __attribute__((__vector_size__(128)))
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clang-format: please reformat the code

-  typedef long HEXAGON_Vect1024 __attribute__((__vector_size__(128)))
-    __attribute__((aligned(128)));
+typedef long HEXAGON_Vect1024 __attribute__((__vector_size__(128)))
+__attribute__((aligned(128)));
Lint: Pre-merge checks: clang-format: please reformat the code ``` - typedef long HEXAGON_Vect1024 __attribute__…
__attribute__((aligned(128)));
typedef long HEXAGON_Vect2048 __attribute__((__vector_size__(256)))
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clang-format: please reformat the code

-  typedef long HEXAGON_Vect2048 __attribute__((__vector_size__(256)))
-    __attribute__((aligned(256)));
+typedef long HEXAGON_Vect2048 __attribute__((__vector_size__(256)))
+__attribute__((aligned(256)));
Lint: Pre-merge checks: clang-format: please reformat the code ``` - typedef long HEXAGON_Vect2048 __attribute__…
__attribute__((aligned(256)));
typedef long HEXAGON_UVect1024 __attribute__((__vector_size__(128)))
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clang-format: please reformat the code

-  typedef long HEXAGON_UVect1024 __attribute__((__vector_size__(128)))
-    __attribute__((aligned(4)));
+typedef long HEXAGON_UVect1024 __attribute__((__vector_size__(128)))
+__attribute__((aligned(4)));
Lint: Pre-merge checks: clang-format: please reformat the code ``` - typedef long HEXAGON_UVect1024 __attribute__…
__attribute__((aligned(4)));
typedef long HEXAGON_UVect2048 __attribute__((__vector_size__(256)))
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clang-format: please reformat the code

-  typedef long HEXAGON_UVect2048 __attribute__((__vector_size__(256)))
-    __attribute__((aligned(4)));
+typedef long HEXAGON_UVect2048 __attribute__((__vector_size__(256)))
+__attribute__((aligned(4)));
Lint: Pre-merge checks: clang-format: please reformat the code ``` - typedef long HEXAGON_UVect2048 __attribute__…
__attribute__((aligned(4)));
#define HVX_VectorPred HEXAGON_VecPred128
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-  #define HVX_VectorPred     HEXAGON_VecPred128
-  #define HVX_Vector         HEXAGON_Vect1024
-  #define HVX_VectorPair     HEXAGON_Vect2048
-  #define HVX_UVector        HEXAGON_UVect1024
-  #define HVX_UVectorPair    HEXAGON_UVect2048
+#define HVX_VectorPred HEXAGON_VecPred128
+#define HVX_Vector HEXAGON_Vect1024
+#define HVX_VectorPair HEXAGON_Vect2048
+#define HVX_UVector HEXAGON_UVect1024
+#define HVX_UVectorPair HEXAGON_UVect2048
Lint: Pre-merge checks: clang-format: please reformat the code ``` - #define HVX_VectorPred HEXAGON_VecPred128…
#define HVX_Vector HEXAGON_Vect1024
#define HVX_VectorPair HEXAGON_Vect2048
#define HVX_UVector HEXAGON_UVect1024
#define HVX_UVectorPair HEXAGON_UVect2048
#else /* defined __HVX__ && (__HVX_LENGTH__ == 128) */
#if defined __HVX__ && (__HVX_LENGTH__ == 64)
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clang-format: please reformat the code

-#if defined __HVX__ &&  (__HVX_LENGTH__ == 64)
-  typedef long HEXAGON_VecPred64 __attribute__((__vector_size__(64)))
-    __attribute__((aligned(64)));
+#if defined __HVX__ && (__HVX_LENGTH__ == 64)
+typedef long HEXAGON_VecPred64 __attribute__((__vector_size__(64)))
+__attribute__((aligned(64)));
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#if defined __HVX__ && (__HVX_LENGTH__ == 64)…
typedef long HEXAGON_VecPred64 __attribute__((__vector_size__(64)))
__attribute__((aligned(64)));
typedef long HEXAGON_Vect512 __attribute__((__vector_size__(64)))
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clang-format: please reformat the code

-  typedef long HEXAGON_Vect512 __attribute__((__vector_size__(64)))
-    __attribute__((aligned(64)));
+typedef long HEXAGON_Vect512 __attribute__((__vector_size__(64)))
+__attribute__((aligned(64)));
Lint: Pre-merge checks: clang-format: please reformat the code ``` - typedef long HEXAGON_Vect512 __attribute__…
__attribute__((aligned(64)));
typedef long HEXAGON_Vect1024 __attribute__((__vector_size__(128)))
Lint: Pre-merge checks
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clang-format: please reformat the code

-  typedef long HEXAGON_Vect1024 __attribute__((__vector_size__(128)))
-    __attribute__((aligned(128)));
+typedef long HEXAGON_Vect1024 __attribute__((__vector_size__(128)))
+__attribute__((aligned(128)));
Lint: Pre-merge checks: clang-format: please reformat the code ``` - typedef long HEXAGON_Vect1024 __attribute__…
__attribute__((aligned(128)));
typedef long HEXAGON_UVect512 __attribute__((__vector_size__(64)))
Lint: Pre-merge checks
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clang-format: please reformat the code

-  typedef long HEXAGON_UVect512 __attribute__((__vector_size__(64)))
-    __attribute__((aligned(4)));
+typedef long HEXAGON_UVect512 __attribute__((__vector_size__(64)))
+__attribute__((aligned(4)));
Lint: Pre-merge checks: clang-format: please reformat the code ``` - typedef long HEXAGON_UVect512 __attribute__…
__attribute__((aligned(4)));
typedef long HEXAGON_UVect1024 __attribute__((__vector_size__(128)))
Lint: Pre-merge checks
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clang-format: please reformat the code

-  typedef long HEXAGON_UVect1024 __attribute__((__vector_size__(128)))
-    __attribute__((aligned(4)));
+typedef long HEXAGON_UVect1024 __attribute__((__vector_size__(128)))
+__attribute__((aligned(4)));
Lint: Pre-merge checks: clang-format: please reformat the code ``` - typedef long HEXAGON_UVect1024 __attribute__…
__attribute__((aligned(4)));
#define HVX_VectorPred HEXAGON_VecPred64
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clang-format: please reformat the code

-  #define HVX_VectorPred     HEXAGON_VecPred64
-  #define HVX_Vector         HEXAGON_Vect512
-  #define HVX_VectorPair     HEXAGON_Vect1024
-  #define HVX_UVector        HEXAGON_UVect512
-  #define HVX_UVectorPair    HEXAGON_UVect1024
+#define HVX_VectorPred HEXAGON_VecPred64
+#define HVX_Vector HEXAGON_Vect512
+#define HVX_VectorPair HEXAGON_Vect1024
+#define HVX_UVector HEXAGON_UVect512
+#define HVX_UVectorPair HEXAGON_UVect1024
Lint: Pre-merge checks: clang-format: please reformat the code ``` - #define HVX_VectorPred HEXAGON_VecPred64…
#define HVX_Vector HEXAGON_Vect512
#define HVX_VectorPair HEXAGON_Vect1024
#define HVX_UVector HEXAGON_UVect512
#define HVX_UVectorPair HEXAGON_UVect1024
#endif /* defined __HVX__ && (__HVX_LENGTH__ == 64) */
#endif /* defined __HVX__ && (__HVX_LENGTH__ == 128) */
#endif /* __HVX_ARCH__ >= 65 */
#endif /* __Q6S_ARCH__ >= 65 */
/* Predicates */
typedef int HEXAGON_Pred;
/***
*** backward compatibility aliases
***/
/* Old names */
#define Q6Vect Q6Vect64
#define Q6V_GET_D Q6V64_GET_D
#define Q6V_GET_UD Q6V64_GET_UD
#define Q6V_GET_W0 Q6V64_GET_W0
#define Q6V_GET_W1 Q6V64_GET_W1
#define Q6V_GET_UW0 Q6V64_GET_UW0
#define Q6V_GET_UW1 Q6V64_GET_UW1
#define Q6V_GET_H0 Q6V64_GET_H0
#define Q6V_GET_H1 Q6V64_GET_H1
#define Q6V_GET_H2 Q6V64_GET_H2
#define Q6V_GET_H3 Q6V64_GET_H3
#define Q6V_GET_UH0 Q6V64_GET_UH0
#define Q6V_GET_UH1 Q6V64_GET_UH1
#define Q6V_GET_UH2 Q6V64_GET_UH2
#define Q6V_GET_UH3 Q6V64_GET_UH3
#define Q6V_GET_B0 Q6V64_GET_B0
#define Q6V_GET_B1 Q6V64_GET_B1
#define Q6V_GET_B2 Q6V64_GET_B2
#define Q6V_GET_B3 Q6V64_GET_B3
#define Q6V_GET_B4 Q6V64_GET_B4
#define Q6V_GET_B5 Q6V64_GET_B5
#define Q6V_GET_B6 Q6V64_GET_B6
#define Q6V_GET_B7 Q6V64_GET_B7
#define Q6V_GET_UB0 Q6V64_GET_UB0
#define Q6V_GET_UB1 Q6V64_GET_UB1
#define Q6V_GET_UB2 Q6V64_GET_UB2
#define Q6V_GET_UB3 Q6V64_GET_UB3
#define Q6V_GET_UB4 Q6V64_GET_UB4
#define Q6V_GET_UB5 Q6V64_GET_UB5
#define Q6V_GET_UB6 Q6V64_GET_UB6
#define Q6V_GET_UB7 Q6V64_GET_UB7
#define Q6V_PUT_D Q6V64_PUT_D
#define Q6V_PUT_W0 Q6V64_PUT_W0
#define Q6V_PUT_W1 Q6V64_PUT_W1
#define Q6V_PUT_H0 Q6V64_PUT_H0
#define Q6V_PUT_H1 Q6V64_PUT_H1
#define Q6V_PUT_H2 Q6V64_PUT_H2
#define Q6V_PUT_H3 Q6V64_PUT_H3
#define Q6V_PUT_B0 Q6V64_PUT_B0
#define Q6V_PUT_B1 Q6V64_PUT_B1
#define Q6V_PUT_B2 Q6V64_PUT_B2
#define Q6V_PUT_B3 Q6V64_PUT_B3
#define Q6V_PUT_B4 Q6V64_PUT_B4
#define Q6V_PUT_B5 Q6V64_PUT_B5
#define Q6V_PUT_B6 Q6V64_PUT_B6
#define Q6V_PUT_B7 Q6V64_PUT_B7
#define Q6V_CREATE_D Q6V64_CREATE_D
#define Q6V_CREATE_W Q6V64_CREATE_W
#define Q6V_CREATE_H Q6V64_CREATE_H
#define Q6V_CREATE_B Q6V64_CREATE_B
#ifdef __cplusplus
#define Q6VectC Q6Vect64C
#endif /* __cplusplus */
/* 64 Bit Vectors */
typedef long long __attribute__((__may_alias__)) Q6Vect64;
/* Extract doubleword macros */
#define Q6V64_GET_D(v) (v)
#define Q6V64_GET_UD(v) ((unsigned long long)(v))
/* Extract word macros */
#define Q6V64_GET_W0(v) \
__extension__({ \
union { \
long long d; \
int w[2]; \
} _Q6V64_internal_union; \
_Q6V64_internal_union.d = (v); \
_Q6V64_internal_union.w[0]; \
})
#define Q6V64_GET_W1(v) \
__extension__({ \
union { \
long long d; \
int w[2]; \
} _Q6V64_internal_union; \
_Q6V64_internal_union.d = (v); \
_Q6V64_internal_union.w[1]; \
})
#define Q6V64_GET_UW0(v) \
__extension__({ \
union { \
long long d; \
unsigned int uw[2]; \
} _Q6V64_internal_union; \
_Q6V64_internal_union.d = (v); \
_Q6V64_internal_union.uw[0]; \
})
#define Q6V64_GET_UW1(v) \
__extension__({ \
union { \
long long d; \
unsigned int uw[2]; \
} _Q6V64_internal_union; \
_Q6V64_internal_union.d = (v); \
_Q6V64_internal_union.uw[1]; \
})
/* Extract half word macros */
#define Q6V64_GET_H0(v) \
__extension__({ \
union { \
long long d; \
short h[4]; \
} _Q6V64_internal_union; \
_Q6V64_internal_union.d = (v); \
_Q6V64_internal_union.h[0]; \
})
#define Q6V64_GET_H1(v) \
__extension__({ \
union { \
long long d; \
short h[4]; \
} _Q6V64_internal_union; \
_Q6V64_internal_union.d = (v); \
_Q6V64_internal_union.h[1]; \
})
#define Q6V64_GET_H2(v) \
__extension__({ \
union { \
long long d; \
short h[4]; \
} _Q6V64_internal_union; \
_Q6V64_internal_union.d = (v); \
_Q6V64_internal_union.h[2]; \
})
#define Q6V64_GET_H3(v) \
__extension__({ \
union { \
long long d; \
short h[4]; \
} _Q6V64_internal_union; \
_Q6V64_internal_union.d = (v); \
_Q6V64_internal_union.h[3]; \
})
#define Q6V64_GET_UH0(v) \
__extension__({ \
union { \
long long d; \
unsigned short uh[4]; \
} _Q6V64_internal_union; \
_Q6V64_internal_union.d = (v); \
_Q6V64_internal_union.uh[0]; \
})
#define Q6V64_GET_UH1(v) \
__extension__({ \
union { \
long long d; \
unsigned short uh[4]; \
} _Q6V64_internal_union; \
_Q6V64_internal_union.d = (v); \
_Q6V64_internal_union.uh[1]; \
})
#define Q6V64_GET_UH2(v) \
__extension__({ \
union { \
long long d; \
unsigned short uh[4]; \
} _Q6V64_internal_union; \
_Q6V64_internal_union.d = (v); \
_Q6V64_internal_union.uh[2]; \
})
#define Q6V64_GET_UH3(v) \
__extension__({ \
union { \
long long d; \
unsigned short uh[4]; \
} _Q6V64_internal_union; \
_Q6V64_internal_union.d = (v); \
_Q6V64_internal_union.uh[3]; \
})
/* Extract byte macros */
#define Q6V64_GET_B0(v) \
__extension__({ \
union { \
long long d; \
signed char b[8]; \
} _Q6V64_internal_union; \
_Q6V64_internal_union.d = (v); \
_Q6V64_internal_union.b[0]; \
})
#define Q6V64_GET_B1(v) \
__extension__({ \
union { \
long long d; \
signed char b[8]; \
} _Q6V64_internal_union; \
_Q6V64_internal_union.d = (v); \
_Q6V64_internal_union.b[1]; \
})
#define Q6V64_GET_B2(v) \
__extension__({ \
union { \
long long d; \
signed char b[8]; \
} _Q6V64_internal_union; \
_Q6V64_internal_union.d = (v); \
_Q6V64_internal_union.b[2]; \
})
#define Q6V64_GET_B3(v) \
__extension__({ \
union { \
long long d; \
signed char b[8]; \
} _Q6V64_internal_union; \
_Q6V64_internal_union.d = (v); \
_Q6V64_internal_union.b[3]; \
})
#define Q6V64_GET_B4(v) \
__extension__({ \
union { \
long long d; \
signed char b[8]; \
} _Q6V64_internal_union; \
_Q6V64_internal_union.d = (v); \
_Q6V64_internal_union.b[4]; \
})
#define Q6V64_GET_B5(v) \
__extension__({ \
union { \
long long d; \
signed char b[8]; \
} _Q6V64_internal_union; \
_Q6V64_internal_union.d = (v); \
_Q6V64_internal_union.b[5]; \
})
#define Q6V64_GET_B6(v) \
__extension__({ \
union { \
long long d; \
signed char b[8]; \
} _Q6V64_internal_union; \
_Q6V64_internal_union.d = (v); \
_Q6V64_internal_union.b[6]; \
})
#define Q6V64_GET_B7(v) \
__extension__({ \
union { \
long long d; \
signed char b[8]; \
} _Q6V64_internal_union; \
_Q6V64_internal_union.d = (v); \
_Q6V64_internal_union.b[7]; \
})
#define Q6V64_GET_UB0(v) \
__extension__({ \
union { \
long long d; \
unsigned char ub[8]; \
} _Q6V64_internal_union; \
_Q6V64_internal_union.d = (v); \
_Q6V64_internal_union.ub[0]; \
})
#define Q6V64_GET_UB1(v) \
__extension__({ \
union { \
long long d; \
unsigned char ub[8]; \
} _Q6V64_internal_union; \
_Q6V64_internal_union.d = (v); \
_Q6V64_internal_union.ub[1]; \
})
#define Q6V64_GET_UB2(v) \
__extension__({ \
union { \
long long d; \
unsigned char ub[8]; \
} _Q6V64_internal_union; \
_Q6V64_internal_union.d = (v); \
_Q6V64_internal_union.ub[2]; \
})
#define Q6V64_GET_UB3(v) \
__extension__({ \
union { \
long long d; \
unsigned char ub[8]; \
} _Q6V64_internal_union; \
_Q6V64_internal_union.d = (v); \
_Q6V64_internal_union.ub[3]; \
})
#define Q6V64_GET_UB4(v) \
__extension__({ \
union { \
long long d; \
unsigned char ub[8]; \
} _Q6V64_internal_union; \
_Q6V64_internal_union.d = (v); \
_Q6V64_internal_union.ub[4]; \
})
#define Q6V64_GET_UB5(v) \
__extension__({ \
union { \
long long d; \
unsigned char ub[8]; \
} _Q6V64_internal_union; \
_Q6V64_internal_union.d = (v); \
_Q6V64_internal_union.ub[5]; \
})
#define Q6V64_GET_UB6(v) \
__extension__({ \
union { \
long long d; \
unsigned char ub[8]; \
} _Q6V64_internal_union; \
_Q6V64_internal_union.d = (v); \
_Q6V64_internal_union.ub[6]; \
})
#define Q6V64_GET_UB7(v) \
__extension__({ \
union { \
long long d; \
unsigned char ub[8]; \
} _Q6V64_internal_union; \
_Q6V64_internal_union.d = (v); \
_Q6V64_internal_union.ub[7]; \
})
/* NOTE: All set macros return a Q6Vect64 type */
/* Set doubleword macro */
#define Q6V64_PUT_D(v, new) (new)
/* Set word macros */
#ifdef __qdsp6__
#define Q6V64_PUT_W0(v, new) \
__extension__({ \
union { \
long long d; \
int w[2]; \
} _Q6V64_internal_union; \
_Q6V64_internal_union.d = (v); \
_Q6V64_internal_union.w[0] = (new); \
_Q6V64_internal_union.d; \
})
#define Q6V64_PUT_W1(v, new) \
__extension__({ \
union { \
long long d; \
int w[2]; \
} _Q6V64_internal_union; \
_Q6V64_internal_union.d = (v); \
_Q6V64_internal_union.w[1] = (new); \
_Q6V64_internal_union.d; \
})
#else /* !__qdsp6__ */
#define Q6V64_PUT_W0(v, new) \
(((v) & 0xffffffff00000000LL) | ((Q6Vect64)((unsigned int)(new))))
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  (((v) & 0xffffffff00000000LL) | ((Q6Vect64)((unsigned int)(new))))
+  (((v)&0xffffffff00000000LL) | ((Q6Vect64)((unsigned int)(new))))
Lint: Pre-merge checks: clang-format: please reformat the code ``` - (((v) & 0xffffffff00000000LL) | ((Q6Vect64)…
#define Q6V64_PUT_W1(v, new) \
(((v) & 0x00000000ffffffffLL) | (((Q6Vect64)(new)) << 32LL))
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  (((v) & 0x00000000ffffffffLL) | (((Q6Vect64)(new)) << 32LL))
+  (((v)&0x00000000ffffffffLL) | (((Q6Vect64)(new)) << 32LL))
Lint: Pre-merge checks: clang-format: please reformat the code ``` - (((v) & 0x00000000ffffffffLL) | (((Q6Vect64)…
#endif /* !__qdsp6__ */
/* Set half word macros */
#ifdef __qdsp6__
#define Q6V64_PUT_H0(v, new) \
__extension__({ \
union { \
long long d; \
short h[4]; \
} _Q6V64_internal_union; \
_Q6V64_internal_union.d = (v); \
_Q6V64_internal_union.h[0] = (new); \
_Q6V64_internal_union.d; \
})
#define Q6V64_PUT_H1(v, new) \
__extension__({ \
union { \
long long d; \
short h[4]; \
} _Q6V64_internal_union; \
_Q6V64_internal_union.d = (v); \
_Q6V64_internal_union.h[1] = (new); \
_Q6V64_internal_union.d; \
})
#define Q6V64_PUT_H2(v, new) \
__extension__({ \
union { \
long long d; \
short h[4]; \
} _Q6V64_internal_union; \
_Q6V64_internal_union.d = (v); \
_Q6V64_internal_union.h[2] = (new); \
_Q6V64_internal_union.d; \
})
#define Q6V64_PUT_H3(v, new) \
__extension__({ \
union { \
long long d; \
short h[4]; \
} _Q6V64_internal_union; \
_Q6V64_internal_union.d = (v); \
_Q6V64_internal_union.h[3] = (new); \
_Q6V64_internal_union.d; \
})
#else /* !__qdsp6__ */
#define Q6V64_PUT_H0(v, new) \
(((v) & 0xffffffffffff0000LL) | ((Q6Vect64)((unsigned short)(new))))
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  (((v) & 0xffffffffffff0000LL) | ((Q6Vect64)((unsigned short)(new))))
+  (((v)&0xffffffffffff0000LL) | ((Q6Vect64)((unsigned short)(new))))
Lint: Pre-merge checks: clang-format: please reformat the code ``` - (((v) & 0xffffffffffff0000LL) | ((Q6Vect64)…
#define Q6V64_PUT_H1(v, new) \
(((v) & 0xffffffff0000ffffLL) | (((Q6Vect64)((unsigned short)(new))) << 16LL))
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  (((v) & 0xffffffff0000ffffLL) | (((Q6Vect64)((unsigned short)(new))) << 16LL))
+  (((v)&0xffffffff0000ffffLL) | (((Q6Vect64)((unsigned short)(new))) << 16LL))
Lint: Pre-merge checks: clang-format: please reformat the code ``` - (((v) & 0xffffffff0000ffffLL) | (((Q6Vect64)…
#define Q6V64_PUT_H2(v, new) \
(((v) & 0xffff0000ffffffffLL) | (((Q6Vect64)((unsigned short)(new))) << 32LL))
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  (((v) & 0xffff0000ffffffffLL) | (((Q6Vect64)((unsigned short)(new))) << 32LL))
+  (((v)&0xffff0000ffffffffLL) | (((Q6Vect64)((unsigned short)(new))) << 32LL))
Lint: Pre-merge checks: clang-format: please reformat the code ``` - (((v) & 0xffff0000ffffffffLL) | (((Q6Vect64)…
#define Q6V64_PUT_H3(v, new) \
(((v) & 0x0000ffffffffffffLL) | (((Q6Vect64)(new)) << 48LL))
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  (((v) & 0x0000ffffffffffffLL) | (((Q6Vect64)(new)) << 48LL))
+  (((v)&0x0000ffffffffffffLL) | (((Q6Vect64)(new)) << 48LL))
Lint: Pre-merge checks: clang-format: please reformat the code ``` - (((v) & 0x0000ffffffffffffLL) | (((Q6Vect64)…
#endif /* !__qdsp6__ */
/* Set byte macros */
#ifdef __qdsp6__
#define Q6V64_PUT_B0(v, new) \
__extension__({ \
union { \
long long d; \
char b[8]; \
} _Q6V64_internal_union; \
_Q6V64_internal_union.d = (v); \
_Q6V64_internal_union.b[0] = (new); \
_Q6V64_internal_union.d; \
})
#define Q6V64_PUT_B1(v, new) \
__extension__({ \
union { \
long long d; \
char b[8]; \
} _Q6V64_internal_union; \
_Q6V64_internal_union.d = (v); \
_Q6V64_internal_union.b[1] = (new); \
_Q6V64_internal_union.d; \
})
#define Q6V64_PUT_B2(v, new) \
__extension__({ \
union { \
long long d; \
char b[8]; \
} _Q6V64_internal_union; \
_Q6V64_internal_union.d = (v); \
_Q6V64_internal_union.b[2] = (new); \
_Q6V64_internal_union.d; \
})
#define Q6V64_PUT_B3(v, new) \
__extension__({ \
union { \
long long d; \
char b[8]; \
} _Q6V64_internal_union; \
_Q6V64_internal_union.d = (v); \
_Q6V64_internal_union.b[3] = (new); \
_Q6V64_internal_union.d; \
})
#define Q6V64_PUT_B4(v, new) \
__extension__({ \
union { \
long long d; \
char b[8]; \
} _Q6V64_internal_union; \
_Q6V64_internal_union.d = (v); \
_Q6V64_internal_union.b[4] = (new); \
_Q6V64_internal_union.d; \
})
#define Q6V64_PUT_B5(v, new) \
__extension__({ \
union { \
long long d; \
char b[8]; \
} _Q6V64_internal_union; \
_Q6V64_internal_union.d = (v); \
_Q6V64_internal_union.b[5] = (new); \
_Q6V64_internal_union.d; \
})
#define Q6V64_PUT_B6(v, new) \
__extension__({ \
union { \
long long d; \
char b[8]; \
} _Q6V64_internal_union; \
_Q6V64_internal_union.d = (v); \
_Q6V64_internal_union.b[6] = (new); \
_Q6V64_internal_union.d; \
})
#define Q6V64_PUT_B7(v, new) \
__extension__({ \
union { \
long long d; \
char b[8]; \
} _Q6V64_internal_union; \
_Q6V64_internal_union.d = (v); \
_Q6V64_internal_union.b[7] = (new); \
_Q6V64_internal_union.d; \
})
#else /* !__qdsp6__ */
#define Q6V64_PUT_B0(v, new) \
(((v) & 0xffffffffffffff00LL) | ((Q6Vect64)((unsigned char)(new))))
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  (((v) & 0xffffffffffffff00LL) | ((Q6Vect64)((unsigned char)(new))))
+  (((v)&0xffffffffffffff00LL) | ((Q6Vect64)((unsigned char)(new))))
Lint: Pre-merge checks: clang-format: please reformat the code ``` - (((v) & 0xffffffffffffff00LL) | ((Q6Vect64)…
#define Q6V64_PUT_B1(v, new) \
(((v) & 0xffffffffffff00ffLL) | (((Q6Vect64)((unsigned char)(new))) << 8LL))
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  (((v) & 0xffffffffffff00ffLL) | (((Q6Vect64)((unsigned char)(new))) << 8LL))
+  (((v)&0xffffffffffff00ffLL) | (((Q6Vect64)((unsigned char)(new))) << 8LL))
Lint: Pre-merge checks: clang-format: please reformat the code ``` - (((v) & 0xffffffffffff00ffLL) | (((Q6Vect64)…
#define Q6V64_PUT_B2(v, new) \
(((v) & 0xffffffffff00ffffLL) | (((Q6Vect64)((unsigned char)(new))) << 16LL))
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  (((v) & 0xffffffffff00ffffLL) | (((Q6Vect64)((unsigned char)(new))) << 16LL))
+  (((v)&0xffffffffff00ffffLL) | (((Q6Vect64)((unsigned char)(new))) << 16LL))
Lint: Pre-merge checks: clang-format: please reformat the code ``` - (((v) & 0xffffffffff00ffffLL) | (((Q6Vect64)…
#define Q6V64_PUT_B3(v, new) \
(((v) & 0xffffffff00ffffffLL) | (((Q6Vect64)((unsigned char)(new))) << 24LL))
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  (((v) & 0xffffffff00ffffffLL) | (((Q6Vect64)((unsigned char)(new))) << 24LL))
+  (((v)&0xffffffff00ffffffLL) | (((Q6Vect64)((unsigned char)(new))) << 24LL))
Lint: Pre-merge checks: clang-format: please reformat the code ``` - (((v) & 0xffffffff00ffffffLL) | (((Q6Vect64)…
#define Q6V64_PUT_B4(v, new) \
(((v) & 0xffffff00ffffffffLL) | (((Q6Vect64)((unsigned char)(new))) << 32LL))
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  (((v) & 0xffffff00ffffffffLL) | (((Q6Vect64)((unsigned char)(new))) << 32LL))
+  (((v)&0xffffff00ffffffffLL) | (((Q6Vect64)((unsigned char)(new))) << 32LL))
Lint: Pre-merge checks: clang-format: please reformat the code ``` - (((v) & 0xffffff00ffffffffLL) | (((Q6Vect64)…
#define Q6V64_PUT_B5(v, new) \
(((v) & 0xffff00ffffffffffLL) | (((Q6Vect64)((unsigned char)(new))) << 40LL))
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  (((v) & 0xffff00ffffffffffLL) | (((Q6Vect64)((unsigned char)(new))) << 40LL))
+  (((v)&0xffff00ffffffffffLL) | (((Q6Vect64)((unsigned char)(new))) << 40LL))
Lint: Pre-merge checks: clang-format: please reformat the code ``` - (((v) & 0xffff00ffffffffffLL) | (((Q6Vect64)…
#define Q6V64_PUT_B6(v, new) \
(((v) & 0xff00ffffffffffffLL) | (((Q6Vect64)((unsigned char)(new))) << 48LL))
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  (((v) & 0xff00ffffffffffffLL) | (((Q6Vect64)((unsigned char)(new))) << 48LL))
+  (((v)&0xff00ffffffffffffLL) | (((Q6Vect64)((unsigned char)(new))) << 48LL))
Lint: Pre-merge checks: clang-format: please reformat the code ``` - (((v) & 0xff00ffffffffffffLL) | (((Q6Vect64)…
#define Q6V64_PUT_B7(v, new) \
(((v) & 0x00ffffffffffffffLL) | (((Q6Vect64)(new)) << 56LL))
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  (((v) & 0x00ffffffffffffffLL) | (((Q6Vect64)(new)) << 56LL))
+  (((v)&0x00ffffffffffffffLL) | (((Q6Vect64)(new)) << 56LL))
Lint: Pre-merge checks: clang-format: please reformat the code ``` - (((v) & 0x00ffffffffffffffLL) | (((Q6Vect64)…
#endif /* !__qdsp6__ */
/* NOTE: All create macros return a Q6Vect64 type */
/* Create from a doubleword */
#define Q6V64_CREATE_D(d) (d)
/* Create from words */
#ifdef __qdsp6__
#define Q6V64_CREATE_W(w1, w0) \
__extension__({ \
union { \
long long d; \
int w[2]; \
} _Q6V64_internal_union; \
_Q6V64_internal_union.w[0] = (w0); \
_Q6V64_internal_union.w[1] = (w1); \
_Q6V64_internal_union.d; \
})
#else /* !__qdsp6__ */
#define Q6V64_CREATE_W(w1, w0) \
((((Q6Vect64)(w1)) << 32LL) | ((Q6Vect64)((w0) & 0xffffffff)))
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  ((((Q6Vect64)(w1)) << 32LL) | ((Q6Vect64)((w0) & 0xffffffff)))
+  ((((Q6Vect64)(w1)) << 32LL) | ((Q6Vect64)((w0)&0xffffffff)))
Lint: Pre-merge checks: clang-format: please reformat the code ``` - ((((Q6Vect64)(w1)) << 32LL) | ((Q6Vect64)((w0) &…
#endif /* !__qdsp6__ */
/* Create from half words */
#ifdef __qdsp6__
#define Q6V64_CREATE_H(h3, h2, h1, h0) \
__extension__({ \
union { \
long long d; \
short h[4]; \
} _Q6V64_internal_union; \
_Q6V64_internal_union.h[0] = (h0); \
_Q6V64_internal_union.h[1] = (h1); \
_Q6V64_internal_union.h[2] = (h2); \
_Q6V64_internal_union.h[3] = (h3); \
_Q6V64_internal_union.d; \
})
#else /* !__qdsp6__ */
#define Q6V64_CREATE_H(h3, h2, h1, h0) \
((((Q6Vect64)(h3)) << 48LL) | (((Q6Vect64)((h2) & 0xffff)) << 32LL) | \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  ((((Q6Vect64)(h3)) << 48LL) | (((Q6Vect64)((h2) & 0xffff)) << 32LL) |        \
-   (((Q6Vect64)((h1) & 0xffff)) << 16LL) | ((Q6Vect64)((h0) & 0xffff)))
+  ((((Q6Vect64)(h3)) << 48LL) | (((Q6Vect64)((h2)&0xffff)) << 32LL) |          \
+   (((Q6Vect64)((h1)&0xffff)) << 16LL) | ((Q6Vect64)((h0)&0xffff)))
Lint: Pre-merge checks: clang-format: please reformat the code ``` - ((((Q6Vect64)(h3)) << 48LL) | (((Q6Vect64)((h2) &…
(((Q6Vect64)((h1) & 0xffff)) << 16LL) | ((Q6Vect64)((h0) & 0xffff)))
#endif /* !__qdsp6__ */
/* Create from bytes */
#ifdef __qdsp6__
#define Q6V64_CREATE_B(b7, b6, b5, b4, b3, b2, b1, b0) \
__extension__({ \
union { \
long long d; \
char b[8]; \
} _Q6V64_internal_union; \
_Q6V64_internal_union.b[0] = (b0); \
_Q6V64_internal_union.b[1] = (b1); \
_Q6V64_internal_union.b[2] = (b2); \
_Q6V64_internal_union.b[3] = (b3); \
_Q6V64_internal_union.b[4] = (b4); \
_Q6V64_internal_union.b[5] = (b5); \
_Q6V64_internal_union.b[6] = (b6); \
_Q6V64_internal_union.b[7] = (b7); \
_Q6V64_internal_union.d; \
})
#else /* !__qdsp6__ */
#define Q6V64_CREATE_B(b7, b6, b5, b4, b3, b2, b1, b0) \
((((Q6Vect64)(b7)) << 56LL) | (((Q6Vect64)((b6) & 0xff)) << 48LL) | \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  ((((Q6Vect64)(b7)) << 56LL) | (((Q6Vect64)((b6) & 0xff)) << 48LL) |          \
-   (((Q6Vect64)((b5) & 0xff)) << 40LL) | (((Q6Vect64)((b4) & 0xff)) << 32LL) | \
-   (((Q6Vect64)((b3) & 0xff)) << 24LL) | (((Q6Vect64)((b2) & 0xff)) << 16LL) | \
-   (((Q6Vect64)((b1) & 0xff)) << 8LL) | ((Q6Vect64)((b0) & 0xff)))
+  ((((Q6Vect64)(b7)) << 56LL) | (((Q6Vect64)((b6)&0xff)) << 48LL) |            \
+   (((Q6Vect64)((b5)&0xff)) << 40LL) | (((Q6Vect64)((b4)&0xff)) << 32LL) |     \
+   (((Q6Vect64)((b3)&0xff)) << 24LL) | (((Q6Vect64)((b2)&0xff)) << 16LL) |     \
+   (((Q6Vect64)((b1)&0xff)) << 8LL) | ((Q6Vect64)((b0)&0xff)))
Lint: Pre-merge checks: clang-format: please reformat the code ``` - ((((Q6Vect64)(b7)) << 56LL) | (((Q6Vect64)((b6) &…
(((Q6Vect64)((b5) & 0xff)) << 40LL) | (((Q6Vect64)((b4) & 0xff)) << 32LL) | \
(((Q6Vect64)((b3) & 0xff)) << 24LL) | (((Q6Vect64)((b2) & 0xff)) << 16LL) | \
(((Q6Vect64)((b1) & 0xff)) << 8LL) | ((Q6Vect64)((b0) & 0xff)))
#endif /* !__qdsp6__ */
#ifdef __cplusplus
class Q6Vect64C {
public:
// Constructors
Q6Vect64C(long long d = 0) : data(d) {};
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  Q6Vect64C(long long d = 0) : data(d) {};
-  Q6Vect64C(int w1, int w0) : data(Q6V64_CREATE_W(w1, w0)) {};
+  Q6Vect64C(long long d = 0) : data(d){};
+  Q6Vect64C(int w1, int w0) : data(Q6V64_CREATE_W(w1, w0)){};
Lint: Pre-merge checks: clang-format: please reformat the code ``` - Q6Vect64C(long long d = 0) : data(d) {}…
Q6Vect64C(int w1, int w0) : data(Q6V64_CREATE_W(w1, w0)) {};
Q6Vect64C(short h3, short h2, short h1, short h0)
: data(Q6V64_CREATE_H(h3, h2, h1, h0)) {};
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-      : data(Q6V64_CREATE_H(h3, h2, h1, h0)) {};
+      : data(Q6V64_CREATE_H(h3, h2, h1, h0)){};
Lint: Pre-merge checks: clang-format: please reformat the code ``` - : data(Q6V64_CREATE_H(h3, h2, h1, h0)) {}; +…
Q6Vect64C(signed char b7, signed char b6, signed char b5, signed char b4,
signed char b3, signed char b2, signed char b1, signed char b0)
: data(Q6V64_CREATE_B(b7, b6, b5, b4, b3, b2, b1, b0)) {};
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-      : data(Q6V64_CREATE_B(b7, b6, b5, b4, b3, b2, b1, b0)) {};
-  Q6Vect64C(const Q6Vect64C &v) : data(v.data) {};
+      : data(Q6V64_CREATE_B(b7, b6, b5, b4, b3, b2, b1, b0)){};
+  Q6Vect64C(const Q6Vect64C &v) : data(v.data){};
Lint: Pre-merge checks: clang-format: please reformat the code ``` - : data(Q6V64_CREATE_B(b7, b6, b5, b4, b3, b2…
Q6Vect64C(const Q6Vect64C &v) : data(v.data) {};
Q6Vect64C &operator=(const Q6Vect64C &v) {
data = v.data;
return *this;
};
operator long long() {
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  operator long long() {
-    return data;
-  };
+  operator long long() { return data; };
Lint: Pre-merge checks: clang-format: please reformat the code ``` - operator long long() { - return data; - }; +…
return data;
};
// Extract doubleword methods
long long D(void) {
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  long long D(void) {
-    return Q6V64_GET_D(data);
-  };
-  unsigned long long UD(void) {
-    return Q6V64_GET_UD(data);
-  };
+  long long D(void) { return Q6V64_GET_D(data); };
+  unsigned long long UD(void) { return Q6V64_GET_UD(data); };
Lint: Pre-merge checks: clang-format: please reformat the code ``` - long long D(void) { - return Q6V64_GET_D(data)…
return Q6V64_GET_D(data);
};
unsigned long long UD(void) {
return Q6V64_GET_UD(data);
};
// Extract word methods
int W0(void) {
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  int W0(void) {
-    return Q6V64_GET_W0(data);
-  };
-  int W1(void) {
-    return Q6V64_GET_W1(data);
-  };
-  unsigned int UW0(void) {
-    return Q6V64_GET_UW0(data);
-  };
-  unsigned int UW1(void) {

6 diff lines are omitted. See full path.

Lint: Pre-merge checks: clang-format: please reformat the code ``` - int W0(void) { - return Q6V64_GET_W0(data)…
return Q6V64_GET_W0(data);
};
int W1(void) {
return Q6V64_GET_W1(data);
};
unsigned int UW0(void) {
return Q6V64_GET_UW0(data);
};
unsigned int UW1(void) {
return Q6V64_GET_UW1(data);
};
// Extract half word methods
short H0(void) {
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  short H0(void) {
-    return Q6V64_GET_H0(data);
-  };
-  short H1(void) {
-    return Q6V64_GET_H1(data);
-  };
-  short H2(void) {
-    return Q6V64_GET_H2(data);
-  };
-  short H3(void) {

22 diff lines are omitted. See full path.

Lint: Pre-merge checks: clang-format: please reformat the code ``` - short H0(void) { - return Q6V64_GET_H0(data)…
return Q6V64_GET_H0(data);
};
short H1(void) {
return Q6V64_GET_H1(data);
};
short H2(void) {
return Q6V64_GET_H2(data);
};
short H3(void) {
return Q6V64_GET_H3(data);
};
unsigned short UH0(void) {
return Q6V64_GET_UH0(data);
};
unsigned short UH1(void) {
return Q6V64_GET_UH1(data);
};
unsigned short UH2(void) {
return Q6V64_GET_UH2(data);
};
unsigned short UH3(void) {
return Q6V64_GET_UH3(data);
};
// Extract byte methods
signed char B0(void) {
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  signed char B0(void) {
-    return Q6V64_GET_B0(data);
-  };
-  signed char B1(void) {
-    return Q6V64_GET_B1(data);
-  };
-  signed char B2(void) {
-    return Q6V64_GET_B2(data);
-  };
-  signed char B3(void) {

54 diff lines are omitted. See full path.

Lint: Pre-merge checks: clang-format: please reformat the code ``` - signed char B0(void) { - return Q6V64_GET_B0…
return Q6V64_GET_B0(data);
};
signed char B1(void) {
return Q6V64_GET_B1(data);
};
signed char B2(void) {
return Q6V64_GET_B2(data);
};
signed char B3(void) {
return Q6V64_GET_B3(data);
};
signed char B4(void) {
return Q6V64_GET_B4(data);
};
signed char B5(void) {
return Q6V64_GET_B5(data);
};
signed char B6(void) {
return Q6V64_GET_B6(data);
};
signed char B7(void) {
return Q6V64_GET_B7(data);
};
unsigned char UB0(void) {
return Q6V64_GET_UB0(data);
};
unsigned char UB1(void) {
return Q6V64_GET_UB1(data);
};
unsigned char UB2(void) {
return Q6V64_GET_UB2(data);
};
unsigned char UB3(void) {
return Q6V64_GET_UB3(data);
};
unsigned char UB4(void) {
return Q6V64_GET_UB4(data);
};
unsigned char UB5(void) {
return Q6V64_GET_UB5(data);
};
unsigned char UB6(void) {
return Q6V64_GET_UB6(data);
};
unsigned char UB7(void) {
return Q6V64_GET_UB7(data);
};
// NOTE: All set methods return a Q6Vect64C type
// Set doubleword method
Q6Vect64C D(long long d) {
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  Q6Vect64C D(long long d) {
-    return Q6Vect64C(Q6V64_PUT_D(data, d));
-  };
+  Q6Vect64C D(long long d) { return Q6Vect64C(Q6V64_PUT_D(data, d)); };
Lint: Pre-merge checks: clang-format: please reformat the code ``` - Q6Vect64C D(long long d) { - return Q6Vect64C…
return Q6Vect64C(Q6V64_PUT_D(data, d));
};
// Set word methods
Q6Vect64C W0(int w) {
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  Q6Vect64C W0(int w) {
-    return Q6Vect64C(Q6V64_PUT_W0(data, w));
-  };
-  Q6Vect64C W1(int w) {
-    return Q6Vect64C(Q6V64_PUT_W1(data, w));
-  };
+  Q6Vect64C W0(int w) { return Q6Vect64C(Q6V64_PUT_W0(data, w)); };
+  Q6Vect64C W1(int w) { return Q6Vect64C(Q6V64_PUT_W1(data, w)); };
Lint: Pre-merge checks: clang-format: please reformat the code ``` - Q6Vect64C W0(int w) { - return Q6Vect64C…
return Q6Vect64C(Q6V64_PUT_W0(data, w));
};
Q6Vect64C W1(int w) {
return Q6Vect64C(Q6V64_PUT_W1(data, w));
};
// Set half word methods
Q6Vect64C H0(short h) {
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  Q6Vect64C H0(short h) {
-    return Q6Vect64C(Q6V64_PUT_H0(data, h));
-  };
-  Q6Vect64C H1(short h) {
-    return Q6Vect64C(Q6V64_PUT_H1(data, h));
-  };
-  Q6Vect64C H2(short h) {
-    return Q6Vect64C(Q6V64_PUT_H2(data, h));
-  };
-  Q6Vect64C H3(short h) {

6 diff lines are omitted. See full path.

Lint: Pre-merge checks: clang-format: please reformat the code ``` - Q6Vect64C H0(short h) { - return Q6Vect64C…
return Q6Vect64C(Q6V64_PUT_H0(data, h));
};
Q6Vect64C H1(short h) {
return Q6Vect64C(Q6V64_PUT_H1(data, h));
};
Q6Vect64C H2(short h) {
return Q6Vect64C(Q6V64_PUT_H2(data, h));
};
Q6Vect64C H3(short h) {
return Q6Vect64C(Q6V64_PUT_H3(data, h));
};
// Set byte methods
Q6Vect64C B0(signed char b) {
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  Q6Vect64C B0(signed char b) {
-    return Q6Vect64C(Q6V64_PUT_B0(data, b));
-  };
-  Q6Vect64C B1(signed char b) {
-    return Q6Vect64C(Q6V64_PUT_B1(data, b));
-  };
-  Q6Vect64C B2(signed char b) {
-    return Q6Vect64C(Q6V64_PUT_B2(data, b));
-  };
-  Q6Vect64C B3(signed char b) {

22 diff lines are omitted. See full path.

Lint: Pre-merge checks: clang-format: please reformat the code ``` - Q6Vect64C B0(signed char b) { - return…
return Q6Vect64C(Q6V64_PUT_B0(data, b));
};
Q6Vect64C B1(signed char b) {
return Q6Vect64C(Q6V64_PUT_B1(data, b));
};
Q6Vect64C B2(signed char b) {
return Q6Vect64C(Q6V64_PUT_B2(data, b));
};
Q6Vect64C B3(signed char b) {
return Q6Vect64C(Q6V64_PUT_B3(data, b));
};
Q6Vect64C B4(signed char b) {
return Q6Vect64C(Q6V64_PUT_B4(data, b));
};
Q6Vect64C B5(signed char b) {
return Q6Vect64C(Q6V64_PUT_B5(data, b));
};
Q6Vect64C B6(signed char b) {
return Q6Vect64C(Q6V64_PUT_B6(data, b));
};
Q6Vect64C B7(signed char b) {
return Q6Vect64C(Q6V64_PUT_B7(data, b));
};
private:
long long data;
};
#endif /* __cplusplus */
/* 32 Bit Vectors */
typedef int Q6Vect32;
/* Extract word macros */
#define Q6V32_GET_W(v) (v)
#define Q6V32_GET_UW(v) ((unsigned int)(v))
/* Extract half word macros */
#define Q6V32_GET_H0(v) \
__extension__({ \
union { \
int w; \
short h[2]; \
} _Q6V32_internal_union; \
_Q6V32_internal_union.w = (v); \
_Q6V32_internal_union.h[0]; \
})
#define Q6V32_GET_H1(v) \
__extension__({ \
union { \
int w; \
short h[2]; \
} _Q6V32_internal_union; \
_Q6V32_internal_union.w = (v); \
_Q6V32_internal_union.h[1]; \
})
#define Q6V32_GET_UH0(v) \
__extension__({ \
union { \
int w; \
unsigned short uh[2]; \
} _Q6V32_internal_union; \
_Q6V32_internal_union.w = (v); \
_Q6V32_internal_union.uh[0]; \
})
#define Q6V32_GET_UH1(v) \
__extension__({ \
union { \
int w; \
unsigned short uh[2]; \
} _Q6V32_internal_union; \
_Q6V32_internal_union.w = (v); \
_Q6V32_internal_union.uh[1]; \
})
/* Extract byte macros */
#define Q6V32_GET_B0(v) \
__extension__({ \
union { \
int w; \
signed char b[4]; \
} _Q6V32_internal_union; \
_Q6V32_internal_union.w = (v); \
_Q6V32_internal_union.b[0]; \
})
#define Q6V32_GET_B1(v) \
__extension__({ \
union { \
int w; \
signed char b[4]; \
} _Q6V32_internal_union; \
_Q6V32_internal_union.w = (v); \
_Q6V32_internal_union.b[1]; \
})
#define Q6V32_GET_B2(v) \
__extension__({ \
union { \
int w; \
signed char b[4]; \
} _Q6V32_internal_union; \
_Q6V32_internal_union.w = (v); \
_Q6V32_internal_union.b[2]; \
})
#define Q6V32_GET_B3(v) \
__extension__({ \
union { \
int w; \
signed char b[4]; \
} _Q6V32_internal_union; \
_Q6V32_internal_union.w = (v); \
_Q6V32_internal_union.b[3]; \
})
#define Q6V32_GET_UB0(v) \
__extension__({ \
union { \
int w; \
unsigned char ub[4]; \
} _Q6V32_internal_union; \
_Q6V32_internal_union.w = (v); \
_Q6V32_internal_union.ub[0]; \
})
#define Q6V32_GET_UB1(v) \
__extension__({ \
union { \
int w; \
unsigned char ub[4]; \
} _Q6V32_internal_union; \
_Q6V32_internal_union.w = (v); \
_Q6V32_internal_union.ub[1]; \
})
#define Q6V32_GET_UB2(v) \
__extension__({ \
union { \
int w; \
unsigned char ub[4]; \
} _Q6V32_internal_union; \
_Q6V32_internal_union.w = (v); \
_Q6V32_internal_union.ub[2]; \
})
#define Q6V32_GET_UB3(v) \
__extension__({ \
union { \
int w; \
unsigned char ub[4]; \
} _Q6V32_internal_union; \
_Q6V32_internal_union.w = (v); \
_Q6V32_internal_union.ub[3]; \
})
/* NOTE: All set macros return a Q6Vect32 type */
/* Set word macro */
#define Q6V32_PUT_W(v, new) (new)
/* Set half word macros */
#ifdef __qdsp6__
#define Q6V32_PUT_H0(v, new) \
__extension__({ \
union { \
int w; \
short h[2]; \
} _Q6V32_internal_union; \
_Q6V32_internal_union.w = (v); \
_Q6V32_internal_union.h[0] = (new); \
_Q6V32_internal_union.w; \
})
#define Q6V32_PUT_H1(v, new) \
__extension__({ \
union { \
int w; \
short h[2]; \
} _Q6V32_internal_union; \
_Q6V32_internal_union.w = (v); \
_Q6V32_internal_union.h[1] = (new); \
_Q6V32_internal_union.w; \
})
#else /* !__qdsp6__ */
#define Q6V32_PUT_H0(v, new) \
(((v) & 0xffff0000) | ((Q6Vect32)((unsigned short)(new))))
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  (((v) & 0xffff0000) | ((Q6Vect32)((unsigned short)(new))))
-#define Q6V32_PUT_H1(v, new) (((v) & 0x0000ffff) | (((Q6Vect32)(new)) << 16))
+  (((v)&0xffff0000) | ((Q6Vect32)((unsigned short)(new))))
+#define Q6V32_PUT_H1(v, new) (((v)&0x0000ffff) | (((Q6Vect32)(new)) << 16))
Lint: Pre-merge checks: clang-format: please reformat the code ``` - (((v) & 0xffff0000) | ((Q6Vect32)((unsigned…
#define Q6V32_PUT_H1(v, new) (((v) & 0x0000ffff) | (((Q6Vect32)(new)) << 16))
#endif /* !__qdsp6__ */
/* Set byte macros */
#ifdef __qdsp6__
#define Q6V32_PUT_B0(v, new) \
__extension__({ \
union { \
int w; \
char b[4]; \
} _Q6V32_internal_union; \
_Q6V32_internal_union.w = (v); \
_Q6V32_internal_union.b[0] = (new); \
_Q6V32_internal_union.w; \
})
#define Q6V32_PUT_B1(v, new) \
__extension__({ \
union { \
int w; \
char b[4]; \
} _Q6V32_internal_union; \
_Q6V32_internal_union.w = (v); \
_Q6V32_internal_union.b[1] = (new); \
_Q6V32_internal_union.w; \
})
#define Q6V32_PUT_B2(v, new) \
__extension__({ \
union { \
int w; \
char b[4]; \
} _Q6V32_internal_union; \
_Q6V32_internal_union.w = (v); \
_Q6V32_internal_union.b[2] = (new); \
_Q6V32_internal_union.w; \
})
#define Q6V32_PUT_B3(v, new) \
__extension__({ \
union { \
int w; \
char b[4]; \
} _Q6V32_internal_union; \
_Q6V32_internal_union.w = (v); \
_Q6V32_internal_union.b[3] = (new); \
_Q6V32_internal_union.w; \
})
#else /* !__qdsp6__ */
#define Q6V32_PUT_B0(v, new) \
(((v) & 0xffffff00) | ((Q6Vect32)((unsigned char)(new))))
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  (((v) & 0xffffff00) | ((Q6Vect32)((unsigned char)(new))))
+  (((v)&0xffffff00) | ((Q6Vect32)((unsigned char)(new))))
Lint: Pre-merge checks: clang-format: please reformat the code ``` - (((v) & 0xffffff00) | ((Q6Vect32)((unsigned char)…
#define Q6V32_PUT_B1(v, new) \
(((v) & 0xffff00ff) | (((Q6Vect32)((unsigned char)(new))) << 8))
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  (((v) & 0xffff00ff) | (((Q6Vect32)((unsigned char)(new))) << 8))
+  (((v)&0xffff00ff) | (((Q6Vect32)((unsigned char)(new))) << 8))
Lint: Pre-merge checks: clang-format: please reformat the code ``` - (((v) & 0xffff00ff) | (((Q6Vect32)((unsigned…
#define Q6V32_PUT_B2(v, new) \
(((v) & 0xff00ffff) | (((Q6Vect32)((unsigned char)(new))) << 16))
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  (((v) & 0xff00ffff) | (((Q6Vect32)((unsigned char)(new))) << 16))
-#define Q6V32_PUT_B3(v, new) (((v) & 0x00ffffff) | (((Q6Vect32)(new)) << 24))
+  (((v)&0xff00ffff) | (((Q6Vect32)((unsigned char)(new))) << 16))
+#define Q6V32_PUT_B3(v, new) (((v)&0x00ffffff) | (((Q6Vect32)(new)) << 24))
Lint: Pre-merge checks: clang-format: please reformat the code ``` - (((v) & 0xff00ffff) | (((Q6Vect32)((unsigned…
#define Q6V32_PUT_B3(v, new) (((v) & 0x00ffffff) | (((Q6Vect32)(new)) << 24))
#endif /* !__qdsp6__ */
/* NOTE: All create macros return a Q6Vect32 type */
/* Create from a word */
#define Q6V32_CREATE_W(w) (w)
/* Create from half words */
#ifdef __qdsp6__
#define Q6V32_CREATE_H(h1, h0) \
__extension__({ \
union { \
long long d; \
short h[2]; \
} _Q6V32_internal_union; \
_Q6V32_internal_union.h[0] = (h0); \
_Q6V32_internal_union.h[1] = (h1); \
_Q6V32_internal_union.d; \
})
#else /* !__qdsp6__ */
#define Q6V32_CREATE_H(h1, h0) \
((((Q6Vect32)(h1)) << 16) | ((Q6Vect32)((h0) & 0xffff)))
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  ((((Q6Vect32)(h1)) << 16) | ((Q6Vect32)((h0) & 0xffff)))
+  ((((Q6Vect32)(h1)) << 16) | ((Q6Vect32)((h0)&0xffff)))
Lint: Pre-merge checks: clang-format: please reformat the code ``` - ((((Q6Vect32)(h1)) << 16) | ((Q6Vect32)((h0) &…
#endif /* !__qdsp6__ */
/* Create from bytes */
#ifdef __qdsp6__
#define Q6V32_CREATE_B(b3, b2, b1, b0) \
__extension__({ \
union { \
long long d; \
char b[4]; \
} _Q6V32_internal_union; \
_Q6V32_internal_union.b[0] = (b0); \
_Q6V32_internal_union.b[1] = (b1); \
_Q6V32_internal_union.b[2] = (b2); \
_Q6V32_internal_union.b[3] = (b3); \
_Q6V32_internal_union.d; \
})
#else /* !__qdsp6__ */
#define Q6V32_CREATE_B(b3, b2, b1, b0) \
((((Q6Vect32)(b3)) << 24) | (((Q6Vect32)((b2) & 0xff)) << 16) | \
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  ((((Q6Vect32)(b3)) << 24) | (((Q6Vect32)((b2) & 0xff)) << 16) |              \
-   (((Q6Vect32)((b1) & 0xff)) << 8) | ((Q6Vect32)((b0) & 0xff)))
+  ((((Q6Vect32)(b3)) << 24) | (((Q6Vect32)((b2)&0xff)) << 16) |                \
+   (((Q6Vect32)((b1)&0xff)) << 8) | ((Q6Vect32)((b0)&0xff)))
Lint: Pre-merge checks: clang-format: please reformat the code ``` - ((((Q6Vect32)(b3)) << 24) | (((Q6Vect32)((b2) &…
(((Q6Vect32)((b1) & 0xff)) << 8) | ((Q6Vect32)((b0) & 0xff)))
#endif /* !__qdsp6__ */
#ifdef __cplusplus
class Q6Vect32C {
public:
// Constructors
Q6Vect32C(int w = 0) : data(w) {};
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  Q6Vect32C(int w = 0) : data(w) {};
-  Q6Vect32C(short h1, short h0) : data(Q6V32_CREATE_H(h1, h0)) {};
+  Q6Vect32C(int w = 0) : data(w){};
+  Q6Vect32C(short h1, short h0) : data(Q6V32_CREATE_H(h1, h0)){};
Lint: Pre-merge checks: clang-format: please reformat the code ``` - Q6Vect32C(int w = 0) : data(w) {}; - Q6Vect32C…
Q6Vect32C(short h1, short h0) : data(Q6V32_CREATE_H(h1, h0)) {};
Q6Vect32C(signed char b3, signed char b2, signed char b1, signed char b0)
: data(Q6V32_CREATE_B(b3, b2, b1, b0)) {};
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-      : data(Q6V32_CREATE_B(b3, b2, b1, b0)) {};
-  Q6Vect32C(const Q6Vect32C &v) : data(v.data) {};
+      : data(Q6V32_CREATE_B(b3, b2, b1, b0)){};
+  Q6Vect32C(const Q6Vect32C &v) : data(v.data){};
Lint: Pre-merge checks: clang-format: please reformat the code ``` - : data(Q6V32_CREATE_B(b3, b2, b1, b0)) {}…
Q6Vect32C(const Q6Vect32C &v) : data(v.data) {};
Q6Vect32C &operator=(const Q6Vect32C &v) {
data = v.data;
return *this;
};
operator int() {
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  operator int() {
-    return data;
-  };
+  operator int() { return data; };
Lint: Pre-merge checks: clang-format: please reformat the code ``` - operator int() { - return data; - }; +…
return data;
};
// Extract word methods
int W(void) {
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-  int W(void) {
-    return Q6V32_GET_W(data);
-  };
-  unsigned int UW(void) {
-    return Q6V32_GET_UW(data);
-  };
+  int W(void) { return Q6V32_GET_W(data); };
+  unsigned int UW(void) { return Q6V32_GET_UW(data); };
Lint: Pre-merge checks: clang-format: please reformat the code ``` - int W(void) { - return Q6V32_GET_W(data); - }…
return Q6V32_GET_W(data);
};
unsigned int UW(void) {
return Q6V32_GET_UW(data);
};
// Extract half word methods
short H0(void) {
Lint: Pre-merge checks
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clang-format: please reformat the code

-  short H0(void) {
-    return Q6V32_GET_H0(data);
-  };
-  short H1(void) {
-    return Q6V32_GET_H1(data);
-  };
-  unsigned short UH0(void) {
-    return Q6V32_GET_UH0(data);
-  };
-  unsigned short UH1(void) {

6 diff lines are omitted. See full path.

Lint: Pre-merge checks: clang-format: please reformat the code ``` - short H0(void) { - return Q6V32_GET_H0(data)…
return Q6V32_GET_H0(data);
};
short H1(void) {
return Q6V32_GET_H1(data);
};
unsigned short UH0(void) {
return Q6V32_GET_UH0(data);
};
unsigned short UH1(void) {
return Q6V32_GET_UH1(data);
};
// Extract byte methods
signed char B0(void) {
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clang-format: please reformat the code

-  signed char B0(void) {
-    return Q6V32_GET_B0(data);
-  };
-  signed char B1(void) {
-    return Q6V32_GET_B1(data);
-  };
-  signed char B2(void) {
-    return Q6V32_GET_B2(data);
-  };
-  signed char B3(void) {

22 diff lines are omitted. See full path.

Lint: Pre-merge checks: clang-format: please reformat the code ``` - signed char B0(void) { - return Q6V32_GET_B0…
return Q6V32_GET_B0(data);
};
signed char B1(void) {
return Q6V32_GET_B1(data);
};
signed char B2(void) {
return Q6V32_GET_B2(data);
};
signed char B3(void) {
return Q6V32_GET_B3(data);
};
unsigned char UB0(void) {
return Q6V32_GET_UB0(data);
};
unsigned char UB1(void) {
return Q6V32_GET_UB1(data);
};
unsigned char UB2(void) {
return Q6V32_GET_UB2(data);
};
unsigned char UB3(void) {
return Q6V32_GET_UB3(data);
};
// NOTE: All set methods return a Q6Vect32C type
// Set word method
Q6Vect32C W(int w) {
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clang-format: please reformat the code

-  Q6Vect32C W(int w) {
-    return Q6Vect32C(Q6V32_PUT_W(data, w));
-  };
+  Q6Vect32C W(int w) { return Q6Vect32C(Q6V32_PUT_W(data, w)); };
Lint: Pre-merge checks: clang-format: please reformat the code ``` - Q6Vect32C W(int w) { - return Q6Vect32C…
return Q6Vect32C(Q6V32_PUT_W(data, w));
};
// Set half word methods
Q6Vect32C H0(short h) {
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clang-format: please reformat the code

-  Q6Vect32C H0(short h) {
-    return Q6Vect32C(Q6V32_PUT_H0(data, h));
-  };
-  Q6Vect32C H1(short h) {
-    return Q6Vect32C(Q6V32_PUT_H1(data, h));
-  };
+  Q6Vect32C H0(short h) { return Q6Vect32C(Q6V32_PUT_H0(data, h)); };
+  Q6Vect32C H1(short h) { return Q6Vect32C(Q6V32_PUT_H1(data, h)); };
Lint: Pre-merge checks: clang-format: please reformat the code ``` - Q6Vect32C H0(short h) { - return Q6Vect32C…
return Q6Vect32C(Q6V32_PUT_H0(data, h));
};
Q6Vect32C H1(short h) {
return Q6Vect32C(Q6V32_PUT_H1(data, h));
};
// Set byte methods
Q6Vect32C B0(signed char b) {
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clang-format: please reformat the code

-  Q6Vect32C B0(signed char b) {
-    return Q6Vect32C(Q6V32_PUT_B0(data, b));
-  };
-  Q6Vect32C B1(signed char b) {
-    return Q6Vect32C(Q6V32_PUT_B1(data, b));
-  };
-  Q6Vect32C B2(signed char b) {
-    return Q6Vect32C(Q6V32_PUT_B2(data, b));
-  };
-  Q6Vect32C B3(signed char b) {

6 diff lines are omitted. See full path.

Lint: Pre-merge checks: clang-format: please reformat the code ``` - Q6Vect32C B0(signed char b) { - return…
return Q6Vect32C(Q6V32_PUT_B0(data, b));
};
Q6Vect32C B1(signed char b) {
return Q6Vect32C(Q6V32_PUT_B1(data, b));
};
Q6Vect32C B2(signed char b) {
return Q6Vect32C(Q6V32_PUT_B2(data, b));
};
Q6Vect32C B3(signed char b) {
return Q6Vect32C(Q6V32_PUT_B3(data, b));
};
private:
int data;
};
#endif /* __cplusplus */
// V65 Vector types
#if __HVX_ARCH__ >= 65
#if defined __HVX__ && (__HVX_LENGTH__ == 128)
typedef long Q6VecPred128 __attribute__((__vector_size__(128)))
__attribute__((aligned(128)));
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clang-format: please reformat the code

-    __attribute__((aligned(128)));
+__attribute__((aligned(128)));
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typedef long Q6Vect1024 __attribute__((__vector_size__(128)))
__attribute__((aligned(128)));
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clang-format: please reformat the code

-    __attribute__((aligned(128)));
+__attribute__((aligned(128)));
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typedef long Q6Vect2048 __attribute__((__vector_size__(256)))
__attribute__((aligned(256)));
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clang-format: please reformat the code

-    __attribute__((aligned(256)));
+__attribute__((aligned(256)));
Lint: Pre-merge checks: clang-format: please reformat the code ``` - __attribute__((aligned(256))); +__attribute__…
#else /* defined __HVX__ && (__HVX_LENGTH__ == 128) */
#if defined __HVX__ && (__HVX_LENGTH__ == 64)
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clang-format: please reformat the code

-#if defined __HVX__ &&  (__HVX_LENGTH__ == 64)
+#if defined __HVX__ && (__HVX_LENGTH__ == 64)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#if defined __HVX__ && (__HVX_LENGTH__ == 64) +#if…
typedef long Q6VecPred64 __attribute__((__vector_size__(64)))
__attribute__((aligned(64)));
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clang-format: please reformat the code

-    __attribute__((aligned(64)));
+__attribute__((aligned(64)));
Lint: Pre-merge checks: clang-format: please reformat the code ``` - __attribute__((aligned(64))); +__attribute__…
typedef long Q6Vect512 __attribute__((__vector_size__(64)))
__attribute__((aligned(64)));
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clang-format: please reformat the code

-    __attribute__((aligned(64)));
+__attribute__((aligned(64)));
Lint: Pre-merge checks: clang-format: please reformat the code ``` - __attribute__((aligned(64))); +__attribute__…
typedef long Q6Vect1024 __attribute__((__vector_size__(128)))
__attribute__((aligned(128)));
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clang-format: please reformat the code

-    __attribute__((aligned(128)));
+__attribute__((aligned(128)));
Lint: Pre-merge checks: clang-format: please reformat the code ``` - __attribute__((aligned(128))); +__attribute__…
#endif /* defined __HVX__ && (__HVX_LENGTH__ == 64) */
#endif /* defined __HVX__ && (__HVX_LENGTH__ == 128) */
#endif /* __HVX_ARCH__ >= 65 */
/* Predicates */
typedef int Q6Pred;
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clang-format: please reformat the code

-
Lint: Pre-merge checks: clang-format: please reformat the code ``` - ```
#ifdef __HVX__
// Extract HVX VectorPair macro.
#define HEXAGON_HVX_GET_W(v) (v)
// Extract HVX Vector macros.
#define HEXAGON_HVX_GET_V0(v) \
__extension__({ \
union { \
HVX_VectorPair W; \
HVX_Vector V[2]; \
} _HEXAGON_HVX_internal_union; \
_HEXAGON_HVX_internal_union.W = (v); \
_HEXAGON_HVX_internal_union.V[0]; \
})
#define HEXAGON_HVX_GET_V1(v) \
__extension__({ \
union { \
HVX_VectorPair W; \
HVX_Vector V[2]; \
} _HEXAGON_HVX_internal_union; \
_HEXAGON_HVX_internal_union.W = (v); \
_HEXAGON_HVX_internal_union.V[1]; \
})
#define HEXAGON_HVX_GET_P(v) \
__extension__({ \
union { \
HVX_VectorPair W; \
HVX_VectorPred P[2]; \
} _HEXAGON_HVX_internal_union; \
_HEXAGON_HVX_internal_union.W = (v); \
_HEXAGON_HVX_internal_union.P[0]; \
})
// Set HVX VectorPair macro.
#define HEXAGON_HVX_PUT_W(v, new) (new)
// Set HVX Vector macros.
#define HEXAGON_HVX_PUT_V0(v, new) \
__extension__({ \
union { \
HVX_VectorPair W; \
HVX_Vector V[2]; \
} _HEXAGON_HVX_internal_union; \
_HEXAGON_HVX_internal_union.W = (v); \
_HEXAGON_HVX_internal_union.V[0] = (new); \
_HEXAGON_HVX_internal_union.W; \
})
#define HEXAGON_HVX_PUT_V1(v, new) \
__extension__({ \
union { \
HVX_VectorPair W; \
HVX_Vector V[2]; \
} _HEXAGON_HVX_internal_union; \
_HEXAGON_HVX_internal_union.W = (v); \
_HEXAGON_HVX_internal_union.V[1] = (new); \
_HEXAGON_HVX_internal_union.W; \
})
#define HEXAGON_HVX_PUT_P(v, new) \
__extension__({ \
union { \
HVX_VectorPair W; \
HVX_VectorPred P[2]; \
} _HEXAGON_HVX_internal_union; \
_HEXAGON_HVX_internal_union.W = (v); \
_HEXAGON_HVX_internal_union.P[0] = (new); \
_HEXAGON_HVX_internal_union.W; \
})
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clang-format: please reformat the code

-
Lint: Pre-merge checks: clang-format: please reformat the code ``` - ```
#define HEXAGON_HVX_CREATE_W(v1, v0) \
__extension__({ \
union { \
HVX_VectorPair W; \
HVX_Vector V[2]; \
} _HEXAGON_HVX_internal_union; \
_HEXAGON_HVX_internal_union.V[0] = (v0); \
_HEXAGON_HVX_internal_union.V[1] = (v1); \
_HEXAGON_HVX_internal_union.W; \
})
#ifdef __cplusplus
class HVX_Vect {
public:
// Constructors.
// Default.
HVX_Vect() : data(Q6_W_vcombine_VV(Q6_V_vzero(), Q6_V_vzero())){};
// Custom constructors.
HVX_Vect(HVX_VectorPair W) : data(W){};
HVX_Vect(HVX_Vector v1, HVX_Vector v0) : data(HEXAGON_HVX_CREATE_W(v1, v0)){};
// Copy constructor.
HVX_Vect(const HVX_Vect &W) = default;
// Move constructor.
HVX_Vect(HVX_Vect &&W) = default;
// Assignment operator.
HVX_Vect &operator=(const HVX_Vect &W) = default;
operator HVX_VectorPair() { return data; };
// Extract VectorPair method.
HVX_VectorPair W(void) { return HEXAGON_HVX_GET_W(data); };
// Extract Vector methods.
HVX_Vector V0(void) { return HEXAGON_HVX_GET_V0(data); };
HVX_Vector V1(void) { return HEXAGON_HVX_GET_V1(data); };
HVX_VectorPred P(void) { return HEXAGON_HVX_GET_P(data); };
// NOTE: All set methods return a HVX_Vect type.
// Set HVX VectorPair method.
HVX_Vect W(HVX_VectorPair w) { return HVX_Vect(HEXAGON_HVX_PUT_W(data, w)); };
// Set HVX Vector methods.
HVX_Vect V0(HVX_Vector v) { return HVX_Vect(HEXAGON_HVX_PUT_V0(data, v)); };
HVX_Vect V1(HVX_Vector v) { return HVX_Vect(HEXAGON_HVX_PUT_V1(data, v)); };
HVX_Vect P(HVX_VectorPred p) { return HVX_Vect(HEXAGON_HVX_PUT_P(data, p)); };
private:
HVX_VectorPair data;
};
#endif /* __cplusplus */
#endif /* __HVX__ */
#define HEXAGON_UDMA_DM0_STATUS_IDLE 0x00000000
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-#define HEXAGON_UDMA_DM0_STATUS_IDLE             0x00000000
-#define HEXAGON_UDMA_DM0_STATUS_RUN              0x00000001
-#define HEXAGON_UDMA_DM0_STATUS_ERROR            0x00000002
-#define HEXAGON_UDMA_DESC_DSTATE_INCOMPLETE      0
-#define HEXAGON_UDMA_DESC_DSTATE_COMPLETE        1
-#define HEXAGON_UDMA_DESC_ORDER_NOORDER          0
-#define HEXAGON_UDMA_DESC_ORDER_ORDER            1
-#define HEXAGON_UDMA_DESC_BYPASS_OFF             0
-#define HEXAGON_UDMA_DESC_BYPASS_ON              1
-#define HEXAGON_UDMA_DESC_COMP_NONE              0

43 diff lines are omitted. See full path.

Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define HEXAGON_UDMA_DM0_STATUS_IDLE…
#define HEXAGON_UDMA_DM0_STATUS_RUN 0x00000001
#define HEXAGON_UDMA_DM0_STATUS_ERROR 0x00000002
#define HEXAGON_UDMA_DESC_DSTATE_INCOMPLETE 0
#define HEXAGON_UDMA_DESC_DSTATE_COMPLETE 1
#define HEXAGON_UDMA_DESC_ORDER_NOORDER 0
#define HEXAGON_UDMA_DESC_ORDER_ORDER 1
#define HEXAGON_UDMA_DESC_BYPASS_OFF 0
#define HEXAGON_UDMA_DESC_BYPASS_ON 1
#define HEXAGON_UDMA_DESC_COMP_NONE 0
#define HEXAGON_UDMA_DESC_COMP_DLBC 1
#define HEXAGON_UDMA_DESC_DESCTYPE_TYPE0 0
#define HEXAGON_UDMA_DESC_DESCTYPE_TYPE1 1
typedef struct hexagon_udma_descriptor_type0_s
{
void *next;
unsigned int length:24;
unsigned int desctype:2;
unsigned int dstcomp:1;
unsigned int srccomp:1;
unsigned int dstbypass:1;
unsigned int srcbypass:1;
unsigned int order:1;
unsigned int dstate:1;
void *src;
void *dst;
} hexagon_udma_descriptor_type0_t;
typedef struct hexagon_udma_descriptor_type1_s
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clang-format: please reformat the code

-typedef struct hexagon_udma_descriptor_type1_s
-{
-    void *next;
-    unsigned int length:24;
-    unsigned int desctype:2;
-    unsigned int dstcomp:1;
-    unsigned int srccomp:1;
-    unsigned int dstbypass:1;
-    unsigned int srcbypass:1;
-    unsigned int order:1;

31 diff lines are omitted. See full path.

Lint: Pre-merge checks: clang-format: please reformat the code ``` -typedef struct hexagon_udma_descriptor_type1_s -{…
{
void *next;
unsigned int length:24;
unsigned int desctype:2;
unsigned int dstcomp:1;
unsigned int srccomp:1;
unsigned int dstbypass:1;
unsigned int srcbypass:1;
unsigned int order:1;
unsigned int dstate:1;
void *src;
void *dst;
unsigned int allocation:28;
unsigned int padding:4;
unsigned int roiwidth:16;
unsigned int roiheight:16;
unsigned int srcstride:16;
unsigned int dststride:16;
unsigned int srcwidthoffset:16;
unsigned int dstwidthoffset:16;
} hexagon_udma_descriptor_type1_t;
#endif /* !HEXAGON_TYPES_H */

clang/lib/Headers/hvx_hexagon_protos.h

  • This file was added.
//===----------------------------------------------------------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
// Automatically generated file, do not edit!
//===----------------------------------------------------------------------===//
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clang-format: please reformat the code

-
-
Lint: Pre-merge checks: clang-format: please reformat the code ``` - - ```
#ifndef _HVX_HEXAGON_PROTOS_H_
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clang-tidy: warning: header guard does not follow preferred style [llvm-header-guard]
not useful

Lint: Pre-merge checks: clang-tidy: warning: header guard does not follow preferred style [llvm-header-guard] [[https…
#define _HVX_HEXAGON_PROTOS_H_ 1
#ifdef __HVX__
#if __HVX_LENGTH__ == 128
#define __BUILTIN_VECTOR_WRAP(a) a ## _128B
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clang-format: please reformat the code

-#define __BUILTIN_VECTOR_WRAP(a) a ## _128B
+#define __BUILTIN_VECTOR_WRAP(a) a##_128B
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define __BUILTIN_VECTOR_WRAP(a) a ## _128B…
#else
#define __BUILTIN_VECTOR_WRAP(a) a
#endif
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Rd32=vextract(Vu32,Rs32)
C Intrinsic Prototype: Word32 Q6_R_vextract_VR(HVX_Vector Vu, Word32 Rs)
Instruction Type: LD
Execution Slots: SLOT0
========================================================================== */
#define Q6_R_vextract_VR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_extractw)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32=hi(Vss32)
C Intrinsic Prototype: HVX_Vector Q6_V_hi_W(HVX_VectorPair Vss)
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_V_hi_W __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_hi)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32=lo(Vss32)
C Intrinsic Prototype: HVX_Vector Q6_V_lo_W(HVX_VectorPair Vss)
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_V_lo_W __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lo)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32=vsplat(Rt32)
C Intrinsic Prototype: HVX_Vector Q6_V_vsplat_R(Word32 Rt)
Instruction Type: CVI_VX_LATE
Execution Slots: SLOT23
========================================================================== */
#define Q6_V_vsplat_R __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lvsplatw)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Qd4=and(Qs4,Qt4)
C Intrinsic Prototype: HVX_VectorPred Q6_Q_and_QQ(HVX_VectorPred Qs, HVX_VectorPred Qt)
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clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPred Q6_Q_and_QQ(HVX_VectorPred Qs, HVX_VectorPred Qt)
-   Instruction Type:      CVI_VA_DV
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_and_QQ(HVX_VectorPred Qs,
+   HVX_VectorPred Qt) Instruction Type:      CVI_VA_DV Execution Slots: SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPred…
Instruction Type: CVI_VA_DV
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Q_and_QQ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_and)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Qd4=and(Qs4,!Qt4)
C Intrinsic Prototype: HVX_VectorPred Q6_Q_and_QQn(HVX_VectorPred Qs, HVX_VectorPred Qt)
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clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPred Q6_Q_and_QQn(HVX_VectorPred Qs, HVX_VectorPred Qt)
-   Instruction Type:      CVI_VA_DV
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_and_QQn(HVX_VectorPred Qs,
+   HVX_VectorPred Qt) Instruction Type:      CVI_VA_DV Execution Slots: SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPred…
Instruction Type: CVI_VA_DV
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Q_and_QQn __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_and_n)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Qd4=not(Qs4)
C Intrinsic Prototype: HVX_VectorPred Q6_Q_not_Q(HVX_VectorPred Qs)
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Q_not_Q __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_not)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Qd4=or(Qs4,Qt4)
C Intrinsic Prototype: HVX_VectorPred Q6_Q_or_QQ(HVX_VectorPred Qs, HVX_VectorPred Qt)
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clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPred Q6_Q_or_QQ(HVX_VectorPred Qs, HVX_VectorPred Qt)
-   Instruction Type:      CVI_VA_DV
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_or_QQ(HVX_VectorPred Qs,
+   HVX_VectorPred Qt) Instruction Type:      CVI_VA_DV Execution Slots: SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPred Q6_Q_or_QQ…
Instruction Type: CVI_VA_DV
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Q_or_QQ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_or)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Qd4=or(Qs4,!Qt4)
C Intrinsic Prototype: HVX_VectorPred Q6_Q_or_QQn(HVX_VectorPred Qs, HVX_VectorPred Qt)
Lint: Pre-merge checks
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clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPred Q6_Q_or_QQn(HVX_VectorPred Qs, HVX_VectorPred Qt)
-   Instruction Type:      CVI_VA_DV
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_or_QQn(HVX_VectorPred Qs,
+   HVX_VectorPred Qt) Instruction Type:      CVI_VA_DV Execution Slots: SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPred…
Instruction Type: CVI_VA_DV
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Q_or_QQn __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_or_n)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Qd4=vsetq(Rt32)
C Intrinsic Prototype: HVX_VectorPred Q6_Q_vsetq_R(Word32 Rt)
Instruction Type: CVI_VP
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Q_vsetq_R __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_scalar2)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Qd4=xor(Qs4,Qt4)
C Intrinsic Prototype: HVX_VectorPred Q6_Q_xor_QQ(HVX_VectorPred Qs, HVX_VectorPred Qt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPred Q6_Q_xor_QQ(HVX_VectorPred Qs, HVX_VectorPred Qt)
-   Instruction Type:      CVI_VA_DV
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_xor_QQ(HVX_VectorPred Qs,
+   HVX_VectorPred Qt) Instruction Type:      CVI_VA_DV Execution Slots: SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPred…
Instruction Type: CVI_VA_DV
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Q_xor_QQ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_xor)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: if (!Qv4) vmem(Rt32+#s4)=Vs32
C Intrinsic Prototype: void Q6_vmem_QnRIV(HVX_VectorPred Qv, HVX_Vector* Rt, HVX_Vector Vs)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: void Q6_vmem_QnRIV(HVX_VectorPred Qv, HVX_Vector* Rt, HVX_Vector Vs)
-   Instruction Type:      CVI_VM_ST
-   Execution Slots:       SLOT0
+   C Intrinsic Prototype: void Q6_vmem_QnRIV(HVX_VectorPred Qv, HVX_Vector* Rt,
+   HVX_Vector Vs) Instruction Type:      CVI_VM_ST Execution Slots:       SLOT0
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: void Q6_vmem_QnRIV…
Instruction Type: CVI_VM_ST
Execution Slots: SLOT0
========================================================================== */
#define Q6_vmem_QnRIV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nqpred_ai)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_vmem_QnRIV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nqpred_ai)
+#define Q6_vmem_QnRIV                                                          \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nqpred_ai)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_vmem_QnRIV __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: if (!Qv4) vmem(Rt32+#s4):nt=Vs32
C Intrinsic Prototype: void Q6_vmem_QnRIV_nt(HVX_VectorPred Qv, HVX_Vector* Rt, HVX_Vector Vs)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: void Q6_vmem_QnRIV_nt(HVX_VectorPred Qv, HVX_Vector* Rt, HVX_Vector Vs)
-   Instruction Type:      CVI_VM_ST
-   Execution Slots:       SLOT0
+   C Intrinsic Prototype: void Q6_vmem_QnRIV_nt(HVX_VectorPred Qv, HVX_Vector*
+   Rt, HVX_Vector Vs) Instruction Type:      CVI_VM_ST Execution Slots: SLOT0
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: void Q6_vmem_QnRIV_nt…
Instruction Type: CVI_VM_ST
Execution Slots: SLOT0
========================================================================== */
#define Q6_vmem_QnRIV_nt __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nt_nqpred_ai)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_vmem_QnRIV_nt __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nt_nqpred_ai)
+#define Q6_vmem_QnRIV_nt                                                       \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nt_nqpred_ai)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_vmem_QnRIV_nt __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: if (Qv4) vmem(Rt32+#s4):nt=Vs32
C Intrinsic Prototype: void Q6_vmem_QRIV_nt(HVX_VectorPred Qv, HVX_Vector* Rt, HVX_Vector Vs)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: void Q6_vmem_QRIV_nt(HVX_VectorPred Qv, HVX_Vector* Rt, HVX_Vector Vs)
-   Instruction Type:      CVI_VM_ST
-   Execution Slots:       SLOT0
+   C Intrinsic Prototype: void Q6_vmem_QRIV_nt(HVX_VectorPred Qv, HVX_Vector*
+   Rt, HVX_Vector Vs) Instruction Type:      CVI_VM_ST Execution Slots: SLOT0
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: void Q6_vmem_QRIV_nt…
Instruction Type: CVI_VM_ST
Execution Slots: SLOT0
========================================================================== */
#define Q6_vmem_QRIV_nt __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nt_qpred_ai)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_vmem_QRIV_nt __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nt_qpred_ai)
+#define Q6_vmem_QRIV_nt                                                        \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nt_qpred_ai)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_vmem_QRIV_nt __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: if (Qv4) vmem(Rt32+#s4)=Vs32
C Intrinsic Prototype: void Q6_vmem_QRIV(HVX_VectorPred Qv, HVX_Vector* Rt, HVX_Vector Vs)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: void Q6_vmem_QRIV(HVX_VectorPred Qv, HVX_Vector* Rt, HVX_Vector Vs)
-   Instruction Type:      CVI_VM_ST
-   Execution Slots:       SLOT0
+   C Intrinsic Prototype: void Q6_vmem_QRIV(HVX_VectorPred Qv, HVX_Vector* Rt,
+   HVX_Vector Vs) Instruction Type:      CVI_VM_ST Execution Slots:       SLOT0
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: void Q6_vmem_QRIV…
Instruction Type: CVI_VM_ST
Execution Slots: SLOT0
========================================================================== */
#define Q6_vmem_QRIV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_qpred_ai)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.uh=vabsdiff(Vu32.h,Vv32.h)
C Intrinsic Prototype: HVX_Vector Q6_Vuh_vabsdiff_VhVh(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vuh_vabsdiff_VhVh(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VX
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_Vector Q6_Vuh_vabsdiff_VhVh(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VX Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VX
Execution Slots: SLOT23
========================================================================== */
#define Q6_Vuh_vabsdiff_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffh)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vuh_vabsdiff_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffh)
+#define Q6_Vuh_vabsdiff_VhVh                                                   \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffh)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vuh_vabsdiff_VhVh __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.ub=vabsdiff(Vu32.ub,Vv32.ub)
C Intrinsic Prototype: HVX_Vector Q6_Vub_vabsdiff_VubVub(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vub_vabsdiff_VubVub(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VX
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_Vector Q6_Vub_vabsdiff_VubVub(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VX Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VX
Execution Slots: SLOT23
========================================================================== */
#define Q6_Vub_vabsdiff_VubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffub)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vub_vabsdiff_VubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffub)
+#define Q6_Vub_vabsdiff_VubVub                                                 \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffub)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vub_vabsdiff_VubVub…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.uh=vabsdiff(Vu32.uh,Vv32.uh)
C Intrinsic Prototype: HVX_Vector Q6_Vuh_vabsdiff_VuhVuh(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vuh_vabsdiff_VuhVuh(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VX
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_Vector Q6_Vuh_vabsdiff_VuhVuh(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VX Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VX
Execution Slots: SLOT23
========================================================================== */
#define Q6_Vuh_vabsdiff_VuhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffuh)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vuh_vabsdiff_VuhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffuh)
+#define Q6_Vuh_vabsdiff_VuhVuh                                                 \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffuh)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vuh_vabsdiff_VuhVuh…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.uw=vabsdiff(Vu32.w,Vv32.w)
C Intrinsic Prototype: HVX_Vector Q6_Vuw_vabsdiff_VwVw(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vuw_vabsdiff_VwVw(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VX
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_Vector Q6_Vuw_vabsdiff_VwVw(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VX Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VX
Execution Slots: SLOT23
========================================================================== */
#define Q6_Vuw_vabsdiff_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffw)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vuw_vabsdiff_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffw)
+#define Q6_Vuw_vabsdiff_VwVw                                                   \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffw)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vuw_vabsdiff_VwVw __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.h=vabs(Vu32.h)
C Intrinsic Prototype: HVX_Vector Q6_Vh_vabs_Vh(HVX_Vector Vu)
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vh_vabs_Vh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsh)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.h=vabs(Vu32.h):sat
C Intrinsic Prototype: HVX_Vector Q6_Vh_vabs_Vh_sat(HVX_Vector Vu)
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vh_vabs_Vh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsh_sat)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.w=vabs(Vu32.w)
C Intrinsic Prototype: HVX_Vector Q6_Vw_vabs_Vw(HVX_Vector Vu)
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vw_vabs_Vw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsw)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.w=vabs(Vu32.w):sat
C Intrinsic Prototype: HVX_Vector Q6_Vw_vabs_Vw_sat(HVX_Vector Vu)
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vw_vabs_Vw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsw_sat)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.b=vadd(Vu32.b,Vv32.b)
C Intrinsic Prototype: HVX_Vector Q6_Vb_vadd_VbVb(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vb_vadd_VbVb(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_vadd_VbVb(HVX_Vector Vu, HVX_Vector
+   Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vb_vadd_VbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddb)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vdd32.b=vadd(Vuu32.b,Vvv32.b)
C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vadd_WbWb(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vadd_WbWb(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
-   Instruction Type:      CVI_VA_DV
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vadd_WbWb(HVX_VectorPair Vuu,
+   HVX_VectorPair Vvv) Instruction Type:      CVI_VA_DV Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VA_DV
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Wb_vadd_WbWb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddb_dv)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: if (!Qv4) Vx32.b+=Vu32.b
C Intrinsic Prototype: HVX_Vector Q6_Vb_condacc_QnVbVb(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vb_condacc_QnVbVb(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_condacc_QnVbVb(HVX_VectorPred Qv,
+   HVX_Vector Vx, HVX_Vector Vu) Instruction Type:      CVI_VA Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vb_condacc_QnVbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbnq)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: if (Qv4) Vx32.b+=Vu32.b
C Intrinsic Prototype: HVX_Vector Q6_Vb_condacc_QVbVb(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vb_condacc_QVbVb(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_condacc_QVbVb(HVX_VectorPred Qv,
+   HVX_Vector Vx, HVX_Vector Vu) Instruction Type:      CVI_VA Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vb_condacc_QVbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbq)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.h=vadd(Vu32.h,Vv32.h)
C Intrinsic Prototype: HVX_Vector Q6_Vh_vadd_VhVh(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vh_vadd_VhVh(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vadd_VhVh(HVX_Vector Vu, HVX_Vector
+   Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vh_vadd_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddh)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vdd32.h=vadd(Vuu32.h,Vvv32.h)
C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vadd_WhWh(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vadd_WhWh(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
-   Instruction Type:      CVI_VA_DV
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vadd_WhWh(HVX_VectorPair Vuu,
+   HVX_VectorPair Vvv) Instruction Type:      CVI_VA_DV Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VA_DV
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Wh_vadd_WhWh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddh_dv)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: if (!Qv4) Vx32.h+=Vu32.h
C Intrinsic Prototype: HVX_Vector Q6_Vh_condacc_QnVhVh(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vh_condacc_QnVhVh(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_condacc_QnVhVh(HVX_VectorPred Qv,
+   HVX_Vector Vx, HVX_Vector Vu) Instruction Type:      CVI_VA Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vh_condacc_QnVhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhnq)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: if (Qv4) Vx32.h+=Vu32.h
C Intrinsic Prototype: HVX_Vector Q6_Vh_condacc_QVhVh(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vh_condacc_QVhVh(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_condacc_QVhVh(HVX_VectorPred Qv,
+   HVX_Vector Vx, HVX_Vector Vu) Instruction Type:      CVI_VA Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vh_condacc_QVhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhq)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.h=vadd(Vu32.h,Vv32.h):sat
C Intrinsic Prototype: HVX_Vector Q6_Vh_vadd_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vh_vadd_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vadd_VhVh_sat(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vh_vadd_VhVh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhsat)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vdd32.h=vadd(Vuu32.h,Vvv32.h):sat
C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vadd_WhWh_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vadd_WhWh_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
-   Instruction Type:      CVI_VA_DV
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vadd_WhWh_sat(HVX_VectorPair Vuu,
+   HVX_VectorPair Vvv) Instruction Type:      CVI_VA_DV Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VA_DV
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Wh_vadd_WhWh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhsat_dv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Wh_vadd_WhWh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhsat_dv)
+#define Q6_Wh_vadd_WhWh_sat                                                    \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhsat_dv)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Wh_vadd_WhWh_sat __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vdd32.w=vadd(Vu32.h,Vv32.h)
C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vadd_VhVh(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vadd_VhVh(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vadd_VhVh(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Ww_vadd_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhw)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vdd32.h=vadd(Vu32.ub,Vv32.ub)
C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vadd_VubVub(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vadd_VubVub(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vadd_VubVub(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Wh_vadd_VubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubh)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.ub=vadd(Vu32.ub,Vv32.ub):sat
C Intrinsic Prototype: HVX_Vector Q6_Vub_vadd_VubVub_sat(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vub_vadd_VubVub_sat(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vub_vadd_VubVub_sat(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vub_vadd_VubVub_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubsat)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vub_vadd_VubVub_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubsat)
+#define Q6_Vub_vadd_VubVub_sat                                                 \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubsat)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vub_vadd_VubVub_sat…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vdd32.ub=vadd(Vuu32.ub,Vvv32.ub):sat
C Intrinsic Prototype: HVX_VectorPair Q6_Wub_vadd_WubWub_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Wub_vadd_WubWub_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
-   Instruction Type:      CVI_VA_DV
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wub_vadd_WubWub_sat(HVX_VectorPair
+   Vuu, HVX_VectorPair Vvv) Instruction Type:      CVI_VA_DV Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VA_DV
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Wub_vadd_WubWub_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubsat_dv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Wub_vadd_WubWub_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubsat_dv)
+#define Q6_Wub_vadd_WubWub_sat                                                 \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubsat_dv)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Wub_vadd_WubWub_sat…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.uh=vadd(Vu32.uh,Vv32.uh):sat
C Intrinsic Prototype: HVX_Vector Q6_Vuh_vadd_VuhVuh_sat(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vuh_vadd_VuhVuh_sat(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vuh_vadd_VuhVuh_sat(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vuh_vadd_VuhVuh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduhsat)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vuh_vadd_VuhVuh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduhsat)
+#define Q6_Vuh_vadd_VuhVuh_sat                                                 \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduhsat)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vuh_vadd_VuhVuh_sat…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vdd32.uh=vadd(Vuu32.uh,Vvv32.uh):sat
C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vadd_WuhWuh_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vadd_WuhWuh_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
-   Instruction Type:      CVI_VA_DV
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vadd_WuhWuh_sat(HVX_VectorPair
+   Vuu, HVX_VectorPair Vvv) Instruction Type:      CVI_VA_DV Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VA_DV
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Wuh_vadd_WuhWuh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduhsat_dv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Wuh_vadd_WuhWuh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduhsat_dv)
+#define Q6_Wuh_vadd_WuhWuh_sat                                                 \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduhsat_dv)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Wuh_vadd_WuhWuh_sat…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vdd32.w=vadd(Vu32.uh,Vv32.uh)
C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vadd_VuhVuh(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vadd_VuhVuh(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vadd_VuhVuh(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Ww_vadd_VuhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduhw)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.w=vadd(Vu32.w,Vv32.w)
C Intrinsic Prototype: HVX_Vector Q6_Vw_vadd_VwVw(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vw_vadd_VwVw(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vadd_VwVw(HVX_Vector Vu, HVX_Vector
+   Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vw_vadd_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddw)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vdd32.w=vadd(Vuu32.w,Vvv32.w)
C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vadd_WwWw(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vadd_WwWw(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
-   Instruction Type:      CVI_VA_DV
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vadd_WwWw(HVX_VectorPair Vuu,
+   HVX_VectorPair Vvv) Instruction Type:      CVI_VA_DV Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VA_DV
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Ww_vadd_WwWw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddw_dv)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: if (!Qv4) Vx32.w+=Vu32.w
C Intrinsic Prototype: HVX_Vector Q6_Vw_condacc_QnVwVw(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vw_condacc_QnVwVw(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_condacc_QnVwVw(HVX_VectorPred Qv,
+   HVX_Vector Vx, HVX_Vector Vu) Instruction Type:      CVI_VA Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vw_condacc_QnVwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddwnq)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: if (Qv4) Vx32.w+=Vu32.w
C Intrinsic Prototype: HVX_Vector Q6_Vw_condacc_QVwVw(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vw_condacc_QVwVw(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_condacc_QVwVw(HVX_VectorPred Qv,
+   HVX_Vector Vx, HVX_Vector Vu) Instruction Type:      CVI_VA Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vw_condacc_QVwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddwq)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.w=vadd(Vu32.w,Vv32.w):sat
C Intrinsic Prototype: HVX_Vector Q6_Vw_vadd_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vw_vadd_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vadd_VwVw_sat(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vw_vadd_VwVw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddwsat)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vdd32.w=vadd(Vuu32.w,Vvv32.w):sat
C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vadd_WwWw_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vadd_WwWw_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
-   Instruction Type:      CVI_VA_DV
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vadd_WwWw_sat(HVX_VectorPair Vuu,
+   HVX_VectorPair Vvv) Instruction Type:      CVI_VA_DV Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VA_DV
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Ww_vadd_WwWw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddwsat_dv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Ww_vadd_WwWw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddwsat_dv)
+#define Q6_Ww_vadd_WwWw_sat                                                    \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddwsat_dv)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Ww_vadd_WwWw_sat __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32=valign(Vu32,Vv32,Rt8)
C Intrinsic Prototype: HVX_Vector Q6_V_valign_VVR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_V_valign_VVR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
-   Instruction Type:      CVI_VP
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_V_valign_VVR(HVX_Vector Vu, HVX_Vector
+   Vv, Word32 Rt) Instruction Type:      CVI_VP Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VP
Execution Slots: SLOT0123
========================================================================== */
#define Q6_V_valign_VVR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_valignb)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32=valign(Vu32,Vv32,#u3)
C Intrinsic Prototype: HVX_Vector Q6_V_valign_VVI(HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_V_valign_VVI(HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3)
-   Instruction Type:      CVI_VP
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_V_valign_VVI(HVX_Vector Vu, HVX_Vector
+   Vv, Word32 Iu3) Instruction Type:      CVI_VP Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VP
Execution Slots: SLOT0123
========================================================================== */
#define Q6_V_valign_VVI __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_valignbi)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32=vand(Vu32,Vv32)
C Intrinsic Prototype: HVX_Vector Q6_V_vand_VV(HVX_Vector Vu, HVX_Vector Vv)
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_V_vand_VV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vand)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32=vand(Qu4,Rt32)
C Intrinsic Prototype: HVX_Vector Q6_V_vand_QR(HVX_VectorPred Qu, Word32 Rt)
Instruction Type: CVI_VX_LATE
Execution Slots: SLOT23
========================================================================== */
#define Q6_V_vand_QR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vx32|=vand(Qu4,Rt32)
C Intrinsic Prototype: HVX_Vector Q6_V_vandor_VQR(HVX_Vector Vx, HVX_VectorPred Qu, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_V_vandor_VQR(HVX_Vector Vx, HVX_VectorPred Qu, Word32 Rt)
-   Instruction Type:      CVI_VX_LATE
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_Vector Q6_V_vandor_VQR(HVX_Vector Vx,
+   HVX_VectorPred Qu, Word32 Rt) Instruction Type:      CVI_VX_LATE Execution
+   Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VX_LATE
Execution Slots: SLOT23
========================================================================== */
#define Q6_V_vandor_VQR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt_acc)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Qd4=vand(Vu32,Rt32)
C Intrinsic Prototype: HVX_VectorPred Q6_Q_vand_VR(HVX_Vector Vu, Word32 Rt)
Instruction Type: CVI_VX_LATE
Execution Slots: SLOT23
========================================================================== */
#define Q6_Q_vand_VR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Qx4|=vand(Vu32,Rt32)
C Intrinsic Prototype: HVX_VectorPred Q6_Q_vandor_QVR(HVX_VectorPred Qx, HVX_Vector Vu, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vandor_QVR(HVX_VectorPred Qx, HVX_Vector Vu, Word32 Rt)
-   Instruction Type:      CVI_VX_LATE
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vandor_QVR(HVX_VectorPred Qx,
+   HVX_Vector Vu, Word32 Rt) Instruction Type:      CVI_VX_LATE Execution Slots:
+   SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPred…
Instruction Type: CVI_VX_LATE
Execution Slots: SLOT23
========================================================================== */
#define Q6_Q_vandor_QVR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt_acc)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.h=vasl(Vu32.h,Rt32)
C Intrinsic Prototype: HVX_Vector Q6_Vh_vasl_VhR(HVX_Vector Vu, Word32 Rt)
Instruction Type: CVI_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vh_vasl_VhR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslh)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.h=vasl(Vu32.h,Vv32.h)
C Intrinsic Prototype: HVX_Vector Q6_Vh_vasl_VhVh(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vh_vasl_VhVh(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VS
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vasl_VhVh(HVX_Vector Vu, HVX_Vector
+   Vv) Instruction Type:      CVI_VS Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vh_vasl_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslhv)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.w=vasl(Vu32.w,Rt32)
C Intrinsic Prototype: HVX_Vector Q6_Vw_vasl_VwR(HVX_Vector Vu, Word32 Rt)
Instruction Type: CVI_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vw_vasl_VwR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslw)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vx32.w+=vasl(Vu32.w,Rt32)
C Intrinsic Prototype: HVX_Vector Q6_Vw_vaslacc_VwVwR(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vw_vaslacc_VwVwR(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)
-   Instruction Type:      CVI_VS
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vaslacc_VwVwR(HVX_Vector Vx,
+   HVX_Vector Vu, Word32 Rt) Instruction Type:      CVI_VS Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vw_vaslacc_VwVwR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslw_acc)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vw_vaslacc_VwVwR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslw_acc)
+#define Q6_Vw_vaslacc_VwVwR                                                    \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslw_acc)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vw_vaslacc_VwVwR __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.w=vasl(Vu32.w,Vv32.w)
C Intrinsic Prototype: HVX_Vector Q6_Vw_vasl_VwVw(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vw_vasl_VwVw(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VS
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vasl_VwVw(HVX_Vector Vu, HVX_Vector
+   Vv) Instruction Type:      CVI_VS Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vw_vasl_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslwv)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.h=vasr(Vu32.h,Rt32)
C Intrinsic Prototype: HVX_Vector Q6_Vh_vasr_VhR(HVX_Vector Vu, Word32 Rt)
Instruction Type: CVI_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vh_vasr_VhR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrh)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.b=vasr(Vu32.h,Vv32.h,Rt8):rnd:sat
C Intrinsic Prototype: HVX_Vector Q6_Vb_vasr_VhVhR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vb_vasr_VhVhR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
-   Instruction Type:      CVI_VS
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_vasr_VhVhR_rnd_sat(HVX_Vector Vu,
+   HVX_Vector Vv, Word32 Rt) Instruction Type:      CVI_VS Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vb_vasr_VhVhR_rnd_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhbrndsat)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vb_vasr_VhVhR_rnd_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhbrndsat)
+#define Q6_Vb_vasr_VhVhR_rnd_sat                                               \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhbrndsat)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vb_vasr_VhVhR_rnd_sat…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.ub=vasr(Vu32.h,Vv32.h,Rt8):rnd:sat
C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_VhVhR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_VhVhR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
-   Instruction Type:      CVI_VS
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_VhVhR_rnd_sat(HVX_Vector Vu,
+   HVX_Vector Vv, Word32 Rt) Instruction Type:      CVI_VS Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vub_vasr_VhVhR_rnd_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhubrndsat)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vub_vasr_VhVhR_rnd_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhubrndsat)
+#define Q6_Vub_vasr_VhVhR_rnd_sat                                              \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhubrndsat)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vub_vasr_VhVhR_rnd_sat…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.ub=vasr(Vu32.h,Vv32.h,Rt8):sat
C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_VhVhR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_VhVhR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
-   Instruction Type:      CVI_VS
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_VhVhR_sat(HVX_Vector Vu,
+   HVX_Vector Vv, Word32 Rt) Instruction Type:      CVI_VS Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vub_vasr_VhVhR_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhubsat)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vub_vasr_VhVhR_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhubsat)
+#define Q6_Vub_vasr_VhVhR_sat                                                  \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhubsat)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vub_vasr_VhVhR_sat __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.h=vasr(Vu32.h,Vv32.h)
C Intrinsic Prototype: HVX_Vector Q6_Vh_vasr_VhVh(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vh_vasr_VhVh(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VS
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vasr_VhVh(HVX_Vector Vu, HVX_Vector
+   Vv) Instruction Type:      CVI_VS Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vh_vasr_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhv)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.w=vasr(Vu32.w,Rt32)
C Intrinsic Prototype: HVX_Vector Q6_Vw_vasr_VwR(HVX_Vector Vu, Word32 Rt)
Instruction Type: CVI_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vw_vasr_VwR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrw)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vx32.w+=vasr(Vu32.w,Rt32)
C Intrinsic Prototype: HVX_Vector Q6_Vw_vasracc_VwVwR(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vw_vasracc_VwVwR(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)
-   Instruction Type:      CVI_VS
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vasracc_VwVwR(HVX_Vector Vx,
+   HVX_Vector Vu, Word32 Rt) Instruction Type:      CVI_VS Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vw_vasracc_VwVwR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrw_acc)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vw_vasracc_VwVwR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrw_acc)
+#define Q6_Vw_vasracc_VwVwR                                                    \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrw_acc)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vw_vasracc_VwVwR __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.h=vasr(Vu32.w,Vv32.w,Rt8)
C Intrinsic Prototype: HVX_Vector Q6_Vh_vasr_VwVwR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vh_vasr_VwVwR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
-   Instruction Type:      CVI_VS
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vasr_VwVwR(HVX_Vector Vu, HVX_Vector
+   Vv, Word32 Rt) Instruction Type:      CVI_VS Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vh_vasr_VwVwR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwh)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.h=vasr(Vu32.w,Vv32.w,Rt8):rnd:sat
C Intrinsic Prototype: HVX_Vector Q6_Vh_vasr_VwVwR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vh_vasr_VwVwR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
-   Instruction Type:      CVI_VS
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vasr_VwVwR_rnd_sat(HVX_Vector Vu,
+   HVX_Vector Vv, Word32 Rt) Instruction Type:      CVI_VS Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vh_vasr_VwVwR_rnd_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwhrndsat)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vh_vasr_VwVwR_rnd_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwhrndsat)
+#define Q6_Vh_vasr_VwVwR_rnd_sat                                               \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwhrndsat)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vh_vasr_VwVwR_rnd_sat…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.h=vasr(Vu32.w,Vv32.w,Rt8):sat
C Intrinsic Prototype: HVX_Vector Q6_Vh_vasr_VwVwR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vh_vasr_VwVwR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
-   Instruction Type:      CVI_VS
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vasr_VwVwR_sat(HVX_Vector Vu,
+   HVX_Vector Vv, Word32 Rt) Instruction Type:      CVI_VS Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vh_vasr_VwVwR_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwhsat)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vh_vasr_VwVwR_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwhsat)
+#define Q6_Vh_vasr_VwVwR_sat                                                   \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwhsat)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vh_vasr_VwVwR_sat __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.uh=vasr(Vu32.w,Vv32.w,Rt8):sat
C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_VwVwR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_VwVwR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
-   Instruction Type:      CVI_VS
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_VwVwR_sat(HVX_Vector Vu,
+   HVX_Vector Vv, Word32 Rt) Instruction Type:      CVI_VS Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vuh_vasr_VwVwR_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwuhsat)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vuh_vasr_VwVwR_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwuhsat)
+#define Q6_Vuh_vasr_VwVwR_sat                                                  \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwuhsat)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vuh_vasr_VwVwR_sat __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.w=vasr(Vu32.w,Vv32.w)
C Intrinsic Prototype: HVX_Vector Q6_Vw_vasr_VwVw(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vw_vasr_VwVw(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VS
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vasr_VwVw(HVX_Vector Vu, HVX_Vector
+   Vv) Instruction Type:      CVI_VS Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vw_vasr_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwv)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32=Vu32
C Intrinsic Prototype: HVX_Vector Q6_V_equals_V(HVX_Vector Vu)
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_V_equals_V __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vassign)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vdd32=Vuu32
C Intrinsic Prototype: HVX_VectorPair Q6_W_equals_W(HVX_VectorPair Vuu)
Instruction Type: CVI_VA_DV
Execution Slots: SLOT0123
========================================================================== */
#define Q6_W_equals_W __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vassignp)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.h=vavg(Vu32.h,Vv32.h)
C Intrinsic Prototype: HVX_Vector Q6_Vh_vavg_VhVh(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vh_vavg_VhVh(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vavg_VhVh(HVX_Vector Vu, HVX_Vector
+   Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vh_vavg_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgh)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.h=vavg(Vu32.h,Vv32.h):rnd
C Intrinsic Prototype: HVX_Vector Q6_Vh_vavg_VhVh_rnd(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vh_vavg_VhVh_rnd(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vavg_VhVh_rnd(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vh_vavg_VhVh_rnd __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavghrnd)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.ub=vavg(Vu32.ub,Vv32.ub)
C Intrinsic Prototype: HVX_Vector Q6_Vub_vavg_VubVub(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vub_vavg_VubVub(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vub_vavg_VubVub(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vub_vavg_VubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgub)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.ub=vavg(Vu32.ub,Vv32.ub):rnd
C Intrinsic Prototype: HVX_Vector Q6_Vub_vavg_VubVub_rnd(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vub_vavg_VubVub_rnd(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vub_vavg_VubVub_rnd(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vub_vavg_VubVub_rnd __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgubrnd)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vub_vavg_VubVub_rnd __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgubrnd)
+#define Q6_Vub_vavg_VubVub_rnd                                                 \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgubrnd)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vub_vavg_VubVub_rnd…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.uh=vavg(Vu32.uh,Vv32.uh)
C Intrinsic Prototype: HVX_Vector Q6_Vuh_vavg_VuhVuh(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vuh_vavg_VuhVuh(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vuh_vavg_VuhVuh(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vuh_vavg_VuhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavguh)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.uh=vavg(Vu32.uh,Vv32.uh):rnd
C Intrinsic Prototype: HVX_Vector Q6_Vuh_vavg_VuhVuh_rnd(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vuh_vavg_VuhVuh_rnd(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vuh_vavg_VuhVuh_rnd(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vuh_vavg_VuhVuh_rnd __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavguhrnd)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vuh_vavg_VuhVuh_rnd __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavguhrnd)
+#define Q6_Vuh_vavg_VuhVuh_rnd                                                 \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavguhrnd)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vuh_vavg_VuhVuh_rnd…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.w=vavg(Vu32.w,Vv32.w)
C Intrinsic Prototype: HVX_Vector Q6_Vw_vavg_VwVw(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vw_vavg_VwVw(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vavg_VwVw(HVX_Vector Vu, HVX_Vector
+   Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vw_vavg_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgw)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.w=vavg(Vu32.w,Vv32.w):rnd
C Intrinsic Prototype: HVX_Vector Q6_Vw_vavg_VwVw_rnd(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vw_vavg_VwVw_rnd(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vavg_VwVw_rnd(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vw_vavg_VwVw_rnd __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgwrnd)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.uh=vcl0(Vu32.uh)
C Intrinsic Prototype: HVX_Vector Q6_Vuh_vcl0_Vuh(HVX_Vector Vu)
Instruction Type: CVI_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vuh_vcl0_Vuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcl0h)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.uw=vcl0(Vu32.uw)
C Intrinsic Prototype: HVX_Vector Q6_Vuw_vcl0_Vuw(HVX_Vector Vu)
Instruction Type: CVI_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vuw_vcl0_Vuw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcl0w)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vdd32=vcombine(Vu32,Vv32)
C Intrinsic Prototype: HVX_VectorPair Q6_W_vcombine_VV(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_W_vcombine_VV(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA_DV
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPair Q6_W_vcombine_VV(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VA_DV Execution Slots: SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VA_DV
Execution Slots: SLOT0123
========================================================================== */
#define Q6_W_vcombine_VV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcombine)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32=#0
C Intrinsic Prototype: HVX_Vector Q6_V_vzero()
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_V_vzero __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vd0)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.b=vdeal(Vu32.b)
C Intrinsic Prototype: HVX_Vector Q6_Vb_vdeal_Vb(HVX_Vector Vu)
Instruction Type: CVI_VP
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vb_vdeal_Vb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdealb)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.b=vdeale(Vu32.b,Vv32.b)
C Intrinsic Prototype: HVX_Vector Q6_Vb_vdeale_VbVb(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vb_vdeale_VbVb(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VP
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_vdeale_VbVb(HVX_Vector Vu, HVX_Vector
+   Vv) Instruction Type:      CVI_VP Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VP
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vb_vdeale_VbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdealb4w)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.h=vdeal(Vu32.h)
C Intrinsic Prototype: HVX_Vector Q6_Vh_vdeal_Vh(HVX_Vector Vu)
Instruction Type: CVI_VP
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vh_vdeal_Vh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdealh)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vdd32=vdeal(Vu32,Vv32,Rt8)
C Intrinsic Prototype: HVX_VectorPair Q6_W_vdeal_VVR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_W_vdeal_VVR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
-   Instruction Type:      CVI_VP_VS
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPair Q6_W_vdeal_VVR(HVX_Vector Vu,
+   HVX_Vector Vv, Word32 Rt) Instruction Type:      CVI_VP_VS Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VP_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_W_vdeal_VVR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdealvdd)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32=vdelta(Vu32,Vv32)
C Intrinsic Prototype: HVX_Vector Q6_V_vdelta_VV(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_V_vdelta_VV(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VP
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_V_vdelta_VV(HVX_Vector Vu, HVX_Vector
+   Vv) Instruction Type:      CVI_VP Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector Q6_V_vdelta_VV…
Instruction Type: CVI_VP
Execution Slots: SLOT0123
========================================================================== */
#define Q6_V_vdelta_VV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdelta)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.h=vdmpy(Vu32.ub,Rt32.b)
C Intrinsic Prototype: HVX_Vector Q6_Vh_vdmpy_VubRb(HVX_Vector Vu, Word32 Rt)
Instruction Type: CVI_VX
Execution Slots: SLOT23
========================================================================== */
#define Q6_Vh_vdmpy_VubRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpybus)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vx32.h+=vdmpy(Vu32.ub,Rt32.b)
C Intrinsic Prototype: HVX_Vector Q6_Vh_vdmpyacc_VhVubRb(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vh_vdmpyacc_VhVubRb(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)
-   Instruction Type:      CVI_VX
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vdmpyacc_VhVubRb(HVX_Vector Vx,
+   HVX_Vector Vu, Word32 Rt) Instruction Type:      CVI_VX Execution Slots:
+   SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VX
Execution Slots: SLOT23
========================================================================== */
#define Q6_Vh_vdmpyacc_VhVubRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpybus_acc)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vh_vdmpyacc_VhVubRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpybus_acc)
+#define Q6_Vh_vdmpyacc_VhVubRb                                                 \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpybus_acc)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vh_vdmpyacc_VhVubRb…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vdd32.h=vdmpy(Vuu32.ub,Rt32.b)
C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vdmpy_WubRb(HVX_VectorPair Vuu, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vdmpy_WubRb(HVX_VectorPair Vuu, Word32 Rt)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vdmpy_WubRb(HVX_VectorPair Vuu,
+   Word32 Rt) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Wh_vdmpy_WubRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpybus_dv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Wh_vdmpy_WubRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpybus_dv)
+#define Q6_Wh_vdmpy_WubRb                                                      \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpybus_dv)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Wh_vdmpy_WubRb __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vxx32.h+=vdmpy(Vuu32.ub,Rt32.b)
C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vdmpyacc_WhWubRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vdmpyacc_WhWubRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt)
-   Instruction Type:      CVI_VX_DV
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vdmpyacc_WhWubRb(HVX_VectorPair
+   Vxx, HVX_VectorPair Vuu, Word32 Rt) Instruction Type:      CVI_VX_DV
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Wh_vdmpyacc_WhWubRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpybus_dv_acc)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Wh_vdmpyacc_WhWubRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpybus_dv_acc)
+#define Q6_Wh_vdmpyacc_WhWubRb                                                 \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpybus_dv_acc)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Wh_vdmpyacc_WhWubRb…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.w=vdmpy(Vu32.h,Rt32.b)
C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_VhRb(HVX_Vector Vu, Word32 Rt)
Instruction Type: CVI_VX
Execution Slots: SLOT23
========================================================================== */
#define Q6_Vw_vdmpy_VhRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhb)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vx32.w+=vdmpy(Vu32.h,Rt32.b)
C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwVhRb(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwVhRb(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)
-   Instruction Type:      CVI_VX
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwVhRb(HVX_Vector Vx,
+   HVX_Vector Vu, Word32 Rt) Instruction Type:      CVI_VX Execution Slots:
+   SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VX
Execution Slots: SLOT23
========================================================================== */
#define Q6_Vw_vdmpyacc_VwVhRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhb_acc)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vw_vdmpyacc_VwVhRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhb_acc)
+#define Q6_Vw_vdmpyacc_VwVhRb                                                  \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhb_acc)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vw_vdmpyacc_VwVhRb __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vdd32.w=vdmpy(Vuu32.h,Rt32.b)
C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vdmpy_WhRb(HVX_VectorPair Vuu, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vdmpy_WhRb(HVX_VectorPair Vuu, Word32 Rt)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vdmpy_WhRb(HVX_VectorPair Vuu,
+   Word32 Rt) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Ww_vdmpy_WhRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhb_dv)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vxx32.w+=vdmpy(Vuu32.h,Rt32.b)
C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vdmpyacc_WwWhRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vdmpyacc_WwWhRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt)
-   Instruction Type:      CVI_VX_DV
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vdmpyacc_WwWhRb(HVX_VectorPair
+   Vxx, HVX_VectorPair Vuu, Word32 Rt) Instruction Type:      CVI_VX_DV
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Ww_vdmpyacc_WwWhRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhb_dv_acc)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Ww_vdmpyacc_WwWhRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhb_dv_acc)
+#define Q6_Ww_vdmpyacc_WwWhRb                                                  \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhb_dv_acc)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Ww_vdmpyacc_WwWhRb __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.w=vdmpy(Vuu32.h,Rt32.h):sat
C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_WhRh_sat(HVX_VectorPair Vuu, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_WhRh_sat(HVX_VectorPair Vuu, Word32 Rt)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_WhRh_sat(HVX_VectorPair Vuu,
+   Word32 Rt) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Vw_vdmpy_WhRh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhisat)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vw_vdmpy_WhRh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhisat)
+#define Q6_Vw_vdmpy_WhRh_sat                                                   \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhisat)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vw_vdmpy_WhRh_sat __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vx32.w+=vdmpy(Vuu32.h,Rt32.h):sat
C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwWhRh_sat(HVX_Vector Vx, HVX_VectorPair Vuu, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwWhRh_sat(HVX_Vector Vx, HVX_VectorPair Vuu, Word32 Rt)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwWhRh_sat(HVX_Vector Vx,
+   HVX_VectorPair Vuu, Word32 Rt) Instruction Type:      CVI_VX_DV Execution
+   Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Vw_vdmpyacc_VwWhRh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhisat_acc)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vw_vdmpyacc_VwWhRh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhisat_acc)
+#define Q6_Vw_vdmpyacc_VwWhRh_sat                                              \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhisat_acc)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vw_vdmpyacc_VwWhRh_sat…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.w=vdmpy(Vu32.h,Rt32.h):sat
C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_VhRh_sat(HVX_Vector Vu, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_VhRh_sat(HVX_Vector Vu, Word32 Rt)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_VhRh_sat(HVX_Vector Vu, Word32
+   Rt) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Vw_vdmpy_VhRh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsat)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vw_vdmpy_VhRh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsat)
+#define Q6_Vw_vdmpy_VhRh_sat                                                   \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsat)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vw_vdmpy_VhRh_sat __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vx32.w+=vdmpy(Vu32.h,Rt32.h):sat
C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwVhRh_sat(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwVhRh_sat(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwVhRh_sat(HVX_Vector Vx,
+   HVX_Vector Vu, Word32 Rt) Instruction Type:      CVI_VX_DV Execution Slots:
+   SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Vw_vdmpyacc_VwVhRh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsat_acc)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vw_vdmpyacc_VwVhRh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsat_acc)
+#define Q6_Vw_vdmpyacc_VwVhRh_sat                                              \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsat_acc)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vw_vdmpyacc_VwVhRh_sat…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.w=vdmpy(Vuu32.h,Rt32.uh,#1):sat
C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_WhRuh_sat(HVX_VectorPair Vuu, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_WhRuh_sat(HVX_VectorPair Vuu, Word32 Rt)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_WhRuh_sat(HVX_VectorPair Vuu,
+   Word32 Rt) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Vw_vdmpy_WhRuh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsuisat)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vw_vdmpy_WhRuh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsuisat)
+#define Q6_Vw_vdmpy_WhRuh_sat                                                  \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsuisat)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vw_vdmpy_WhRuh_sat __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vx32.w+=vdmpy(Vuu32.h,Rt32.uh,#1):sat
C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwWhRuh_sat(HVX_Vector Vx, HVX_VectorPair Vuu, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwWhRuh_sat(HVX_Vector Vx, HVX_VectorPair Vuu, Word32 Rt)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwWhRuh_sat(HVX_Vector Vx,
+   HVX_VectorPair Vuu, Word32 Rt) Instruction Type:      CVI_VX_DV Execution
+   Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Vw_vdmpyacc_VwWhRuh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsuisat_acc)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vw_vdmpyacc_VwWhRuh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsuisat_acc)
+#define Q6_Vw_vdmpyacc_VwWhRuh_sat                                             \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsuisat_acc)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vw_vdmpyacc_VwWhRuh_sat…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.w=vdmpy(Vu32.h,Rt32.uh):sat
C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_VhRuh_sat(HVX_Vector Vu, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_VhRuh_sat(HVX_Vector Vu, Word32 Rt)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_VhRuh_sat(HVX_Vector Vu, Word32
+   Rt) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Vw_vdmpy_VhRuh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsusat)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vw_vdmpy_VhRuh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsusat)
+#define Q6_Vw_vdmpy_VhRuh_sat                                                  \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsusat)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vw_vdmpy_VhRuh_sat __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vx32.w+=vdmpy(Vu32.h,Rt32.uh):sat
C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwVhRuh_sat(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwVhRuh_sat(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwVhRuh_sat(HVX_Vector Vx,
+   HVX_Vector Vu, Word32 Rt) Instruction Type:      CVI_VX_DV Execution Slots:
+   SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Vw_vdmpyacc_VwVhRuh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsusat_acc)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vw_vdmpyacc_VwVhRuh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsusat_acc)
+#define Q6_Vw_vdmpyacc_VwVhRuh_sat                                             \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsusat_acc)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vw_vdmpyacc_VwVhRuh_sat…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.w=vdmpy(Vu32.h,Vv32.h):sat
C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_VhVh_sat(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Vw_vdmpy_VhVh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhvsat)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vw_vdmpy_VhVh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhvsat)
+#define Q6_Vw_vdmpy_VhVh_sat                                                   \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhvsat)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vw_vdmpy_VhVh_sat __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vx32.w+=vdmpy(Vu32.h,Vv32.h):sat
C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwVhVh_sat(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwVhVh_sat(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwVhVh_sat(HVX_Vector Vx,
+   HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VX_DV Execution
+   Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Vw_vdmpyacc_VwVhVh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhvsat_acc)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vw_vdmpyacc_VwVhVh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhvsat_acc)
+#define Q6_Vw_vdmpyacc_VwVhVh_sat                                              \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhvsat_acc)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vw_vdmpyacc_VwVhVh_sat…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vdd32.uw=vdsad(Vuu32.uh,Rt32.uh)
C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vdsad_WuhRuh(HVX_VectorPair Vuu, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vdsad_WuhRuh(HVX_VectorPair Vuu, Word32 Rt)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vdsad_WuhRuh(HVX_VectorPair Vuu,
+   Word32 Rt) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Wuw_vdsad_WuhRuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdsaduh)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vxx32.uw+=vdsad(Vuu32.uh,Rt32.uh)
C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vdsadacc_WuwWuhRuh(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vdsadacc_WuwWuhRuh(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt)
+   C Intrinsic Prototype: HVX_VectorPair
+   Q6_Wuw_vdsadacc_WuwWuhRuh(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt)
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Wuw_vdsadacc_WuwWuhRuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdsaduh_acc)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Wuw_vdsadacc_WuwWuhRuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdsaduh_acc)
+#define Q6_Wuw_vdsadacc_WuwWuhRuh                                              \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdsaduh_acc)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Wuw_vdsadacc_WuwWuhRuh…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Qd4=vcmp.eq(Vu32.b,Vv32.b)
C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VbVb(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VbVb(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VbVb(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPred…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Q_vcmp_eq_VbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqb)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Qx4&=vcmp.eq(Vu32.b,Vv32.b)
C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVbVb(HVX_VectorPred
+   Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VA Execution
+   Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPred…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Q_vcmp_eqand_QVbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqb_and)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Q_vcmp_eqand_QVbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqb_and)
+#define Q6_Q_vcmp_eqand_QVbVb                                                  \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqb_and)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Q_vcmp_eqand_QVbVb __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Qx4|=vcmp.eq(Vu32.b,Vv32.b)
C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVbVb(HVX_VectorPred Qx,
+   HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VA Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPred…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Q_vcmp_eqor_QVbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqb_or)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Qx4^=vcmp.eq(Vu32.b,Vv32.b)
C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVbVb(HVX_VectorPred
+   Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VA Execution
+   Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPred…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Q_vcmp_eqxacc_QVbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqb_xor)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Q_vcmp_eqxacc_QVbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqb_xor)
+#define Q6_Q_vcmp_eqxacc_QVbVb                                                 \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqb_xor)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Q_vcmp_eqxacc_QVbVb…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Qd4=vcmp.eq(Vu32.h,Vv32.h)
C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VhVh(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VhVh(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VhVh(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPred…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Q_vcmp_eq_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqh)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Qx4&=vcmp.eq(Vu32.h,Vv32.h)
C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVhVh(HVX_VectorPred
+   Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VA Execution
+   Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPred…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Q_vcmp_eqand_QVhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqh_and)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Q_vcmp_eqand_QVhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqh_and)
+#define Q6_Q_vcmp_eqand_QVhVh                                                  \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqh_and)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Q_vcmp_eqand_QVhVh __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Qx4|=vcmp.eq(Vu32.h,Vv32.h)
C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVhVh(HVX_VectorPred Qx,
+   HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VA Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPred…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Q_vcmp_eqor_QVhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqh_or)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Qx4^=vcmp.eq(Vu32.h,Vv32.h)
C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVhVh(HVX_VectorPred
+   Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VA Execution
+   Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPred…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Q_vcmp_eqxacc_QVhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqh_xor)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Q_vcmp_eqxacc_QVhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqh_xor)
+#define Q6_Q_vcmp_eqxacc_QVhVh                                                 \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqh_xor)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Q_vcmp_eqxacc_QVhVh…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Qd4=vcmp.eq(Vu32.w,Vv32.w)
C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VwVw(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VwVw(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VwVw(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPred…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Q_vcmp_eq_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqw)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Qx4&=vcmp.eq(Vu32.w,Vv32.w)
C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVwVw(HVX_VectorPred
+   Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VA Execution
+   Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPred…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Q_vcmp_eqand_QVwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqw_and)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Q_vcmp_eqand_QVwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqw_and)
+#define Q6_Q_vcmp_eqand_QVwVw                                                  \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqw_and)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Q_vcmp_eqand_QVwVw __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Qx4|=vcmp.eq(Vu32.w,Vv32.w)
C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVwVw(HVX_VectorPred Qx,
+   HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VA Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPred…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Q_vcmp_eqor_QVwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqw_or)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Qx4^=vcmp.eq(Vu32.w,Vv32.w)
C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVwVw(HVX_VectorPred
+   Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VA Execution
+   Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPred…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Q_vcmp_eqxacc_QVwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqw_xor)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Q_vcmp_eqxacc_QVwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqw_xor)
+#define Q6_Q_vcmp_eqxacc_QVwVw                                                 \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqw_xor)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Q_vcmp_eqxacc_QVwVw…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Qd4=vcmp.gt(Vu32.b,Vv32.b)
C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VbVb(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VbVb(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VbVb(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPred…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Q_vcmp_gt_VbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtb)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Qx4&=vcmp.gt(Vu32.b,Vv32.b)
C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVbVb(HVX_VectorPred
+   Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VA Execution
+   Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPred…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Q_vcmp_gtand_QVbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtb_and)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Q_vcmp_gtand_QVbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtb_and)
+#define Q6_Q_vcmp_gtand_QVbVb                                                  \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtb_and)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Q_vcmp_gtand_QVbVb __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Qx4|=vcmp.gt(Vu32.b,Vv32.b)
C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVbVb(HVX_VectorPred Qx,
+   HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VA Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPred…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Q_vcmp_gtor_QVbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtb_or)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Qx4^=vcmp.gt(Vu32.b,Vv32.b)
C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVbVb(HVX_VectorPred
+   Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VA Execution
+   Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPred…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Q_vcmp_gtxacc_QVbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtb_xor)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Q_vcmp_gtxacc_QVbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtb_xor)
+#define Q6_Q_vcmp_gtxacc_QVbVb                                                 \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtb_xor)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Q_vcmp_gtxacc_QVbVb…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Qd4=vcmp.gt(Vu32.h,Vv32.h)
C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VhVh(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VhVh(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VhVh(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPred…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Q_vcmp_gt_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgth)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Qx4&=vcmp.gt(Vu32.h,Vv32.h)
C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVhVh(HVX_VectorPred
+   Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VA Execution
+   Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPred…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Q_vcmp_gtand_QVhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgth_and)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Q_vcmp_gtand_QVhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgth_and)
+#define Q6_Q_vcmp_gtand_QVhVh                                                  \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgth_and)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Q_vcmp_gtand_QVhVh __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Qx4|=vcmp.gt(Vu32.h,Vv32.h)
C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVhVh(HVX_VectorPred Qx,
+   HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VA Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPred…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Q_vcmp_gtor_QVhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgth_or)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Qx4^=vcmp.gt(Vu32.h,Vv32.h)
C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVhVh(HVX_VectorPred
+   Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VA Execution
+   Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPred…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Q_vcmp_gtxacc_QVhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgth_xor)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Q_vcmp_gtxacc_QVhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgth_xor)
+#define Q6_Q_vcmp_gtxacc_QVhVh                                                 \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgth_xor)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Q_vcmp_gtxacc_QVhVh…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Qd4=vcmp.gt(Vu32.ub,Vv32.ub)
C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VubVub(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VubVub(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VubVub(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPred…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Q_vcmp_gt_VubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtub)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Qx4&=vcmp.gt(Vu32.ub,Vv32.ub)
C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVubVub(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVubVub(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVubVub(HVX_VectorPred
+   Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VA Execution
+   Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPred…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Q_vcmp_gtand_QVubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtub_and)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Q_vcmp_gtand_QVubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtub_and)
+#define Q6_Q_vcmp_gtand_QVubVub                                                \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtub_and)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Q_vcmp_gtand_QVubVub…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Qx4|=vcmp.gt(Vu32.ub,Vv32.ub)
C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVubVub(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVubVub(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVubVub(HVX_VectorPred
+   Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VA Execution
+   Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPred…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Q_vcmp_gtor_QVubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtub_or)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Q_vcmp_gtor_QVubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtub_or)
+#define Q6_Q_vcmp_gtor_QVubVub                                                 \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtub_or)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Q_vcmp_gtor_QVubVub…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Qx4^=vcmp.gt(Vu32.ub,Vv32.ub)
C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVubVub(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVubVub(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVubVub(HVX_VectorPred
+   Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VA Execution
+   Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPred…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Q_vcmp_gtxacc_QVubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtub_xor)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Q_vcmp_gtxacc_QVubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtub_xor)
+#define Q6_Q_vcmp_gtxacc_QVubVub                                               \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtub_xor)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Q_vcmp_gtxacc_QVubVub…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Qd4=vcmp.gt(Vu32.uh,Vv32.uh)
C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VuhVuh(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VuhVuh(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VuhVuh(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPred…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Q_vcmp_gt_VuhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuh)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Qx4&=vcmp.gt(Vu32.uh,Vv32.uh)
C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVuhVuh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVuhVuh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVuhVuh(HVX_VectorPred
+   Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VA Execution
+   Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPred…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Q_vcmp_gtand_QVuhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuh_and)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Q_vcmp_gtand_QVuhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuh_and)
+#define Q6_Q_vcmp_gtand_QVuhVuh                                                \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuh_and)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Q_vcmp_gtand_QVuhVuh…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Qx4|=vcmp.gt(Vu32.uh,Vv32.uh)
C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVuhVuh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVuhVuh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVuhVuh(HVX_VectorPred
+   Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VA Execution
+   Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPred…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Q_vcmp_gtor_QVuhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuh_or)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Q_vcmp_gtor_QVuhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuh_or)
+#define Q6_Q_vcmp_gtor_QVuhVuh                                                 \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuh_or)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Q_vcmp_gtor_QVuhVuh…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Qx4^=vcmp.gt(Vu32.uh,Vv32.uh)
C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVuhVuh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVuhVuh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVuhVuh(HVX_VectorPred
+   Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VA Execution
+   Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPred…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Q_vcmp_gtxacc_QVuhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuh_xor)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Q_vcmp_gtxacc_QVuhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuh_xor)
+#define Q6_Q_vcmp_gtxacc_QVuhVuh                                               \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuh_xor)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Q_vcmp_gtxacc_QVuhVuh…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Qd4=vcmp.gt(Vu32.uw,Vv32.uw)
C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VuwVuw(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VuwVuw(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VuwVuw(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPred…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Q_vcmp_gt_VuwVuw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuw)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Qx4&=vcmp.gt(Vu32.uw,Vv32.uw)
C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVuwVuw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVuwVuw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVuwVuw(HVX_VectorPred
+   Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VA Execution
+   Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPred…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Q_vcmp_gtand_QVuwVuw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuw_and)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Q_vcmp_gtand_QVuwVuw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuw_and)
+#define Q6_Q_vcmp_gtand_QVuwVuw                                                \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuw_and)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Q_vcmp_gtand_QVuwVuw…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Qx4|=vcmp.gt(Vu32.uw,Vv32.uw)
C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVuwVuw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVuwVuw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVuwVuw(HVX_VectorPred
+   Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VA Execution
+   Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPred…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Q_vcmp_gtor_QVuwVuw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuw_or)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Q_vcmp_gtor_QVuwVuw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuw_or)
+#define Q6_Q_vcmp_gtor_QVuwVuw                                                 \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuw_or)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Q_vcmp_gtor_QVuwVuw…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Qx4^=vcmp.gt(Vu32.uw,Vv32.uw)
C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVuwVuw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVuwVuw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVuwVuw(HVX_VectorPred
+   Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VA Execution
+   Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPred…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Q_vcmp_gtxacc_QVuwVuw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuw_xor)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Q_vcmp_gtxacc_QVuwVuw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuw_xor)
+#define Q6_Q_vcmp_gtxacc_QVuwVuw                                               \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuw_xor)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Q_vcmp_gtxacc_QVuwVuw…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Qd4=vcmp.gt(Vu32.w,Vv32.w)
C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VwVw(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VwVw(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VwVw(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPred…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Q_vcmp_gt_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtw)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Qx4&=vcmp.gt(Vu32.w,Vv32.w)
C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVwVw(HVX_VectorPred
+   Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VA Execution
+   Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPred…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Q_vcmp_gtand_QVwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtw_and)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Q_vcmp_gtand_QVwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtw_and)
+#define Q6_Q_vcmp_gtand_QVwVw                                                  \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtw_and)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Q_vcmp_gtand_QVwVw __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Qx4|=vcmp.gt(Vu32.w,Vv32.w)
C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVwVw(HVX_VectorPred Qx,
+   HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VA Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPred…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Q_vcmp_gtor_QVwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtw_or)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Qx4^=vcmp.gt(Vu32.w,Vv32.w)
C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVwVw(HVX_VectorPred
+   Qx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VA Execution
+   Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPred…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Q_vcmp_gtxacc_QVwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtw_xor)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Q_vcmp_gtxacc_QVwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtw_xor)
+#define Q6_Q_vcmp_gtxacc_QVwVw                                                 \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtw_xor)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Q_vcmp_gtxacc_QVwVw…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vx32.w=vinsert(Rt32)
C Intrinsic Prototype: HVX_Vector Q6_Vw_vinsert_VwR(HVX_Vector Vx, Word32 Rt)
Instruction Type: CVI_VX_LATE
Execution Slots: SLOT23
========================================================================== */
#define Q6_Vw_vinsert_VwR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vinsertwr)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32=vlalign(Vu32,Vv32,Rt8)
C Intrinsic Prototype: HVX_Vector Q6_V_vlalign_VVR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_V_vlalign_VVR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
-   Instruction Type:      CVI_VP
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_V_vlalign_VVR(HVX_Vector Vu, HVX_Vector
+   Vv, Word32 Rt) Instruction Type:      CVI_VP Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VP
Execution Slots: SLOT0123
========================================================================== */
#define Q6_V_vlalign_VVR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlalignb)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32=vlalign(Vu32,Vv32,#u3)
C Intrinsic Prototype: HVX_Vector Q6_V_vlalign_VVI(HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_V_vlalign_VVI(HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3)
-   Instruction Type:      CVI_VP
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_V_vlalign_VVI(HVX_Vector Vu, HVX_Vector
+   Vv, Word32 Iu3) Instruction Type:      CVI_VP Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VP
Execution Slots: SLOT0123
========================================================================== */
#define Q6_V_vlalign_VVI __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlalignbi)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.uh=vlsr(Vu32.uh,Rt32)
C Intrinsic Prototype: HVX_Vector Q6_Vuh_vlsr_VuhR(HVX_Vector Vu, Word32 Rt)
Instruction Type: CVI_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vuh_vlsr_VuhR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrh)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.h=vlsr(Vu32.h,Vv32.h)
C Intrinsic Prototype: HVX_Vector Q6_Vh_vlsr_VhVh(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vh_vlsr_VhVh(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VS
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vlsr_VhVh(HVX_Vector Vu, HVX_Vector
+   Vv) Instruction Type:      CVI_VS Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vh_vlsr_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrhv)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.uw=vlsr(Vu32.uw,Rt32)
C Intrinsic Prototype: HVX_Vector Q6_Vuw_vlsr_VuwR(HVX_Vector Vu, Word32 Rt)
Instruction Type: CVI_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vuw_vlsr_VuwR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrw)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.w=vlsr(Vu32.w,Vv32.w)
C Intrinsic Prototype: HVX_Vector Q6_Vw_vlsr_VwVw(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vw_vlsr_VwVw(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VS
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vlsr_VwVw(HVX_Vector Vu, HVX_Vector
+   Vv) Instruction Type:      CVI_VS Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vw_vlsr_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrwv)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.b=vlut32(Vu32.b,Vv32.b,Rt8)
C Intrinsic Prototype: HVX_Vector Q6_Vb_vlut32_VbVbR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vb_vlut32_VbVbR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
-   Instruction Type:      CVI_VP
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_vlut32_VbVbR(HVX_Vector Vu,
+   HVX_Vector Vv, Word32 Rt) Instruction Type:      CVI_VP Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VP
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vb_vlut32_VbVbR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvb)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vx32.b|=vlut32(Vu32.b,Vv32.b,Rt8)
C Intrinsic Prototype: HVX_Vector Q6_Vb_vlut32or_VbVbVbR(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vb_vlut32or_VbVbVbR(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
-   Instruction Type:      CVI_VP_VS
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_vlut32or_VbVbVbR(HVX_Vector Vx,
+   HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) Instruction Type:      CVI_VP_VS
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VP_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vb_vlut32or_VbVbVbR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvb_oracc)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vb_vlut32or_VbVbVbR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvb_oracc)
+#define Q6_Vb_vlut32or_VbVbVbR                                                 \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvb_oracc)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vb_vlut32or_VbVbVbR…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vdd32.h=vlut16(Vu32.b,Vv32.h,Rt8)
C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vlut16_VbVhR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vlut16_VbVhR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
-   Instruction Type:      CVI_VP_VS
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vlut16_VbVhR(HVX_Vector Vu,
+   HVX_Vector Vv, Word32 Rt) Instruction Type:      CVI_VP_VS Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VP_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Wh_vlut16_VbVhR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwh)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vxx32.h|=vlut16(Vu32.b,Vv32.h,Rt8)
C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vlut16or_WhVbVhR(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vlut16or_WhVbVhR(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
-   Instruction Type:      CVI_VP_VS
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vlut16or_WhVbVhR(HVX_VectorPair
+   Vxx, HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) Instruction Type: CVI_VP_VS
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VP_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Wh_vlut16or_WhVbVhR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwh_oracc)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Wh_vlut16or_WhVbVhR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwh_oracc)
+#define Q6_Wh_vlut16or_WhVbVhR                                                 \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwh_oracc)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Wh_vlut16or_WhVbVhR…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.h=vmax(Vu32.h,Vv32.h)
C Intrinsic Prototype: HVX_Vector Q6_Vh_vmax_VhVh(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vh_vmax_VhVh(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vmax_VhVh(HVX_Vector Vu, HVX_Vector
+   Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vh_vmax_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxh)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.ub=vmax(Vu32.ub,Vv32.ub)
C Intrinsic Prototype: HVX_Vector Q6_Vub_vmax_VubVub(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vub_vmax_VubVub(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vub_vmax_VubVub(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vub_vmax_VubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxub)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.uh=vmax(Vu32.uh,Vv32.uh)
C Intrinsic Prototype: HVX_Vector Q6_Vuh_vmax_VuhVuh(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vuh_vmax_VuhVuh(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vuh_vmax_VuhVuh(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vuh_vmax_VuhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxuh)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.w=vmax(Vu32.w,Vv32.w)
C Intrinsic Prototype: HVX_Vector Q6_Vw_vmax_VwVw(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vw_vmax_VwVw(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vmax_VwVw(HVX_Vector Vu, HVX_Vector
+   Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vw_vmax_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxw)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.h=vmin(Vu32.h,Vv32.h)
C Intrinsic Prototype: HVX_Vector Q6_Vh_vmin_VhVh(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vh_vmin_VhVh(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vmin_VhVh(HVX_Vector Vu, HVX_Vector
+   Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vh_vmin_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminh)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.ub=vmin(Vu32.ub,Vv32.ub)
C Intrinsic Prototype: HVX_Vector Q6_Vub_vmin_VubVub(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vub_vmin_VubVub(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vub_vmin_VubVub(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vub_vmin_VubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminub)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.uh=vmin(Vu32.uh,Vv32.uh)
C Intrinsic Prototype: HVX_Vector Q6_Vuh_vmin_VuhVuh(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vuh_vmin_VuhVuh(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vuh_vmin_VuhVuh(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vuh_vmin_VuhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminuh)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.w=vmin(Vu32.w,Vv32.w)
C Intrinsic Prototype: HVX_Vector Q6_Vw_vmin_VwVw(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vw_vmin_VwVw(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vmin_VwVw(HVX_Vector Vu, HVX_Vector
+   Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vw_vmin_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminw)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vdd32.h=vmpa(Vuu32.ub,Rt32.b)
C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpa_WubRb(HVX_VectorPair Vuu, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpa_WubRb(HVX_VectorPair Vuu, Word32 Rt)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpa_WubRb(HVX_VectorPair Vuu,
+   Word32 Rt) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Wh_vmpa_WubRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabus)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vxx32.h+=vmpa(Vuu32.ub,Rt32.b)
C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpaacc_WhWubRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpaacc_WhWubRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt)
-   Instruction Type:      CVI_VX_DV
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpaacc_WhWubRb(HVX_VectorPair
+   Vxx, HVX_VectorPair Vuu, Word32 Rt) Instruction Type:      CVI_VX_DV
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Wh_vmpaacc_WhWubRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabus_acc)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Wh_vmpaacc_WhWubRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabus_acc)
+#define Q6_Wh_vmpaacc_WhWubRb                                                  \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabus_acc)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Wh_vmpaacc_WhWubRb __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vdd32.h=vmpa(Vuu32.ub,Vvv32.b)
C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpa_WubWb(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpa_WubWb(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpa_WubWb(HVX_VectorPair Vuu,
+   HVX_VectorPair Vvv) Instruction Type:      CVI_VX_DV Execution Slots: SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Wh_vmpa_WubWb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabusv)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vdd32.h=vmpa(Vuu32.ub,Vvv32.ub)
C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpa_WubWub(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpa_WubWub(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpa_WubWub(HVX_VectorPair Vuu,
+   HVX_VectorPair Vvv) Instruction Type:      CVI_VX_DV Execution Slots: SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Wh_vmpa_WubWub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabuuv)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vdd32.w=vmpa(Vuu32.h,Rt32.b)
C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpa_WhRb(HVX_VectorPair Vuu, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpa_WhRb(HVX_VectorPair Vuu, Word32 Rt)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpa_WhRb(HVX_VectorPair Vuu,
+   Word32 Rt) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Ww_vmpa_WhRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpahb)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vxx32.w+=vmpa(Vuu32.h,Rt32.b)
C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpaacc_WwWhRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpaacc_WwWhRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt)
-   Instruction Type:      CVI_VX_DV
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpaacc_WwWhRb(HVX_VectorPair
+   Vxx, HVX_VectorPair Vuu, Word32 Rt) Instruction Type:      CVI_VX_DV
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Ww_vmpaacc_WwWhRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpahb_acc)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Ww_vmpaacc_WwWhRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpahb_acc)
+#define Q6_Ww_vmpaacc_WwWhRb                                                   \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpahb_acc)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Ww_vmpaacc_WwWhRb __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vdd32.h=vmpy(Vu32.ub,Rt32.b)
C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpy_VubRb(HVX_Vector Vu, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpy_VubRb(HVX_Vector Vu, Word32 Rt)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpy_VubRb(HVX_Vector Vu, Word32
+   Rt) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Wh_vmpy_VubRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybus)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vxx32.h+=vmpy(Vu32.ub,Rt32.b)
C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpyacc_WhVubRb(HVX_VectorPair Vxx, HVX_Vector Vu, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpyacc_WhVubRb(HVX_VectorPair Vxx, HVX_Vector Vu, Word32 Rt)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpyacc_WhVubRb(HVX_VectorPair
+   Vxx, HVX_Vector Vu, Word32 Rt) Instruction Type:      CVI_VX_DV Execution
+   Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Wh_vmpyacc_WhVubRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybus_acc)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Wh_vmpyacc_WhVubRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybus_acc)
+#define Q6_Wh_vmpyacc_WhVubRb                                                  \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybus_acc)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Wh_vmpyacc_WhVubRb __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vdd32.h=vmpy(Vu32.ub,Vv32.b)
C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpy_VubVb(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpy_VubVb(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpy_VubVb(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Wh_vmpy_VubVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybusv)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vxx32.h+=vmpy(Vu32.ub,Vv32.b)
C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpyacc_WhVubVb(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpyacc_WhVubVb(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpyacc_WhVubVb(HVX_VectorPair
+   Vxx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VX_DV Execution
+   Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Wh_vmpyacc_WhVubVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybusv_acc)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Wh_vmpyacc_WhVubVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybusv_acc)
+#define Q6_Wh_vmpyacc_WhVubVb                                                  \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybusv_acc)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Wh_vmpyacc_WhVubVb __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vdd32.h=vmpy(Vu32.b,Vv32.b)
C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpy_VbVb(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpy_VbVb(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpy_VbVb(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Wh_vmpy_VbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybv)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vxx32.h+=vmpy(Vu32.b,Vv32.b)
C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpyacc_WhVbVb(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpyacc_WhVbVb(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpyacc_WhVbVb(HVX_VectorPair
+   Vxx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VX_DV Execution
+   Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Wh_vmpyacc_WhVbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybv_acc)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Wh_vmpyacc_WhVbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybv_acc)
+#define Q6_Wh_vmpyacc_WhVbVb                                                   \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybv_acc)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Wh_vmpyacc_WhVbVb __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.w=vmpye(Vu32.w,Vv32.uh)
C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpye_VwVuh(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpye_VwVuh(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpye_VwVuh(HVX_Vector Vu, HVX_Vector
+   Vv) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Vw_vmpye_VwVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyewuh)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vdd32.w=vmpy(Vu32.h,Rt32.h)
C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpy_VhRh(HVX_Vector Vu, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpy_VhRh(HVX_Vector Vu, Word32 Rt)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpy_VhRh(HVX_Vector Vu, Word32
+   Rt) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Ww_vmpy_VhRh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyh)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vxx32.w+=vmpy(Vu32.h,Rt32.h):sat
C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpyacc_WwVhRh_sat(HVX_VectorPair Vxx, HVX_Vector Vu, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpyacc_WwVhRh_sat(HVX_VectorPair Vxx, HVX_Vector Vu, Word32 Rt)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpyacc_WwVhRh_sat(HVX_VectorPair
+   Vxx, HVX_Vector Vu, Word32 Rt) Instruction Type:      CVI_VX_DV Execution
+   Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Ww_vmpyacc_WwVhRh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhsat_acc)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Ww_vmpyacc_WwVhRh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhsat_acc)
+#define Q6_Ww_vmpyacc_WwVhRh_sat                                               \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhsat_acc)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Ww_vmpyacc_WwVhRh_sat…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.h=vmpy(Vu32.h,Rt32.h):<<1:rnd:sat
C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpy_VhRh_s1_rnd_sat(HVX_Vector Vu, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpy_VhRh_s1_rnd_sat(HVX_Vector Vu, Word32 Rt)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpy_VhRh_s1_rnd_sat(HVX_Vector Vu,
+   Word32 Rt) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Vh_vmpy_VhRh_s1_rnd_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhsrs)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vh_vmpy_VhRh_s1_rnd_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhsrs)
+#define Q6_Vh_vmpy_VhRh_s1_rnd_sat                                             \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhsrs)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vh_vmpy_VhRh_s1_rnd_sat…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.h=vmpy(Vu32.h,Rt32.h):<<1:sat
C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpy_VhRh_s1_sat(HVX_Vector Vu, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpy_VhRh_s1_sat(HVX_Vector Vu, Word32 Rt)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpy_VhRh_s1_sat(HVX_Vector Vu,
+   Word32 Rt) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Vh_vmpy_VhRh_s1_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhss)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vh_vmpy_VhRh_s1_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhss)
+#define Q6_Vh_vmpy_VhRh_s1_sat                                                 \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhss)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vh_vmpy_VhRh_s1_sat…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vdd32.w=vmpy(Vu32.h,Vv32.uh)
C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpy_VhVuh(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpy_VhVuh(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpy_VhVuh(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Ww_vmpy_VhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhus)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vxx32.w+=vmpy(Vu32.h,Vv32.uh)
C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpyacc_WwVhVuh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpyacc_WwVhVuh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpyacc_WwVhVuh(HVX_VectorPair
+   Vxx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VX_DV Execution
+   Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Ww_vmpyacc_WwVhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhus_acc)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Ww_vmpyacc_WwVhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhus_acc)
+#define Q6_Ww_vmpyacc_WwVhVuh                                                  \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhus_acc)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Ww_vmpyacc_WwVhVuh __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vdd32.w=vmpy(Vu32.h,Vv32.h)
C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpy_VhVh(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpy_VhVh(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpy_VhVh(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Ww_vmpy_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhv)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vxx32.w+=vmpy(Vu32.h,Vv32.h)
C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpyacc_WwVhVh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpyacc_WwVhVh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpyacc_WwVhVh(HVX_VectorPair
+   Vxx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VX_DV Execution
+   Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Ww_vmpyacc_WwVhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhv_acc)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Ww_vmpyacc_WwVhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhv_acc)
+#define Q6_Ww_vmpyacc_WwVhVh                                                   \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhv_acc)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Ww_vmpyacc_WwVhVh __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.h=vmpy(Vu32.h,Vv32.h):<<1:rnd:sat
C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpy_VhVh_s1_rnd_sat(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpy_VhVh_s1_rnd_sat(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpy_VhVh_s1_rnd_sat(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Vh_vmpy_VhVh_s1_rnd_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhvsrs)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vh_vmpy_VhVh_s1_rnd_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhvsrs)
+#define Q6_Vh_vmpy_VhVh_s1_rnd_sat                                             \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhvsrs)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vh_vmpy_VhVh_s1_rnd_sat…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.w=vmpyieo(Vu32.h,Vv32.h)
C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyieo_VhVh(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyieo_VhVh(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VX
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyieo_VhVh(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VX Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VX
Execution Slots: SLOT23
========================================================================== */
#define Q6_Vw_vmpyieo_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyieoh)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vx32.w+=vmpyie(Vu32.w,Vv32.h)
C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyieacc_VwVwVh(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyieacc_VwVwVh(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyieacc_VwVwVh(HVX_Vector Vx,
+   HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VX_DV Execution
+   Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Vw_vmpyieacc_VwVwVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiewh_acc)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vw_vmpyieacc_VwVwVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiewh_acc)
+#define Q6_Vw_vmpyieacc_VwVwVh                                                 \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiewh_acc)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vw_vmpyieacc_VwVwVh…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.w=vmpyie(Vu32.w,Vv32.uh)
C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyie_VwVuh(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyie_VwVuh(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyie_VwVuh(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Vw_vmpyie_VwVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiewuh)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vx32.w+=vmpyie(Vu32.w,Vv32.uh)
C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyieacc_VwVwVuh(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyieacc_VwVwVuh(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyieacc_VwVwVuh(HVX_Vector Vx,
+   HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VX_DV Execution
+   Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Vw_vmpyieacc_VwVwVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiewuh_acc)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vw_vmpyieacc_VwVwVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiewuh_acc)
+#define Q6_Vw_vmpyieacc_VwVwVuh                                                \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiewuh_acc)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vw_vmpyieacc_VwVwVuh…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.h=vmpyi(Vu32.h,Vv32.h)
C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpyi_VhVh(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpyi_VhVh(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpyi_VhVh(HVX_Vector Vu, HVX_Vector
+   Vv) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Vh_vmpyi_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyih)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vx32.h+=vmpyi(Vu32.h,Vv32.h)
C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpyiacc_VhVhVh(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpyiacc_VhVhVh(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpyiacc_VhVhVh(HVX_Vector Vx,
+   HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VX_DV Execution
+   Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Vh_vmpyiacc_VhVhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyih_acc)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vh_vmpyiacc_VhVhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyih_acc)
+#define Q6_Vh_vmpyiacc_VhVhVh                                                  \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyih_acc)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vh_vmpyiacc_VhVhVh __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.h=vmpyi(Vu32.h,Rt32.b)
C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpyi_VhRb(HVX_Vector Vu, Word32 Rt)
Instruction Type: CVI_VX
Execution Slots: SLOT23
========================================================================== */
#define Q6_Vh_vmpyi_VhRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyihb)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vx32.h+=vmpyi(Vu32.h,Rt32.b)
C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpyiacc_VhVhRb(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpyiacc_VhVhRb(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)
-   Instruction Type:      CVI_VX
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpyiacc_VhVhRb(HVX_Vector Vx,
+   HVX_Vector Vu, Word32 Rt) Instruction Type:      CVI_VX Execution Slots:
+   SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VX
Execution Slots: SLOT23
========================================================================== */
#define Q6_Vh_vmpyiacc_VhVhRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyihb_acc)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vh_vmpyiacc_VhVhRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyihb_acc)
+#define Q6_Vh_vmpyiacc_VhVhRb                                                  \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyihb_acc)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vh_vmpyiacc_VhVhRb __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.w=vmpyio(Vu32.w,Vv32.h)
C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyio_VwVh(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyio_VwVh(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyio_VwVh(HVX_Vector Vu, HVX_Vector
+   Vv) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Vw_vmpyio_VwVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiowh)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.w=vmpyi(Vu32.w,Rt32.b)
C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyi_VwRb(HVX_Vector Vu, Word32 Rt)
Instruction Type: CVI_VX
Execution Slots: SLOT23
========================================================================== */
#define Q6_Vw_vmpyi_VwRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwb)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vx32.w+=vmpyi(Vu32.w,Rt32.b)
C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyiacc_VwVwRb(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyiacc_VwVwRb(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)
-   Instruction Type:      CVI_VX
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyiacc_VwVwRb(HVX_Vector Vx,
+   HVX_Vector Vu, Word32 Rt) Instruction Type:      CVI_VX Execution Slots:
+   SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VX
Execution Slots: SLOT23
========================================================================== */
#define Q6_Vw_vmpyiacc_VwVwRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwb_acc)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vw_vmpyiacc_VwVwRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwb_acc)
+#define Q6_Vw_vmpyiacc_VwVwRb                                                  \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwb_acc)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vw_vmpyiacc_VwVwRb __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.w=vmpyi(Vu32.w,Rt32.h)
C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyi_VwRh(HVX_Vector Vu, Word32 Rt)
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Vw_vmpyi_VwRh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwh)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vx32.w+=vmpyi(Vu32.w,Rt32.h)
C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyiacc_VwVwRh(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyiacc_VwVwRh(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyiacc_VwVwRh(HVX_Vector Vx,
+   HVX_Vector Vu, Word32 Rt) Instruction Type:      CVI_VX_DV Execution Slots:
+   SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Vw_vmpyiacc_VwVwRh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwh_acc)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vw_vmpyiacc_VwVwRh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwh_acc)
+#define Q6_Vw_vmpyiacc_VwVwRh                                                  \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwh_acc)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vw_vmpyiacc_VwVwRh __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.w=vmpyo(Vu32.w,Vv32.h):<<1:sat
C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyo_VwVh_s1_sat(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyo_VwVh_s1_sat(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyo_VwVh_s1_sat(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Vw_vmpyo_VwVh_s1_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vw_vmpyo_VwVh_s1_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh)
+#define Q6_Vw_vmpyo_VwVh_s1_sat                                                \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vw_vmpyo_VwVh_s1_sat…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.w=vmpyo(Vu32.w,Vv32.h):<<1:rnd:sat
C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyo_VwVh_s1_rnd_sat(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyo_VwVh_s1_rnd_sat(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyo_VwVh_s1_rnd_sat(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Vw_vmpyo_VwVh_s1_rnd_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_rnd)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vw_vmpyo_VwVh_s1_rnd_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_rnd)
+#define Q6_Vw_vmpyo_VwVh_s1_rnd_sat                                            \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_rnd)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vw_vmpyo_VwVh_s1_rnd_sat…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vx32.w+=vmpyo(Vu32.w,Vv32.h):<<1:rnd:sat:shift
C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyoacc_VwVwVh_s1_rnd_sat_shift(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyoacc_VwVwVh_s1_rnd_sat_shift(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_Vector
+   Q6_Vw_vmpyoacc_VwVwVh_s1_rnd_sat_shift(HVX_Vector Vx, HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Vw_vmpyoacc_VwVwVh_s1_rnd_sat_shift __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_rnd_sacc)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vw_vmpyoacc_VwVwVh_s1_rnd_sat_shift __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_rnd_sacc)
+#define Q6_Vw_vmpyoacc_VwVwVh_s1_rnd_sat_shift                                 \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_rnd_sacc)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vw_vmpyoacc_VwVwVh_s1_rnd_sat_shift…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vx32.w+=vmpyo(Vu32.w,Vv32.h):<<1:sat:shift
C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyoacc_VwVwVh_s1_sat_shift(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyoacc_VwVwVh_s1_sat_shift(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_Vector
+   Q6_Vw_vmpyoacc_VwVwVh_s1_sat_shift(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector
+   Vv) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Vw_vmpyoacc_VwVwVh_s1_sat_shift __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_sacc)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vw_vmpyoacc_VwVwVh_s1_sat_shift __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_sacc)
+#define Q6_Vw_vmpyoacc_VwVwVh_s1_sat_shift                                     \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_sacc)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vw_vmpyoacc_VwVwVh_s1_sat_shift…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vdd32.uh=vmpy(Vu32.ub,Rt32.ub)
C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vmpy_VubRub(HVX_Vector Vu, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vmpy_VubRub(HVX_Vector Vu, Word32 Rt)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vmpy_VubRub(HVX_Vector Vu,
+   Word32 Rt) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Wuh_vmpy_VubRub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyub)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vxx32.uh+=vmpy(Vu32.ub,Rt32.ub)
C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vmpyacc_WuhVubRub(HVX_VectorPair Vxx, HVX_Vector Vu, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vmpyacc_WuhVubRub(HVX_VectorPair Vxx, HVX_Vector Vu, Word32 Rt)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vmpyacc_WuhVubRub(HVX_VectorPair
+   Vxx, HVX_Vector Vu, Word32 Rt) Instruction Type:      CVI_VX_DV Execution
+   Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Wuh_vmpyacc_WuhVubRub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyub_acc)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Wuh_vmpyacc_WuhVubRub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyub_acc)
+#define Q6_Wuh_vmpyacc_WuhVubRub                                               \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyub_acc)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Wuh_vmpyacc_WuhVubRub…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vdd32.uh=vmpy(Vu32.ub,Vv32.ub)
C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vmpy_VubVub(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vmpy_VubVub(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vmpy_VubVub(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Wuh_vmpy_VubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyubv)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vxx32.uh+=vmpy(Vu32.ub,Vv32.ub)
C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vmpyacc_WuhVubVub(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vmpyacc_WuhVubVub(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vmpyacc_WuhVubVub(HVX_VectorPair
+   Vxx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VX_DV Execution
+   Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Wuh_vmpyacc_WuhVubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyubv_acc)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Wuh_vmpyacc_WuhVubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyubv_acc)
+#define Q6_Wuh_vmpyacc_WuhVubVub                                               \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyubv_acc)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Wuh_vmpyacc_WuhVubVub…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vdd32.uw=vmpy(Vu32.uh,Rt32.uh)
C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vmpy_VuhRuh(HVX_Vector Vu, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vmpy_VuhRuh(HVX_Vector Vu, Word32 Rt)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vmpy_VuhRuh(HVX_Vector Vu,
+   Word32 Rt) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Wuw_vmpy_VuhRuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuh)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vxx32.uw+=vmpy(Vu32.uh,Rt32.uh)
C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vmpyacc_WuwVuhRuh(HVX_VectorPair Vxx, HVX_Vector Vu, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vmpyacc_WuwVuhRuh(HVX_VectorPair Vxx, HVX_Vector Vu, Word32 Rt)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vmpyacc_WuwVuhRuh(HVX_VectorPair
+   Vxx, HVX_Vector Vu, Word32 Rt) Instruction Type:      CVI_VX_DV Execution
+   Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Wuw_vmpyacc_WuwVuhRuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuh_acc)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Wuw_vmpyacc_WuwVuhRuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuh_acc)
+#define Q6_Wuw_vmpyacc_WuwVuhRuh                                               \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuh_acc)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Wuw_vmpyacc_WuwVuhRuh…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vdd32.uw=vmpy(Vu32.uh,Vv32.uh)
C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vmpy_VuhVuh(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vmpy_VuhVuh(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vmpy_VuhVuh(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Wuw_vmpy_VuhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhv)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vxx32.uw+=vmpy(Vu32.uh,Vv32.uh)
C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vmpyacc_WuwVuhVuh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vmpyacc_WuwVuhVuh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vmpyacc_WuwVuhVuh(HVX_VectorPair
+   Vxx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VX_DV Execution
+   Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Wuw_vmpyacc_WuwVuhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhv_acc)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Wuw_vmpyacc_WuwVuhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhv_acc)
+#define Q6_Wuw_vmpyacc_WuwVuhVuh                                               \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhv_acc)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Wuw_vmpyacc_WuwVuhVuh…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32=vmux(Qt4,Vu32,Vv32)
C Intrinsic Prototype: HVX_Vector Q6_V_vmux_QVV(HVX_VectorPred Qt, HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_V_vmux_QVV(HVX_VectorPred Qt, HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_V_vmux_QVV(HVX_VectorPred Qt, HVX_Vector
+   Vu, HVX_Vector Vv) Instruction Type:      CVI_VA Execution Slots: SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector Q6_V_vmux_QVV…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_V_vmux_QVV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmux)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.h=vnavg(Vu32.h,Vv32.h)
C Intrinsic Prototype: HVX_Vector Q6_Vh_vnavg_VhVh(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vh_vnavg_VhVh(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vnavg_VhVh(HVX_Vector Vu, HVX_Vector
+   Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vh_vnavg_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnavgh)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.b=vnavg(Vu32.ub,Vv32.ub)
C Intrinsic Prototype: HVX_Vector Q6_Vb_vnavg_VubVub(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vb_vnavg_VubVub(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_vnavg_VubVub(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vb_vnavg_VubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnavgub)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.w=vnavg(Vu32.w,Vv32.w)
C Intrinsic Prototype: HVX_Vector Q6_Vw_vnavg_VwVw(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vw_vnavg_VwVw(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vnavg_VwVw(HVX_Vector Vu, HVX_Vector
+   Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vw_vnavg_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnavgw)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.h=vnormamt(Vu32.h)
C Intrinsic Prototype: HVX_Vector Q6_Vh_vnormamt_Vh(HVX_Vector Vu)
Instruction Type: CVI_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vh_vnormamt_Vh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnormamth)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.w=vnormamt(Vu32.w)
C Intrinsic Prototype: HVX_Vector Q6_Vw_vnormamt_Vw(HVX_Vector Vu)
Instruction Type: CVI_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vw_vnormamt_Vw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnormamtw)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32=vnot(Vu32)
C Intrinsic Prototype: HVX_Vector Q6_V_vnot_V(HVX_Vector Vu)
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_V_vnot_V __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnot)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32=vor(Vu32,Vv32)
C Intrinsic Prototype: HVX_Vector Q6_V_vor_VV(HVX_Vector Vu, HVX_Vector Vv)
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_V_vor_VV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vor)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.b=vpacke(Vu32.h,Vv32.h)
C Intrinsic Prototype: HVX_Vector Q6_Vb_vpacke_VhVh(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vb_vpacke_VhVh(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VP
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_vpacke_VhVh(HVX_Vector Vu, HVX_Vector
+   Vv) Instruction Type:      CVI_VP Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VP
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vb_vpacke_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackeb)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.h=vpacke(Vu32.w,Vv32.w)
C Intrinsic Prototype: HVX_Vector Q6_Vh_vpacke_VwVw(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vh_vpacke_VwVw(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VP
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vpacke_VwVw(HVX_Vector Vu, HVX_Vector
+   Vv) Instruction Type:      CVI_VP Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VP
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vh_vpacke_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackeh)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.b=vpack(Vu32.h,Vv32.h):sat
C Intrinsic Prototype: HVX_Vector Q6_Vb_vpack_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vb_vpack_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VP
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_vpack_VhVh_sat(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VP Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VP
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vb_vpack_VhVh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackhb_sat)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vb_vpack_VhVh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackhb_sat)
+#define Q6_Vb_vpack_VhVh_sat                                                   \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackhb_sat)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vb_vpack_VhVh_sat __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.ub=vpack(Vu32.h,Vv32.h):sat
C Intrinsic Prototype: HVX_Vector Q6_Vub_vpack_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vub_vpack_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VP
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vub_vpack_VhVh_sat(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VP Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VP
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vub_vpack_VhVh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackhub_sat)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vub_vpack_VhVh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackhub_sat)
+#define Q6_Vub_vpack_VhVh_sat                                                  \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackhub_sat)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vub_vpack_VhVh_sat __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.b=vpacko(Vu32.h,Vv32.h)
C Intrinsic Prototype: HVX_Vector Q6_Vb_vpacko_VhVh(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vb_vpacko_VhVh(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VP
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_vpacko_VhVh(HVX_Vector Vu, HVX_Vector
+   Vv) Instruction Type:      CVI_VP Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VP
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vb_vpacko_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackob)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.h=vpacko(Vu32.w,Vv32.w)
C Intrinsic Prototype: HVX_Vector Q6_Vh_vpacko_VwVw(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vh_vpacko_VwVw(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VP
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vpacko_VwVw(HVX_Vector Vu, HVX_Vector
+   Vv) Instruction Type:      CVI_VP Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VP
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vh_vpacko_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackoh)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.h=vpack(Vu32.w,Vv32.w):sat
C Intrinsic Prototype: HVX_Vector Q6_Vh_vpack_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vh_vpack_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VP
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vpack_VwVw_sat(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VP Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VP
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vh_vpack_VwVw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackwh_sat)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vh_vpack_VwVw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackwh_sat)
+#define Q6_Vh_vpack_VwVw_sat                                                   \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackwh_sat)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vh_vpack_VwVw_sat __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.uh=vpack(Vu32.w,Vv32.w):sat
C Intrinsic Prototype: HVX_Vector Q6_Vuh_vpack_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vuh_vpack_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VP
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vuh_vpack_VwVw_sat(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VP Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VP
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vuh_vpack_VwVw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackwuh_sat)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vuh_vpack_VwVw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackwuh_sat)
+#define Q6_Vuh_vpack_VwVw_sat                                                  \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackwuh_sat)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vuh_vpack_VwVw_sat __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.h=vpopcount(Vu32.h)
C Intrinsic Prototype: HVX_Vector Q6_Vh_vpopcount_Vh(HVX_Vector Vu)
Instruction Type: CVI_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vh_vpopcount_Vh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpopcounth)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vh_vpopcount_Vh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpopcounth)
+#define Q6_Vh_vpopcount_Vh                                                     \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpopcounth)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vh_vpopcount_Vh __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32=vrdelta(Vu32,Vv32)
C Intrinsic Prototype: HVX_Vector Q6_V_vrdelta_VV(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_V_vrdelta_VV(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VP
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_V_vrdelta_VV(HVX_Vector Vu, HVX_Vector
+   Vv) Instruction Type:      CVI_VP Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VP
Execution Slots: SLOT0123
========================================================================== */
#define Q6_V_vrdelta_VV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrdelta)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.w=vrmpy(Vu32.ub,Rt32.b)
C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpy_VubRb(HVX_Vector Vu, Word32 Rt)
Instruction Type: CVI_VX
Execution Slots: SLOT23
========================================================================== */
#define Q6_Vw_vrmpy_VubRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybus)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vx32.w+=vrmpy(Vu32.ub,Rt32.b)
C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpyacc_VwVubRb(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpyacc_VwVubRb(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)
-   Instruction Type:      CVI_VX
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpyacc_VwVubRb(HVX_Vector Vx,
+   HVX_Vector Vu, Word32 Rt) Instruction Type:      CVI_VX Execution Slots:
+   SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VX
Execution Slots: SLOT23
========================================================================== */
#define Q6_Vw_vrmpyacc_VwVubRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybus_acc)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vw_vrmpyacc_VwVubRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybus_acc)
+#define Q6_Vw_vrmpyacc_VwVubRb                                                 \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybus_acc)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vw_vrmpyacc_VwVubRb…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vdd32.w=vrmpy(Vuu32.ub,Rt32.b,#u1)
C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vrmpy_WubRbI(HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vrmpy_WubRbI(HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vrmpy_WubRbI(HVX_VectorPair Vuu,
+   Word32 Rt, Word32 Iu1) Instruction Type:      CVI_VX_DV Execution Slots:
+   SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Ww_vrmpy_WubRbI __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybusi)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vxx32.w+=vrmpy(Vuu32.ub,Rt32.b,#u1)
C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vrmpyacc_WwWubRbI(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vrmpyacc_WwWubRbI(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1)
-   Instruction Type:      CVI_VX_DV
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vrmpyacc_WwWubRbI(HVX_VectorPair
+   Vxx, HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1) Instruction Type: CVI_VX_DV
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Ww_vrmpyacc_WwWubRbI __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybusi_acc)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Ww_vrmpyacc_WwWubRbI __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybusi_acc)
+#define Q6_Ww_vrmpyacc_WwWubRbI                                                \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybusi_acc)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Ww_vrmpyacc_WwWubRbI…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.w=vrmpy(Vu32.ub,Vv32.b)
C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpy_VubVb(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpy_VubVb(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VX
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpy_VubVb(HVX_Vector Vu, HVX_Vector
+   Vv) Instruction Type:      CVI_VX Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VX
Execution Slots: SLOT23
========================================================================== */
#define Q6_Vw_vrmpy_VubVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybusv)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vx32.w+=vrmpy(Vu32.ub,Vv32.b)
C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpyacc_VwVubVb(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpyacc_VwVubVb(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpyacc_VwVubVb(HVX_Vector Vx,
+   HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VX_DV Execution
+   Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Vw_vrmpyacc_VwVubVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybusv_acc)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vw_vrmpyacc_VwVubVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybusv_acc)
+#define Q6_Vw_vrmpyacc_VwVubVb                                                 \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybusv_acc)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vw_vrmpyacc_VwVubVb…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.w=vrmpy(Vu32.b,Vv32.b)
C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpy_VbVb(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpy_VbVb(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VX
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpy_VbVb(HVX_Vector Vu, HVX_Vector
+   Vv) Instruction Type:      CVI_VX Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VX
Execution Slots: SLOT23
========================================================================== */
#define Q6_Vw_vrmpy_VbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybv)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vx32.w+=vrmpy(Vu32.b,Vv32.b)
C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpyacc_VwVbVb(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpyacc_VwVbVb(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpyacc_VwVbVb(HVX_Vector Vx,
+   HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VX_DV Execution
+   Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Vw_vrmpyacc_VwVbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybv_acc)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vw_vrmpyacc_VwVbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybv_acc)
+#define Q6_Vw_vrmpyacc_VwVbVb                                                  \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybv_acc)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vw_vrmpyacc_VwVbVb __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.uw=vrmpy(Vu32.ub,Rt32.ub)
C Intrinsic Prototype: HVX_Vector Q6_Vuw_vrmpy_VubRub(HVX_Vector Vu, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vuw_vrmpy_VubRub(HVX_Vector Vu, Word32 Rt)
-   Instruction Type:      CVI_VX
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_Vector Q6_Vuw_vrmpy_VubRub(HVX_Vector Vu, Word32
+   Rt) Instruction Type:      CVI_VX Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VX
Execution Slots: SLOT23
========================================================================== */
#define Q6_Vuw_vrmpy_VubRub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyub)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vx32.uw+=vrmpy(Vu32.ub,Rt32.ub)
C Intrinsic Prototype: HVX_Vector Q6_Vuw_vrmpyacc_VuwVubRub(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vuw_vrmpyacc_VuwVubRub(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)
-   Instruction Type:      CVI_VX
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_Vector Q6_Vuw_vrmpyacc_VuwVubRub(HVX_Vector Vx,
+   HVX_Vector Vu, Word32 Rt) Instruction Type:      CVI_VX Execution Slots:
+   SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VX
Execution Slots: SLOT23
========================================================================== */
#define Q6_Vuw_vrmpyacc_VuwVubRub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyub_acc)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vuw_vrmpyacc_VuwVubRub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyub_acc)
+#define Q6_Vuw_vrmpyacc_VuwVubRub                                              \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyub_acc)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vuw_vrmpyacc_VuwVubRub…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vdd32.uw=vrmpy(Vuu32.ub,Rt32.ub,#u1)
C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vrmpy_WubRubI(HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vrmpy_WubRubI(HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vrmpy_WubRubI(HVX_VectorPair
+   Vuu, Word32 Rt, Word32 Iu1) Instruction Type:      CVI_VX_DV Execution Slots:
+   SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Wuw_vrmpy_WubRubI __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyubi)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Wuw_vrmpy_WubRubI __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyubi)
+#define Q6_Wuw_vrmpy_WubRubI                                                   \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyubi)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Wuw_vrmpy_WubRubI __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vxx32.uw+=vrmpy(Vuu32.ub,Rt32.ub,#u1)
C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vrmpyacc_WuwWubRubI(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vrmpyacc_WuwWubRubI(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_VectorPair
+   Q6_Wuw_vrmpyacc_WuwWubRubI(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt,
+   Word32 Iu1) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Wuw_vrmpyacc_WuwWubRubI __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyubi_acc)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Wuw_vrmpyacc_WuwWubRubI __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyubi_acc)
+#define Q6_Wuw_vrmpyacc_WuwWubRubI                                             \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyubi_acc)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Wuw_vrmpyacc_WuwWubRubI…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.uw=vrmpy(Vu32.ub,Vv32.ub)
C Intrinsic Prototype: HVX_Vector Q6_Vuw_vrmpy_VubVub(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vuw_vrmpy_VubVub(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VX
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_Vector Q6_Vuw_vrmpy_VubVub(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VX Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VX
Execution Slots: SLOT23
========================================================================== */
#define Q6_Vuw_vrmpy_VubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyubv)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vx32.uw+=vrmpy(Vu32.ub,Vv32.ub)
C Intrinsic Prototype: HVX_Vector Q6_Vuw_vrmpyacc_VuwVubVub(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vuw_vrmpyacc_VuwVubVub(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_Vector Q6_Vuw_vrmpyacc_VuwVubVub(HVX_Vector Vx,
+   HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VX_DV Execution
+   Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Vuw_vrmpyacc_VuwVubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyubv_acc)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vuw_vrmpyacc_VuwVubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyubv_acc)
+#define Q6_Vuw_vrmpyacc_VuwVubVub                                              \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyubv_acc)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vuw_vrmpyacc_VuwVubVub…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32=vror(Vu32,Rt32)
C Intrinsic Prototype: HVX_Vector Q6_V_vror_VR(HVX_Vector Vu, Word32 Rt)
Instruction Type: CVI_VP
Execution Slots: SLOT0123
========================================================================== */
#define Q6_V_vror_VR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vror)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.b=vround(Vu32.h,Vv32.h):sat
C Intrinsic Prototype: HVX_Vector Q6_Vb_vround_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vb_vround_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VS
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_vround_VhVh_sat(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VS Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vb_vround_VhVh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundhb)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vb_vround_VhVh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundhb)
+#define Q6_Vb_vround_VhVh_sat                                                  \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundhb)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vb_vround_VhVh_sat __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.ub=vround(Vu32.h,Vv32.h):sat
C Intrinsic Prototype: HVX_Vector Q6_Vub_vround_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vub_vround_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VS
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vub_vround_VhVh_sat(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VS Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vub_vround_VhVh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundhub)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vub_vround_VhVh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundhub)
+#define Q6_Vub_vround_VhVh_sat                                                 \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundhub)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vub_vround_VhVh_sat…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.h=vround(Vu32.w,Vv32.w):sat
C Intrinsic Prototype: HVX_Vector Q6_Vh_vround_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vh_vround_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VS
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vround_VwVw_sat(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VS Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vh_vround_VwVw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundwh)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vh_vround_VwVw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundwh)
+#define Q6_Vh_vround_VwVw_sat                                                  \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundwh)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vh_vround_VwVw_sat __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.uh=vround(Vu32.w,Vv32.w):sat
C Intrinsic Prototype: HVX_Vector Q6_Vuh_vround_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vuh_vround_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VS
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vuh_vround_VwVw_sat(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VS Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vuh_vround_VwVw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundwuh)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vuh_vround_VwVw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundwuh)
+#define Q6_Vuh_vround_VwVw_sat                                                 \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundwuh)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vuh_vround_VwVw_sat…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vdd32.uw=vrsad(Vuu32.ub,Rt32.ub,#u1)
C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vrsad_WubRubI(HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vrsad_WubRubI(HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vrsad_WubRubI(HVX_VectorPair
+   Vuu, Word32 Rt, Word32 Iu1) Instruction Type:      CVI_VX_DV Execution Slots:
+   SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Wuw_vrsad_WubRubI __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrsadubi)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Wuw_vrsad_WubRubI __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrsadubi)
+#define Q6_Wuw_vrsad_WubRubI                                                   \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrsadubi)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Wuw_vrsad_WubRubI __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vxx32.uw+=vrsad(Vuu32.ub,Rt32.ub,#u1)
C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vrsadacc_WuwWubRubI(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vrsadacc_WuwWubRubI(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_VectorPair
+   Q6_Wuw_vrsadacc_WuwWubRubI(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt,
+   Word32 Iu1) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Wuw_vrsadacc_WuwWubRubI __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrsadubi_acc)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Wuw_vrsadacc_WuwWubRubI __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrsadubi_acc)
+#define Q6_Wuw_vrsadacc_WuwWubRubI                                             \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrsadubi_acc)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Wuw_vrsadacc_WuwWubRubI…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.ub=vsat(Vu32.h,Vv32.h)
C Intrinsic Prototype: HVX_Vector Q6_Vub_vsat_VhVh(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vub_vsat_VhVh(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vub_vsat_VhVh(HVX_Vector Vu, HVX_Vector
+   Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vub_vsat_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsathub)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.h=vsat(Vu32.w,Vv32.w)
C Intrinsic Prototype: HVX_Vector Q6_Vh_vsat_VwVw(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vh_vsat_VwVw(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vsat_VwVw(HVX_Vector Vu, HVX_Vector
+   Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vh_vsat_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsatwh)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vdd32.h=vsxt(Vu32.b)
C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vsxt_Vb(HVX_Vector Vu)
Instruction Type: CVI_VA_DV
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Wh_vsxt_Vb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsb)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vdd32.w=vsxt(Vu32.h)
C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vsxt_Vh(HVX_Vector Vu)
Instruction Type: CVI_VA_DV
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Ww_vsxt_Vh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsh)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.h=vshuffe(Vu32.h,Vv32.h)
C Intrinsic Prototype: HVX_Vector Q6_Vh_vshuffe_VhVh(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vh_vshuffe_VhVh(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vshuffe_VhVh(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vh_vshuffe_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshufeh)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.b=vshuff(Vu32.b)
C Intrinsic Prototype: HVX_Vector Q6_Vb_vshuff_Vb(HVX_Vector Vu)
Instruction Type: CVI_VP
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vb_vshuff_Vb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffb)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.b=vshuffe(Vu32.b,Vv32.b)
C Intrinsic Prototype: HVX_Vector Q6_Vb_vshuffe_VbVb(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vb_vshuffe_VbVb(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_vshuffe_VbVb(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vb_vshuffe_VbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffeb)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.h=vshuff(Vu32.h)
C Intrinsic Prototype: HVX_Vector Q6_Vh_vshuff_Vh(HVX_Vector Vu)
Instruction Type: CVI_VP
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vh_vshuff_Vh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffh)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.b=vshuffo(Vu32.b,Vv32.b)
C Intrinsic Prototype: HVX_Vector Q6_Vb_vshuffo_VbVb(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vb_vshuffo_VbVb(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_vshuffo_VbVb(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vb_vshuffo_VbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffob)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vdd32=vshuff(Vu32,Vv32,Rt8)
C Intrinsic Prototype: HVX_VectorPair Q6_W_vshuff_VVR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_W_vshuff_VVR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
-   Instruction Type:      CVI_VP_VS
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPair Q6_W_vshuff_VVR(HVX_Vector Vu,
+   HVX_Vector Vv, Word32 Rt) Instruction Type:      CVI_VP_VS Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VP_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_W_vshuff_VVR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffvdd)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vdd32.b=vshuffoe(Vu32.b,Vv32.b)
C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vshuffoe_VbVb(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vshuffoe_VbVb(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA_DV
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vshuffoe_VbVb(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VA_DV Execution Slots: SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VA_DV
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Wb_vshuffoe_VbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshufoeb)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vdd32.h=vshuffoe(Vu32.h,Vv32.h)
C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vshuffoe_VhVh(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vshuffoe_VhVh(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA_DV
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vshuffoe_VhVh(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VA_DV Execution Slots: SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VA_DV
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Wh_vshuffoe_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshufoeh)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.h=vshuffo(Vu32.h,Vv32.h)
C Intrinsic Prototype: HVX_Vector Q6_Vh_vshuffo_VhVh(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vh_vshuffo_VhVh(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vshuffo_VhVh(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vh_vshuffo_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshufoh)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.b=vsub(Vu32.b,Vv32.b)
C Intrinsic Prototype: HVX_Vector Q6_Vb_vsub_VbVb(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vb_vsub_VbVb(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_vsub_VbVb(HVX_Vector Vu, HVX_Vector
+   Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vb_vsub_VbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubb)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vdd32.b=vsub(Vuu32.b,Vvv32.b)
C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vsub_WbWb(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vsub_WbWb(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
-   Instruction Type:      CVI_VA_DV
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vsub_WbWb(HVX_VectorPair Vuu,
+   HVX_VectorPair Vvv) Instruction Type:      CVI_VA_DV Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VA_DV
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Wb_vsub_WbWb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubb_dv)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: if (!Qv4) Vx32.b-=Vu32.b
C Intrinsic Prototype: HVX_Vector Q6_Vb_condnac_QnVbVb(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vb_condnac_QnVbVb(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_condnac_QnVbVb(HVX_VectorPred Qv,
+   HVX_Vector Vx, HVX_Vector Vu) Instruction Type:      CVI_VA Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vb_condnac_QnVbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubbnq)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: if (Qv4) Vx32.b-=Vu32.b
C Intrinsic Prototype: HVX_Vector Q6_Vb_condnac_QVbVb(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vb_condnac_QVbVb(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_condnac_QVbVb(HVX_VectorPred Qv,
+   HVX_Vector Vx, HVX_Vector Vu) Instruction Type:      CVI_VA Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vb_condnac_QVbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubbq)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.h=vsub(Vu32.h,Vv32.h)
C Intrinsic Prototype: HVX_Vector Q6_Vh_vsub_VhVh(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vh_vsub_VhVh(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vsub_VhVh(HVX_Vector Vu, HVX_Vector
+   Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vh_vsub_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubh)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vdd32.h=vsub(Vuu32.h,Vvv32.h)
C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vsub_WhWh(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vsub_WhWh(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
-   Instruction Type:      CVI_VA_DV
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vsub_WhWh(HVX_VectorPair Vuu,
+   HVX_VectorPair Vvv) Instruction Type:      CVI_VA_DV Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VA_DV
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Wh_vsub_WhWh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubh_dv)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: if (!Qv4) Vx32.h-=Vu32.h
C Intrinsic Prototype: HVX_Vector Q6_Vh_condnac_QnVhVh(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vh_condnac_QnVhVh(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_condnac_QnVhVh(HVX_VectorPred Qv,
+   HVX_Vector Vx, HVX_Vector Vu) Instruction Type:      CVI_VA Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vh_condnac_QnVhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhnq)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: if (Qv4) Vx32.h-=Vu32.h
C Intrinsic Prototype: HVX_Vector Q6_Vh_condnac_QVhVh(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vh_condnac_QVhVh(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_condnac_QVhVh(HVX_VectorPred Qv,
+   HVX_Vector Vx, HVX_Vector Vu) Instruction Type:      CVI_VA Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vh_condnac_QVhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhq)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.h=vsub(Vu32.h,Vv32.h):sat
C Intrinsic Prototype: HVX_Vector Q6_Vh_vsub_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vh_vsub_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vsub_VhVh_sat(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vh_vsub_VhVh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhsat)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vdd32.h=vsub(Vuu32.h,Vvv32.h):sat
C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vsub_WhWh_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vsub_WhWh_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
-   Instruction Type:      CVI_VA_DV
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vsub_WhWh_sat(HVX_VectorPair Vuu,
+   HVX_VectorPair Vvv) Instruction Type:      CVI_VA_DV Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VA_DV
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Wh_vsub_WhWh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhsat_dv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Wh_vsub_WhWh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhsat_dv)
+#define Q6_Wh_vsub_WhWh_sat                                                    \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhsat_dv)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Wh_vsub_WhWh_sat __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vdd32.w=vsub(Vu32.h,Vv32.h)
C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vsub_VhVh(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vsub_VhVh(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vsub_VhVh(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Ww_vsub_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhw)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vdd32.h=vsub(Vu32.ub,Vv32.ub)
C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vsub_VubVub(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vsub_VubVub(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vsub_VubVub(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Wh_vsub_VubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsububh)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.ub=vsub(Vu32.ub,Vv32.ub):sat
C Intrinsic Prototype: HVX_Vector Q6_Vub_vsub_VubVub_sat(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vub_vsub_VubVub_sat(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vub_vsub_VubVub_sat(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vub_vsub_VubVub_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsububsat)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vub_vsub_VubVub_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsububsat)
+#define Q6_Vub_vsub_VubVub_sat                                                 \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsububsat)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vub_vsub_VubVub_sat…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vdd32.ub=vsub(Vuu32.ub,Vvv32.ub):sat
C Intrinsic Prototype: HVX_VectorPair Q6_Wub_vsub_WubWub_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Wub_vsub_WubWub_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
-   Instruction Type:      CVI_VA_DV
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wub_vsub_WubWub_sat(HVX_VectorPair
+   Vuu, HVX_VectorPair Vvv) Instruction Type:      CVI_VA_DV Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VA_DV
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Wub_vsub_WubWub_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsububsat_dv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Wub_vsub_WubWub_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsububsat_dv)
+#define Q6_Wub_vsub_WubWub_sat                                                 \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsububsat_dv)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Wub_vsub_WubWub_sat…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.uh=vsub(Vu32.uh,Vv32.uh):sat
C Intrinsic Prototype: HVX_Vector Q6_Vuh_vsub_VuhVuh_sat(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vuh_vsub_VuhVuh_sat(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vuh_vsub_VuhVuh_sat(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vuh_vsub_VuhVuh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuhsat)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vuh_vsub_VuhVuh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuhsat)
+#define Q6_Vuh_vsub_VuhVuh_sat                                                 \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuhsat)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vuh_vsub_VuhVuh_sat…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vdd32.uh=vsub(Vuu32.uh,Vvv32.uh):sat
C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vsub_WuhWuh_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vsub_WuhWuh_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
-   Instruction Type:      CVI_VA_DV
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vsub_WuhWuh_sat(HVX_VectorPair
+   Vuu, HVX_VectorPair Vvv) Instruction Type:      CVI_VA_DV Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VA_DV
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Wuh_vsub_WuhWuh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuhsat_dv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Wuh_vsub_WuhWuh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuhsat_dv)
+#define Q6_Wuh_vsub_WuhWuh_sat                                                 \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuhsat_dv)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Wuh_vsub_WuhWuh_sat…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vdd32.w=vsub(Vu32.uh,Vv32.uh)
C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vsub_VuhVuh(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vsub_VuhVuh(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vsub_VuhVuh(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Ww_vsub_VuhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuhw)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.w=vsub(Vu32.w,Vv32.w)
C Intrinsic Prototype: HVX_Vector Q6_Vw_vsub_VwVw(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vw_vsub_VwVw(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vsub_VwVw(HVX_Vector Vu, HVX_Vector
+   Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vw_vsub_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubw)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vdd32.w=vsub(Vuu32.w,Vvv32.w)
C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vsub_WwWw(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vsub_WwWw(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
-   Instruction Type:      CVI_VA_DV
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vsub_WwWw(HVX_VectorPair Vuu,
+   HVX_VectorPair Vvv) Instruction Type:      CVI_VA_DV Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VA_DV
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Ww_vsub_WwWw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubw_dv)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: if (!Qv4) Vx32.w-=Vu32.w
C Intrinsic Prototype: HVX_Vector Q6_Vw_condnac_QnVwVw(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vw_condnac_QnVwVw(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_condnac_QnVwVw(HVX_VectorPred Qv,
+   HVX_Vector Vx, HVX_Vector Vu) Instruction Type:      CVI_VA Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vw_condnac_QnVwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubwnq)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: if (Qv4) Vx32.w-=Vu32.w
C Intrinsic Prototype: HVX_Vector Q6_Vw_condnac_QVwVw(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vw_condnac_QVwVw(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_condnac_QVwVw(HVX_VectorPred Qv,
+   HVX_Vector Vx, HVX_Vector Vu) Instruction Type:      CVI_VA Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vw_condnac_QVwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubwq)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32.w=vsub(Vu32.w,Vv32.w):sat
C Intrinsic Prototype: HVX_Vector Q6_Vw_vsub_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vw_vsub_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vsub_VwVw_sat(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vw_vsub_VwVw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubwsat)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vdd32.w=vsub(Vuu32.w,Vvv32.w):sat
C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vsub_WwWw_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vsub_WwWw_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
-   Instruction Type:      CVI_VA_DV
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vsub_WwWw_sat(HVX_VectorPair Vuu,
+   HVX_VectorPair Vvv) Instruction Type:      CVI_VA_DV Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VA_DV
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Ww_vsub_WwWw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubwsat_dv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Ww_vsub_WwWw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubwsat_dv)
+#define Q6_Ww_vsub_WwWw_sat                                                    \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubwsat_dv)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Ww_vsub_WwWw_sat __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vdd32=vswap(Qt4,Vu32,Vv32)
C Intrinsic Prototype: HVX_VectorPair Q6_W_vswap_QVV(HVX_VectorPred Qt, HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_W_vswap_QVV(HVX_VectorPred Qt, HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA_DV
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPair Q6_W_vswap_QVV(HVX_VectorPred Qt,
+   HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VA_DV Execution
+   Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VA_DV
Execution Slots: SLOT0123
========================================================================== */
#define Q6_W_vswap_QVV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vswap)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vdd32.h=vtmpy(Vuu32.b,Rt32.b)
C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vtmpy_WbRb(HVX_VectorPair Vuu, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vtmpy_WbRb(HVX_VectorPair Vuu, Word32 Rt)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vtmpy_WbRb(HVX_VectorPair Vuu,
+   Word32 Rt) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Wh_vtmpy_WbRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpyb)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vxx32.h+=vtmpy(Vuu32.b,Rt32.b)
C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vtmpyacc_WhWbRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vtmpyacc_WhWbRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt)
-   Instruction Type:      CVI_VX_DV
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vtmpyacc_WhWbRb(HVX_VectorPair
+   Vxx, HVX_VectorPair Vuu, Word32 Rt) Instruction Type:      CVI_VX_DV
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Wh_vtmpyacc_WhWbRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpyb_acc)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Wh_vtmpyacc_WhWbRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpyb_acc)
+#define Q6_Wh_vtmpyacc_WhWbRb                                                  \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpyb_acc)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Wh_vtmpyacc_WhWbRb __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vdd32.h=vtmpy(Vuu32.ub,Rt32.b)
C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vtmpy_WubRb(HVX_VectorPair Vuu, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vtmpy_WubRb(HVX_VectorPair Vuu, Word32 Rt)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vtmpy_WubRb(HVX_VectorPair Vuu,
+   Word32 Rt) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Wh_vtmpy_WubRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpybus)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vxx32.h+=vtmpy(Vuu32.ub,Rt32.b)
C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vtmpyacc_WhWubRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vtmpyacc_WhWubRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt)
-   Instruction Type:      CVI_VX_DV
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vtmpyacc_WhWubRb(HVX_VectorPair
+   Vxx, HVX_VectorPair Vuu, Word32 Rt) Instruction Type:      CVI_VX_DV
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Wh_vtmpyacc_WhWubRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpybus_acc)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Wh_vtmpyacc_WhWubRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpybus_acc)
+#define Q6_Wh_vtmpyacc_WhWubRb                                                 \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpybus_acc)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Wh_vtmpyacc_WhWubRb…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vdd32.w=vtmpy(Vuu32.h,Rt32.b)
C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vtmpy_WhRb(HVX_VectorPair Vuu, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vtmpy_WhRb(HVX_VectorPair Vuu, Word32 Rt)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vtmpy_WhRb(HVX_VectorPair Vuu,
+   Word32 Rt) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Ww_vtmpy_WhRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpyhb)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vxx32.w+=vtmpy(Vuu32.h,Rt32.b)
C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vtmpyacc_WwWhRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vtmpyacc_WwWhRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt)
-   Instruction Type:      CVI_VX_DV
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vtmpyacc_WwWhRb(HVX_VectorPair
+   Vxx, HVX_VectorPair Vuu, Word32 Rt) Instruction Type:      CVI_VX_DV
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Ww_vtmpyacc_WwWhRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpyhb_acc)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Ww_vtmpyacc_WwWhRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpyhb_acc)
+#define Q6_Ww_vtmpyacc_WwWhRb                                                  \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpyhb_acc)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Ww_vtmpyacc_WwWhRb __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vdd32.h=vunpack(Vu32.b)
C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vunpack_Vb(HVX_Vector Vu)
Instruction Type: CVI_VP_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Wh_vunpack_Vb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackb)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vdd32.w=vunpack(Vu32.h)
C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vunpack_Vh(HVX_Vector Vu)
Instruction Type: CVI_VP_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Ww_vunpack_Vh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackh)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vxx32.h|=vunpacko(Vu32.b)
C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vunpackoor_WhVb(HVX_VectorPair Vxx, HVX_Vector Vu)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vunpackoor_WhVb(HVX_VectorPair Vxx, HVX_Vector Vu)
-   Instruction Type:      CVI_VP_VS
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vunpackoor_WhVb(HVX_VectorPair
+   Vxx, HVX_Vector Vu) Instruction Type:      CVI_VP_VS Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VP_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Wh_vunpackoor_WhVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackob)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Wh_vunpackoor_WhVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackob)
+#define Q6_Wh_vunpackoor_WhVb                                                  \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackob)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Wh_vunpackoor_WhVb __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vxx32.w|=vunpacko(Vu32.h)
C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vunpackoor_WwVh(HVX_VectorPair Vxx, HVX_Vector Vu)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vunpackoor_WwVh(HVX_VectorPair Vxx, HVX_Vector Vu)
-   Instruction Type:      CVI_VP_VS
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vunpackoor_WwVh(HVX_VectorPair
+   Vxx, HVX_Vector Vu) Instruction Type:      CVI_VP_VS Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VP_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Ww_vunpackoor_WwVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackoh)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Ww_vunpackoor_WwVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackoh)
+#define Q6_Ww_vunpackoor_WwVh                                                  \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackoh)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Ww_vunpackoor_WwVh __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vdd32.uh=vunpack(Vu32.ub)
C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vunpack_Vub(HVX_Vector Vu)
Instruction Type: CVI_VP_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Wuh_vunpack_Vub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackub)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vdd32.uw=vunpack(Vu32.uh)
C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vunpack_Vuh(HVX_Vector Vu)
Instruction Type: CVI_VP_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Wuw_vunpack_Vuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackuh)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vd32=vxor(Vu32,Vv32)
C Intrinsic Prototype: HVX_Vector Q6_V_vxor_VV(HVX_Vector Vu, HVX_Vector Vv)
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_V_vxor_VV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vxor)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vdd32.uh=vzxt(Vu32.ub)
C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vzxt_Vub(HVX_Vector Vu)
Instruction Type: CVI_VA_DV
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Wuh_vzxt_Vub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vzb)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 60
/* ==========================================================================
Assembly Syntax: Vdd32.uw=vzxt(Vu32.uh)
C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vzxt_Vuh(HVX_Vector Vu)
Instruction Type: CVI_VA_DV
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Wuw_vzxt_Vuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vzh)
#endif /* __HEXAGON_ARCH___ >= 60 */
#if __HVX_ARCH__ >= 62
/* ==========================================================================
Assembly Syntax: Vd32.b=vsplat(Rt32)
C Intrinsic Prototype: HVX_Vector Q6_Vb_vsplat_R(Word32 Rt)
Instruction Type: CVI_VX_LATE
Execution Slots: SLOT23
========================================================================== */
#define Q6_Vb_vsplat_R __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lvsplatb)
#endif /* __HEXAGON_ARCH___ >= 62 */
#if __HVX_ARCH__ >= 62
/* ==========================================================================
Assembly Syntax: Vd32.h=vsplat(Rt32)
C Intrinsic Prototype: HVX_Vector Q6_Vh_vsplat_R(Word32 Rt)
Instruction Type: CVI_VX_LATE
Execution Slots: SLOT23
========================================================================== */
#define Q6_Vh_vsplat_R __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lvsplath)
#endif /* __HEXAGON_ARCH___ >= 62 */
#if __HVX_ARCH__ >= 62
/* ==========================================================================
Assembly Syntax: Qd4=vsetq2(Rt32)
C Intrinsic Prototype: HVX_VectorPred Q6_Q_vsetq2_R(Word32 Rt)
Instruction Type: CVI_VP
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Q_vsetq2_R __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_scalar2v2)
#endif /* __HEXAGON_ARCH___ >= 62 */
#if __HVX_ARCH__ >= 62
/* ==========================================================================
Assembly Syntax: Qd4.b=vshuffe(Qs4.h,Qt4.h)
C Intrinsic Prototype: HVX_VectorPred Q6_Qb_vshuffe_QhQh(HVX_VectorPred Qs, HVX_VectorPred Qt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPred Q6_Qb_vshuffe_QhQh(HVX_VectorPred Qs, HVX_VectorPred Qt)
-   Instruction Type:      CVI_VA_DV
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPred Q6_Qb_vshuffe_QhQh(HVX_VectorPred Qs,
+   HVX_VectorPred Qt) Instruction Type:      CVI_VA_DV Execution Slots: SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPred…
Instruction Type: CVI_VA_DV
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Qb_vshuffe_QhQh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_shuffeqh)
#endif /* __HEXAGON_ARCH___ >= 62 */
#if __HVX_ARCH__ >= 62
/* ==========================================================================
Assembly Syntax: Qd4.h=vshuffe(Qs4.w,Qt4.w)
C Intrinsic Prototype: HVX_VectorPred Q6_Qh_vshuffe_QwQw(HVX_VectorPred Qs, HVX_VectorPred Qt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPred Q6_Qh_vshuffe_QwQw(HVX_VectorPred Qs, HVX_VectorPred Qt)
-   Instruction Type:      CVI_VA_DV
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPred Q6_Qh_vshuffe_QwQw(HVX_VectorPred Qs,
+   HVX_VectorPred Qt) Instruction Type:      CVI_VA_DV Execution Slots: SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPred…
Instruction Type: CVI_VA_DV
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Qh_vshuffe_QwQw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_shuffeqw)
#endif /* __HEXAGON_ARCH___ >= 62 */
#if __HVX_ARCH__ >= 62
/* ==========================================================================
Assembly Syntax: Vd32.b=vadd(Vu32.b,Vv32.b):sat
C Intrinsic Prototype: HVX_Vector Q6_Vb_vadd_VbVb_sat(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vb_vadd_VbVb_sat(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_vadd_VbVb_sat(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vb_vadd_VbVb_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbsat)
#endif /* __HEXAGON_ARCH___ >= 62 */
#if __HVX_ARCH__ >= 62
/* ==========================================================================
Assembly Syntax: Vdd32.b=vadd(Vuu32.b,Vvv32.b):sat
C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vadd_WbWb_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vadd_WbWb_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
-   Instruction Type:      CVI_VA_DV
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vadd_WbWb_sat(HVX_VectorPair Vuu,
+   HVX_VectorPair Vvv) Instruction Type:      CVI_VA_DV Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VA_DV
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Wb_vadd_WbWb_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbsat_dv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Wb_vadd_WbWb_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbsat_dv)
+#define Q6_Wb_vadd_WbWb_sat                                                    \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbsat_dv)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Wb_vadd_WbWb_sat __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 62 */
#if __HVX_ARCH__ >= 62
/* ==========================================================================
Assembly Syntax: Vd32.w=vadd(Vu32.w,Vv32.w,Qx4):carry
C Intrinsic Prototype: HVX_Vector Q6_Vw_vadd_VwVwQ_carry(HVX_Vector Vu, HVX_Vector Vv, HVX_VectorPred* Qx)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vw_vadd_VwVwQ_carry(HVX_Vector Vu, HVX_Vector Vv, HVX_VectorPred* Qx)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vadd_VwVwQ_carry(HVX_Vector Vu,
+   HVX_Vector Vv, HVX_VectorPred* Qx) Instruction Type:      CVI_VA Execution
+   Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vw_vadd_VwVwQ_carry __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddcarry)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vw_vadd_VwVwQ_carry __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddcarry)
+#define Q6_Vw_vadd_VwVwQ_carry                                                 \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddcarry)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vw_vadd_VwVwQ_carry…
#endif /* __HEXAGON_ARCH___ >= 62 */
#if __HVX_ARCH__ >= 62
/* ==========================================================================
Assembly Syntax: Vd32.h=vadd(vclb(Vu32.h),Vv32.h)
C Intrinsic Prototype: HVX_Vector Q6_Vh_vadd_vclb_VhVh(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vh_vadd_vclb_VhVh(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VS
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vadd_vclb_VhVh(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VS Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vh_vadd_vclb_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddclbh)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vh_vadd_vclb_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddclbh)
+#define Q6_Vh_vadd_vclb_VhVh                                                   \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddclbh)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vh_vadd_vclb_VhVh __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 62 */
#if __HVX_ARCH__ >= 62
/* ==========================================================================
Assembly Syntax: Vd32.w=vadd(vclb(Vu32.w),Vv32.w)
C Intrinsic Prototype: HVX_Vector Q6_Vw_vadd_vclb_VwVw(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vw_vadd_vclb_VwVw(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VS
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vadd_vclb_VwVw(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VS Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vw_vadd_vclb_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddclbw)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vw_vadd_vclb_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddclbw)
+#define Q6_Vw_vadd_vclb_VwVw                                                   \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddclbw)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vw_vadd_vclb_VwVw __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 62 */
#if __HVX_ARCH__ >= 62
/* ==========================================================================
Assembly Syntax: Vxx32.w+=vadd(Vu32.h,Vv32.h)
C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vaddacc_WwVhVh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vaddacc_WwVhVh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vaddacc_WwVhVh(HVX_VectorPair
+   Vxx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VX_DV Execution
+   Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Ww_vaddacc_WwVhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhw_acc)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Ww_vaddacc_WwVhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhw_acc)
+#define Q6_Ww_vaddacc_WwVhVh                                                   \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhw_acc)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Ww_vaddacc_WwVhVh __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 62 */
#if __HVX_ARCH__ >= 62
/* ==========================================================================
Assembly Syntax: Vxx32.h+=vadd(Vu32.ub,Vv32.ub)
C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vaddacc_WhVubVub(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vaddacc_WhVubVub(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vaddacc_WhVubVub(HVX_VectorPair
+   Vxx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VX_DV Execution
+   Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Wh_vaddacc_WhVubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubh_acc)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Wh_vaddacc_WhVubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubh_acc)
+#define Q6_Wh_vaddacc_WhVubVub                                                 \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubh_acc)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Wh_vaddacc_WhVubVub…
#endif /* __HEXAGON_ARCH___ >= 62 */
#if __HVX_ARCH__ >= 62
/* ==========================================================================
Assembly Syntax: Vd32.ub=vadd(Vu32.ub,Vv32.b):sat
C Intrinsic Prototype: HVX_Vector Q6_Vub_vadd_VubVb_sat(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vub_vadd_VubVb_sat(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vub_vadd_VubVb_sat(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vub_vadd_VubVb_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddububb_sat)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vub_vadd_VubVb_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddububb_sat)
+#define Q6_Vub_vadd_VubVb_sat                                                  \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddububb_sat)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vub_vadd_VubVb_sat __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 62 */
#if __HVX_ARCH__ >= 62
/* ==========================================================================
Assembly Syntax: Vxx32.w+=vadd(Vu32.uh,Vv32.uh)
C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vaddacc_WwVuhVuh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vaddacc_WwVuhVuh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vaddacc_WwVuhVuh(HVX_VectorPair
+   Vxx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VX_DV Execution
+   Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Ww_vaddacc_WwVuhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduhw_acc)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Ww_vaddacc_WwVuhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduhw_acc)
+#define Q6_Ww_vaddacc_WwVuhVuh                                                 \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduhw_acc)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Ww_vaddacc_WwVuhVuh…
#endif /* __HEXAGON_ARCH___ >= 62 */
#if __HVX_ARCH__ >= 62
/* ==========================================================================
Assembly Syntax: Vd32.uw=vadd(Vu32.uw,Vv32.uw):sat
C Intrinsic Prototype: HVX_Vector Q6_Vuw_vadd_VuwVuw_sat(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vuw_vadd_VuwVuw_sat(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vuw_vadd_VuwVuw_sat(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vuw_vadd_VuwVuw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduwsat)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vuw_vadd_VuwVuw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduwsat)
+#define Q6_Vuw_vadd_VuwVuw_sat                                                 \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduwsat)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vuw_vadd_VuwVuw_sat…
#endif /* __HEXAGON_ARCH___ >= 62 */
#if __HVX_ARCH__ >= 62
/* ==========================================================================
Assembly Syntax: Vdd32.uw=vadd(Vuu32.uw,Vvv32.uw):sat
C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vadd_WuwWuw_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vadd_WuwWuw_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
-   Instruction Type:      CVI_VA_DV
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vadd_WuwWuw_sat(HVX_VectorPair
+   Vuu, HVX_VectorPair Vvv) Instruction Type:      CVI_VA_DV Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VA_DV
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Wuw_vadd_WuwWuw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduwsat_dv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Wuw_vadd_WuwWuw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduwsat_dv)
+#define Q6_Wuw_vadd_WuwWuw_sat                                                 \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduwsat_dv)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Wuw_vadd_WuwWuw_sat…
#endif /* __HEXAGON_ARCH___ >= 62 */
#if __HVX_ARCH__ >= 62
/* ==========================================================================
Assembly Syntax: Vd32=vand(!Qu4,Rt32)
C Intrinsic Prototype: HVX_Vector Q6_V_vand_QnR(HVX_VectorPred Qu, Word32 Rt)
Instruction Type: CVI_VX_LATE
Execution Slots: SLOT23
========================================================================== */
#define Q6_V_vand_QnR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandnqrt)
#endif /* __HEXAGON_ARCH___ >= 62 */
#if __HVX_ARCH__ >= 62
/* ==========================================================================
Assembly Syntax: Vx32|=vand(!Qu4,Rt32)
C Intrinsic Prototype: HVX_Vector Q6_V_vandor_VQnR(HVX_Vector Vx, HVX_VectorPred Qu, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_V_vandor_VQnR(HVX_Vector Vx, HVX_VectorPred Qu, Word32 Rt)
-   Instruction Type:      CVI_VX_LATE
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_Vector Q6_V_vandor_VQnR(HVX_Vector Vx,
+   HVX_VectorPred Qu, Word32 Rt) Instruction Type:      CVI_VX_LATE Execution
+   Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VX_LATE
Execution Slots: SLOT23
========================================================================== */
#define Q6_V_vandor_VQnR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandnqrt_acc)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_V_vandor_VQnR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandnqrt_acc)
+#define Q6_V_vandor_VQnR                                                       \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandnqrt_acc)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_V_vandor_VQnR __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 62 */
#if __HVX_ARCH__ >= 62
/* ==========================================================================
Assembly Syntax: Vd32=vand(!Qv4,Vu32)
C Intrinsic Prototype: HVX_Vector Q6_V_vand_QnV(HVX_VectorPred Qv, HVX_Vector Vu)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_V_vand_QnV(HVX_VectorPred Qv, HVX_Vector Vu)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_V_vand_QnV(HVX_VectorPred Qv, HVX_Vector
+   Vu) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector Q6_V_vand_QnV…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_V_vand_QnV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvnqv)
#endif /* __HEXAGON_ARCH___ >= 62 */
#if __HVX_ARCH__ >= 62
/* ==========================================================================
Assembly Syntax: Vd32=vand(Qv4,Vu32)
C Intrinsic Prototype: HVX_Vector Q6_V_vand_QV(HVX_VectorPred Qv, HVX_Vector Vu)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_V_vand_QV(HVX_VectorPred Qv, HVX_Vector Vu)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_V_vand_QV(HVX_VectorPred Qv, HVX_Vector
+   Vu) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector Q6_V_vand_QV…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_V_vand_QV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvqv)
#endif /* __HEXAGON_ARCH___ >= 62 */
#if __HVX_ARCH__ >= 62
/* ==========================================================================
Assembly Syntax: Vd32.b=vasr(Vu32.h,Vv32.h,Rt8):sat
C Intrinsic Prototype: HVX_Vector Q6_Vb_vasr_VhVhR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vb_vasr_VhVhR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
-   Instruction Type:      CVI_VS
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_vasr_VhVhR_sat(HVX_Vector Vu,
+   HVX_Vector Vv, Word32 Rt) Instruction Type:      CVI_VS Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vb_vasr_VhVhR_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhbsat)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vb_vasr_VhVhR_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhbsat)
+#define Q6_Vb_vasr_VhVhR_sat                                                   \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhbsat)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vb_vasr_VhVhR_sat __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 62 */
#if __HVX_ARCH__ >= 62
/* ==========================================================================
Assembly Syntax: Vd32.uh=vasr(Vu32.uw,Vv32.uw,Rt8):rnd:sat
C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_VuwVuwR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_VuwVuwR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
-   Instruction Type:      CVI_VS
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_VuwVuwR_rnd_sat(HVX_Vector Vu,
+   HVX_Vector Vv, Word32 Rt) Instruction Type:      CVI_VS Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vuh_vasr_VuwVuwR_rnd_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruwuhrndsat)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vuh_vasr_VuwVuwR_rnd_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruwuhrndsat)
+#define Q6_Vuh_vasr_VuwVuwR_rnd_sat                                            \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruwuhrndsat)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vuh_vasr_VuwVuwR_rnd_sat…
#endif /* __HEXAGON_ARCH___ >= 62 */
#if __HVX_ARCH__ >= 62
/* ==========================================================================
Assembly Syntax: Vd32.uh=vasr(Vu32.w,Vv32.w,Rt8):rnd:sat
C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_VwVwR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_VwVwR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
-   Instruction Type:      CVI_VS
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_VwVwR_rnd_sat(HVX_Vector Vu,
+   HVX_Vector Vv, Word32 Rt) Instruction Type:      CVI_VS Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vuh_vasr_VwVwR_rnd_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwuhrndsat)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vuh_vasr_VwVwR_rnd_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwuhrndsat)
+#define Q6_Vuh_vasr_VwVwR_rnd_sat                                              \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwuhrndsat)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vuh_vasr_VwVwR_rnd_sat…
#endif /* __HEXAGON_ARCH___ >= 62 */
#if __HVX_ARCH__ >= 62
/* ==========================================================================
Assembly Syntax: Vd32.ub=vlsr(Vu32.ub,Rt32)
C Intrinsic Prototype: HVX_Vector Q6_Vub_vlsr_VubR(HVX_Vector Vu, Word32 Rt)
Instruction Type: CVI_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vub_vlsr_VubR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrb)
#endif /* __HEXAGON_ARCH___ >= 62 */
#if __HVX_ARCH__ >= 62
/* ==========================================================================
Assembly Syntax: Vd32.b=vlut32(Vu32.b,Vv32.b,Rt8):nomatch
C Intrinsic Prototype: HVX_Vector Q6_Vb_vlut32_VbVbR_nomatch(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vb_vlut32_VbVbR_nomatch(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
-   Instruction Type:      CVI_VP
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_vlut32_VbVbR_nomatch(HVX_Vector Vu,
+   HVX_Vector Vv, Word32 Rt) Instruction Type:      CVI_VP Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VP
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vb_vlut32_VbVbR_nomatch __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvb_nm)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vb_vlut32_VbVbR_nomatch __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvb_nm)
+#define Q6_Vb_vlut32_VbVbR_nomatch                                             \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvb_nm)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vb_vlut32_VbVbR_nomatch…
#endif /* __HEXAGON_ARCH___ >= 62 */
#if __HVX_ARCH__ >= 62
/* ==========================================================================
Assembly Syntax: Vx32.b|=vlut32(Vu32.b,Vv32.b,#u3)
C Intrinsic Prototype: HVX_Vector Q6_Vb_vlut32or_VbVbVbI(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vb_vlut32or_VbVbVbI(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3)
-   Instruction Type:      CVI_VP_VS
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_vlut32or_VbVbVbI(HVX_Vector Vx,
+   HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3) Instruction Type:      CVI_VP_VS
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VP_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vb_vlut32or_VbVbVbI __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvb_oracci)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vb_vlut32or_VbVbVbI __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvb_oracci)
+#define Q6_Vb_vlut32or_VbVbVbI                                                 \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvb_oracci)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vb_vlut32or_VbVbVbI…
#endif /* __HEXAGON_ARCH___ >= 62 */
#if __HVX_ARCH__ >= 62
/* ==========================================================================
Assembly Syntax: Vd32.b=vlut32(Vu32.b,Vv32.b,#u3)
C Intrinsic Prototype: HVX_Vector Q6_Vb_vlut32_VbVbI(HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vb_vlut32_VbVbI(HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3)
-   Instruction Type:      CVI_VP
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_vlut32_VbVbI(HVX_Vector Vu,
+   HVX_Vector Vv, Word32 Iu3) Instruction Type:      CVI_VP Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VP
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vb_vlut32_VbVbI __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvbi)
#endif /* __HEXAGON_ARCH___ >= 62 */
#if __HVX_ARCH__ >= 62
/* ==========================================================================
Assembly Syntax: Vdd32.h=vlut16(Vu32.b,Vv32.h,Rt8):nomatch
C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vlut16_VbVhR_nomatch(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vlut16_VbVhR_nomatch(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
-   Instruction Type:      CVI_VP_VS
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vlut16_VbVhR_nomatch(HVX_Vector
+   Vu, HVX_Vector Vv, Word32 Rt) Instruction Type:      CVI_VP_VS Execution
+   Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VP_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Wh_vlut16_VbVhR_nomatch __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwh_nm)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Wh_vlut16_VbVhR_nomatch __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwh_nm)
+#define Q6_Wh_vlut16_VbVhR_nomatch                                             \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwh_nm)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Wh_vlut16_VbVhR_nomatch…
#endif /* __HEXAGON_ARCH___ >= 62 */
#if __HVX_ARCH__ >= 62
/* ==========================================================================
Assembly Syntax: Vxx32.h|=vlut16(Vu32.b,Vv32.h,#u3)
C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vlut16or_WhVbVhI(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vlut16or_WhVbVhI(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3)
-   Instruction Type:      CVI_VP_VS
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vlut16or_WhVbVhI(HVX_VectorPair
+   Vxx, HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3) Instruction Type: CVI_VP_VS
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VP_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Wh_vlut16or_WhVbVhI __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwh_oracci)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Wh_vlut16or_WhVbVhI __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwh_oracci)
+#define Q6_Wh_vlut16or_WhVbVhI                                                 \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwh_oracci)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Wh_vlut16or_WhVbVhI…
#endif /* __HEXAGON_ARCH___ >= 62 */
#if __HVX_ARCH__ >= 62
/* ==========================================================================
Assembly Syntax: Vdd32.h=vlut16(Vu32.b,Vv32.h,#u3)
C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vlut16_VbVhI(HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vlut16_VbVhI(HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3)
-   Instruction Type:      CVI_VP_VS
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vlut16_VbVhI(HVX_Vector Vu,
+   HVX_Vector Vv, Word32 Iu3) Instruction Type:      CVI_VP_VS Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VP_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Wh_vlut16_VbVhI __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwhi)
#endif /* __HEXAGON_ARCH___ >= 62 */
#if __HVX_ARCH__ >= 62
/* ==========================================================================
Assembly Syntax: Vd32.b=vmax(Vu32.b,Vv32.b)
C Intrinsic Prototype: HVX_Vector Q6_Vb_vmax_VbVb(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vb_vmax_VbVb(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_vmax_VbVb(HVX_Vector Vu, HVX_Vector
+   Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vb_vmax_VbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxb)
#endif /* __HEXAGON_ARCH___ >= 62 */
#if __HVX_ARCH__ >= 62
/* ==========================================================================
Assembly Syntax: Vd32.b=vmin(Vu32.b,Vv32.b)
C Intrinsic Prototype: HVX_Vector Q6_Vb_vmin_VbVb(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vb_vmin_VbVb(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_vmin_VbVb(HVX_Vector Vu, HVX_Vector
+   Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vb_vmin_VbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminb)
#endif /* __HEXAGON_ARCH___ >= 62 */
#if __HVX_ARCH__ >= 62
/* ==========================================================================
Assembly Syntax: Vdd32.w=vmpa(Vuu32.uh,Rt32.b)
C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpa_WuhRb(HVX_VectorPair Vuu, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpa_WuhRb(HVX_VectorPair Vuu, Word32 Rt)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpa_WuhRb(HVX_VectorPair Vuu,
+   Word32 Rt) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Ww_vmpa_WuhRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpauhb)
#endif /* __HEXAGON_ARCH___ >= 62 */
#if __HVX_ARCH__ >= 62
/* ==========================================================================
Assembly Syntax: Vxx32.w+=vmpa(Vuu32.uh,Rt32.b)
C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpaacc_WwWuhRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpaacc_WwWuhRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt)
-   Instruction Type:      CVI_VX_DV
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpaacc_WwWuhRb(HVX_VectorPair
+   Vxx, HVX_VectorPair Vuu, Word32 Rt) Instruction Type:      CVI_VX_DV
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Ww_vmpaacc_WwWuhRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpauhb_acc)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Ww_vmpaacc_WwWuhRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpauhb_acc)
+#define Q6_Ww_vmpaacc_WwWuhRb                                                  \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpauhb_acc)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Ww_vmpaacc_WwWuhRb __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 62 */
#if __HVX_ARCH__ >= 62
/* ==========================================================================
Assembly Syntax: Vdd32=vmpye(Vu32.w,Vv32.uh)
C Intrinsic Prototype: HVX_VectorPair Q6_W_vmpye_VwVuh(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_W_vmpye_VwVuh(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_VectorPair Q6_W_vmpye_VwVuh(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_W_vmpye_VwVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyewuh_64)
#endif /* __HEXAGON_ARCH___ >= 62 */
#if __HVX_ARCH__ >= 62
/* ==========================================================================
Assembly Syntax: Vd32.w=vmpyi(Vu32.w,Rt32.ub)
C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyi_VwRub(HVX_Vector Vu, Word32 Rt)
Instruction Type: CVI_VX
Execution Slots: SLOT23
========================================================================== */
#define Q6_Vw_vmpyi_VwRub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwub)
#endif /* __HEXAGON_ARCH___ >= 62 */
#if __HVX_ARCH__ >= 62
/* ==========================================================================
Assembly Syntax: Vx32.w+=vmpyi(Vu32.w,Rt32.ub)
C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyiacc_VwVwRub(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyiacc_VwVwRub(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)
-   Instruction Type:      CVI_VX
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyiacc_VwVwRub(HVX_Vector Vx,
+   HVX_Vector Vu, Word32 Rt) Instruction Type:      CVI_VX Execution Slots:
+   SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VX
Execution Slots: SLOT23
========================================================================== */
#define Q6_Vw_vmpyiacc_VwVwRub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwub_acc)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vw_vmpyiacc_VwVwRub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwub_acc)
+#define Q6_Vw_vmpyiacc_VwVwRub                                                 \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwub_acc)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vw_vmpyiacc_VwVwRub…
#endif /* __HEXAGON_ARCH___ >= 62 */
#if __HVX_ARCH__ >= 62
/* ==========================================================================
Assembly Syntax: Vxx32+=vmpyo(Vu32.w,Vv32.h)
C Intrinsic Prototype: HVX_VectorPair Q6_W_vmpyoacc_WVwVh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_W_vmpyoacc_WVwVh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_VectorPair Q6_W_vmpyoacc_WVwVh(HVX_VectorPair Vxx,
+   HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VX_DV Execution
+   Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_W_vmpyoacc_WVwVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_64_acc)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_W_vmpyoacc_WVwVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_64_acc)
+#define Q6_W_vmpyoacc_WVwVh                                                    \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_64_acc)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_W_vmpyoacc_WVwVh __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 62 */
#if __HVX_ARCH__ >= 62
/* ==========================================================================
Assembly Syntax: Vd32.ub=vround(Vu32.uh,Vv32.uh):sat
C Intrinsic Prototype: HVX_Vector Q6_Vub_vround_VuhVuh_sat(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vub_vround_VuhVuh_sat(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VS
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vub_vround_VuhVuh_sat(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VS Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vub_vround_VuhVuh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrounduhub)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vub_vround_VuhVuh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrounduhub)
+#define Q6_Vub_vround_VuhVuh_sat                                               \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrounduhub)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vub_vround_VuhVuh_sat…
#endif /* __HEXAGON_ARCH___ >= 62 */
#if __HVX_ARCH__ >= 62
/* ==========================================================================
Assembly Syntax: Vd32.uh=vround(Vu32.uw,Vv32.uw):sat
C Intrinsic Prototype: HVX_Vector Q6_Vuh_vround_VuwVuw_sat(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vuh_vround_VuwVuw_sat(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VS
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vuh_vround_VuwVuw_sat(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VS Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vuh_vround_VuwVuw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrounduwuh)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vuh_vround_VuwVuw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrounduwuh)
+#define Q6_Vuh_vround_VuwVuw_sat                                               \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrounduwuh)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vuh_vround_VuwVuw_sat…
#endif /* __HEXAGON_ARCH___ >= 62 */
#if __HVX_ARCH__ >= 62
/* ==========================================================================
Assembly Syntax: Vd32.uh=vsat(Vu32.uw,Vv32.uw)
C Intrinsic Prototype: HVX_Vector Q6_Vuh_vsat_VuwVuw(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vuh_vsat_VuwVuw(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vuh_vsat_VuwVuw(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vuh_vsat_VuwVuw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsatuwuh)
#endif /* __HEXAGON_ARCH___ >= 62 */
#if __HVX_ARCH__ >= 62
/* ==========================================================================
Assembly Syntax: Vd32.b=vsub(Vu32.b,Vv32.b):sat
C Intrinsic Prototype: HVX_Vector Q6_Vb_vsub_VbVb_sat(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vb_vsub_VbVb_sat(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_vsub_VbVb_sat(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vb_vsub_VbVb_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubbsat)
#endif /* __HEXAGON_ARCH___ >= 62 */
#if __HVX_ARCH__ >= 62
/* ==========================================================================
Assembly Syntax: Vdd32.b=vsub(Vuu32.b,Vvv32.b):sat
C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vsub_WbWb_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vsub_WbWb_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
-   Instruction Type:      CVI_VA_DV
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vsub_WbWb_sat(HVX_VectorPair Vuu,
+   HVX_VectorPair Vvv) Instruction Type:      CVI_VA_DV Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VA_DV
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Wb_vsub_WbWb_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubbsat_dv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Wb_vsub_WbWb_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubbsat_dv)
+#define Q6_Wb_vsub_WbWb_sat                                                    \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubbsat_dv)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Wb_vsub_WbWb_sat __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 62 */
#if __HVX_ARCH__ >= 62
/* ==========================================================================
Assembly Syntax: Vd32.w=vsub(Vu32.w,Vv32.w,Qx4):carry
C Intrinsic Prototype: HVX_Vector Q6_Vw_vsub_VwVwQ_carry(HVX_Vector Vu, HVX_Vector Vv, HVX_VectorPred* Qx)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vw_vsub_VwVwQ_carry(HVX_Vector Vu, HVX_Vector Vv, HVX_VectorPred* Qx)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vsub_VwVwQ_carry(HVX_Vector Vu,
+   HVX_Vector Vv, HVX_VectorPred* Qx) Instruction Type:      CVI_VA Execution
+   Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vw_vsub_VwVwQ_carry __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubcarry)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vw_vsub_VwVwQ_carry __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubcarry)
+#define Q6_Vw_vsub_VwVwQ_carry                                                 \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubcarry)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vw_vsub_VwVwQ_carry…
#endif /* __HEXAGON_ARCH___ >= 62 */
#if __HVX_ARCH__ >= 62
/* ==========================================================================
Assembly Syntax: Vd32.ub=vsub(Vu32.ub,Vv32.b):sat
C Intrinsic Prototype: HVX_Vector Q6_Vub_vsub_VubVb_sat(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vub_vsub_VubVb_sat(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vub_vsub_VubVb_sat(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vub_vsub_VubVb_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubububb_sat)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vub_vsub_VubVb_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubububb_sat)
+#define Q6_Vub_vsub_VubVb_sat                                                  \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubububb_sat)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vub_vsub_VubVb_sat __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 62 */
#if __HVX_ARCH__ >= 62
/* ==========================================================================
Assembly Syntax: Vd32.uw=vsub(Vu32.uw,Vv32.uw):sat
C Intrinsic Prototype: HVX_Vector Q6_Vuw_vsub_VuwVuw_sat(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vuw_vsub_VuwVuw_sat(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vuw_vsub_VuwVuw_sat(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vuw_vsub_VuwVuw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuwsat)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vuw_vsub_VuwVuw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuwsat)
+#define Q6_Vuw_vsub_VuwVuw_sat                                                 \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuwsat)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vuw_vsub_VuwVuw_sat…
#endif /* __HEXAGON_ARCH___ >= 62 */
#if __HVX_ARCH__ >= 62
/* ==========================================================================
Assembly Syntax: Vdd32.uw=vsub(Vuu32.uw,Vvv32.uw):sat
C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vsub_WuwWuw_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vsub_WuwWuw_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
-   Instruction Type:      CVI_VA_DV
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vsub_WuwWuw_sat(HVX_VectorPair
+   Vuu, HVX_VectorPair Vvv) Instruction Type:      CVI_VA_DV Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VA_DV
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Wuw_vsub_WuwWuw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuwsat_dv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Wuw_vsub_WuwWuw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuwsat_dv)
+#define Q6_Wuw_vsub_WuwWuw_sat                                                 \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuwsat_dv)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Wuw_vsub_WuwWuw_sat…
#endif /* __HEXAGON_ARCH___ >= 62 */
#if __HVX_ARCH__ >= 65
/* ==========================================================================
Assembly Syntax: Vd32.b=vabs(Vu32.b)
C Intrinsic Prototype: HVX_Vector Q6_Vb_vabs_Vb(HVX_Vector Vu)
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vb_vabs_Vb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsb)
#endif /* __HEXAGON_ARCH___ >= 65 */
#if __HVX_ARCH__ >= 65
/* ==========================================================================
Assembly Syntax: Vd32.b=vabs(Vu32.b):sat
C Intrinsic Prototype: HVX_Vector Q6_Vb_vabs_Vb_sat(HVX_Vector Vu)
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vb_vabs_Vb_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsb_sat)
#endif /* __HEXAGON_ARCH___ >= 65 */
#if __HVX_ARCH__ >= 65
/* ==========================================================================
Assembly Syntax: Vx32.h+=vasl(Vu32.h,Rt32)
C Intrinsic Prototype: HVX_Vector Q6_Vh_vaslacc_VhVhR(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vh_vaslacc_VhVhR(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)
-   Instruction Type:      CVI_VS
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vaslacc_VhVhR(HVX_Vector Vx,
+   HVX_Vector Vu, Word32 Rt) Instruction Type:      CVI_VS Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vh_vaslacc_VhVhR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslh_acc)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vh_vaslacc_VhVhR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslh_acc)
+#define Q6_Vh_vaslacc_VhVhR                                                    \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslh_acc)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vh_vaslacc_VhVhR __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 65 */
#if __HVX_ARCH__ >= 65
/* ==========================================================================
Assembly Syntax: Vx32.h+=vasr(Vu32.h,Rt32)
C Intrinsic Prototype: HVX_Vector Q6_Vh_vasracc_VhVhR(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vh_vasracc_VhVhR(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)
-   Instruction Type:      CVI_VS
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vasracc_VhVhR(HVX_Vector Vx,
+   HVX_Vector Vu, Word32 Rt) Instruction Type:      CVI_VS Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vh_vasracc_VhVhR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrh_acc)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vh_vasracc_VhVhR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrh_acc)
+#define Q6_Vh_vasracc_VhVhR                                                    \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrh_acc)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vh_vasracc_VhVhR __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 65 */
#if __HVX_ARCH__ >= 65
/* ==========================================================================
Assembly Syntax: Vd32.ub=vasr(Vu32.uh,Vv32.uh,Rt8):rnd:sat
C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_VuhVuhR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_VuhVuhR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
-   Instruction Type:      CVI_VS
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_VuhVuhR_rnd_sat(HVX_Vector Vu,
+   HVX_Vector Vv, Word32 Rt) Instruction Type:      CVI_VS Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vub_vasr_VuhVuhR_rnd_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruhubrndsat)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vub_vasr_VuhVuhR_rnd_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruhubrndsat)
+#define Q6_Vub_vasr_VuhVuhR_rnd_sat                                            \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruhubrndsat)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vub_vasr_VuhVuhR_rnd_sat…
#endif /* __HEXAGON_ARCH___ >= 65 */
#if __HVX_ARCH__ >= 65
/* ==========================================================================
Assembly Syntax: Vd32.ub=vasr(Vu32.uh,Vv32.uh,Rt8):sat
C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_VuhVuhR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_VuhVuhR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
-   Instruction Type:      CVI_VS
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_VuhVuhR_sat(HVX_Vector Vu,
+   HVX_Vector Vv, Word32 Rt) Instruction Type:      CVI_VS Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vub_vasr_VuhVuhR_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruhubsat)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vub_vasr_VuhVuhR_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruhubsat)
+#define Q6_Vub_vasr_VuhVuhR_sat                                                \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruhubsat)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vub_vasr_VuhVuhR_sat…
#endif /* __HEXAGON_ARCH___ >= 65 */
#if __HVX_ARCH__ >= 65
/* ==========================================================================
Assembly Syntax: Vd32.uh=vasr(Vu32.uw,Vv32.uw,Rt8):sat
C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_VuwVuwR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_VuwVuwR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt)
-   Instruction Type:      CVI_VS
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_VuwVuwR_sat(HVX_Vector Vu,
+   HVX_Vector Vv, Word32 Rt) Instruction Type:      CVI_VS Execution Slots:
+   SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vuh_vasr_VuwVuwR_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruwuhsat)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vuh_vasr_VuwVuwR_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruwuhsat)
+#define Q6_Vuh_vasr_VuwVuwR_sat                                                \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruwuhsat)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vuh_vasr_VuwVuwR_sat…
#endif /* __HEXAGON_ARCH___ >= 65 */
#if __HVX_ARCH__ >= 65
/* ==========================================================================
Assembly Syntax: Vd32.b=vavg(Vu32.b,Vv32.b)
C Intrinsic Prototype: HVX_Vector Q6_Vb_vavg_VbVb(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vb_vavg_VbVb(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_vavg_VbVb(HVX_Vector Vu, HVX_Vector
+   Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vb_vavg_VbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgb)
#endif /* __HEXAGON_ARCH___ >= 65 */
#if __HVX_ARCH__ >= 65
/* ==========================================================================
Assembly Syntax: Vd32.b=vavg(Vu32.b,Vv32.b):rnd
C Intrinsic Prototype: HVX_Vector Q6_Vb_vavg_VbVb_rnd(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vb_vavg_VbVb_rnd(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_vavg_VbVb_rnd(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vb_vavg_VbVb_rnd __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgbrnd)
#endif /* __HEXAGON_ARCH___ >= 65 */
#if __HVX_ARCH__ >= 65
/* ==========================================================================
Assembly Syntax: Vd32.uw=vavg(Vu32.uw,Vv32.uw)
C Intrinsic Prototype: HVX_Vector Q6_Vuw_vavg_VuwVuw(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vuw_vavg_VuwVuw(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vuw_vavg_VuwVuw(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vuw_vavg_VuwVuw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavguw)
#endif /* __HEXAGON_ARCH___ >= 65 */
#if __HVX_ARCH__ >= 65
/* ==========================================================================
Assembly Syntax: Vd32.uw=vavg(Vu32.uw,Vv32.uw):rnd
C Intrinsic Prototype: HVX_Vector Q6_Vuw_vavg_VuwVuw_rnd(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vuw_vavg_VuwVuw_rnd(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vuw_vavg_VuwVuw_rnd(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vuw_vavg_VuwVuw_rnd __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavguwrnd)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vuw_vavg_VuwVuw_rnd __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavguwrnd)
+#define Q6_Vuw_vavg_VuwVuw_rnd                                                 \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavguwrnd)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vuw_vavg_VuwVuw_rnd…
#endif /* __HEXAGON_ARCH___ >= 65 */
#if __HVX_ARCH__ >= 65
/* ==========================================================================
Assembly Syntax: Vdd32=#0
C Intrinsic Prototype: HVX_VectorPair Q6_W_vzero()
Instruction Type: MAPPING
Execution Slots: SLOT0123
========================================================================== */
#define Q6_W_vzero __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdd0)
#endif /* __HEXAGON_ARCH___ >= 65 */
#if __HVX_ARCH__ >= 65
/* ==========================================================================
Assembly Syntax: vtmp.h=vgather(Rt32,Mu2,Vv32.h).h
C Intrinsic Prototype: void Q6_vgather_ARMVh(HVX_Vector* Rs, Word32 Rt, Word32 Mu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: void Q6_vgather_ARMVh(HVX_Vector* Rs, Word32 Rt, Word32 Mu, HVX_Vector Vv)
-   Instruction Type:      CVI_GATHER
-   Execution Slots:       SLOT01
+   C Intrinsic Prototype: void Q6_vgather_ARMVh(HVX_Vector* Rs, Word32 Rt,
+   Word32 Mu, HVX_Vector Vv) Instruction Type:      CVI_GATHER Execution Slots:
+   SLOT01
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: void Q6_vgather_ARMVh…
Instruction Type: CVI_GATHER
Execution Slots: SLOT01
========================================================================== */
#define Q6_vgather_ARMVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermh)
#endif /* __HEXAGON_ARCH___ >= 65 */
#if __HVX_ARCH__ >= 65
/* ==========================================================================
Assembly Syntax: if (Qs4) vtmp.h=vgather(Rt32,Mu2,Vv32.h).h
C Intrinsic Prototype: void Q6_vgather_AQRMVh(HVX_Vector* Rs, HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: void Q6_vgather_AQRMVh(HVX_Vector* Rs, HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_Vector Vv)
-   Instruction Type:      CVI_GATHER
+   C Intrinsic Prototype: void Q6_vgather_AQRMVh(HVX_Vector* Rs, HVX_VectorPred
+   Qs, Word32 Rt, Word32 Mu, HVX_Vector Vv) Instruction Type:      CVI_GATHER
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: void Q6_vgather_AQRMVh…
Instruction Type: CVI_GATHER
Execution Slots: SLOT01
========================================================================== */
#define Q6_vgather_AQRMVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermhq)
#endif /* __HEXAGON_ARCH___ >= 65 */
#if __HVX_ARCH__ >= 65
/* ==========================================================================
Assembly Syntax: vtmp.h=vgather(Rt32,Mu2,Vvv32.w).h
C Intrinsic Prototype: void Q6_vgather_ARMWw(HVX_Vector* Rs, Word32 Rt, Word32 Mu, HVX_VectorPair Vvv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: void Q6_vgather_ARMWw(HVX_Vector* Rs, Word32 Rt, Word32 Mu, HVX_VectorPair Vvv)
-   Instruction Type:      CVI_GATHER_DV
-   Execution Slots:       SLOT01
+   C Intrinsic Prototype: void Q6_vgather_ARMWw(HVX_Vector* Rs, Word32 Rt,
+   Word32 Mu, HVX_VectorPair Vvv) Instruction Type:      CVI_GATHER_DV Execution
+   Slots:       SLOT01
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: void Q6_vgather_ARMWw…
Instruction Type: CVI_GATHER_DV
Execution Slots: SLOT01
========================================================================== */
#define Q6_vgather_ARMWw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermhw)
#endif /* __HEXAGON_ARCH___ >= 65 */
#if __HVX_ARCH__ >= 65
/* ==========================================================================
Assembly Syntax: if (Qs4) vtmp.h=vgather(Rt32,Mu2,Vvv32.w).h
C Intrinsic Prototype: void Q6_vgather_AQRMWw(HVX_Vector* Rs, HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_VectorPair Vvv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: void Q6_vgather_AQRMWw(HVX_Vector* Rs, HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_VectorPair Vvv)
-   Instruction Type:      CVI_GATHER_DV
+   C Intrinsic Prototype: void Q6_vgather_AQRMWw(HVX_Vector* Rs, HVX_VectorPred
+   Qs, Word32 Rt, Word32 Mu, HVX_VectorPair Vvv) Instruction Type: CVI_GATHER_DV
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: void Q6_vgather_AQRMWw…
Instruction Type: CVI_GATHER_DV
Execution Slots: SLOT01
========================================================================== */
#define Q6_vgather_AQRMWw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermhwq)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_vgather_AQRMWw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermhwq)
+#define Q6_vgather_AQRMWw                                                      \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermhwq)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_vgather_AQRMWw __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 65 */
#if __HVX_ARCH__ >= 65
/* ==========================================================================
Assembly Syntax: vtmp.w=vgather(Rt32,Mu2,Vv32.w).w
C Intrinsic Prototype: void Q6_vgather_ARMVw(HVX_Vector* Rs, Word32 Rt, Word32 Mu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: void Q6_vgather_ARMVw(HVX_Vector* Rs, Word32 Rt, Word32 Mu, HVX_Vector Vv)
-   Instruction Type:      CVI_GATHER
-   Execution Slots:       SLOT01
+   C Intrinsic Prototype: void Q6_vgather_ARMVw(HVX_Vector* Rs, Word32 Rt,
+   Word32 Mu, HVX_Vector Vv) Instruction Type:      CVI_GATHER Execution Slots:
+   SLOT01
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: void Q6_vgather_ARMVw…
Instruction Type: CVI_GATHER
Execution Slots: SLOT01
========================================================================== */
#define Q6_vgather_ARMVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermw)
#endif /* __HEXAGON_ARCH___ >= 65 */
#if __HVX_ARCH__ >= 65
/* ==========================================================================
Assembly Syntax: if (Qs4) vtmp.w=vgather(Rt32,Mu2,Vv32.w).w
C Intrinsic Prototype: void Q6_vgather_AQRMVw(HVX_Vector* Rs, HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: void Q6_vgather_AQRMVw(HVX_Vector* Rs, HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_Vector Vv)
-   Instruction Type:      CVI_GATHER
+   C Intrinsic Prototype: void Q6_vgather_AQRMVw(HVX_Vector* Rs, HVX_VectorPred
+   Qs, Word32 Rt, Word32 Mu, HVX_Vector Vv) Instruction Type:      CVI_GATHER
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: void Q6_vgather_AQRMVw…
Instruction Type: CVI_GATHER
Execution Slots: SLOT01
========================================================================== */
#define Q6_vgather_AQRMVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermwq)
#endif /* __HEXAGON_ARCH___ >= 65 */
#if __HVX_ARCH__ >= 65
/* ==========================================================================
Assembly Syntax: Vd32.h=vlut4(Vu32.uh,Rtt32.h)
C Intrinsic Prototype: HVX_Vector Q6_Vh_vlut4_VuhPh(HVX_Vector Vu, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vh_vlut4_VuhPh(HVX_Vector Vu, Word64 Rtt)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT2
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vlut4_VuhPh(HVX_Vector Vu, Word64
+   Rtt) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT2
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT2
========================================================================== */
#define Q6_Vh_vlut4_VuhPh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlut4)
#endif /* __HEXAGON_ARCH___ >= 65 */
#if __HVX_ARCH__ >= 65
/* ==========================================================================
Assembly Syntax: Vdd32.h=vmpa(Vuu32.ub,Rt32.ub)
C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpa_WubRub(HVX_VectorPair Vuu, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpa_WubRub(HVX_VectorPair Vuu, Word32 Rt)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpa_WubRub(HVX_VectorPair Vuu,
+   Word32 Rt) Instruction Type:      CVI_VX_DV Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Wh_vmpa_WubRub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabuu)
#endif /* __HEXAGON_ARCH___ >= 65 */
#if __HVX_ARCH__ >= 65
/* ==========================================================================
Assembly Syntax: Vxx32.h+=vmpa(Vuu32.ub,Rt32.ub)
C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpaacc_WhWubRub(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpaacc_WhWubRub(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt)
-   Instruction Type:      CVI_VX_DV
+   C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpaacc_WhWubRub(HVX_VectorPair
+   Vxx, HVX_VectorPair Vuu, Word32 Rt) Instruction Type:      CVI_VX_DV
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Wh_vmpaacc_WhWubRub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabuu_acc)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Wh_vmpaacc_WhWubRub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabuu_acc)
+#define Q6_Wh_vmpaacc_WhWubRub                                                 \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabuu_acc)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Wh_vmpaacc_WhWubRub…
#endif /* __HEXAGON_ARCH___ >= 65 */
#if __HVX_ARCH__ >= 65
/* ==========================================================================
Assembly Syntax: Vx32.h=vmpa(Vx32.h,Vu32.h,Rtt32.h):sat
C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpa_VhVhVhPh_sat(HVX_Vector Vx, HVX_Vector Vu, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpa_VhVhVhPh_sat(HVX_Vector Vx, HVX_Vector Vu, Word64 Rtt)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT2
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpa_VhVhVhPh_sat(HVX_Vector Vx,
+   HVX_Vector Vu, Word64 Rtt) Instruction Type:      CVI_VX_DV Execution Slots:
+   SLOT2
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT2
========================================================================== */
#define Q6_Vh_vmpa_VhVhVhPh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpahhsat)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vh_vmpa_VhVhVhPh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpahhsat)
+#define Q6_Vh_vmpa_VhVhVhPh_sat                                                \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpahhsat)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vh_vmpa_VhVhVhPh_sat…
#endif /* __HEXAGON_ARCH___ >= 65 */
#if __HVX_ARCH__ >= 65
/* ==========================================================================
Assembly Syntax: Vx32.h=vmpa(Vx32.h,Vu32.uh,Rtt32.uh):sat
C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpa_VhVhVuhPuh_sat(HVX_Vector Vx, HVX_Vector Vu, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpa_VhVhVuhPuh_sat(HVX_Vector Vx, HVX_Vector Vu, Word64 Rtt)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT2
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpa_VhVhVuhPuh_sat(HVX_Vector Vx,
+   HVX_Vector Vu, Word64 Rtt) Instruction Type:      CVI_VX_DV Execution Slots:
+   SLOT2
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT2
========================================================================== */
#define Q6_Vh_vmpa_VhVhVuhPuh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpauhuhsat)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vh_vmpa_VhVhVuhPuh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpauhuhsat)
+#define Q6_Vh_vmpa_VhVhVuhPuh_sat                                              \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpauhuhsat)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vh_vmpa_VhVhVuhPuh_sat…
#endif /* __HEXAGON_ARCH___ >= 65 */
#if __HVX_ARCH__ >= 65
/* ==========================================================================
Assembly Syntax: Vx32.h=vmps(Vx32.h,Vu32.uh,Rtt32.uh):sat
C Intrinsic Prototype: HVX_Vector Q6_Vh_vmps_VhVhVuhPuh_sat(HVX_Vector Vx, HVX_Vector Vu, Word64 Rtt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vh_vmps_VhVhVuhPuh_sat(HVX_Vector Vx, HVX_Vector Vu, Word64 Rtt)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT2
+   C Intrinsic Prototype: HVX_Vector Q6_Vh_vmps_VhVhVuhPuh_sat(HVX_Vector Vx,
+   HVX_Vector Vu, Word64 Rtt) Instruction Type:      CVI_VX_DV Execution Slots:
+   SLOT2
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT2
========================================================================== */
#define Q6_Vh_vmps_VhVhVuhPuh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpsuhuhsat)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vh_vmps_VhVhVuhPuh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpsuhuhsat)
+#define Q6_Vh_vmps_VhVhVuhPuh_sat                                              \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpsuhuhsat)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vh_vmps_VhVhVuhPuh_sat…
#endif /* __HEXAGON_ARCH___ >= 65 */
#if __HVX_ARCH__ >= 65
/* ==========================================================================
Assembly Syntax: Vxx32.w+=vmpy(Vu32.h,Rt32.h)
C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpyacc_WwVhRh(HVX_VectorPair Vxx, HVX_Vector Vu, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpyacc_WwVhRh(HVX_VectorPair Vxx, HVX_Vector Vu, Word32 Rt)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpyacc_WwVhRh(HVX_VectorPair
+   Vxx, HVX_Vector Vu, Word32 Rt) Instruction Type:      CVI_VX_DV Execution
+   Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Ww_vmpyacc_WwVhRh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyh_acc)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Ww_vmpyacc_WwVhRh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyh_acc)
+#define Q6_Ww_vmpyacc_WwVhRh                                                   \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyh_acc)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Ww_vmpyacc_WwVhRh __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 65 */
#if __HVX_ARCH__ >= 65
/* ==========================================================================
Assembly Syntax: Vd32.uw=vmpye(Vu32.uh,Rt32.uh)
C Intrinsic Prototype: HVX_Vector Q6_Vuw_vmpye_VuhRuh(HVX_Vector Vu, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vuw_vmpye_VuhRuh(HVX_Vector Vu, Word32 Rt)
-   Instruction Type:      CVI_VX
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_Vector Q6_Vuw_vmpye_VuhRuh(HVX_Vector Vu, Word32
+   Rt) Instruction Type:      CVI_VX Execution Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VX
Execution Slots: SLOT23
========================================================================== */
#define Q6_Vuw_vmpye_VuhRuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhe)
#endif /* __HEXAGON_ARCH___ >= 65 */
#if __HVX_ARCH__ >= 65
/* ==========================================================================
Assembly Syntax: Vx32.uw+=vmpye(Vu32.uh,Rt32.uh)
C Intrinsic Prototype: HVX_Vector Q6_Vuw_vmpyeacc_VuwVuhRuh(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vuw_vmpyeacc_VuwVuhRuh(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt)
-   Instruction Type:      CVI_VX
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_Vector Q6_Vuw_vmpyeacc_VuwVuhRuh(HVX_Vector Vx,
+   HVX_Vector Vu, Word32 Rt) Instruction Type:      CVI_VX Execution Slots:
+   SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VX
Execution Slots: SLOT23
========================================================================== */
#define Q6_Vuw_vmpyeacc_VuwVuhRuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhe_acc)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vuw_vmpyeacc_VuwVuhRuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhe_acc)
+#define Q6_Vuw_vmpyeacc_VuwVuhRuh                                              \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhe_acc)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vuw_vmpyeacc_VuwVuhRuh…
#endif /* __HEXAGON_ARCH___ >= 65 */
#if __HVX_ARCH__ >= 65
/* ==========================================================================
Assembly Syntax: Vd32.b=vnavg(Vu32.b,Vv32.b)
C Intrinsic Prototype: HVX_Vector Q6_Vb_vnavg_VbVb(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vb_vnavg_VbVb(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vb_vnavg_VbVb(HVX_Vector Vu, HVX_Vector
+   Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vb_vnavg_VbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnavgb)
#endif /* __HEXAGON_ARCH___ >= 65 */
#if __HVX_ARCH__ >= 65
/* ==========================================================================
Assembly Syntax: Vd32.b=prefixsum(Qv4)
C Intrinsic Prototype: HVX_Vector Q6_Vb_prefixsum_Q(HVX_VectorPred Qv)
Instruction Type: CVI_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vb_prefixsum_Q __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vprefixqb)
#endif /* __HEXAGON_ARCH___ >= 65 */
#if __HVX_ARCH__ >= 65
/* ==========================================================================
Assembly Syntax: Vd32.h=prefixsum(Qv4)
C Intrinsic Prototype: HVX_Vector Q6_Vh_prefixsum_Q(HVX_VectorPred Qv)
Instruction Type: CVI_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vh_prefixsum_Q __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vprefixqh)
#endif /* __HEXAGON_ARCH___ >= 65 */
#if __HVX_ARCH__ >= 65
/* ==========================================================================
Assembly Syntax: Vd32.w=prefixsum(Qv4)
C Intrinsic Prototype: HVX_Vector Q6_Vw_prefixsum_Q(HVX_VectorPred Qv)
Instruction Type: CVI_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vw_prefixsum_Q __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vprefixqw)
#endif /* __HEXAGON_ARCH___ >= 65 */
#if __HVX_ARCH__ >= 65
/* ==========================================================================
Assembly Syntax: vscatter(Rt32,Mu2,Vv32.h).h=Vw32
C Intrinsic Prototype: void Q6_vscatter_RMVhV(Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: void Q6_vscatter_RMVhV(Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw)
-   Instruction Type:      CVI_SCATTER
-   Execution Slots:       SLOT0
+   C Intrinsic Prototype: void Q6_vscatter_RMVhV(Word32 Rt, Word32 Mu,
+   HVX_Vector Vv, HVX_Vector Vw) Instruction Type:      CVI_SCATTER Execution
+   Slots:       SLOT0
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: void Q6_vscatter_RMVhV…
Instruction Type: CVI_SCATTER
Execution Slots: SLOT0
========================================================================== */
#define Q6_vscatter_RMVhV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermh)
#endif /* __HEXAGON_ARCH___ >= 65 */
#if __HVX_ARCH__ >= 65
/* ==========================================================================
Assembly Syntax: vscatter(Rt32,Mu2,Vv32.h).h+=Vw32
C Intrinsic Prototype: void Q6_vscatteracc_RMVhV(Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: void Q6_vscatteracc_RMVhV(Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw)
-   Instruction Type:      CVI_SCATTER
-   Execution Slots:       SLOT0
+   C Intrinsic Prototype: void Q6_vscatteracc_RMVhV(Word32 Rt, Word32 Mu,
+   HVX_Vector Vv, HVX_Vector Vw) Instruction Type:      CVI_SCATTER Execution
+   Slots:       SLOT0
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: void Q6_vscatteracc_RMVhV…
Instruction Type: CVI_SCATTER
Execution Slots: SLOT0
========================================================================== */
#define Q6_vscatteracc_RMVhV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermh_add)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_vscatteracc_RMVhV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermh_add)
+#define Q6_vscatteracc_RMVhV                                                   \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermh_add)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_vscatteracc_RMVhV __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 65 */
#if __HVX_ARCH__ >= 65
/* ==========================================================================
Assembly Syntax: if (Qs4) vscatter(Rt32,Mu2,Vv32.h).h=Vw32
C Intrinsic Prototype: void Q6_vscatter_QRMVhV(HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: void Q6_vscatter_QRMVhV(HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw)
-   Instruction Type:      CVI_SCATTER
+   C Intrinsic Prototype: void Q6_vscatter_QRMVhV(HVX_VectorPred Qs, Word32 Rt,
+   Word32 Mu, HVX_Vector Vv, HVX_Vector Vw) Instruction Type:      CVI_SCATTER
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: void Q6_vscatter_QRMVhV…
Instruction Type: CVI_SCATTER
Execution Slots: SLOT0
========================================================================== */
#define Q6_vscatter_QRMVhV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhq)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_vscatter_QRMVhV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhq)
+#define Q6_vscatter_QRMVhV                                                     \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhq)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_vscatter_QRMVhV __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 65 */
#if __HVX_ARCH__ >= 65
/* ==========================================================================
Assembly Syntax: vscatter(Rt32,Mu2,Vvv32.w).h=Vw32
C Intrinsic Prototype: void Q6_vscatter_RMWwV(Word32 Rt, Word32 Mu, HVX_VectorPair Vvv, HVX_Vector Vw)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: void Q6_vscatter_RMWwV(Word32 Rt, Word32 Mu, HVX_VectorPair Vvv, HVX_Vector Vw)
-   Instruction Type:      CVI_SCATTER_DV
+   C Intrinsic Prototype: void Q6_vscatter_RMWwV(Word32 Rt, Word32 Mu,
+   HVX_VectorPair Vvv, HVX_Vector Vw) Instruction Type:      CVI_SCATTER_DV
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: void Q6_vscatter_RMWwV…
Instruction Type: CVI_SCATTER_DV
Execution Slots: SLOT0
========================================================================== */
#define Q6_vscatter_RMWwV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhw)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_vscatter_RMWwV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhw)
+#define Q6_vscatter_RMWwV                                                      \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhw)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_vscatter_RMWwV __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 65 */
#if __HVX_ARCH__ >= 65
/* ==========================================================================
Assembly Syntax: vscatter(Rt32,Mu2,Vvv32.w).h+=Vw32
C Intrinsic Prototype: void Q6_vscatteracc_RMWwV(Word32 Rt, Word32 Mu, HVX_VectorPair Vvv, HVX_Vector Vw)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: void Q6_vscatteracc_RMWwV(Word32 Rt, Word32 Mu, HVX_VectorPair Vvv, HVX_Vector Vw)
-   Instruction Type:      CVI_SCATTER_DV
+   C Intrinsic Prototype: void Q6_vscatteracc_RMWwV(Word32 Rt, Word32 Mu,
+   HVX_VectorPair Vvv, HVX_Vector Vw) Instruction Type:      CVI_SCATTER_DV
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: void Q6_vscatteracc_RMWwV…
Instruction Type: CVI_SCATTER_DV
Execution Slots: SLOT0
========================================================================== */
#define Q6_vscatteracc_RMWwV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhw_add)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_vscatteracc_RMWwV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhw_add)
+#define Q6_vscatteracc_RMWwV                                                   \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhw_add)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_vscatteracc_RMWwV __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 65 */
#if __HVX_ARCH__ >= 65
/* ==========================================================================
Assembly Syntax: if (Qs4) vscatter(Rt32,Mu2,Vvv32.w).h=Vw32
C Intrinsic Prototype: void Q6_vscatter_QRMWwV(HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_VectorPair Vvv, HVX_Vector Vw)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: void Q6_vscatter_QRMWwV(HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_VectorPair Vvv, HVX_Vector Vw)
-   Instruction Type:      CVI_SCATTER_DV
-   Execution Slots:       SLOT0
+   C Intrinsic Prototype: void Q6_vscatter_QRMWwV(HVX_VectorPred Qs, Word32 Rt,
+   Word32 Mu, HVX_VectorPair Vvv, HVX_Vector Vw) Instruction Type:
+   CVI_SCATTER_DV Execution Slots:       SLOT0
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: void Q6_vscatter_QRMWwV…
Instruction Type: CVI_SCATTER_DV
Execution Slots: SLOT0
========================================================================== */
#define Q6_vscatter_QRMWwV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhwq)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_vscatter_QRMWwV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhwq)
+#define Q6_vscatter_QRMWwV                                                     \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhwq)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_vscatter_QRMWwV __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 65 */
#if __HVX_ARCH__ >= 65
/* ==========================================================================
Assembly Syntax: vscatter(Rt32,Mu2,Vv32.w).w=Vw32
C Intrinsic Prototype: void Q6_vscatter_RMVwV(Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: void Q6_vscatter_RMVwV(Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw)
-   Instruction Type:      CVI_SCATTER
-   Execution Slots:       SLOT0
+   C Intrinsic Prototype: void Q6_vscatter_RMVwV(Word32 Rt, Word32 Mu,
+   HVX_Vector Vv, HVX_Vector Vw) Instruction Type:      CVI_SCATTER Execution
+   Slots:       SLOT0
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: void Q6_vscatter_RMVwV…
Instruction Type: CVI_SCATTER
Execution Slots: SLOT0
========================================================================== */
#define Q6_vscatter_RMVwV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermw)
#endif /* __HEXAGON_ARCH___ >= 65 */
#if __HVX_ARCH__ >= 65
/* ==========================================================================
Assembly Syntax: vscatter(Rt32,Mu2,Vv32.w).w+=Vw32
C Intrinsic Prototype: void Q6_vscatteracc_RMVwV(Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: void Q6_vscatteracc_RMVwV(Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw)
-   Instruction Type:      CVI_SCATTER
-   Execution Slots:       SLOT0
+   C Intrinsic Prototype: void Q6_vscatteracc_RMVwV(Word32 Rt, Word32 Mu,
+   HVX_Vector Vv, HVX_Vector Vw) Instruction Type:      CVI_SCATTER Execution
+   Slots:       SLOT0
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: void Q6_vscatteracc_RMVwV…
Instruction Type: CVI_SCATTER
Execution Slots: SLOT0
========================================================================== */
#define Q6_vscatteracc_RMVwV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermw_add)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_vscatteracc_RMVwV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermw_add)
+#define Q6_vscatteracc_RMVwV                                                   \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermw_add)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_vscatteracc_RMVwV __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 65 */
#if __HVX_ARCH__ >= 65
/* ==========================================================================
Assembly Syntax: if (Qs4) vscatter(Rt32,Mu2,Vv32.w).w=Vw32
C Intrinsic Prototype: void Q6_vscatter_QRMVwV(HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: void Q6_vscatter_QRMVwV(HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw)
-   Instruction Type:      CVI_SCATTER
+   C Intrinsic Prototype: void Q6_vscatter_QRMVwV(HVX_VectorPred Qs, Word32 Rt,
+   Word32 Mu, HVX_Vector Vv, HVX_Vector Vw) Instruction Type:      CVI_SCATTER
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: void Q6_vscatter_QRMVwV…
Instruction Type: CVI_SCATTER
Execution Slots: SLOT0
========================================================================== */
#define Q6_vscatter_QRMVwV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermwq)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_vscatter_QRMVwV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermwq)
+#define Q6_vscatter_QRMVwV                                                     \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermwq)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_vscatter_QRMVwV __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 65 */
#if __HVX_ARCH__ >= 66
/* ==========================================================================
Assembly Syntax: Vd32.w=vadd(Vu32.w,Vv32.w,Qs4):carry:sat
C Intrinsic Prototype: HVX_Vector Q6_Vw_vadd_VwVwQ_carry_sat(HVX_Vector Vu, HVX_Vector Vv, HVX_VectorPred Qs)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vw_vadd_VwVwQ_carry_sat(HVX_Vector Vu, HVX_Vector Vv, HVX_VectorPred Qs)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vadd_VwVwQ_carry_sat(HVX_Vector Vu,
+   HVX_Vector Vv, HVX_VectorPred Qs) Instruction Type:      CVI_VA Execution
+   Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vw_vadd_VwVwQ_carry_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddcarrysat)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Vw_vadd_VwVwQ_carry_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddcarrysat)
+#define Q6_Vw_vadd_VwVwQ_carry_sat                                             \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddcarrysat)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Vw_vadd_VwVwQ_carry_sat…
#endif /* __HEXAGON_ARCH___ >= 66 */
#if __HVX_ARCH__ >= 66
/* ==========================================================================
Assembly Syntax: Vxx32.w=vasrinto(Vu32.w,Vv32.w)
C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vasrinto_WwVwVw(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vasrinto_WwVwVw(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VP_VS
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vasrinto_WwVwVw(HVX_VectorPair
+   Vxx, HVX_Vector Vu, HVX_Vector Vv) Instruction Type:      CVI_VP_VS Execution
+   Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VP_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Ww_vasrinto_WwVwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasr_into)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Ww_vasrinto_WwVwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasr_into)
+#define Q6_Ww_vasrinto_WwVwVw                                                  \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasr_into)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Ww_vasrinto_WwVwVw __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 66 */
#if __HVX_ARCH__ >= 66
/* ==========================================================================
Assembly Syntax: Vd32.uw=vrotr(Vu32.uw,Vv32.uw)
C Intrinsic Prototype: HVX_Vector Q6_Vuw_vrotr_VuwVuw(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vuw_vrotr_VuwVuw(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VS
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vuw_vrotr_VuwVuw(HVX_Vector Vu,
+   HVX_Vector Vv) Instruction Type:      CVI_VS Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VS
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vuw_vrotr_VuwVuw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrotr)
#endif /* __HEXAGON_ARCH___ >= 66 */
#if __HVX_ARCH__ >= 66
/* ==========================================================================
Assembly Syntax: Vd32.w=vsatdw(Vu32.w,Vv32.w)
C Intrinsic Prototype: HVX_Vector Q6_Vw_vsatdw_VwVw(HVX_Vector Vu, HVX_Vector Vv)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_Vector Q6_Vw_vsatdw_VwVw(HVX_Vector Vu, HVX_Vector Vv)
-   Instruction Type:      CVI_VA
-   Execution Slots:       SLOT0123
+   C Intrinsic Prototype: HVX_Vector Q6_Vw_vsatdw_VwVw(HVX_Vector Vu, HVX_Vector
+   Vv) Instruction Type:      CVI_VA Execution Slots:       SLOT0123
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_Vector…
Instruction Type: CVI_VA
Execution Slots: SLOT0123
========================================================================== */
#define Q6_Vw_vsatdw_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsatdw)
#endif /* __HEXAGON_ARCH___ >= 66 */
#if __HVX_ARCH__ >= 68
/* ==========================================================================
Assembly Syntax: Vdd32.w=v6mpy(Vuu32.ub,Vvv32.b,#u2):h
C Intrinsic Prototype: HVX_VectorPair Q6_Ww_v6mpy_WubWbI_h(HVX_VectorPair Vuu, HVX_VectorPair Vvv, Word32 Iu2)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_v6mpy_WubWbI_h(HVX_VectorPair Vuu, HVX_VectorPair Vvv, Word32 Iu2)
-   Instruction Type:      CVI_VX_DV
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_v6mpy_WubWbI_h(HVX_VectorPair
+   Vuu, HVX_VectorPair Vvv, Word32 Iu2) Instruction Type:      CVI_VX_DV
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Ww_v6mpy_WubWbI_h __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyhubs10)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Ww_v6mpy_WubWbI_h __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyhubs10)
+#define Q6_Ww_v6mpy_WubWbI_h                                                   \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyhubs10)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Ww_v6mpy_WubWbI_h __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 68 */
#if __HVX_ARCH__ >= 68
/* ==========================================================================
Assembly Syntax: Vxx32.w+=v6mpy(Vuu32.ub,Vvv32.b,#u2):h
C Intrinsic Prototype: HVX_VectorPair Q6_Ww_v6mpyacc_WwWubWbI_h(HVX_VectorPair Vxx, HVX_VectorPair Vuu, HVX_VectorPair Vvv, Word32 Iu2)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_v6mpyacc_WwWubWbI_h(HVX_VectorPair Vxx, HVX_VectorPair Vuu, HVX_VectorPair Vvv, Word32 Iu2)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_VectorPair
+   Q6_Ww_v6mpyacc_WwWubWbI_h(HVX_VectorPair Vxx, HVX_VectorPair Vuu,
+   HVX_VectorPair Vvv, Word32 Iu2) Instruction Type:      CVI_VX_DV Execution
+   Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Ww_v6mpyacc_WwWubWbI_h __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyhubs10_vxx)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Ww_v6mpyacc_WwWubWbI_h __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyhubs10_vxx)
+#define Q6_Ww_v6mpyacc_WwWubWbI_h                                              \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyhubs10_vxx)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Ww_v6mpyacc_WwWubWbI_h…
#endif /* __HEXAGON_ARCH___ >= 68 */
#if __HVX_ARCH__ >= 68
/* ==========================================================================
Assembly Syntax: Vdd32.w=v6mpy(Vuu32.ub,Vvv32.b,#u2):v
C Intrinsic Prototype: HVX_VectorPair Q6_Ww_v6mpy_WubWbI_v(HVX_VectorPair Vuu, HVX_VectorPair Vvv, Word32 Iu2)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_v6mpy_WubWbI_v(HVX_VectorPair Vuu, HVX_VectorPair Vvv, Word32 Iu2)
-   Instruction Type:      CVI_VX_DV
+   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_v6mpy_WubWbI_v(HVX_VectorPair
+   Vuu, HVX_VectorPair Vvv, Word32 Iu2) Instruction Type:      CVI_VX_DV
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Ww_v6mpy_WubWbI_v __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyvubs10)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Ww_v6mpy_WubWbI_v __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyvubs10)
+#define Q6_Ww_v6mpy_WubWbI_v                                                   \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyvubs10)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Ww_v6mpy_WubWbI_v __BUILTIN_VECTOR_WRAP…
#endif /* __HEXAGON_ARCH___ >= 68 */
#if __HVX_ARCH__ >= 68
/* ==========================================================================
Assembly Syntax: Vxx32.w+=v6mpy(Vuu32.ub,Vvv32.b,#u2):v
C Intrinsic Prototype: HVX_VectorPair Q6_Ww_v6mpyacc_WwWubWbI_v(HVX_VectorPair Vxx, HVX_VectorPair Vuu, HVX_VectorPair Vvv, Word32 Iu2)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-   C Intrinsic Prototype: HVX_VectorPair Q6_Ww_v6mpyacc_WwWubWbI_v(HVX_VectorPair Vxx, HVX_VectorPair Vuu, HVX_VectorPair Vvv, Word32 Iu2)
-   Instruction Type:      CVI_VX_DV
-   Execution Slots:       SLOT23
+   C Intrinsic Prototype: HVX_VectorPair
+   Q6_Ww_v6mpyacc_WwWubWbI_v(HVX_VectorPair Vxx, HVX_VectorPair Vuu,
+   HVX_VectorPair Vvv, Word32 Iu2) Instruction Type:      CVI_VX_DV Execution
+   Slots:       SLOT23
Lint: Pre-merge checks: clang-format: please reformat the code ``` - C Intrinsic Prototype: HVX_VectorPair…
Instruction Type: CVI_VX_DV
Execution Slots: SLOT23
========================================================================== */
#define Q6_Ww_v6mpyacc_WwWubWbI_v __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyvubs10_vxx)
Lint: Pre-merge checks
Inline Actions

clang-format: please reformat the code

-#define Q6_Ww_v6mpyacc_WwWubWbI_v __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyvubs10_vxx)
+#define Q6_Ww_v6mpyacc_WwWubWbI_v                                              \
+  __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyvubs10_vxx)
Lint: Pre-merge checks: clang-format: please reformat the code ``` -#define Q6_Ww_v6mpyacc_WwWubWbI_v…
#endif /* __HEXAGON_ARCH___ >= 68 */
#endif /* __HVX__ */
#endif

clang/test/Headers/hexagon-audio-headers.c

  • This file was added.
// REQUIRES: hexagon-registered-target
// RUN: %clang_cc1 -O0 -internal-isystem %S/../../lib/Headers/ \
// RUN: -target-cpu hexagonv67t -triple hexagon-unknown-elf \
// RUN: -emit-llvm %s -o - | FileCheck %s
// RUN: %clang_cc1 -O0 -internal-isystem %S/../../lib/Headers/ \
// RUN: -target-cpu hexagonv67t -triple hexagon-unknown-elf -x c++ \
// RUN: -emit-llvm %s -o - | FileCheck %s
// RUN: not %clang_cc1 -O0 -internal-isystem %S/../../lib/Headers/ \
// RUN: -target-cpu hexagonv68 -triple hexagon-unknown-elf -x c++ \
// RUN: -fsyntax-only %s 2>&1 | FileCheck --implicit-check-not='error:' \
// RUN: --check-prefix=CHECK-ERR-CXX %s
// RUN: not %clang_cc1 -O0 -internal-isystem %S/../../lib/Headers/ \
// RUN: -target-cpu hexagonv68 -triple hexagon-unknown-elf -std=c99 \
// RUN: -Wimplicit-function-declaration -Werror -fsyntax-only %s 2>&1 | \
// RUN: FileCheck --implicit-check-not='error:' --check-prefix=CHECK-ERR-C99 %s
#include <hexagon_protos.h>
void test_audio() {
unsigned int b;
unsigned long long c;
// CHECK-ERR-CXX: error: use of undeclared identifier 'Q6_R_clip_RI'
// CHECK-ERR-C99: error: implicit declaration of function 'Q6_R_clip_RI' is invalid in C99
// CHECK: call i32 @llvm.hexagon.A7.clip
b = Q6_R_clip_RI(b, 9);
// CHECK-ERR-CXX: error: use of undeclared identifier 'Q6_P_cround_PI'
// CHECK-ERR-C99: error: implicit declaration of function 'Q6_P_cround_PI' is invalid in C99
// CHECK: call i64 @llvm.hexagon.A7.cround
c = Q6_P_cround_PI(c, 12);
}

clang/test/Headers/hexagon-headers.c

  • This file was added.
// REQUIRES: hexagon-registered-target
// RUN: %clang_cc1 -O0 -internal-isystem %S/../../lib/Headers/ \
// RUN: -target-cpu hexagonv68 -triple hexagon-unknown-elf \
// RUN: -emit-llvm %s -o - | FileCheck %s
// RUN: %clang_cc1 -O0 -internal-isystem %S/../../lib/Headers/ \
// RUN: -target-cpu hexagonv68 -triple hexagon-unknown-elf -x c++ \
// RUN: -emit-llvm %s -o - | FileCheck %s
#include <hexagon_protos.h>
// expected-no-diagnostics
void test_protos(float a, unsigned int b) {
unsigned char c;
// CHECK: call i64 @llvm.hexagon.A2.absp
b = Q6_P_abs_P(b);
}
void test_dma() {
unsigned int b;
// CHECK: call i32 @llvm.hexagon.Y6.dmpoll
b = Q6_R_dmpoll();
// CHECK: call i32 @llvm.hexagon.Y6.dmpause
b = Q6_R_dmpause();
}

clang/test/Headers/hexagon-hvx-headers.c

  • This file was added.
// REQUIRES: hexagon-registered-target
// RUN: %clang_cc1 -O0 -internal-isystem %S/../../lib/Headers/ \
// RUN: -target-cpu hexagonv68 -triple hexagon-unknown-elf \
// RUN: -target-feature +hvx-length128b -target-feature +hvxv68 \
// RUN: -emit-llvm %s -o - | FileCheck --check-prefix=CHECK %s
// RUN: %clang_cc1 -O0 -internal-isystem %S/../../lib/Headers/ \
// RUN: -target-cpu hexagonv68 -triple hexagon-unknown-elf -DDIRECT \
// RUN: -target-feature +hvx-length128b -target-feature +hvxv68 \
// RUN: -emit-llvm %s -o - | FileCheck --check-prefix=CHECK %s
// RUN: %clang_cc1 -O0 -internal-isystem %S/../../lib/Headers/ \
// RUN: -target-cpu hexagonv68 -triple hexagon-unknown-elf -x c++ \
// RUN: -target-feature +hvx-length128b -target-feature +hvxv68 \
// RUN: -emit-llvm %s -o - | FileCheck --check-prefix=CHECK %s
// RUN: %clang_cc1 -O0 -internal-isystem %S/../../lib/Headers/ \
// RUN: -target-cpu hexagonv68 -triple hexagon-unknown-elf \
// RUN: -target-feature +hvx-length64b -target-feature +hvxv68 \
// RUN: -emit-llvm %s -o - | FileCheck --check-prefix=CHECK-64 %s
#ifdef DIRECT
#include <hvx_hexagon_protos.h>
#else
#include <hexagon_protos.h>
#endif
#include <hexagon_types.h>
// expected-no-diagnostics
void test_hvx_protos(float a, unsigned int b) {
HVX_VectorPair c;
// CHECK-64: call <32 x i32> @llvm.hexagon.V6.v6mpyhubs10
// CHECK: call <64 x i32> @llvm.hexagon.V6.v6mpyhubs10.128B
c = Q6_Ww_v6mpy_WubWbI_h(c, c, 12);
}