MIR Serialization: Serialize machine instruction names.

[arphaman]

Summary

This patch is based on a patch that implements initial serialization of machine basic blocks (http://reviews.llvm.org/D10465).

This patch is the initial patch for machine instruction serialization. Only the machine instruction names are serialized by this patch. The instructions are represented using a YAML sequence of string literals and are a part of machine basic block YAML mapping. An example of such MBB mapping is shown below:

name: entry
instructions:
  - mov32r0
  - retq

A machine instruction parser class 'MIParser' is introduced by this patch. This class will be used to parse the machine instructions. A supporting machine instruction lexing class will be added in the upcoming patch.

[ab]

lib/CodeGen/MIRPrinter.cpp

115

Why lower-case? I'd much prefer the exact same as the C++/MI enums/names. And if no one else does this lowercasing already (I don't think so), this can introduce ambiguity (it will).

include/llvm/CodeGen/MIRYamlMapping.h

 
 #ifndef LLVM_LIB_CODEGEN_MIRYAMLMAPPING_H
 #define LLVM_LIB_CODEGEN_MIRYAMLMAPPING_H
 
 #include "llvm/ADT/StringRef.h"
 #include "llvm/Support/YAMLTraits.h"
 #include <vector>
 
+LLVM_YAML_IS_SEQUENCE_VECTOR(std::string)
+
 namespace llvm {
 namespace yaml {
 
 struct MachineBasicBlock {
   std::string Name;
   unsigned Alignment;
   bool IsLandingPad;
   bool AddressTaken;
   // TODO: Serialize the successors and liveins.
-  // TODO: Serialize machine instructions.
+
+  std::vector<std::string> Instructions;
 };
 
 template <> struct MappingTraits<MachineBasicBlock> {
   static void mapping(IO &YamlIO, MachineBasicBlock &MBB) {
     YamlIO.mapOptional("name", MBB.Name,
                        std::string()); // Don't print out an empty name.
     YamlIO.mapOptional("alignment", MBB.Alignment);
     YamlIO.mapOptional("isLandingPad", MBB.IsLandingPad);
     YamlIO.mapOptional("addressTaken", MBB.AddressTaken);
+    YamlIO.mapOptional("instructions", MBB.Instructions);
   }
 };
 
 } // end namespace yaml
 } // end namespace llvm
 
 LLVM_YAML_IS_SEQUENCE_VECTOR(llvm::yaml::MachineBasicBlock)
 

lib/CodeGen/MIRParser/CMakeLists.txt

 add_llvm_library(LLVMMIRParser
+  MIParser.cpp
   MIRParser.cpp
   )
 
 add_dependencies(LLVMMIRParser intrinsics_gen)

lib/CodeGen/MIRParser/MIParser.h

+//===- MIParser.h - Machine Instructions Parser ---------------------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file declares the function that parses the machine instructions.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_CODEGEN_MIRPARSER_MIPARSER_H
+#define LLVM_LIB_CODEGEN_MIRPARSER_MIPARSER_H
+
+#include "llvm/ADT/StringRef.h"
+
+namespace llvm {
+
+class MachineInstr;
+class MachineFunction;
+class SMDiagnostic;
+class SourceMgr;
+
+MachineInstr *parseMachineInstr(SourceMgr &SM, MachineFunction &MF,
+                                StringRef Src, SMDiagnostic &Error);
+
+} // end namespace llvm
+
+#endif

lib/CodeGen/MIRParser/MIParser.cpp

+//===- MIParser.cpp - Machine instructions parser implementation ----------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the parsing of machine instructions.
+//
+//===----------------------------------------------------------------------===//
+
+#include "MIParser.h"
+#include "llvm/ADT/StringMap.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/Support/raw_ostream.h"
+#include "llvm/Support/SourceMgr.h"
+#include "llvm/Target/TargetSubtargetInfo.h"
+#include "llvm/Target/TargetInstrInfo.h"
+
+using namespace llvm;
+
+namespace {
+
+class MIParser {
+  SourceMgr &SM;
+  MachineFunction &MF;
+  SMDiagnostic &Error;
+  StringRef Source;
+  /// Maps from instruction names to op codes.
+  StringMap<unsigned> Names2InstrOpCodes;
+
+public:
+  MIParser(SourceMgr &SM, MachineFunction &MF, SMDiagnostic &Error,
+           StringRef Source);
+
+  /// Report an error at the current location with the given message.
+  ///
+  /// This function always return true.
+  bool error(const Twine &Msg);
+
+  MachineInstr *parse();
+
+private:
+  void initNames2InstrOpCodes();
+
+  /// Try to convert an instruction name to an opcode. Return true if the
+  /// instruction name is invalid.
+  bool parseInstrName(StringRef InstrName, unsigned &OpCode);
+};
+
+} // end anonymous namespace
+
+MIParser::MIParser(SourceMgr &SM, MachineFunction &MF, SMDiagnostic &Error,
+                   StringRef Source)
+    : SM(SM), MF(MF), Error(Error), Source(Source) {}
+
+bool MIParser::error(const Twine &Msg) {
+  // TODO: Get the proper location in the MIR file, not just a location inside
+  // the string.
+  Error =
+      SMDiagnostic(SM, SMLoc(), SM.getMemoryBuffer(SM.getMainFileID())
+                                    ->getBufferIdentifier(),
+                   1, 0, SourceMgr::DK_Error, Msg.str(), Source, None, None);
+  return true;
+}
+
+MachineInstr *MIParser::parse() {
+  StringRef InstrName = Source;
+  unsigned OpCode;
+  if (parseInstrName(InstrName, OpCode)) {
+    error(Twine("unknown machine instruction name '") + InstrName + "'");
+    return nullptr;
+  }
+
+  const auto &MCID = MF.getSubtarget().getInstrInfo()->get(OpCode);
+  auto *MI = MF.CreateMachineInstr(MCID, DebugLoc());
+  return MI;
+}
+
+void MIParser::initNames2InstrOpCodes() {
+  if (!Names2InstrOpCodes.empty())
+    return;
+  const auto *TII = MF.getSubtarget().getInstrInfo();
+  for (unsigned I = 0, E = TII->getNumOpcodes(); I < E; ++I)
+    Names2InstrOpCodes.insert(
+        std::make_pair(StringRef(TII->getName(I)).lower(), I));
+}
+
+bool MIParser::parseInstrName(StringRef InstrName, unsigned &OpCode) {
+  initNames2InstrOpCodes();
+  auto InstrInfo = Names2InstrOpCodes.find(InstrName);
+  if (InstrInfo == Names2InstrOpCodes.end())
+    return true;
+  OpCode = InstrInfo->getValue();
+  return false;
+}
+
+MachineInstr *llvm::parseMachineInstr(SourceMgr &SM, MachineFunction &MF,
+                                      StringRef Src, SMDiagnostic &Error) {
+  return MIParser(SM, MF, Error, Src).parse();
+}

lib/CodeGen/MIRParser/MIRParser.cpp

 //===- MIRParser.cpp - MIR serialization format parser implementation -----===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the class that parses the optional LLVM IR and machine
 // functions that are stored in MIR files.
 //
 //===----------------------------------------------------------------------===//
 
 #include "llvm/CodeGen/MIRParser/MIRParser.h"
+#include "MIParser.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/ADT/StringMap.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/AsmParser/Parser.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MIRYamlMapping.h"
 #include "llvm/IR/BasicBlock.h"
 #include "llvm/IR/DiagnosticInfo.h"
public:
   /// file.
   ///
   /// Return true if error occurred.
   bool initializeMachineFunction(MachineFunction &MF);
 
   /// Initialize the machine basic block using it's YAML representation.
   ///
   /// Return true if an error occurred.
-  bool initializeMachineBasicBlock(MachineBasicBlock &MBB,
+  bool initializeMachineBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB,
                                    const yaml::MachineBasicBlock &YamlMBB);
 
 private:
   /// Return a MIR diagnostic converted from an LLVM assembly diagnostic.
   SMDiagnostic diagFromLLVMAssemblyDiag(const SMDiagnostic &Error,
                                         SMRange SourceRange);
 
   /// Create an empty function with the given name.
bool MIRParserImpl::initializeMachineFunction(MachineFunction &MF) {
   MF.setExposesReturnsTwice(YamlMF.ExposesReturnsTwice);
   MF.setHasInlineAsm(YamlMF.HasInlineAsm);
   for (const auto &YamlMBB : YamlMF.BasicBlocks) {
     const BasicBlock *BB = nullptr;
     if (!YamlMBB.Name.empty())
       BB = findBasicBlock(MF.getFunction(), YamlMBB.Name);
     auto *MBB = MF.CreateMachineBasicBlock(BB);
     MF.insert(MF.end(), MBB);
-    if (initializeMachineBasicBlock(*MBB, YamlMBB))
+    if (initializeMachineBasicBlock(MF, *MBB, YamlMBB))
       return true;
   }
   return false;
 }
 
 bool MIRParserImpl::initializeMachineBasicBlock(
-    MachineBasicBlock &MBB, const yaml::MachineBasicBlock &YamlMBB) {
+    MachineFunction &MF, MachineBasicBlock &MBB,
+    const yaml::MachineBasicBlock &YamlMBB) {
   MBB.setAlignment(YamlMBB.Alignment);
   if (YamlMBB.AddressTaken)
     MBB.setHasAddressTaken();
   MBB.setIsLandingPad(YamlMBB.IsLandingPad);
+  // Parse the instructions.
+  for (const auto &MISource : YamlMBB.Instructions) {
+    SMDiagnostic Error;
+    if (auto *MI = parseMachineInstr(SM, MF, MISource, Error)) {
+      MBB.insert(MBB.end(), MI);
+      continue;
+    }
+    reportDiagnostic(Error);
+    return true;
+  }
   return false;
 }
 
 SMDiagnostic MIRParserImpl::diagFromLLVMAssemblyDiag(const SMDiagnostic &Error,
                                                      SMRange SourceRange) {
   assert(SourceRange.isValid());
 
   // Translate the location of the error from the location in the llvm IR string

lib/CodeGen/MIRPrinter.cpp

 #include "llvm/ADT/STLExtras.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MIRYamlMapping.h"
 #include "llvm/IR/BasicBlock.h"
 #include "llvm/IR/Module.h"
 #include "llvm/Support/MemoryBuffer.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/Support/YAMLTraits.h"
+#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/Target/TargetSubtargetInfo.h"
 
 using namespace llvm;
 
 namespace {
 
 /// This class prints out the machine functions using the MIR serialization
 /// format.
 class MIRPrinter {
   raw_ostream &OS;
 
 public:
   MIRPrinter(raw_ostream &OS) : OS(OS) {}
 
   void print(const MachineFunction &MF);
 
   void convert(yaml::MachineBasicBlock &YamlMBB, const MachineBasicBlock &MBB);
 };
 
+/// This class prints out the machine instructions using the MIR serialization
+/// format.
+class MIPrinter {
+  raw_ostream &OS;
+
+public:
+  MIPrinter(raw_ostream &OS) : OS(OS) {}
+
+  void print(const MachineInstr &MI);
+};
+
 } // end anonymous namespace
 
 namespace llvm {
 namespace yaml {
 
 /// This struct serializes the LLVM IR module.
 template <> struct BlockScalarTraits<Module> {
   static void output(const Module &Mod, void *Ctxt, raw_ostream &OS) {
void MIRPrinter::convert(yaml::MachineBasicBlock &YamlMBB,
   const auto *BB = MBB.getBasicBlock();
   if (BB && BB->hasName())
     YamlMBB.Name = BB->getName();
   else
     YamlMBB.Name = "";
   YamlMBB.Alignment = MBB.getAlignment();
   YamlMBB.AddressTaken = MBB.hasAddressTaken();
   YamlMBB.IsLandingPad = MBB.isLandingPad();
+
+  // Print the machine instructions.
+  YamlMBB.Instructions.reserve(MBB.size());
+  std::string Str;
+  for (const auto &MI : MBB) {
+    raw_string_ostream StrOS(Str);
+    MIPrinter(StrOS).print(MI);
+    YamlMBB.Instructions.push_back(StrOS.str());
+    Str.clear();
+  }
+}
+
+void MIPrinter::print(const MachineInstr &MI) {
+  const auto &SubTarget = MI.getParent()->getParent()->getSubtarget();
+  const auto *TII = SubTarget.getInstrInfo();
+
+  OS << StringRef(TII->getName(MI.getOpcode())).lower();
 }
 
 void llvm::printMIR(raw_ostream &OS, const Module &M) {
   yaml::Output Out(OS);
   Out << const_cast<Module &>(M);
 }
 
 void llvm::printMIR(raw_ostream &OS, const MachineFunction &MF) {
   MIRPrinter Printer(OS);
   Printer.print(MF);
 }

test/CodeGen/MIR/X86/lit.local.cfg

+if not 'X86' in config.root.targets:
+    config.unsupported = True

test/CodeGen/MIR/X86/machine-instructions.mir

+# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s
+# This test ensures that the MIR parser parses X86 machine instructions
+# correctly.
+
+--- |
+
+  define i32 @inc(i32 %a) {
+  entry:
+    %b = mul i32 %a, 11
+    ret i32 %b
+  }
+
+...
+---
+# CHECK: name: inc
+name:            inc
+body:
+ - name:         entry
+   instructions:
+     # CHECK:      - imul32rri8
+     # CHECK-NEXT: - retq
+     - imul32rri8
+     - retq
+...

test/CodeGen/MIR/X86/unknown-instruction.mir

+# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s
+# This test ensures that an error is reported when an unknown instruction is
+# encountered.
+
+--- |
+
+  define i32 @foo() {
+  entry:
+    ret i32 0
+  }
+
+...
+---
+name:            foo
+body:
+ - name:         entry
+   instructions:
+     # CHECK: 1:1: unknown machine instruction name 'retJust0'
+     - retJust0
+...