[mips][microMIPS] Implement SLL and NOP instructions

[zbuljan]

Summary

The patch implements microMIPSr6 SLL and NOP instructions.

[dsanders]

lib/Target/Mips/MicroMips32r6InstrFormats.td

267–268

The documentation calls them 'rt' and 'rs' respectively. That doesn't sound right though, 'rd' and 'rt' sound more likely.

lib/Target/Mips/MipsInstrInfo.td

425–436

Please use the existing uimm5 operand. You can add the range checking in a separate patch (either before or after) this one.

[zbuljan]

Used existing operand uimm5 instead of new one.
Range checking for uimm5 will be added in separate patch later.

[dsanders]

LGTM

lib/Target/Mips/MicroMips32r6InstrFormats.td

267–268

I've found out a bit more about this kind of thing and I suggest we leave it as-is for now.

The issue is that MIPS and microMIPS don't always agree on the names since the names are derived from the fields of the encoding table and these two encodings sometimes use different fields. I'm currently thinking of a reasonable way to account for this without making the code ugly.

[zbuljan]

Closed by commit rL241150: [mips][microMIPS] Implement SLL and NOP instructions

lib/Target/Mips/MicroMips32r6InstrFormats.td

class TRAP_MMR6_ENC<bits<6> funct> : MipsR6Inst {
   let Inst{31-26} = 0x00;
   let Inst{25-21} = rt;
   let Inst{20-16} = rs;
   let Inst{15-12} = code_;
   let Inst{11-6} = funct;
   let Inst{5-0}  = 0x3c;
 }
 
+class SHIFT_MMR6_ENC<string instr_asm, bits<10> funct, bit rotate> : MMR6Arch<instr_asm> {
+  bits<5> rd;
+  bits<5> rt;
+  bits<5> shamt;
+
+  bits<32> Inst;
+
+  let Inst{31-26} = 0;
+  let Inst{25-21} = rd;
+  let Inst{20-16} = rt;
+  let Inst{15-11} = shamt;
+  let Inst{10}    = rotate;
+  let Inst{9-0}   = funct;
+}

lib/Target/Mips/MicroMips32r6InstrInfo.td

 class NOR_MMR6_ENC : ARITH_FM_MMR6<"nor", 0x2d0>;
 class OR_MMR6_ENC : ARITH_FM_MMR6<"or", 0x290>;
 class ORI_MMR6_ENC : ADDI_FM_MMR6<"ori", 0x14>;
 class PREF_MMR6_ENC : CACHE_PREF_FM_MMR6<0b011000, 0b0010>;
 class SEB_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seb", 0b0010101100>;
 class SEH_MMR6_ENC : SIGN_EXTEND_FM_MMR6<"seh", 0b0011101100>;
 class SELEQZ_MMR6_ENC : POOL32A_FM_MMR6<0b0101000000>;
 class SELNEZ_MMR6_ENC : POOL32A_FM_MMR6<0b0110000000>;
+class SLL_MMR6_ENC : SHIFT_MMR6_ENC<"sll", 0x00, 0b0>;
 class SUB_MMR6_ENC : ARITH_FM_MMR6<"sub", 0x190>;
 class SUBU_MMR6_ENC : ARITH_FM_MMR6<"subu", 0x1d0>;
 class XOR_MMR6_ENC : ARITH_FM_MMR6<"xor", 0x310>;
 class XORI_MMR6_ENC : ADDI_FM_MMR6<"xori", 0x1c>;
 
 class CMP_CBR_RT_Z_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd,
                                   RegisterOperand GPROpnd>
     : BRANCH_DESC_BASE, MMR6Arch<instr_asm> {
class SELEQNE_Z_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
   dag OutOperandList = (outs GPROpnd:$rd);
   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
   string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
   list<dag> Pattern = [];
 }
 
 class SELEQZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"seleqz", GPR32Opnd>;
 class SELNEZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"selnez", GPR32Opnd>;
+class SLL_MMR6_DESC : shift_rotate_imm<"sll", uimm5opnd, GPR32Opnd, II_SLL>;
 class DIV_MMR6_DESC : ArithLogicR<"div", GPR32Opnd>;
 class DIVU_MMR6_DESC : ArithLogicR<"divu", GPR32Opnd>;
 class MOD_MMR6_DESC : ArithLogicR<"mod", GPR32Opnd>;
 class MODU_MMR6_DESC : ArithLogicR<"modu", GPR32Opnd>;
 class AND_MMR6_DESC : ArithLogicR<"and", GPR32Opnd>;
 class ANDI_MMR6_DESC : ArithLogicI<"andi", simm16, GPR32Opnd>;
 class NOR_MMR6_DESC : ArithLogicR<"nor", GPR32Opnd>;
 class OR_MMR6_DESC : ArithLogicR<"or", GPR32Opnd>;

 def ORI_MMR6 : StdMMR6Rel, ORI_MMR6_DESC, ORI_MMR6_ENC, ISA_MICROMIPS32R6;
 def PREF_MMR6 : R6MMR6Rel, PREF_MMR6_ENC, PREF_MMR6_DESC, ISA_MICROMIPS32R6;
 def SEB_MMR6 : StdMMR6Rel, SEB_MMR6_DESC, SEB_MMR6_ENC, ISA_MICROMIPS32R6;
 def SEH_MMR6 : StdMMR6Rel, SEH_MMR6_DESC, SEH_MMR6_ENC, ISA_MICROMIPS32R6;
 def SELEQZ_MMR6 : R6MMR6Rel, SELEQZ_MMR6_ENC, SELEQZ_MMR6_DESC,
                   ISA_MICROMIPS32R6;
 def SELNEZ_MMR6 : R6MMR6Rel, SELNEZ_MMR6_ENC, SELNEZ_MMR6_DESC,
                   ISA_MICROMIPS32R6;
+def SLL_MMR6 : StdMMR6Rel, SLL_MMR6_DESC, SLL_MMR6_ENC, ISA_MICROMIPS32R6;
 def SUB_MMR6 : StdMMR6Rel, SUB_MMR6_DESC, SUB_MMR6_ENC, ISA_MICROMIPS32R6;
 def SUBU_MMR6 : StdMMR6Rel, SUBU_MMR6_DESC, SUBU_MMR6_ENC, ISA_MICROMIPS32R6;
 def XOR_MMR6 : StdMMR6Rel, XOR_MMR6_DESC, XOR_MMR6_ENC, ISA_MICROMIPS32R6;
 def XORI_MMR6 : StdMMR6Rel, XORI_MMR6_DESC, XORI_MMR6_ENC, ISA_MICROMIPS32R6;
 def TEQ_MMR6 : StdMMR6Rel, TEQ_MMR6_ENC, TEQ_MMR6_DESC, ISA_MICROMIPS32R6;
 def TGE_MMR6 : StdMMR6Rel, TGE_MMR6_ENC, TGE_MMR6_DESC, ISA_MICROMIPS32R6;
 def TGEU_MMR6 : StdMMR6Rel, TGEU_MMR6_ENC, TGEU_MMR6_DESC, ISA_MICROMIPS32R6;
 def TLT_MMR6 : StdMMR6Rel, TLT_MMR6_ENC, TLT_MMR6_DESC, ISA_MICROMIPS32R6;
 def TLTU_MMR6 : StdMMR6Rel, TLTU_MMR6_ENC, TLTU_MMR6_DESC, ISA_MICROMIPS32R6;
 def TNE_MMR6 : StdMMR6Rel, TNE_MMR6_ENC, TNE_MMR6_DESC, ISA_MICROMIPS32R6;
 }
+
+//===----------------------------------------------------------------------===//
+//
+// MicroMips instruction aliases
+//
+//===----------------------------------------------------------------------===//
+
+def : MipsInstAlias<"nop", (SLL_MMR6 ZERO, ZERO, 0), 1>, ISA_MICROMIPS32R6;

lib/Target/Mips/MicroMipsInstrInfo.td

def SDIV_MM  : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
                  MULT_FM_MM<0x2ac>;
   def UDIV_MM  : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
                  MULT_FM_MM<0x2ec>;
 
   /// Arithmetic Instructions with PC and Immediate
   def ADDIUPC_MM : AddImmUPC<"addiupc", GPRMM16Opnd>, ADDIUPC_FM_MM;
 
   /// Shift Instructions
-  def SLL_MM   : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>,
+  def SLL_MM   : MMRel, shift_rotate_imm<"sll", uimm5opnd, GPR32Opnd, II_SLL>,
                  SRA_FM_MM<0, 0>;
   def SRL_MM   : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL>,
                  SRA_FM_MM<0x40, 0>;
   def SRA_MM   : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA>,
                  SRA_FM_MM<0x80, 0>;
   def SLLV_MM  : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV>,
                  SRLV_FM_MM<0x10, 0>;
   def SRLV_MM  : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV>,

lib/Target/Mips/MipsInstrInfo.td

 def uimm3 : Operand<i32> {
   let PrintMethod = "printUnsignedImm";
 }
 
 def uimm5       : Operand<i32> {
   let PrintMethod = "printUnsignedImm";
 }
 
+def MipsUImm5AsmOperand : AsmOperandClass {
+  let Name = "UImm5";
+  let RenderMethod = "addImmOperands";
+  let ParserMethod = "parseImm";
+  let PredicateMethod = "isUImm<5>";
+}
+
+def uimm5opnd      : Operand<i32> {
+  let PrintMethod = "printUnsignedImm";
+  let ParserMatchClass = MipsUImm5AsmOperand;
+}
+
 def uimm6 : Operand<i32> {
   let PrintMethod = "printUnsignedImm";
 }
 
 def uimm16      : Operand<i32> {
   let PrintMethod = "printUnsignedImm";
 }
 
def OR    : MMRel, StdMMR6Rel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
             ADD_FM<0, 0x25>;
 def XOR   : MMRel, StdMMR6Rel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
             ADD_FM<0, 0x26>;
 }
 def NOR   : MMRel, StdMMR6Rel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
 
 /// Shift Instructions
 let AdditionalPredicates = [NotInMicroMips] in {
-def SLL  : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl,
+def SLL  : MMRel, shift_rotate_imm<"sll", uimm5opnd, GPR32Opnd, II_SLL, shl,
                                    immZExt5>, SRA_FM<0, 0>;
 def SRL  : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl,
                                    immZExt5>, SRA_FM<2, 0>;
 }
 def SRA  : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra,
                                    immZExt5>, SRA_FM<3, 0>;
 def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>,
            SRLV_FM<4, 0>;

 def : MipsInstAlias<"xor $rs, $rt, $imm",
                     (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
 def : MipsInstAlias<"xor $rs, $imm",
                     (XORi GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>;
 def : MipsInstAlias<"or $rs, $rt, $imm",
                     (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
 def : MipsInstAlias<"or $rs, $imm",
                     (ORi GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>;
+let AdditionalPredicates = [NotInMicroMips] in {
 def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
+}
 def : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
 def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
 def : MipsInstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
 def : MipsInstAlias<"mtc2 $rt, $rd", (MTC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
 let AdditionalPredicates = [NotInMicroMips] in {
 def : MipsInstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>;
 }
 def : MipsInstAlias<"bnez $rs,$offset",

test/MC/Disassembler/Mips/micromips32r6.txt

 0x00 0xa4 0x18 0x18 # CHECK: mul $3, $4, $5
 
 0x00 0xa4 0x18 0x58 # CHECK: muh $3, $4, $5
 
 0x00 0xa4 0x18 0x98 # CHECK: mulu $3, $4, $5
 
 0x00 0xa4,0x18,0xd8 # CHECK: muhu $3, $4, $5
 
+0x00 0x00 0x00 0x00 # CHECK: nop
+
 0x00 0xa4 0x1a 0xd0 # CHECK: nor $3, $4, $5
 
 0x00,0xa4,0x1a,0x90 # CHECK: or $3, $4, $5
 
 0x50 0x64 0x04 0xd2 # CHECK: ori $3, $4, 1234
 
 0x60 0x25 0x20 0x08 # CHECK: pref 1, 8($5)
 
 0x00 0x83 0x11 0x40 # CHECK: seleqz $2, $3, $4
 
 0x00 0x83 0x11 0x80 # CHECK: selnez $2, $3, $4
 
+0x00 0x83 0x38 0x00 # CHECK: sll $4, $3, 7
+
 0x00 0xa4 0x19 0x90 # CHECK: sub $3, $4, $5
 
 0x00 0xa4 0x19 0xd0 # CHECK: subu $3, $4, $5
 
 0x00 0xa4 0x1b 0x10 # CHECK: xor $3, $4, $5
 
 0x70 0x64 0x04 0xd2 # CHECK: xori $3, $4, 1234
 

test/MC/Mips/micromips-invalid.s

# RUN: FileCheck %s < %t1
   movep   $5, $6, $5, $3  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   movep   $5, $6, $2, $9  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   break 1024        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   break 1024, 5     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   break 7, 1024     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   break 1024, 1024  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   wait 1024         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   prefx 33, $8($5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
+  sll $33, $3, 7    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+  sll $4, $34, 7    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+  sll $4, $3, 32    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction

test/MC/Mips/micromips32r6/invalid.s

# RUN: FileCheck %s < %t1
   tne $8, $35, 6           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   tne $8, $9, 16           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
   teq $8, $9, $2           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   tge $8, $9, $2           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   tgeu $8, $9, $2          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   tlt $8, $9, $2           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   tltu $8, $9, $2          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   tne $8, $9, $2           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+  sll $33, $3, 7           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+  sll $4, $34, 7           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+  sll $4, $3, 32           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction

test/MC/Mips/micromips32r6/valid.s

# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips | FileCheck %s
   lsa $2, $3, $4, 3        # CHECK: lsa  $2, $3, $4, 3  # encoding: [0x00,0x43,0x26,0x0f]
   lwpc    $2,268           # CHECK: lwpc $2, 268        # encoding: [0x78,0x48,0x00,0x43]
   mod $3, $4, $5           # CHECK: mod $3, $4, $5      # encoding: [0x00,0xa4,0x19,0x58]
   modu $3, $4, $5          # CHECK: modu $3, $4, $5     # encoding: [0x00,0xa4,0x19,0xd8]
   mul $3, $4, $5           # CHECK mul $3, $4, $5       # encoding: [0x00,0xa4,0x18,0x18]
   muh $3, $4, $5           # CHECK muh $3, $4, $5       # encoding: [0x00,0xa4,0x18,0x58]
   mulu $3, $4, $5          # CHECK mulu $3, $4, $5      # encoding: [0x00,0xa4,0x18,0x98]
   muhu $3, $4, $5          # CHECK muhu $3, $4, $5      # encoding: [0x00,0xa4,0x18,0xd8]
+  nop                      # CHECK: nop                 # encoding: [0x00,0x00,0x00,0x00]
   nor $3, $4, $5           # CHECK: nor $3, $4, $5      # encoding: [0x00,0xa4,0x1a,0xd0]
   or $3, $4, $5            # CHECK: or $3, $4, $5       # encoding: [0x00,0xa4,0x1a,0x90]
   ori $3, $4, 1234         # CHECK: ori $3, $4, 1234    # encoding: [0x50,0x64,0x04,0xd2]
   pref 1, 8($5)            # CHECK: pref 1, 8($5)       # encoding: [0x60,0x25,0x20,0x08]
   seb $3, $4               # CHECK: seb $3, $4          # encoding: [0x00,0x64,0x2b,0x3c]
   seh $3, $4               # CHECK: seh $3, $4          # encoding: [0x00,0x64,0x3b,0x3c]
   seleqz $2,$3,$4          # CHECK: seleqz $2, $3, $4   # encoding: [0x00,0x83,0x11,0x40]
   selnez $2,$3,$4          # CHECK: selnez $2, $3, $4   # encoding: [0x00,0x83,0x11,0x80]
+  sll $4, $3, 7            # CHECK: sll $4, $3, 7       # encoding: [0x00,0x83,0x38,0x00]
+
   sub $3, $4, $5           # CHECK: sub $3, $4, $5      # encoding: [0x00,0xa4,0x19,0x90]
   subu $3, $4, $5          # CHECK: subu $3, $4, $5     # encoding: [0x00,0xa4,0x19,0xd0]
 
   xor $3, $4, $5           # CHECK: xor $3, $4, $5      # encoding: [0x00,0xa4,0x1b,0x10]
   xori $3, $4, 1234        # CHECK: xori $3, $4, 1234   # encoding: [0x70,0x64,0x04,0xd2]
 
   teq $8, $9               # CHECK: teq $8, $9          # encoding: [0x01,0x28,0x00,0x3c]
   teq $5, $7, 15           # CHECK: teq $5, $7, 15      # encoding: [0x00,0xe5,0xf0,0x3c]

test/MC/Mips/mips32r6/invalid.s

# RUN: FileCheck %s < %t1 -check-prefix=ASM
         jalr.hb $31, $31 # ASM: :[[@LINE]]:9: error: source and destination must be different
         ldc2    $8,-21181($at)   # ASM: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         sdc2    $20,23157($s2)   # ASM: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         swc2    $25,24880($s0)   # ASM: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         break 1024        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         break 1024, 5     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         break 7, 1024     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         break 1024, 1024  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        sll $33, $3, 7    # ASM: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        sll $4, $34, 7    # ASM: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        sll $4, $3, 32    # ASM: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction

test/MC/Mips/mips64r6/invalid.s

 # Instructions that are available for the current ISA but should be rejected by
 # the assembler (e.g. invalid set of operands or operand's restrictions not met).
 
 # RUN: not llvm-mc %s -triple=mips64-unknown-linux -mcpu=mips64r6 2>%t1
 # RUN: FileCheck %s < %t1 -check-prefix=ASM
 
         .text
         .set noreorder
   .set noat
         jalr.hb $31 # ASM: :[[@LINE]]:9: error: source and destination must be different
         jalr.hb $31, $31 # ASM: :[[@LINE]]:9: error: source and destination must be different
         ldc2    $8,-21181($at)   # ASM: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         break 1024        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         break 1024, 5     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         break 7, 1024     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
         break 1024, 1024  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        sll $33, $3, 7    # ASM: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        sll $4, $34, 7    # ASM: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+        sll $4, $3, 32    # ASM: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction