This is an archive of the discontinued LLVM Phabricator instance.

Differential D104685

[M68k] Add testcases for shift and rotate instructions
ClosedPublic

Authored by Jim on Jun 21 2021, 9:02 PM.

Details

Reviewers
myhsu
Commits
rG0365af1a87eb: [M68k] Add testcases for shift and rotate instructions
Summary

Add codegen testcases for lsl, lsr, asr, rol and ror instructions.

Diff Detail

Event Timeline

Jim requested review of this revision.Jun 21 2021, 9:02 PM
Jim created this revision.
Herald added a project: Restricted Project. · View Herald TranscriptJun 21 2021, 9:02 PM
Herald added a subscriber: llvm-commits. · View Herald Transcript
Jim edited the summary of this revision. (Show Details)Jun 21 2021, 9:04 PM
Jim added a reviewer: myhsu.
Harbormaster completed remote builds in B110333: Diff 353545.Jun 21 2021, 9:40 PM
myhsu accepted this revision.Jun 22 2021, 9:43 PM

LGTM
Thank you!

This revision is now accepted and ready to land.Jun 22 2021, 9:43 PM
This revision was landed with ongoing or failed builds.Jun 22 2021, 10:25 PM
Closed by commit rG0365af1a87eb: [M68k] Add testcases for shift and rotate instructions (authored by Jim). · Explain Why
This revision was automatically updated to reflect the committed changes.
Jim added a commit: rG0365af1a87eb: [M68k] Add testcases for shift and rotate instructions.

Revision Contents

PathSize
llvm/
test/
CodeGen/
M68k/
ShiftRotate/
75 lines
75 lines
75 lines
79 lines
79 lines

Diff 353851

llvm/test/CodeGen/M68k/ShiftRotate/asr.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=m68k-linux -verify-machineinstrs | FileCheck %s
; op reg, reg
define zeroext i8 @asrb(i8 zeroext %a, i8 zeroext %b) nounwind {
; CHECK-LABEL: asrb:
; CHECK: ; %bb.0:
; CHECK-NEXT: move.b (11,%sp), %d0
; CHECK-NEXT: move.b (7,%sp), %d1
; CHECK-NEXT: asr.b %d0, %d1
; CHECK-NEXT: move.l %d1, %d0
; CHECK-NEXT: and.l #255, %d0
; CHECK-NEXT: rts
%1 = ashr i8 %a, %b
ret i8 %1
}
define zeroext i16 @asrw(i16 zeroext %a, i16 zeroext %b) nounwind {
; CHECK-LABEL: asrw:
; CHECK: ; %bb.0:
; CHECK-NEXT: move.w (10,%sp), %d0
; CHECK-NEXT: move.w (6,%sp), %d1
; CHECK-NEXT: asr.w %d0, %d1
; CHECK-NEXT: move.l %d1, %d0
; CHECK-NEXT: and.l #65535, %d0
; CHECK-NEXT: rts
%1 = ashr i16 %a, %b
ret i16 %1
}
define i32 @asrl(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: asrl:
; CHECK: ; %bb.0:
; CHECK-NEXT: move.l (8,%sp), %d1
; CHECK-NEXT: move.l (4,%sp), %d0
; CHECK-NEXT: asr.l %d1, %d0
; CHECK-NEXT: rts
%1 = ashr i32 %a, %b
ret i32 %1
}
; op reg, imm
define zeroext i8 @asrib(i8 zeroext %a) nounwind {
; CHECK-LABEL: asrib:
; CHECK: ; %bb.0:
; CHECK-NEXT: move.b (7,%sp), %d0
; CHECK-NEXT: asr.b #3, %d0
; CHECK-NEXT: and.l #255, %d0
; CHECK-NEXT: rts
%1 = ashr i8 %a, 3
ret i8 %1
}
define zeroext i16 @asriw(i16 zeroext %a) nounwind {
; CHECK-LABEL: asriw:
; CHECK: ; %bb.0:
; CHECK-NEXT: move.w (6,%sp), %d0
; CHECK-NEXT: asr.w #5, %d0
; CHECK-NEXT: and.l #65535, %d0
; CHECK-NEXT: rts
%1 = ashr i16 %a, 5
ret i16 %1
}
define i32 @asril(i32 %a) nounwind {
; CHECK-LABEL: asril:
; CHECK: ; %bb.0:
; CHECK-NEXT: move.l (4,%sp), %d0
; CHECK-NEXT: asr.l #7, %d0
; CHECK-NEXT: rts
%1 = ashr i32 %a, 7
ret i32 %1
}

llvm/test/CodeGen/M68k/ShiftRotate/lsl.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=m68k-linux -verify-machineinstrs | FileCheck %s
; op reg, reg
define zeroext i8 @lslb(i8 zeroext %a, i8 zeroext %b) nounwind {
; CHECK-LABEL: lslb:
; CHECK: ; %bb.0:
; CHECK-NEXT: move.b (11,%sp), %d0
; CHECK-NEXT: move.b (7,%sp), %d1
; CHECK-NEXT: lsl.b %d0, %d1
; CHECK-NEXT: move.l %d1, %d0
; CHECK-NEXT: and.l #255, %d0
; CHECK-NEXT: rts
%1 = shl i8 %a, %b
ret i8 %1
}
define zeroext i16 @lslw(i16 zeroext %a, i16 zeroext %b) nounwind {
; CHECK-LABEL: lslw:
; CHECK: ; %bb.0:
; CHECK-NEXT: move.w (10,%sp), %d0
; CHECK-NEXT: move.w (6,%sp), %d1
; CHECK-NEXT: lsl.w %d0, %d1
; CHECK-NEXT: move.l %d1, %d0
; CHECK-NEXT: and.l #65535, %d0
; CHECK-NEXT: rts
%1 = shl i16 %a, %b
ret i16 %1
}
define i32 @lsll(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: lsll:
; CHECK: ; %bb.0:
; CHECK-NEXT: move.l (8,%sp), %d1
; CHECK-NEXT: move.l (4,%sp), %d0
; CHECK-NEXT: lsl.l %d1, %d0
; CHECK-NEXT: rts
%1 = shl i32 %a, %b
ret i32 %1
}
; op reg, imm
define zeroext i8 @lslib(i8 zeroext %a) nounwind {
; CHECK-LABEL: lslib:
; CHECK: ; %bb.0:
; CHECK-NEXT: move.b (7,%sp), %d0
; CHECK-NEXT: lsl.b #3, %d0
; CHECK-NEXT: and.l #255, %d0
; CHECK-NEXT: rts
%1 = shl i8 %a, 3
ret i8 %1
}
define zeroext i16 @lsliw(i16 zeroext %a) nounwind {
; CHECK-LABEL: lsliw:
; CHECK: ; %bb.0:
; CHECK-NEXT: move.w (6,%sp), %d0
; CHECK-NEXT: lsl.w #5, %d0
; CHECK-NEXT: and.l #65535, %d0
; CHECK-NEXT: rts
%1 = shl i16 %a, 5
ret i16 %1
}
define i32 @lslil(i32 %a) nounwind {
; CHECK-LABEL: lslil:
; CHECK: ; %bb.0:
; CHECK-NEXT: move.l (4,%sp), %d0
; CHECK-NEXT: lsl.l #7, %d0
; CHECK-NEXT: rts
%1 = shl i32 %a, 7
ret i32 %1
}

llvm/test/CodeGen/M68k/ShiftRotate/lsr.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=m68k-linux -verify-machineinstrs | FileCheck %s
; op reg, reg
define zeroext i8 @lsrb(i8 zeroext %a, i8 zeroext %b) nounwind {
; CHECK-LABEL: lsrb:
; CHECK: ; %bb.0:
; CHECK-NEXT: move.b (11,%sp), %d0
; CHECK-NEXT: move.b (7,%sp), %d1
; CHECK-NEXT: lsr.b %d0, %d1
; CHECK-NEXT: move.l %d1, %d0
; CHECK-NEXT: and.l #255, %d0
; CHECK-NEXT: rts
%1 = lshr i8 %a, %b
ret i8 %1
}
define zeroext i16 @lsrw(i16 zeroext %a, i16 zeroext %b) nounwind {
; CHECK-LABEL: lsrw:
; CHECK: ; %bb.0:
; CHECK-NEXT: move.w (10,%sp), %d0
; CHECK-NEXT: move.w (6,%sp), %d1
; CHECK-NEXT: lsr.w %d0, %d1
; CHECK-NEXT: move.l %d1, %d0
; CHECK-NEXT: and.l #65535, %d0
; CHECK-NEXT: rts
%1 = lshr i16 %a, %b
ret i16 %1
}
define i32 @lsrl(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: lsrl:
; CHECK: ; %bb.0:
; CHECK-NEXT: move.l (8,%sp), %d1
; CHECK-NEXT: move.l (4,%sp), %d0
; CHECK-NEXT: lsr.l %d1, %d0
; CHECK-NEXT: rts
%1 = lshr i32 %a, %b
ret i32 %1
}
; op reg, imm
define zeroext i8 @lsrib(i8 zeroext %a) nounwind {
; CHECK-LABEL: lsrib:
; CHECK: ; %bb.0:
; CHECK-NEXT: move.b (7,%sp), %d0
; CHECK-NEXT: lsr.b #3, %d0
; CHECK-NEXT: and.l #255, %d0
; CHECK-NEXT: rts
%1 = lshr i8 %a, 3
ret i8 %1
}
define zeroext i16 @lsriw(i16 zeroext %a) nounwind {
; CHECK-LABEL: lsriw:
; CHECK: ; %bb.0:
; CHECK-NEXT: move.w (6,%sp), %d0
; CHECK-NEXT: lsr.w #5, %d0
; CHECK-NEXT: and.l #65535, %d0
; CHECK-NEXT: rts
%1 = lshr i16 %a, 5
ret i16 %1
}
define i32 @lsril(i32 %a) nounwind {
; CHECK-LABEL: lsril:
; CHECK: ; %bb.0:
; CHECK-NEXT: move.l (4,%sp), %d0
; CHECK-NEXT: lsr.l #7, %d0
; CHECK-NEXT: rts
%1 = lshr i32 %a, 7
ret i32 %1
}

llvm/test/CodeGen/M68k/ShiftRotate/rol.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=m68k-linux -verify-machineinstrs | FileCheck %s
declare i8 @llvm.fshl.i8(i8, i8, i8)
declare i16 @llvm.fshl.i16(i16, i16, i16)
declare i32 @llvm.fshl.i32(i32, i32, i32)
; op reg, reg
define zeroext i8 @rolb(i8 zeroext %a, i8 zeroext %b) nounwind {
; CHECK-LABEL: rolb:
; CHECK: ; %bb.0:
; CHECK-NEXT: move.b (11,%sp), %d0
; CHECK-NEXT: move.b (7,%sp), %d1
; CHECK-NEXT: rol.b %d0, %d1
; CHECK-NEXT: move.l %d1, %d0
; CHECK-NEXT: and.l #255, %d0
; CHECK-NEXT: rts
%1 = tail call i8 @llvm.fshl.i8(i8 %a, i8 %a, i8 %b)
ret i8 %1
}
define zeroext i16 @rolw(i16 zeroext %a, i16 zeroext %b) nounwind {
; CHECK-LABEL: rolw:
; CHECK: ; %bb.0:
; CHECK-NEXT: move.w (10,%sp), %d0
; CHECK-NEXT: move.w (6,%sp), %d1
; CHECK-NEXT: rol.w %d0, %d1
; CHECK-NEXT: move.l %d1, %d0
; CHECK-NEXT: and.l #65535, %d0
; CHECK-NEXT: rts
%1 = tail call i16 @llvm.fshl.i16(i16 %a, i16 %a, i16 %b)
ret i16 %1
}
define i32 @roll(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: roll:
; CHECK: ; %bb.0:
; CHECK-NEXT: move.l (8,%sp), %d1
; CHECK-NEXT: move.l (4,%sp), %d0
; CHECK-NEXT: rol.l %d1, %d0
; CHECK-NEXT: rts
%1 = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 %b)
ret i32 %1
}
; op reg, imm
define zeroext i8 @rolib(i8 zeroext %a) nounwind {
; CHECK-LABEL: rolib:
; CHECK: ; %bb.0:
; CHECK-NEXT: move.b (7,%sp), %d0
; CHECK-NEXT: rol.b #3, %d0
; CHECK-NEXT: and.l #255, %d0
; CHECK-NEXT: rts
%1 = tail call i8 @llvm.fshl.i8(i8 %a, i8 %a, i8 3)
ret i8 %1
}
define zeroext i16 @roliw(i16 zeroext %a) nounwind {
; CHECK-LABEL: roliw:
; CHECK: ; %bb.0:
; CHECK-NEXT: move.w (6,%sp), %d0
; CHECK-NEXT: rol.w #5, %d0
; CHECK-NEXT: and.l #65535, %d0
; CHECK-NEXT: rts
%1 = tail call i16 @llvm.fshl.i16(i16 %a, i16 %a, i16 5)
ret i16 %1
}
define i32 @rolil(i32 %a) nounwind {
; CHECK-LABEL: rolil:
; CHECK: ; %bb.0:
; CHECK-NEXT: move.l (4,%sp), %d0
; CHECK-NEXT: rol.l #7, %d0
; CHECK-NEXT: rts
%1 = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 7)
ret i32 %1
}

llvm/test/CodeGen/M68k/ShiftRotate/ror.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=m68k-linux -verify-machineinstrs | FileCheck %s
declare i8 @llvm.fshr.i8(i8, i8, i8)
declare i16 @llvm.fshr.i16(i16, i16, i16)
declare i32 @llvm.fshr.i32(i32, i32, i32)
; op reg, reg
define zeroext i8 @rorb(i8 zeroext %a, i8 zeroext %b) nounwind {
; CHECK-LABEL: rorb:
; CHECK: ; %bb.0:
; CHECK-NEXT: move.b (11,%sp), %d0
; CHECK-NEXT: move.b (7,%sp), %d1
; CHECK-NEXT: ror.b %d0, %d1
; CHECK-NEXT: move.l %d1, %d0
; CHECK-NEXT: and.l #255, %d0
; CHECK-NEXT: rts
%1 = tail call i8 @llvm.fshr.i8(i8 %a, i8 %a, i8 %b)
ret i8 %1
}
define zeroext i16 @rorw(i16 zeroext %a, i16 zeroext %b) nounwind {
; CHECK-LABEL: rorw:
; CHECK: ; %bb.0:
; CHECK-NEXT: move.w (10,%sp), %d0
; CHECK-NEXT: move.w (6,%sp), %d1
; CHECK-NEXT: ror.w %d0, %d1
; CHECK-NEXT: move.l %d1, %d0
; CHECK-NEXT: and.l #65535, %d0
; CHECK-NEXT: rts
%1 = tail call i16 @llvm.fshr.i16(i16 %a, i16 %a, i16 %b)
ret i16 %1
}
define i32 @rorl(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: rorl:
; CHECK: ; %bb.0:
; CHECK-NEXT: move.l (8,%sp), %d1
; CHECK-NEXT: move.l (4,%sp), %d0
; CHECK-NEXT: ror.l %d1, %d0
; CHECK-NEXT: rts
%1 = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 %b)
ret i32 %1
}
; op reg, imm
define zeroext i8 @rorib(i8 zeroext %a) nounwind {
; CHECK-LABEL: rorib:
; CHECK: ; %bb.0:
; CHECK-NEXT: move.b (7,%sp), %d0
; CHECK-NEXT: ror.b #3, %d0
; CHECK-NEXT: and.l #255, %d0
; CHECK-NEXT: rts
%1 = tail call i8 @llvm.fshr.i8(i8 %a, i8 %a, i8 3)
ret i8 %1
}
define zeroext i16 @roriw(i16 zeroext %a) nounwind {
; CHECK-LABEL: roriw:
; CHECK: ; %bb.0:
; CHECK-NEXT: move.w (6,%sp), %d0
; CHECK-NEXT: ror.w #5, %d0
; CHECK-NEXT: and.l #65535, %d0
; CHECK-NEXT: rts
%1 = tail call i16 @llvm.fshr.i16(i16 %a, i16 %a, i16 5)
ret i16 %1
}
define i32 @roril(i32 %a) nounwind {
; CHECK-LABEL: roril:
; CHECK: ; %bb.0:
; CHECK-NEXT: move.l (4,%sp), %d0
; CHECK-NEXT: ror.l #7, %d0
; CHECK-NEXT: rts
%1 = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 7)
ret i32 %1
}