[MIPS] Emulation of MIPS64 floating-point branch instructions

[jaydeep]

Summary

1. Added emulation of MIPS64 floating-point branch instructions
2. Updated GetRegisterInfo to recognize floating-point registers
3. Provided CPU information while creating createMCSubtargetInfo in disassembler
4. Bug fix in emulation of JIC and JIALC
5. Correct identification of breakpoint when set in a delay slot of a branch instruction

[jaydeep]

Hi clayborg,

Could you please find some time to review this patch?

Thanks,
Jaydeep

[clayborg]

source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp

640

Initialize this with "" for now and then remove the setting to "" in the default. Just in case someone later adds code and doesn't set cpu to something.

source/Plugins/Process/Linux/NativeProcessLinux.cpp

3487–3505

This should probably be moved somewhere more generic so that this code doesn't get duplicated for each process plug-in.

[jaydeep]

Thanks for the comments.

source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp

640

We would still need cpu = "" in the default case to avoid -Wswitch warning.

source/Plugins/Process/Linux/NativeProcessLinux.cpp

3487–3505

We will remove it from this patch and submit a separate patch.

[jaydeep]

Addressed review comments

[clayborg]

source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp

640–679

Is CPU needed here? We are passing the triple which should contain the CPU name right? Why do we need "cpu" here as a separate thing?

[jaydeep]

source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp

640–679

The triple does not contain MIPS ISA revision (like r2, r3, r5, r6 etc.) which is required for disassembly.

[clayborg]

Ok, thanks for the explanation. Looks good then.

source/Plugins/Disassembler/llvm/DisassemblerLLVMC.h

 
 class DisassemblerLLVMC : public lldb_private::Disassembler
 {
     // Since we need to make two actual MC Disassemblers for ARM (ARM & THUMB), and there's a bit of goo to set up and own
     // in the MC disassembler world, I added this class to manage the actual disassemblers.
     class LLVMCDisassembler
     {
     public:
-        LLVMCDisassembler (const char *triple, unsigned flavor, DisassemblerLLVMC &owner);
+        LLVMCDisassembler (const char *triple, const char *cpu, unsigned flavor, DisassemblerLLVMC &owner);
 
         ~LLVMCDisassembler();
 
         uint64_t GetMCInst (const uint8_t *opcode_data, size_t opcode_data_len, lldb::addr_t pc, llvm::MCInst &mc_inst);
         uint64_t PrintMCInst (llvm::MCInst &mc_inst, char *output_buffer, size_t out_buffer_len);
         void     SetStyle (bool use_hex_immed, HexImmediateStyle hex_style);
         bool     CanBranch (llvm::MCInst &mc_inst);
         bool     IsValid()

source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp

protected:
     DisassemblerSP          m_disasm_sp; // for ownership
     LazyBool                m_does_branch;
     bool                    m_is_valid;
     bool                    m_using_file_addr;
 };
 
 
 
-DisassemblerLLVMC::LLVMCDisassembler::LLVMCDisassembler (const char *triple, unsigned flavor, DisassemblerLLVMC &owner):
+DisassemblerLLVMC::LLVMCDisassembler::LLVMCDisassembler (const char *triple, const char *cpu, unsigned flavor, DisassemblerLLVMC &owner):
     m_is_valid(true)
 {
     std::string Error;
     const llvm::Target *curr_target = llvm::TargetRegistry::lookupTarget(triple, Error);
     if (!curr_target)
     {
         m_is_valid = false;
         return;
     }
 
     m_instr_info_ap.reset(curr_target->createMCInstrInfo());
     m_reg_info_ap.reset (curr_target->createMCRegInfo(triple));
 
     std::string features_str;
 
-    m_subtarget_info_ap.reset(curr_target->createMCSubtargetInfo(triple, "",
+    m_subtarget_info_ap.reset(curr_target->createMCSubtargetInfo(triple, cpu,
                                                                 features_str));
 
     std::unique_ptr<llvm::MCRegisterInfo> reg_info(curr_target->createMCRegInfo(triple));
     m_asm_info_ap.reset(curr_target->createMCAsmInfo(*reg_info, triple));
 
     if (m_instr_info_ap.get() == NULL || m_reg_info_ap.get() == NULL || m_subtarget_info_ap.get() == NULL || m_asm_info_ap.get() == NULL)
     {
         m_is_valid = false;
DisassemblerLLVMC::DisassemblerLLVMC (const ArchSpec &arch, const char *flavor_string) :
     if (arch.GetTriple().getArch() == llvm::Triple::arm
         && (arch.GetCore() == ArchSpec::Core::eCore_arm_armv7m
             || arch.GetCore() == ArchSpec::Core::eCore_arm_armv7em
             || arch.GetCore() == ArchSpec::Core::eCore_arm_armv6m))
     {
         triple = thumb_arch.GetTriple().getTriple().c_str();
     }
 
-    m_disasm_ap.reset (new LLVMCDisassembler(triple, flavor, *this));
+    const char *cpu;
+    
+    switch (arch.GetCore())
+    {
+        case ArchSpec::eCore_mips32:
+        case ArchSpec::eCore_mips32el:
+            cpu = "mips32"; break;
+        case ArchSpec::eCore_mips32r2:
+        case ArchSpec::eCore_mips32r2el:
+            cpu = "mips32r2"; break;
+        case ArchSpec::eCore_mips32r3:
+        case ArchSpec::eCore_mips32r3el:
+            cpu = "mips32r3"; break;
+        case ArchSpec::eCore_mips32r5:
+        case ArchSpec::eCore_mips32r5el:
+            cpu = "mips32r5"; break;
+        case ArchSpec::eCore_mips32r6:
+        case ArchSpec::eCore_mips32r6el:
+            cpu = "mips32r6"; break;
+        case ArchSpec::eCore_mips64:
+        case ArchSpec::eCore_mips64el:
+            cpu = "mips64"; break;
+        case ArchSpec::eCore_mips64r2:
+        case ArchSpec::eCore_mips64r2el:
+            cpu = "mips64r2"; break;
+        case ArchSpec::eCore_mips64r3:
+        case ArchSpec::eCore_mips64r3el:
+            cpu = "mips64r3"; break;
+        case ArchSpec::eCore_mips64r5:
+        case ArchSpec::eCore_mips64r5el:
+            cpu = "mips64r5"; break;
+        case ArchSpec::eCore_mips64r6:
+        case ArchSpec::eCore_mips64r6el:
+            cpu = "mips64r6"; break;
+        default:
+            cpu = ""; break;
+    }
+    
+    m_disasm_ap.reset (new LLVMCDisassembler(triple, cpu, flavor, *this));
     if (!m_disasm_ap->IsValid())
     {
         // We use m_disasm_ap.get() to tell whether we are valid or not, so if this isn't good for some reason,
         // we reset it, and then we won't be valid and FindPlugin will fail and we won't get used.
         m_disasm_ap.reset();
     }
 
     // For arm CPUs that can execute arm or thumb instructions, also create a thumb instruction disassembler.
     if (arch.GetTriple().getArch() == llvm::Triple::arm)
     {
         std::string thumb_triple(thumb_arch.GetTriple().getTriple());
-        m_alternate_disasm_ap.reset(new LLVMCDisassembler(thumb_triple.c_str(), flavor, *this));
+        m_alternate_disasm_ap.reset(new LLVMCDisassembler(thumb_triple.c_str(), nullptr, flavor, *this));
         if (!m_alternate_disasm_ap->IsValid())
         {
             m_disasm_ap.reset();
             m_alternate_disasm_ap.reset();
         }
     }
 }
 

source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h

protected:
 
     bool
     Emulate_JIC (llvm::MCInst& insn);
 
     bool
     Emulate_JR (llvm::MCInst& insn);
 
     bool
+    Emulate_BC1F (llvm::MCInst& insn);
+
+    bool
+    Emulate_BC1T (llvm::MCInst& insn);
+
+    bool
+    Emulate_BC1FL (llvm::MCInst& insn);
+
+    bool
+    Emulate_BC1TL (llvm::MCInst& insn);
+
+    bool
+    Emulate_BC1EQZ (llvm::MCInst& insn);
+
+    bool
+    Emulate_BC1NEZ (llvm::MCInst& insn);
+
+    bool
+    Emulate_BC1ANY2F  (llvm::MCInst& insn);
+
+    bool
+    Emulate_BC1ANY2T  (llvm::MCInst& insn);
+
+    bool
+    Emulate_BC1ANY4F  (llvm::MCInst& insn);
+
+    bool
+    Emulate_BC1ANY4T  (llvm::MCInst& insn);
+
+    bool
     nonvolatile_reg_p (uint64_t regnum);
 
     const char *
     GetRegisterName (unsigned reg_num, bool altnernate_name);
 
 private:
     std::unique_ptr<llvm::MCDisassembler>   m_disasm;
     std::unique_ptr<llvm::MCSubtargetInfo>  m_subtype_info;
     std::unique_ptr<llvm::MCRegisterInfo>   m_reg_info;
     std::unique_ptr<llvm::MCAsmInfo>        m_asm_info;
     std::unique_ptr<llvm::MCContext>        m_context;
     std::unique_ptr<llvm::MCInstrInfo>      m_insn_info;
 };
 
 #endif  // EmulateInstructionMIPS64_h_

source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp

 
 const char *
 EmulateInstructionMIPS64::GetRegisterName (unsigned reg_num, bool alternate_name)
 {
     if (alternate_name)
     {
         switch (reg_num)
         {
-            case gcc_dwarf_sp_mips64: return "r29"; 
+            case gcc_dwarf_sp_mips64:  return "r29"; 
             case gcc_dwarf_r30_mips64: return "r30"; 
-            case gcc_dwarf_ra_mips64: return "r31";
+            case gcc_dwarf_ra_mips64:  return "r31";
+            case gcc_dwarf_f0_mips64:  return "f0";
+            case gcc_dwarf_f1_mips64:  return "f1";
+            case gcc_dwarf_f2_mips64:  return "f2";
+            case gcc_dwarf_f3_mips64:  return "f3";
+            case gcc_dwarf_f4_mips64:  return "f4";
+            case gcc_dwarf_f5_mips64:  return "f5";
+            case gcc_dwarf_f6_mips64:  return "f6";
+            case gcc_dwarf_f7_mips64:  return "f7";
+            case gcc_dwarf_f8_mips64:  return "f8";
+            case gcc_dwarf_f9_mips64:  return "f9";
+            case gcc_dwarf_f10_mips64: return "f10";
+            case gcc_dwarf_f11_mips64: return "f11";
+            case gcc_dwarf_f12_mips64: return "f12";
+            case gcc_dwarf_f13_mips64: return "f13";
+            case gcc_dwarf_f14_mips64: return "f14";
+            case gcc_dwarf_f15_mips64: return "f15";
+            case gcc_dwarf_f16_mips64: return "f16";
+            case gcc_dwarf_f17_mips64: return "f17";
+            case gcc_dwarf_f18_mips64: return "f18";
+            case gcc_dwarf_f19_mips64: return "f19";
+            case gcc_dwarf_f20_mips64: return "f20";
+            case gcc_dwarf_f21_mips64: return "f21";
+            case gcc_dwarf_f22_mips64: return "f22";
+            case gcc_dwarf_f23_mips64: return "f23";
+            case gcc_dwarf_f24_mips64: return "f24";
+            case gcc_dwarf_f25_mips64: return "f25";
+            case gcc_dwarf_f26_mips64: return "f26";
+            case gcc_dwarf_f27_mips64: return "f27";
+            case gcc_dwarf_f28_mips64: return "f28";
+            case gcc_dwarf_f29_mips64: return "f29";
+            case gcc_dwarf_f30_mips64: return "f30";
+            case gcc_dwarf_f31_mips64: return "f31";
             default:
                 break;
         }
         return nullptr;
     }
 
     switch (reg_num)
     {
switch (reg_num)
         case gcc_dwarf_r30_mips64:      return "fp";
         case gcc_dwarf_ra_mips64:       return "ra";
         case gcc_dwarf_sr_mips64:       return "sr";
         case gcc_dwarf_lo_mips64:       return "lo";
         case gcc_dwarf_hi_mips64:       return "hi";
         case gcc_dwarf_bad_mips64:      return "bad";
         case gcc_dwarf_cause_mips64:    return "cause";
         case gcc_dwarf_pc_mips64:       return "pc";
-
+        case gcc_dwarf_f0_mips64:       return "fp_reg[0]";
+        case gcc_dwarf_f1_mips64:       return "fp_reg[1]";
+        case gcc_dwarf_f2_mips64:       return "fp_reg[2]";
+        case gcc_dwarf_f3_mips64:       return "fp_reg[3]";
+        case gcc_dwarf_f4_mips64:       return "fp_reg[4]";
+        case gcc_dwarf_f5_mips64:       return "fp_reg[5]";
+        case gcc_dwarf_f6_mips64:       return "fp_reg[6]";
+        case gcc_dwarf_f7_mips64:       return "fp_reg[7]";
+        case gcc_dwarf_f8_mips64:       return "fp_reg[8]";
+        case gcc_dwarf_f9_mips64:       return "fp_reg[9]";
+        case gcc_dwarf_f10_mips64:      return "fp_reg[10]";
+        case gcc_dwarf_f11_mips64:      return "fp_reg[11]";
+        case gcc_dwarf_f12_mips64:      return "fp_reg[12]";
+        case gcc_dwarf_f13_mips64:      return "fp_reg[13]";
+        case gcc_dwarf_f14_mips64:      return "fp_reg[14]";
+        case gcc_dwarf_f15_mips64:      return "fp_reg[15]";
+        case gcc_dwarf_f16_mips64:      return "fp_reg[16]";
+        case gcc_dwarf_f17_mips64:      return "fp_reg[17]";
+        case gcc_dwarf_f18_mips64:      return "fp_reg[18]";
+        case gcc_dwarf_f19_mips64:      return "fp_reg[19]";
+        case gcc_dwarf_f20_mips64:      return "fp_reg[20]";
+        case gcc_dwarf_f21_mips64:      return "fp_reg[21]";
+        case gcc_dwarf_f22_mips64:      return "fp_reg[22]";
+        case gcc_dwarf_f23_mips64:      return "fp_reg[23]";
+        case gcc_dwarf_f24_mips64:      return "fp_reg[24]";
+        case gcc_dwarf_f25_mips64:      return "fp_reg[25]";
+        case gcc_dwarf_f26_mips64:      return "fp_reg[26]";
+        case gcc_dwarf_f27_mips64:      return "fp_reg[27]";
+        case gcc_dwarf_f28_mips64:      return "fp_reg[28]";
+        case gcc_dwarf_f29_mips64:      return "fp_reg[29]";
+        case gcc_dwarf_f30_mips64:      return "fp_reg[30]";
+        case gcc_dwarf_f31_mips64:      return "fp_reg[31]";
+        case gcc_dwarf_fcsr_mips64:     return "fcsr";
+        case gcc_dwarf_fir_mips64:      return "fir";
     }
     return nullptr;
 }
 
 bool
 EmulateInstructionMIPS64::GetRegisterInfo (RegisterKind reg_kind, uint32_t reg_num, RegisterInfo &reg_info)
 {
     if (reg_kind == eRegisterKindGeneric)
if (reg_kind == eRegisterKindGeneric)
         }
     }
 
     if (reg_kind == eRegisterKindDWARF)
     {
        ::memset (&reg_info, 0, sizeof(RegisterInfo));
        ::memset (reg_info.kinds, LLDB_INVALID_REGNUM, sizeof(reg_info.kinds));
 
-       if (reg_num == gcc_dwarf_sr_mips64)
+       if (reg_num == gcc_dwarf_sr_mips64 || reg_num == gcc_dwarf_fcsr_mips || reg_num == gcc_dwarf_fir_mips)
        {
            reg_info.byte_size = 4;
            reg_info.format = eFormatHex;
            reg_info.encoding = eEncodingUint;
        }
-       else if ((int)reg_num >= gcc_dwarf_zero_mips64 && (int)reg_num <= gcc_dwarf_pc_mips64)
+       else if ((int)reg_num >= gcc_dwarf_zero_mips64 && (int)reg_num <= gcc_dwarf_f31_mips)
        {
            reg_info.byte_size = 8;
            reg_info.format = eFormatHex;
            reg_info.encoding = eEncodingUint;
        }
        else
        {
            return false;
g_opcodes[] =
         { "JAL",        &EmulateInstructionMIPS64::Emulate_JAL,         "JAL target"                },
         { "JALX",       &EmulateInstructionMIPS64::Emulate_JAL,         "JALX target"               },
         { "JALR",       &EmulateInstructionMIPS64::Emulate_JALR,        "JALR target"               },
         { "JALR_HB",    &EmulateInstructionMIPS64::Emulate_JALR,        "JALR.HB target"            },
         { "JIALC",      &EmulateInstructionMIPS64::Emulate_JIALC,       "JIALC rt,offset"           },
         { "JIC",        &EmulateInstructionMIPS64::Emulate_JIC,         "JIC rt,offset"             },
         { "JR",         &EmulateInstructionMIPS64::Emulate_JR,          "JR target"                 },
         { "JR_HB",      &EmulateInstructionMIPS64::Emulate_JR,          "JR.HB target"              },
+        { "BC1F",       &EmulateInstructionMIPS64::Emulate_BC1F,        "BC1F cc, offset"           },
+        { "BC1T",       &EmulateInstructionMIPS64::Emulate_BC1T,        "BC1T cc, offset"           },
+        { "BC1FL",      &EmulateInstructionMIPS64::Emulate_BC1FL,       "BC1FL cc, offset"          },
+        { "BC1EQZ",     &EmulateInstructionMIPS64::Emulate_BC1EQZ,      "BC1EQZ ft, offset"         },
+        { "BC1NEZ",     &EmulateInstructionMIPS64::Emulate_BC1NEZ,      "BC1NEZ ft, offset"         },
+        { "BC1ANY2F",   &EmulateInstructionMIPS64::Emulate_BC1ANY2F,    "BC1ANY2F cc, offset"       },
+        { "BC1ANY2T",   &EmulateInstructionMIPS64::Emulate_BC1ANY2T,    "BC1ANY2T cc, offset"       },
+        { "BC1ANY4F",   &EmulateInstructionMIPS64::Emulate_BC1ANY4F,    "BC1ANY4F cc, offset"       },
+        { "BC1ANY4T",   &EmulateInstructionMIPS64::Emulate_BC1ANY4T,    "BC1ANY4T cc, offset"       },
     };
 
     static const size_t k_num_mips_opcodes = llvm::array_lengthof(g_opcodes);
 
     for (size_t i = 0; i < k_num_mips_opcodes; ++i)
     {
         if (! strcasecmp (g_opcodes[i].op_name, op_name))
             return &g_opcodes[i];
EmulateInstructionMIPS64::Emulate_JIALC (llvm::MCInst& insn)
 
     /* 
      * JIALC rt, offset
      *      offset = sign_ext (offset)
      *      PC = GPR[rt] + offset
      *      RA = PC + 4
     */
     rt = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
-    offset = insn.getOperand(0).getImm();
+    offset = insn.getOperand(1).getImm();
 
     pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success);
     if (!success)
         return false;
 
     rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rt, 0, &success);
     if (!success)
         return false;
EmulateInstructionMIPS64::Emulate_JIC (llvm::MCInst& insn)
     int64_t target, offset, rt_val;
 
     /* 
      * JIC rt, offset
      *      offset = sign_ext (offset)
      *      PC = GPR[rt] + offset
     */
     rt = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
-    offset = insn.getOperand(0).getImm();
+    offset = insn.getOperand(1).getImm();
 
     rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rt, 0, &success);
     if (!success)
         return false;
 
     target = rt_val + offset;
 
     Context context;
EmulateInstructionMIPS64::Emulate_JR (llvm::MCInst& insn)
 
     Context context;
 
     if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, rs_val))
         return false;
 
     return true;
 }
+
+bool
+EmulateInstructionMIPS64::Emulate_BC1F (llvm::MCInst& insn)
+{
+    bool success = false;
+    uint32_t cc, fcsr;
+    int64_t target, pc, offset;
+    
+    /*
+     * BC1F cc, offset
+     *  condition <- (FPConditionCode(cc) == 0)
+     *      if condition then
+     *          offset = sign_ext (offset)
+     *          PC = PC + offset
+    */
+    cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
+    offset = insn.getOperand(1).getImm();
+    
+    pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success);
+    if (!success)
+        return false;
+
+    fcsr = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_fcsr_mips64, 0, &success);
+    if (!success)
+        return false;
+
+    /* fcsr[23], fcsr[25-31] are vaild condition bits */
+    fcsr = ((fcsr >> 24) & 0xfe) | ((fcsr >> 23) & 0x01);
+    
+    if ((fcsr & (1 << cc)) == 0)
+        target = pc + offset;
+    else
+        target = pc + 4;
+    
+    Context context;
+
+    if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target))
+        return false;
+
+    return true;
+}
+
+bool
+EmulateInstructionMIPS64::Emulate_BC1T (llvm::MCInst& insn)
+{
+    bool success = false;
+    uint32_t cc, fcsr;
+    int64_t target, pc, offset;
+    
+    /*
+     * BC1T cc, offset
+     *  condition <- (FPConditionCode(cc) != 0)
+     *      if condition then
+     *          offset = sign_ext (offset)
+     *          PC = PC + offset
+    */
+    cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
+    offset = insn.getOperand(1).getImm();
+    
+    pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success);
+    if (!success)
+        return false;
+
+    fcsr = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_fcsr_mips64, 0, &success);
+    if (!success)
+        return false;
+
+    /* fcsr[23], fcsr[25-31] are vaild condition bits */
+    fcsr = ((fcsr >> 24) & 0xfe) | ((fcsr >> 23) & 0x01);
+    
+    if ((fcsr & (1 << cc)) != 0)
+        target = pc + offset;
+    else
+        target = pc + 4;
+    
+    Context context;
+
+    if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target))
+        return false;
+
+    return true;
+}
+
+bool
+EmulateInstructionMIPS64::Emulate_BC1FL (llvm::MCInst& insn)
+{
+    bool success = false;
+    uint32_t cc, fcsr;
+    int64_t target, pc, offset;
+    
+    /*
+     * BC1F cc, offset
+     *  condition <- (FPConditionCode(cc) == 0)
+     *      if condition then
+     *          offset = sign_ext (offset)
+     *          PC = PC + offset
+    */
+    cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
+    offset = insn.getOperand(1).getImm();
+    
+    pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success);
+    if (!success)
+        return false;
+
+    fcsr = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_fcsr_mips64, 0, &success);
+    if (!success)
+        return false;
+
+    /* fcsr[23], fcsr[25-31] are vaild condition bits */
+    fcsr = ((fcsr >> 24) & 0xfe) | ((fcsr >> 23) & 0x01);
+    
+    if ((fcsr & (1 << cc)) == 0)
+        target = pc + offset;
+    else
+        target = pc + 8;    /* skip delay slot */
+    
+    Context context;
+
+    if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target))
+        return false;
+
+    return true;
+}
+
+bool
+EmulateInstructionMIPS64::Emulate_BC1TL (llvm::MCInst& insn)
+{
+    bool success = false;
+    uint32_t cc, fcsr;
+    int64_t target, pc, offset;
+    
+    /*
+     * BC1T cc, offset
+     *  condition <- (FPConditionCode(cc) != 0)
+     *      if condition then
+     *          offset = sign_ext (offset)
+     *          PC = PC + offset
+    */
+    cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
+    offset = insn.getOperand(1).getImm();
+    
+    pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success);
+    if (!success)
+        return false;
+
+    fcsr = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_fcsr_mips64, 0, &success);
+    if (!success)
+        return false;
+
+    /* fcsr[23], fcsr[25-31] are vaild condition bits */
+    fcsr = ((fcsr >> 24) & 0xfe) | ((fcsr >> 23) & 0x01);
+    
+    if ((fcsr & (1 << cc)) != 0)
+        target = pc + offset;
+    else
+        target = pc + 8;    /* skip delay slot */
+    
+    Context context;
+
+    if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target))
+        return false;
+
+    return true;
+}
+
+bool
+EmulateInstructionMIPS64::Emulate_BC1EQZ (llvm::MCInst& insn)
+{
+    bool success = false;
+    uint32_t ft;
+    uint64_t ft_val;
+    int64_t target, pc, offset;
+    
+    /*
+     * BC1EQZ ft, offset
+     *  condition <- (FPR[ft].bit0 == 0)
+     *      if condition then
+     *          offset = sign_ext (offset)
+     *          PC = PC + 4 + offset
+    */
+    ft = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
+    offset = insn.getOperand(1).getImm();
+    
+    pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success);
+    if (!success)
+        return false;
+
+    ft_val = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + ft, 0, &success);
+    if (!success)
+        return false;
+
+    if ((ft_val & 1) == 0)
+        target = pc + 4 + offset;
+    else
+        target = pc + 4;
+    
+    Context context;
+
+    if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target))
+        return false;
+
+    return true;
+}
+
+bool
+EmulateInstructionMIPS64::Emulate_BC1NEZ (llvm::MCInst& insn)
+{
+    bool success = false;
+    uint32_t ft;
+    uint64_t ft_val;
+    int64_t target, pc, offset;
+    
+    /*
+     * BC1NEZ ft, offset
+     *  condition <- (FPR[ft].bit0 != 0)
+     *      if condition then
+     *          offset = sign_ext (offset)
+     *          PC = PC + 4 + offset
+    */
+    ft = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
+    offset = insn.getOperand(1).getImm();
+    
+    pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success);
+    if (!success)
+        return false;
+
+    ft_val = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + ft, 0, &success);
+    if (!success)
+        return false;
+
+    if ((ft_val & 1) != 0)
+        target = pc + 4 + offset;
+    else
+        target = pc + 4;
+    
+    Context context;
+
+    if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target))
+        return false;
+
+    return true;
+}
+
+bool
+EmulateInstructionMIPS64::Emulate_BC1ANY2F (llvm::MCInst& insn)
+{
+    bool success = false;
+    uint32_t cc, fcsr;
+    int64_t target, pc, offset;
+    
+    /*
+     * BC1ANY2F cc, offset
+     *  condition <- (FPConditionCode(cc) == 0 
+     *                  || FPConditionCode(cc+1) == 0)
+     *      if condition then
+     *          offset = sign_ext (offset)
+     *          PC = PC + offset
+    */
+    cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
+    offset = insn.getOperand(1).getImm();
+    
+    pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success);
+    if (!success)
+        return false;
+
+    fcsr = (uint32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_fcsr_mips64, 0, &success);
+    if (!success)
+        return false;
+
+    /* fcsr[23], fcsr[25-31] are vaild condition bits */
+    fcsr = ((fcsr >> 24) & 0xfe) | ((fcsr >> 23) & 0x01);
+
+    /* if any one bit is 0 */
+    if (((fcsr >> cc) & 3) != 3)
+        target = pc + offset;
+    else
+        target = pc + 4;
+    
+    Context context;
+
+    if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target))
+        return false;
+
+    return true;
+}
+
+bool
+EmulateInstructionMIPS64::Emulate_BC1ANY2T (llvm::MCInst& insn)
+{
+    bool success = false;
+    uint32_t cc, fcsr;
+    int64_t target, pc, offset;
+    
+    /*
+     * BC1ANY2T cc, offset
+     *  condition <- (FPConditionCode(cc) == 1 
+     *                  || FPConditionCode(cc+1) == 1)
+     *      if condition then
+     *          offset = sign_ext (offset)
+     *          PC = PC + offset
+    */
+    cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
+    offset = insn.getOperand(1).getImm();
+    
+    pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success);
+    if (!success)
+        return false;
+
+    fcsr = (uint32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_fcsr_mips64, 0, &success);
+    if (!success)
+        return false;
+
+    /* fcsr[23], fcsr[25-31] are vaild condition bits */
+    fcsr = ((fcsr >> 24) & 0xfe) | ((fcsr >> 23) & 0x01);
+
+    /* if any one bit is 1 */
+    if (((fcsr >> cc) & 3) != 0)
+        target = pc + offset;
+    else
+        target = pc + 4;
+    
+    Context context;
+
+    if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target))
+        return false;
+
+    return true;
+}
+
+bool
+EmulateInstructionMIPS64::Emulate_BC1ANY4F (llvm::MCInst& insn)
+{
+    bool success = false;
+    uint32_t cc, fcsr;
+    int64_t target, pc, offset;
+    
+    /*
+     * BC1ANY4F cc, offset
+     *  condition <- (FPConditionCode(cc) == 0 
+     *                  || FPConditionCode(cc+1) == 0)
+     *                  || FPConditionCode(cc+2) == 0)
+     *                  || FPConditionCode(cc+3) == 0)
+     *      if condition then
+     *          offset = sign_ext (offset)
+     *          PC = PC + offset
+    */
+    cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
+    offset = insn.getOperand(1).getImm();
+    
+    pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success);
+    if (!success)
+        return false;
+
+    fcsr = (uint32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_fcsr_mips64, 0, &success);
+    if (!success)
+        return false;
+
+    /* fcsr[23], fcsr[25-31] are vaild condition bits */
+    fcsr = ((fcsr >> 24) & 0xfe) | ((fcsr >> 23) & 0x01);
+
+    /* if any one bit is 0 */
+    if (((fcsr >> cc) & 0xf) != 0xf)
+        target = pc + offset;
+    else
+        target = pc + 4;
+    
+    Context context;
+
+    if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target))
+        return false;
+
+    return true;
+}
+
+bool
+EmulateInstructionMIPS64::Emulate_BC1ANY4T (llvm::MCInst& insn)
+{
+    bool success = false;
+    uint32_t cc, fcsr;
+    int64_t target, pc, offset;
+    
+    /*
+     * BC1ANY4T cc, offset
+     *  condition <- (FPConditionCode(cc) == 1 
+     *                  || FPConditionCode(cc+1) == 1)
+     *                  || FPConditionCode(cc+2) == 1)
+     *                  || FPConditionCode(cc+3) == 1)
+     *      if condition then
+     *          offset = sign_ext (offset)
+     *          PC = PC + offset
+    */
+    cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
+    offset = insn.getOperand(1).getImm();
+    
+    pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success);
+    if (!success)
+        return false;
+
+    fcsr = (uint32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_fcsr_mips64, 0, &success);
+    if (!success)
+        return false;
+
+    /* fcsr[23], fcsr[25-31] are vaild condition bits */
+    fcsr = ((fcsr >> 24) & 0xfe) | ((fcsr >> 23) & 0x01);
+
+    /* if any one bit is 1 */
+    if (((fcsr >> cc) & 0xf) != 0)
+        target = pc + offset;
+    else
+        target = pc + 4;
+    
+    Context context;
+
+    if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target))
+        return false;
+
+    return true;
+}

source/Plugins/Process/Linux/NativeProcessLinux.cpp

if (breakpoint_size > 0)
         // Do not allow breakpoint probe to wrap around.
         if (breakpoint_addr >= breakpoint_size)
             breakpoint_addr -= breakpoint_size;
     }
 
     // Check if we stopped because of a breakpoint.
     NativeBreakpointSP breakpoint_sp;
     error = m_breakpoint_list.GetBreakpoint (breakpoint_addr, breakpoint_sp);
+
+#if defined (__mips__)
+    /*
+     * The breakpoint might be in a delay slot. In this case PC points
+     * to the delayed branch instruction rather then the instruction
+     * in the delay slot. If the CAUSE.BD flag is set then adjust the 
+     * PC based on the size of the branch instruction.
+    */
+    const RegisterInfo *cause_reg_info = context_sp->GetRegisterInfoByName ("cause");
+    uint32_t cause = context_sp->ReadRegisterAsUnsigned (cause_reg_info, 0);
+    if ((!error.Success () || !breakpoint_sp) && (cause >> 31))
+    {
+        uint64_t branch_delay = 0;
+        if (log)
+            log->Printf ("NativeProcessLinux::%s MIPS cause register 0x%" PRIx32, __FUNCTION__, cause);
+        branch_delay = 4;   // FIXME - Adjust according to size of branch instruction at PC
+        breakpoint_addr = initial_pc_addr + branch_delay;
+        error = m_breakpoint_list.GetBreakpoint (breakpoint_addr, breakpoint_sp);
+    }
+#endif
+
     if (!error.Success () || !breakpoint_sp)
     {
         // We didn't find one at a software probe location.  Nothing to do.
         if (log)
             log->Printf ("NativeProcessLinux::%s pid %" PRIu64 " no lldb breakpoint found at current pc with adjustment: 0x%" PRIx64, __FUNCTION__, GetID (), breakpoint_addr);
         return Error ();
     }