Refactor: Simplify boolean conditional return statements in lib/Target/Arm

[LegalizeAdulthood]

Summary

Use clang-tidy to simplify boolean conditional return statements.

[craig.topper]

lib/Target/ARM/ARMFrameLowering.cpp

111–112

This should really be aligned right after the opening parenthese on the previous line. That's really probably true of many of these patches, but it looks particularly bad here.

lib/Target/ARM/ARMISelLowering.cpp

5127

Push negate through

5160

Push negate through

10449–10450

Push negate through and use != and &&. Align second line after the return.

lib/Target/ARM/AsmParser/ARMAsmParser.cpp

1263 ↗

(On Diff #26406)

Push the negate through this expression and all the similar ones below.

[LegalizeAdulthood]

lib/Target/ARM/ARMFrameLowering.cpp

111–112

Fixed.

I forgot to run clang-format on these before posting them; I'm doing that now.

lib/Target/ARM/ARMISelLowering.cpp

5127

Fixed.

5160

Fixed.

10449–10450

Fixed.

lib/Target/ARM/AsmParser/ARMAsmParser.cpp

1263 ↗

(On Diff #26406)

Fixed.

[LegalizeAdulthood]

Update from comments, clang-format

[LegalizeAdulthood]

Update to latest

lib/Target/ARM/ARMBaseInstrInfo.cpp

 }
 
 bool ARMBaseInstrInfo::isSwiftFastImmShift(const MachineInstr *MI) const {
   if (MI->getNumOperands() < 4)
     return true;
   unsigned ShOpVal = MI->getOperand(3).getImm();
   unsigned ShImm = ARM_AM::getSORegOffset(ShOpVal);
   // Swift supports faster shifts for: lsl 2, lsl 1, and lsr 1.
-  if ((ShImm == 1 && ARM_AM::getSORegShOp(ShOpVal) == ARM_AM::lsr) ||
+  return (ShImm == 1 && ARM_AM::getSORegShOp(ShOpVal) == ARM_AM::lsr) ||
          ((ShImm == 1 || ShImm == 2) &&
-       ARM_AM::getSORegShOp(ShOpVal) == ARM_AM::lsl))
-    return true;
-
-  return false;
+          ARM_AM::getSORegShOp(ShOpVal) == ARM_AM::lsl);
 }
 
 bool ARMBaseInstrInfo::getRegSequenceLikeInputs(
     const MachineInstr &MI, unsigned DefIdx,
     SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const {
   assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");
   assert(MI.isRegSequenceLike() && "Invalid kind of instruction");
 

lib/Target/ARM/ARMBaseRegisterInfo.cpp

bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
   // reserve a Base Pointer.
   if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) {
     // Conservatively estimate whether the negative offset from the frame
     // pointer will be sufficient to reach. If a function has a smallish
     // frame, it's less likely to have lots of spills and callee saved
     // space, so it's all more likely to be within range of the frame pointer.
     // If it's wrong, the scavenger will still enable access to work, it just
     // won't be optimal.
-    if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128)
-      return false;
-    return true;
+    return !(AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128);
   }
 
   return false;
 }
 
 bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
   const MachineRegisterInfo *MRI = &MF.getRegInfo();
   const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
   // immediate.
   if ((Offset & (Scale-1)) != 0)
     return false;
 
   if (isSigned && Offset < 0)
     Offset = -Offset;
 
   unsigned Mask = (1 << NumBits) - 1;
-  if ((unsigned)Offset <= Mask * Scale)
-    return true;
-
-  return false;
+  return (unsigned)Offset <= Mask * Scale;
 }
 
 void
 ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
                                          int SPAdj, unsigned FIOperandNum,
                                          RegScavenger *RS) const {
   MachineInstr &MI = *II;
   MachineBasicBlock &MBB = *MI.getParent();

lib/Target/ARM/ARMFrameLowering.cpp

static bool isCSRestore(MachineInstr *MI,
   // Integer spill area is handled with "pop".
   if (isPopOpcode(MI->getOpcode())) {
     // The first two operands are predicates. The last two are
     // imp-def and imp-use of SP. Check everything in between.
     for (int i = 5, e = MI->getNumOperands(); i != e; ++i)
       if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs))
         return false;
     return true;
   }
-  if ((MI->getOpcode() == ARM::LDR_POST_IMM ||
+  return (MI->getOpcode() == ARM::LDR_POST_IMM ||
           MI->getOpcode() == ARM::LDR_POST_REG ||
           MI->getOpcode() == ARM::t2LDR_POST) &&
          isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs) &&
-      MI->getOperand(1).getReg() == ARM::SP)
-    return true;
-
-  return false;
+         MI->getOperand(1).getReg() == ARM::SP;
 }
 
 static void emitRegPlusImmediate(bool isARM, MachineBasicBlock &MBB,
                                  MachineBasicBlock::iterator &MBBI, DebugLoc dl,
                                  const ARMBaseInstrInfo &TII, unsigned DestReg,
                                  unsigned SrcReg, int NumBytes,
                                  unsigned MIFlags = MachineInstr::NoFlags,
                                  ARMCC::CondCodes Pred = ARMCC::AL,

lib/Target/ARM/ARMISelLowering.cpp

 }
 
 bool ARMTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
   if (!Subtarget->supportsTailCall())
     return false;
 
   auto Attr =
       CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
-  if (!CI->isTailCall() || Attr.getValueAsString() == "true")
-    return false;
-
-  return true;
+  return !(!CI->isTailCall() || Attr.getValueAsString() == "true");
 }
 
 // Trying to write a 64 bit value so need to split into two 32 bit values first,
 // and pass the lower and high parts through.
 static SDValue LowerWRITE_REGISTER(SDValue Op, SelectionDAG &DAG) {
   SDLoc DL(Op);
   SDValue WriteValue = Op->getOperand(2);
 
for (unsigned j = 0; j < NumElts; ++j) {
         return false;
     }
   }
 
   if (M.size() == NumElts*2)
     WhichResult = 0;
 
   // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
-  if (VT.is64BitVector() && EltSz == 32)
-    return false;
-
-  return true;
+  return !(VT.is64BitVector() && EltSz == 32);
 }
 
 /// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of
 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
 static bool isVUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
   unsigned EltSz = VT.getVectorElementType().getSizeInBits();
   if (EltSz == 64)
for (unsigned j = 0; j < NumElts; j += Half) {
       }
     }
   }
 
   if (M.size() == NumElts*2)
     WhichResult = 0;
 
   // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
-  if (VT.is64BitVector() && EltSz == 32)
-    return false;
-
-  return true;
+  return !(VT.is64BitVector() && EltSz == 32);
 }
 
 // Checks whether the shuffle mask represents a vector zip (VZIP) by checking
 // that pairs of elements of the shufflemask represent the same index in each
 // vector incrementing sequentially through the vectors.
 // e.g. For v1,v2 of type v4i32 a valid shuffle mask is: [0, 4, 1, 5]
 //  v1={a,b,c,d} => x=shufflevector v1, v2 shufflemask => x={a,e,b,f}
 //  v2={e,f,g,h}
for (unsigned j = 0; j < NumElts; j += 2) {
       Idx += 1;
     }
   }
 
   if (M.size() == NumElts*2)
     WhichResult = 0;
 
   // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
-  if (VT.is64BitVector() && EltSz == 32)
-    return false;
-
-  return true;
+  return !(VT.is64BitVector() && EltSz == 32);
 }
 
 /// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of
 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
 static bool isVZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
   unsigned EltSz = VT.getVectorElementType().getSizeInBits();
   if (EltSz == 64)
for (unsigned j = 0; j < NumElts; j += 2) {
       Idx += 1;
     }
   }
 
   if (M.size() == NumElts*2)
     WhichResult = 0;
 
   // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
-  if (VT.is64BitVector() && EltSz == 32)
-    return false;
-
-  return true;
+  return !(VT.is64BitVector() && EltSz == 32);
 }
 
 /// Check if \p ShuffleMask is a NEON two-result shuffle (VZIP, VUZP, VTRN),
 /// and return the corresponding ARMISD opcode if it is, or 0 if it isn't.
 static unsigned isNEONTwoResultShuffleMask(ArrayRef<int> ShuffleMask, EVT VT,
                                            unsigned &WhichResult,
                                            bool &isV_UNDEF) {
   isV_UNDEF = false;
bool ARMTargetLowering::isVectorLoadExtDesirable(SDValue ExtVal) const {
   // instruction.
   // If there's more than one user instruction, the loadext is desirable no
   // matter what.  There can be two uses by the same instruction.
   if (ExtVal->use_empty() ||
       !ExtVal->use_begin()->isOnlyUserOf(ExtVal.getNode()))
     return true;
 
   SDNode *U = *ExtVal->use_begin();
-  if ((U->getOpcode() == ISD::ADD || U->getOpcode() == ISD::SUB ||
-       U->getOpcode() == ISD::SHL || U->getOpcode() == ARMISD::VSHL))
-    return false;
-
-  return true;
+  return !(U->getOpcode() == ISD::ADD || U->getOpcode() == ISD::SUB ||
+           U->getOpcode() == ISD::SHL || U->getOpcode() == ARMISD::VSHL);
 }
 
 bool ARMTargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
   if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
     return false;
 
   if (!isTypeLegal(EVT::getEVT(Ty1)))
     return false;

 
 /// \brief Returns true if it is beneficial to convert a load of a constant
 /// to just the constant itself.
 bool ARMTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
                                                           Type *Ty) const {
   assert(Ty->isIntegerTy());
 
   unsigned Bits = Ty->getPrimitiveSizeInBits();
-  if (Bits == 0 || Bits > 32)
-    return false;
-  return true;
+  return !(Bits == 0 || Bits > 32);
 }
 
 Instruction* ARMTargetLowering::makeDMB(IRBuilder<> &Builder,
                                         ARM_MB::MemBOpt Domain) const {
   Module *M = Builder.GetInsertBlock()->getParent()->getParent();
 
   // First, if the target has no DMB, see what fallback we can use.
   if (!Subtarget->hasDataBarrier()) {

lib/Target/ARM/ARMSubtarget.cpp

ARMSubtarget::GVIsIndirectSymbol(const GlobalValue *GV,
                                  Reloc::Model RelocM) const {
   if (RelocM == Reloc::Static)
     return false;
 
   bool isDef = GV->isStrongDefinitionForLinker();
 
   if (!isTargetMachO()) {
     // Extra load is needed for all externally visible.
-    if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
-      return false;
-    return true;
+    return !(GV->hasLocalLinkage() || GV->hasHiddenVisibility());
   } else {
     // If this is a strong reference to a definition, it is definitely not
     // through a stub.
     if (isDef)
       return false;
 
     // Unless we have a symbol with hidden visibility, we have to go through a
     // normal $non_lazy_ptr stub because this symbol might be resolved late.