[RISCV] fixes cross unwinding failure

[kamleshbhalui]

Summary

https://reviews.llvm.org/D80690 This introduced build failure when LIBUNWIND_ENABLE_CROSS_UNWINDING enabled.
This patch fixes that.

[compnerd]

Ah right, the !RISCV -> RISCV case. This makes sense to commit to fix the immediate issue.

Thinking about this more, ILP32 is not permitted on RISC-V 64 and ILP-64 is not permitted on RISC-V 32 (which for some reason I had backwards). I think that it would make sense to avoid using RISC-V macros entirely and use __SIZEOF_POINTER__ to select the register width (__SIZEOF_POINTER__ == 8 would mean that we should use uint64_t and a value of 4 would indicate uint32_t). Furthermore, we could then replace the use of __riscv_flen with __SIZEOF_DOUBLE__ to select between float and double for the fpret_t rather than the __riscv_flen. That would completely alleviate having to have 4 different configurations to worry about - {native, x-unwind} * {defined, undefined}.

libunwind/src/Registers.hpp

 }
 #endif // _LIBUNWIND_TARGET_HEXAGON
 
 
 #if defined(_LIBUNWIND_TARGET_RISCV)
 /// Registers_riscv holds the register state of a thread in a RISC-V
 /// process.
 
-# if __riscv_xlen == 32
+// This check makes it safe when LIBUNWIND_ENABLE_CROSS_UNWINDING enabled.
+# ifdef __riscv
+#  if __riscv_xlen == 32
 typedef uint32_t reg_t;
-# elif __riscv_xlen == 64
+#  elif __riscv_xlen == 64
 typedef uint64_t reg_t;
-# else
-#  error "Unsupported __riscv_xlen"
-# endif
+#  else
+#   error "Unsupported __riscv_xlen"
+#  endif
 
-# if defined(__riscv_flen)
-#  if __riscv_flen == 64
+#  if defined(__riscv_flen)
+#   if __riscv_flen == 64
 typedef double fp_t;
-#  elif __riscv_flen == 32
+#   elif __riscv_flen == 32
 typedef float fp_t;
-#  else
-#   error "Unsupported __riscv_flen"
-#  endif
-# else
+#   else
+#    error "Unsupported __riscv_flen"
+#   endif
+#  else
 // This is just for supressing undeclared error of fp_t.
 typedef double fp_t;
-# endif
+#  endif
+# else
+// Use Max possible width when cross unwinding
+typedef uint64_t reg_t;
+typedef double fp_t;
+# define __riscv_xlen 64
+# define __riscv_flen 64
+#endif
 
 /// Registers_riscv holds the register state of a thread.
 class _LIBUNWIND_HIDDEN Registers_riscv {
 public:
   Registers_riscv();
   Registers_riscv(const void *registers);
 
   bool        validRegister(int num) const;