[AMDGPU] Remove SI_MASK_BRANCH

[ruiling]

Summary

This is already deprecated, so remove code working on this.
Also update the tests by using S_CBRANCH_EXECZ instead of SI_MASK_BRANCH.
The tests to specifically test the insert-skip feature are not valid
anymore, so just remove them.

[arsenm]

llvm/lib/Target/AMDGPU/SIInsertSkips.cpp

213

If SIInsertSkips is no longer inserting skips, it needs a new name

[ruiling]

I find it is not a good idea to remove the tests. So I adjust the lit-test to make sure RemoveShortExecBranches works correctly.

[ruiling]

llvm/lib/Target/AMDGPU/SIInsertSkips.cpp

213

I don't have good idea on that. I am happy if some one could came up with a good name. And I believe that should be in a separate patch. This patch just aims to remove "SI_MASK_BRANCH".

[critson]

I agree with renaming being a follow up patch.
I wonder if this entire pass could be merged with SIRemoveShortExecBranches and the result renamed SILateBranchLowering?

[ruiling]

ping, anybody would like to take a look?

[foad]

LGTM, with renaming or moving the pass as a follow-up.

llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp

void AMDGPUAsmPrinter::emitInstruction(const MachineInstr *MI) {
   if (MI->isBundle()) {
     const MachineBasicBlock *MBB = MI->getParent();
     MachineBasicBlock::const_instr_iterator I = ++MI->getIterator();
     while (I != MBB->instr_end() && I->isInsideBundle()) {
       emitInstruction(&*I);
       ++I;
     }
   } else {
-    // We don't want SI_MASK_BRANCH/SI_RETURN_TO_EPILOG encoded. They are
+    // We don't want these pseudo instructions encoded. They are
     // placeholder terminator instructions and should only be printed as
     // comments.
-    if (MI->getOpcode() == AMDGPU::SI_MASK_BRANCH) {
-      if (isVerbose()) {
-        SmallVector<char, 16> BBStr;
-        raw_svector_ostream Str(BBStr);
-
-        const MachineBasicBlock *MBB = MI->getOperand(0).getMBB();
-        const MCSymbolRefExpr *Expr
-          = MCSymbolRefExpr::create(MBB->getSymbol(), OutContext);
-        Expr->print(Str, MAI);
-        OutStreamer->emitRawComment(Twine(" mask branch ") + BBStr);
-      }
-
-      return;
-    }
-
     if (MI->getOpcode() == AMDGPU::SI_RETURN_TO_EPILOG) {
       if (isVerbose())
         OutStreamer->emitRawComment(" return to shader part epilog");
       return;
     }
 
     if (MI->getOpcode() == AMDGPU::WAVE_BARRIER) {
       if (isVerbose())

llvm/lib/Target/AMDGPU/SIInsertSkips.cpp

 //===-- SIInsertSkips.cpp - Use predicates for control flow ---------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 /// \file
-/// This pass inserts branches on the 0 exec mask over divergent branches
-/// branches when it's expected that jumping over the untaken control flow will
-/// be cheaper than having every workitem no-op through it.
+/// This pass mainly lowers early terminate pseudo instructions.
 //
 //===----------------------------------------------------------------------===//
 
 #include "AMDGPU.h"
 #include "GCNSubtarget.h"
 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
 #include "llvm/ADT/DepthFirstIterator.h"
 #include "llvm/CodeGen/MachineDominators.h"
 #include "llvm/InitializePasses.h"
 
 using namespace llvm;
 
 #define DEBUG_TYPE "si-insert-skips"
 
-static cl::opt<unsigned> SkipThresholdFlag(
-  "amdgpu-skip-threshold-legacy",
-  cl::desc("Number of instructions before jumping over divergent control flow"),
-  cl::init(12), cl::Hidden);
-
 namespace {
 
 class SIInsertSkips : public MachineFunctionPass {
 private:
   const SIRegisterInfo *TRI = nullptr;
   const SIInstrInfo *TII = nullptr;
-  unsigned SkipThreshold = 0;
   MachineDominatorTree *MDT = nullptr;
 
   MachineBasicBlock *EarlyExitBlock = nullptr;
   bool EarlyExitClearsExec = false;
 
-  bool shouldSkip(const MachineBasicBlock &From,
-                  const MachineBasicBlock &To) const;
-
   void ensureEarlyExitBlock(MachineBasicBlock &MBB, bool ClearExec);
 
   void earlyTerm(MachineInstr &MI);
 
-  bool skipMaskBranch(MachineInstr &MI, MachineBasicBlock &MBB);
-
 public:
   static char ID;
 
   unsigned MovOpc;
   Register ExecReg;
 
   SIInsertSkips() : MachineFunctionPass(ID) {}
 
INITIALIZE_PASS_END(SIInsertSkips, DEBUG_TYPE,
                     "SI insert s_cbranch_execz instructions", false, false)
 
 char &llvm::SIInsertSkipsPassID = SIInsertSkips::ID;
 
 static bool opcodeEmitsNoInsts(const MachineInstr &MI) {
   if (MI.isMetaInstruction())
     return true;
 
-  // Handle target specific opcodes.
-  switch (MI.getOpcode()) {
-  case AMDGPU::SI_MASK_BRANCH:
-    return true;
-  default:
-    return false;
-  }
-}
-
-bool SIInsertSkips::shouldSkip(const MachineBasicBlock &From,
-                               const MachineBasicBlock &To) const {
-  unsigned NumInstr = 0;
-  const MachineFunction *MF = From.getParent();
-
-  for (MachineFunction::const_iterator MBBI(&From), ToI(&To), End = MF->end();
-       MBBI != End && MBBI != ToI; ++MBBI) {
-    const MachineBasicBlock &MBB = *MBBI;
-
-    for (MachineBasicBlock::const_iterator I = MBB.begin(), E = MBB.end();
-         NumInstr < SkipThreshold && I != E; ++I) {
-      if (opcodeEmitsNoInsts(*I))
-        continue;
-
-      // FIXME: Since this is required for correctness, this should be inserted
-      // during SILowerControlFlow.
-
-      // When a uniform loop is inside non-uniform control flow, the branch
-      // leaving the loop might be an S_CBRANCH_VCCNZ, which is never taken
-      // when EXEC = 0. We should skip the loop lest it becomes infinite.
-      if (I->getOpcode() == AMDGPU::S_CBRANCH_VCCNZ ||
-          I->getOpcode() == AMDGPU::S_CBRANCH_VCCZ)
-        return true;
-
-      if (TII->hasUnwantedEffectsWhenEXECEmpty(*I))
-        return true;
-
-      // These instructions are potentially expensive even if EXEC = 0.
-      if (TII->isSMRD(*I) || TII->isVMEM(*I) || TII->isFLAT(*I) ||
-          I->getOpcode() == AMDGPU::S_WAITCNT)
-        return true;
-
-      ++NumInstr;
-      if (NumInstr >= SkipThreshold)
-        return true;
-    }
-  }
-
   return false;
 }
 
 static void generateEndPgm(MachineBasicBlock &MBB,
                            MachineBasicBlock::iterator I, DebugLoc DL,
                            const SIInstrInfo *TII, bool IsPS) {
   // "null export"
   if (IsPS) {
void SIInsertSkips::earlyTerm(MachineInstr &MI) {
 
   if (Next != MBB.end() && !Next->isTerminator())
     splitBlock(MBB, *BranchMI, MDT);
 
   MBB.addSuccessor(EarlyExitBlock);
   MDT->getBase().insertEdge(&MBB, EarlyExitBlock);
 }
 
-// Returns true if a branch over the block was inserted.
-bool SIInsertSkips::skipMaskBranch(MachineInstr &MI,
-                                   MachineBasicBlock &SrcMBB) {
-  MachineBasicBlock *DestBB = MI.getOperand(0).getMBB();
-
-  if (!shouldSkip(**SrcMBB.succ_begin(), *DestBB))
-    return false;
-
-  const DebugLoc &DL = MI.getDebugLoc();
-  MachineBasicBlock::iterator InsPt = std::next(MI.getIterator());
-
-  BuildMI(SrcMBB, InsPt, DL, TII->get(AMDGPU::S_CBRANCH_EXECZ))
-    .addMBB(DestBB);
-
-  return true;
-}
-
 bool SIInsertSkips::runOnMachineFunction(MachineFunction &MF) {
   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
   TII = ST.getInstrInfo();
   TRI = &TII->getRegisterInfo();
   MDT = &getAnalysis<MachineDominatorTree>();
-  SkipThreshold = SkipThresholdFlag;
 
   MovOpc = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64;
   ExecReg = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
 
   SmallVector<MachineInstr *, 4> EarlyTermInstrs;
   bool MadeChange = false;
 
   for (MachineBasicBlock &MBB : MF) {
     MachineBasicBlock::iterator I, Next;
     for (I = MBB.begin(); I != MBB.end(); I = Next) {
       Next = std::next(I);
       MachineInstr &MI = *I;
 
       switch (MI.getOpcode()) {
-      case AMDGPU::SI_MASK_BRANCH:
-        MadeChange |= skipMaskBranch(MI, MBB);
-        break;
-
       case AMDGPU::S_BRANCH:
         // Optimize out branches to the next block.
         // FIXME: Shouldn't this be handled by BranchFolding?
         if (MBB.isLayoutSuccessor(MI.getOperand(0).getMBB())) {
           assert(&MI == &MBB.back());
           MI.eraseFromParent();
           MadeChange = true;
         }

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

bool SIInstrInfo::analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
                                 bool AllowModify) const {
   MachineBasicBlock::iterator I = MBB.getFirstTerminator();
   auto E = MBB.end();
   if (I == E)
     return false;
 
   // Skip over the instructions that are artificially terminators for special
   // exec management.
-  while (I != E && !I->isBranch() && !I->isReturn() &&
-         I->getOpcode() != AMDGPU::SI_MASK_BRANCH) {
+  while (I != E && !I->isBranch() && !I->isReturn()) {
     switch (I->getOpcode()) {
-    case AMDGPU::SI_MASK_BRANCH:
     case AMDGPU::S_MOV_B64_term:
     case AMDGPU::S_XOR_B64_term:
     case AMDGPU::S_OR_B64_term:
     case AMDGPU::S_ANDN2_B64_term:
     case AMDGPU::S_AND_B64_term:
     case AMDGPU::S_MOV_B32_term:
     case AMDGPU::S_XOR_B32_term:
     case AMDGPU::S_OR_B32_term:
while (I != E && !I->isBranch() && !I->isReturn()) {
     }
 
     ++I;
   }
 
   if (I == E)
     return false;
 
-  if (I->getOpcode() != AMDGPU::SI_MASK_BRANCH)
-    return analyzeBranchImpl(MBB, I, TBB, FBB, Cond, AllowModify);
-
-  ++I;
-
-  // TODO: Should be able to treat as fallthrough?
-  if (I == MBB.end())
-    return true;
-
-  if (analyzeBranchImpl(MBB, I, TBB, FBB, Cond, AllowModify))
-    return true;
-
-  MachineBasicBlock *MaskBrDest = I->getOperand(0).getMBB();
-
-  // Specifically handle the case where the conditional branch is to the same
-  // destination as the mask branch. e.g.
-  //
-  // si_mask_branch BB8
-  // s_cbranch_execz BB8
-  // s_cbranch BB9
-  //
-  // This is required to understand divergent loops which may need the branches
-  // to be relaxed.
-  if (TBB != MaskBrDest || Cond.empty())
-    return true;
-
-  auto Pred = Cond[0].getImm();
-  return (Pred != EXECZ && Pred != EXECNZ);
 }
 
 unsigned SIInstrInfo::removeBranch(MachineBasicBlock &MBB,
                                    int *BytesRemoved) const {
   MachineBasicBlock::iterator I = MBB.getFirstTerminator();
 
   unsigned Count = 0;
   unsigned RemovedSize = 0;
   while (I != MBB.end()) {
     MachineBasicBlock::iterator Next = std::next(I);
-    if (I->getOpcode() == AMDGPU::SI_MASK_BRANCH) {
-      I = Next;
-      continue;
-    }
-
     RemovedSize += getInstSizeInBytes(*I);
     I->eraseFromParent();
     ++Count;
     I = Next;
   }
 
   if (BytesRemoved)
     *BytesRemoved = RemovedSize;

llvm/lib/Target/AMDGPU/SIInstructions.td

def WAVE_BARRIER : SPseudoInstSI<(outs), (ins),
   let isConvergent = 1;
   let FixedSize = 1;
   let Size = 0;
 }
 
 // SI pseudo instructions. These are used by the CFG structurizer pass
 // and should be lowered to ISA instructions prior to codegen.
 
-// Dummy terminator instruction to use after control flow instructions
-// replaced with exec mask operations.
-def SI_MASK_BRANCH : VPseudoInstSI <
-  (outs), (ins brtarget:$target)> {
-  let isBranch = 0;
-  let isTerminator = 1;
-  let isBarrier = 0;
-  let SchedRW = [];
-  let hasNoSchedulingInfo = 1;
-  let FixedSize = 1;
-  let Size = 0;
-}
-
 let isTerminator = 1 in {
 
 let OtherPredicates = [EnableLateCFGStructurize] in {
  def SI_NON_UNIFORM_BRCOND_PSEUDO : CFPseudoInstSI <
   (outs),
   (ins SReg_1:$vcc, brtarget:$target),
   [(brcond i1:$vcc, bb:$target)]> {
     let Size = 12;

llvm/test/CodeGen/AMDGPU/coalescer-extend-pruned-subrange.mir

bb.1:
     S_ENDPGM 0
 
   bb.2:
     successors: %bb.3, %bb.4
     %19:sreg_64 = V_CMP_EQ_U32_e64 1, %7, implicit $exec
     %20:sreg_64 = COPY $exec, implicit-def $exec
     %21:sreg_64 = S_AND_B64 %20, %19, implicit-def dead $scc
     $exec = S_MOV_B64_term %21
-    SI_MASK_BRANCH %bb.4, implicit $exec
+    S_CBRANCH_EXECZ %bb.4, implicit $exec
     S_BRANCH %bb.3
 
   bb.3:
     successors: %bb.4
     undef %22.sub0:sgpr_128 = COPY %8
     %22.sub1:sgpr_128 = COPY %8
     %22.sub2:sgpr_128 = COPY %8
     %23:sgpr_128 = COPY %22
bb.7:
     successors: %bb.8, %bb.10
     %25:vgpr_32 = V_AND_B32_e32 target-flags(amdgpu-gotprel32-hi) 1, %10.sub2, implicit $exec
     %26:sreg_64 = V_CMP_EQ_U32_e64 1, %25, implicit $exec
     %27:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
     %28:vgpr_32 = COPY %27
     %29:sreg_64 = COPY $exec, implicit-def $exec
     %30:sreg_64 = S_AND_B64 %29, %26, implicit-def dead $scc
     $exec = S_MOV_B64_term %30
-    SI_MASK_BRANCH %bb.10, implicit $exec
+    S_CBRANCH_EXECZ %bb.10, implicit $exec
     S_BRANCH %bb.8
 
   bb.8:
     successors: %bb.10
     %31:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN undef %32:vgpr_32, undef %33:sgpr_128, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from constant-pool, align 1, addrspace 4)
     %34:sreg_64_xexec = V_CMP_NE_U32_e64 0, %31, implicit $exec
     %35:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, -1, %34, implicit $exec
     %28:vgpr_32 = COPY %35

llvm/test/CodeGen/AMDGPU/coalescer-subranges-another-prune-error.mir

bb.4:
     %39:vreg_128 = IMPLICIT_DEF
     %40:vgpr_32 = IMPLICIT_DEF
     %41:vgpr_32 = COPY killed %35
     %42:vgpr_32 = COPY killed %34
     %43:sreg_64 = COPY $exec, implicit-def $exec
     %44:sreg_64 = S_AND_B64 %43, %30, implicit-def dead $scc
     %45:sreg_64 = S_XOR_B64 %44, %43, implicit-def dead $scc
     $exec = S_MOV_B64_term killed %44
-    SI_MASK_BRANCH %bb.9, implicit $exec
+    S_CBRANCH_EXECZ %bb.9, implicit $exec
     S_BRANCH %bb.8
 
   bb.5:
     successors: %bb.9(0x80000000)
     $exec = S_OR_B64 $exec, %46, implicit-def $scc
     %47:vgpr_32 = COPY killed %48
     %49:vgpr_32 = COPY killed %50
     %51:vreg_128 = COPY killed %52
bb.6:
     successors: %bb.7(0x40000000), %bb.13(0x40000000)
     $exec = S_OR_B64 $exec, killed %60, implicit-def $scc
     %61:sreg_64 = V_CMP_NE_U32_e64 0, killed %62, implicit $exec
     %63:vreg_128 = COPY killed %64
     %65:vgpr_32 = COPY killed %66
     %67:sreg_64 = COPY $exec, implicit-def $exec
     %68:sreg_64 = S_AND_B64 %67, %61, implicit-def dead $scc
     $exec = S_MOV_B64_term killed %68
-    SI_MASK_BRANCH %bb.13, implicit $exec
+    S_CBRANCH_EXECZ %bb.13, implicit $exec
     S_BRANCH %bb.7
 
   bb.7:
     successors: %bb.13(0x80000000)
     %69:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec
     %70:vreg_128 = COPY killed %33
     %63:vreg_128 = COPY killed %70
     %65:vgpr_32 = COPY killed %69
bb.12:
     %54:vreg_128 = COPY killed %23
     %52:vreg_128 = IMPLICIT_DEF
     %50:vgpr_32 = IMPLICIT_DEF
     %48:vgpr_32 = COPY killed %88
     %89:sreg_64 = COPY $exec, implicit-def $exec
     %90:sreg_64 = S_AND_B64 %89, %87, implicit-def dead $scc
     %46:sreg_64 = S_XOR_B64 %90, %89, implicit-def dead $scc
     $exec = S_MOV_B64_term killed %90
-    SI_MASK_BRANCH %bb.5, implicit $exec
+    S_CBRANCH_EXECZ %bb.5, implicit $exec
     S_BRANCH %bb.15
 
   bb.13:
     successors: %bb.14(0x40000000), %bb.16(0x40000000)
     $exec = S_OR_B64 $exec, killed %67, implicit-def $scc
     %91:vgpr_32 = COPY killed %65
     %92:vreg_128 = COPY killed %63
     %93:sreg_64 = V_CMP_NE_U32_e64 0, killed %91, implicit $exec
     %94:vreg_128 = COPY killed %78
     %95:sreg_64 = COPY $exec, implicit-def $exec
     %96:sreg_64 = S_AND_B64 %95, %93, implicit-def dead $scc
     $exec = S_MOV_B64_term killed %96
-    SI_MASK_BRANCH %bb.16, implicit $exec
+    S_CBRANCH_EXECZ %bb.16, implicit $exec
     S_BRANCH %bb.14
 
   bb.14:
     successors: %bb.16(0x80000000)
     %97:vreg_128 = COPY killed %92
     %94:vreg_128 = COPY killed %97
     S_BRANCH %bb.16
 

llvm/test/CodeGen/AMDGPU/coalescer-subregjoin-fullcopy.mir

bb.6:
     %18:sreg_64 = S_AND_B64 killed %17, killed %14, implicit-def dead $scc
     %19:sreg_64 = COPY %10
     %20:vreg_128 = COPY %13
     %21:vreg_128 = IMPLICIT_DEF
     %22:sreg_64 = COPY $exec, implicit-def $exec
     %23:sreg_64 = S_AND_B64 %22, %18, implicit-def dead $scc
     %24:sreg_64 = S_XOR_B64 %23, %22, implicit-def dead $scc
     $exec = S_MOV_B64_term killed %23
-    SI_MASK_BRANCH %bb.7, implicit $exec
+    S_CBRANCH_EXECZ %bb.7, implicit $exec
     S_BRANCH %bb.18
 
   bb.7:
     successors: %bb.6(0x40000000), %bb.8(0x40000000)
     $exec = S_OR_B64 $exec, %24, implicit-def $scc
     %25:vreg_128 = COPY killed %21
     %26:vreg_128 = COPY killed %20
     %27:sreg_64 = COPY killed %19

llvm/test/CodeGen/AMDGPU/coalescer-with-subregs-bad-identical.mir

bb.4:
     %18:vgpr_32 = nofpexcept V_MIN_F32_e32 1065353216, killed %17, implicit $mode, implicit $exec
     %19:sreg_64_xexec = nofpexcept V_CMP_NEQ_F32_e64 0, 1065353216, 0, killed %18, 0, implicit $mode, implicit $exec
     %20:vgpr_32 = V_MOV_B32_e32 2143289344, implicit $exec
     %21:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, killed %20, killed %19, implicit $exec
     %22:sreg_64 = nofpexcept V_CMP_LT_F32_e64 0, 0, 0, killed %21, 0, implicit $mode, implicit $exec
     %23:sreg_64 = COPY $exec, implicit-def $exec
     %24:sreg_64 = S_AND_B64 %23, %22, implicit-def dead $scc
     $exec = S_MOV_B64_term killed %24
-    SI_MASK_BRANCH %bb.7, implicit $exec
+    S_CBRANCH_EXECZ %bb.7, implicit $exec
     S_BRANCH %bb.5
 
   bb.5:
     successors: %bb.7(0x80000000)
     S_BRANCH %bb.7
 
   bb.6:
     successors: %bb.8(0x40000000), %bb.10(0x40000000)
bb.14:
     %43:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM undef %44:sgpr_128, 12, 0, 0 :: (dereferenceable invariant load 4)
     %45:vgpr_32 = V_MUL_LO_I32_e64 killed %42, killed %43, implicit $exec
     %46:vgpr_32 = V_LSHLREV_B32_e32 2, killed %45, implicit $exec
     %47:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN killed %46, undef %48:sgpr_128, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from constant-pool, align 1, addrspace 4)
     %49:sreg_64 = V_CMP_NE_U32_e64 0, killed %47, implicit $exec
     %50:sreg_64 = COPY $exec, implicit-def $exec
     %51:sreg_64 = S_AND_B64 %50, %49, implicit-def dead $scc
     $exec = S_MOV_B64_term killed %51
-    SI_MASK_BRANCH %bb.16, implicit $exec
+    S_CBRANCH_EXECZ %bb.16, implicit $exec
     S_BRANCH %bb.15
 
   bb.15:
     successors: %bb.16(0x80000000)
 
   bb.16:
     successors: %bb.17(0x80000000)
     $exec = S_OR_B64 $exec, killed %50, implicit-def $scc

llvm/test/CodeGen/AMDGPU/collapse-endcf2.mir

body:             |
   ; GCN:   successors: %bb.1(0x40000000), %bb.4(0x40000000)
   ; GCN:   liveins: $vgpr0, $sgpr0_sgpr1
   ; GCN:   [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr0_sgpr1
   ; GCN:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
   ; GCN:   [[V_CMP_LT_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_U32_e64 1, [[COPY1]], implicit $exec
   ; GCN:   [[COPY2:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
   ; GCN:   [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY2]], [[V_CMP_LT_U32_e64_]], implicit-def dead $scc
   ; GCN:   $exec = S_MOV_B64_term [[S_AND_B64_]]
-  ; GCN:   SI_MASK_BRANCH %bb.4, implicit $exec
+  ; GCN:   S_CBRANCH_EXECZ %bb.4, implicit $exec
   ; GCN:   S_BRANCH %bb.1
   ; GCN: bb.1:
   ; GCN:   successors: %bb.2(0x40000000), %bb.3(0x40000000)
   ; GCN:   undef %5.sub0_sub1:sgpr_128 = S_LOAD_DWORDX2_IMM [[COPY]], 9, 0, 0 :: (dereferenceable invariant load 8, align 4, addrspace 4)
   ; GCN:   undef %6.sub0:vreg_64 = V_LSHLREV_B32_e32 2, [[COPY1]], implicit $exec
   ; GCN:   %6.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec
   ; GCN:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY %5.sub1
   ; GCN:   undef %8.sub0:vreg_64, %9:sreg_64_xexec = V_ADD_CO_U32_e64 %5.sub0, %6.sub0, 0, implicit $exec
   ; GCN:   %8.sub1:vreg_64, dead %10:sreg_64_xexec = V_ADDC_U32_e64 0, [[COPY3]], %9, 0, implicit $exec
   ; GCN:   %5.sub3:sgpr_128 = S_MOV_B32 61440
   ; GCN:   %5.sub2:sgpr_128 = S_MOV_B32 0
   ; GCN:   BUFFER_STORE_DWORD_ADDR64 %6.sub1, %6, %5, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
   ; GCN:   [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 2, [[COPY1]], implicit $exec
   ; GCN:   [[COPY4:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
   ; GCN:   [[S_AND_B64_1:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY4]], [[V_CMP_NE_U32_e64_]], implicit-def dead $scc
   ; GCN:   $exec = S_MOV_B64_term [[S_AND_B64_1]]
-  ; GCN:   SI_MASK_BRANCH %bb.3, implicit $exec
+  ; GCN:   S_CBRANCH_EXECZ %bb.3, implicit $exec
   ; GCN:   S_BRANCH %bb.2
   ; GCN: bb.2:
   ; GCN:   successors: %bb.3(0x80000000)
   ; GCN:   %5.sub0:sgpr_128 = COPY %5.sub2
   ; GCN:   %5.sub1:sgpr_128 = COPY %5.sub2
   ; GCN:   [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
   ; GCN:   BUFFER_STORE_DWORD_ADDR64 [[V_MOV_B32_e32_]], %8, %5, 0, 4, 0, 0, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
   ; GCN: bb.3:
bb.0:
     liveins: $vgpr0, $sgpr0_sgpr1
 
     %1:sgpr_64 = COPY $sgpr0_sgpr1
     %0:vgpr_32 = COPY $vgpr0
     %2:sreg_64 = V_CMP_LT_U32_e64 1, %0, implicit $exec
     %3:sreg_64 = COPY $exec, implicit-def $exec
     %4:sreg_64 = S_AND_B64 %3, %2, implicit-def dead $scc
     $exec = S_MOV_B64_term %4
-    SI_MASK_BRANCH %bb.4, implicit $exec
+    S_CBRANCH_EXECZ %bb.4, implicit $exec
     S_BRANCH %bb.1
 
   bb.1:
     successors: %bb.2, %bb.3
 
     undef %5.sub0_sub1:sgpr_128 = S_LOAD_DWORDX2_IMM %1, 9, 0, 0 :: (dereferenceable invariant load 8, align 4, addrspace 4)
     undef %6.sub0:vreg_64 = V_LSHLREV_B32_e32 2, %0, implicit $exec
     %6.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec
     %7:vgpr_32 = COPY %5.sub1
     undef %8.sub0:vreg_64, %9:sreg_64_xexec = V_ADD_CO_U32_e64 %5.sub0, %6.sub0, 0, implicit $exec
     %8.sub1:vreg_64, dead %10:sreg_64_xexec = V_ADDC_U32_e64 0, %7, %9, 0, implicit $exec
     %5.sub3:sgpr_128 = S_MOV_B32 61440
     %5.sub2:sgpr_128 = S_MOV_B32 0
     BUFFER_STORE_DWORD_ADDR64 %6.sub1, %6, %5, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
     %11:sreg_64 = V_CMP_NE_U32_e64 2, %0, implicit $exec
     %12:sreg_64 = COPY $exec, implicit-def $exec
     %13:sreg_64 = S_AND_B64 %12, %11, implicit-def dead $scc
     $exec = S_MOV_B64_term %13
-    SI_MASK_BRANCH %bb.3, implicit $exec
+    S_CBRANCH_EXECZ %bb.3, implicit $exec
     S_BRANCH %bb.2
 
   bb.2:
     %5.sub0:sgpr_128 = COPY %5.sub2
     %5.sub1:sgpr_128 = COPY %5.sub2
     %14:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
     BUFFER_STORE_DWORD_ADDR64 %14, %8, %5, 0, 4, 0, 0, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
 

llvm/test/CodeGen/AMDGPU/insert-skips-flat-vmem-ds.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=amdgcn -mcpu=polaris10 -run-pass si-insert-skips -amdgpu-skip-threshold-legacy=1 -verify-machineinstrs  %s -o - | FileCheck %s
+# RUN: llc -march=amdgcn -mcpu=polaris10 -run-pass si-remove-short-exec-branches -amdgpu-skip-threshold=1 -verify-machineinstrs  %s -o - | FileCheck %s
 
 ---
 
 name: skip_execz_flat
 body: |
   ; CHECK-LABEL: name: skip_execz_flat
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
-  ; CHECK:   SI_MASK_BRANCH %bb.2, implicit $exec
   ; CHECK:   S_CBRANCH_EXECZ %bb.2, implicit $exec
   ; CHECK: bb.1:
   ; CHECK:   successors: %bb.2(0x80000000)
   ; CHECK:   $vgpr0 = V_MOV_B32_e32 0, implicit $exec
   ; CHECK:   FLAT_STORE_DWORD undef $vgpr1_vgpr2, $vgpr0, 0, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
   ; CHECK: bb.2:
   ; CHECK:   S_ENDPGM 0
   bb.0:
     successors: %bb.1, %bb.2
-    SI_MASK_BRANCH %bb.2, implicit $exec
+    S_CBRANCH_EXECZ   %bb.2, implicit $exec
 
   bb.1:
     successors: %bb.2
     $vgpr0 = V_MOV_B32_e32 0, implicit $exec
     FLAT_STORE_DWORD undef $vgpr1_vgpr2, $vgpr0, 0, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
 
   bb.2:
     S_ENDPGM 0
 ...
 
 ---
 
 name: skip_execz_mubuf
 body: |
   ; CHECK-LABEL: name: skip_execz_mubuf
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
-  ; CHECK:   SI_MASK_BRANCH %bb.2, implicit $exec
   ; CHECK:   S_CBRANCH_EXECZ %bb.2, implicit $exec
   ; CHECK: bb.1:
   ; CHECK:   successors: %bb.2(0x80000000)
   ; CHECK:   $vgpr0 = V_MOV_B32_e32 0, implicit $exec
   ; CHECK:   BUFFER_STORE_DWORD_OFFSET $vgpr0, undef $sgpr0_sgpr1_sgpr2_sgpr3, undef $sgpr4, 0, 0, 0, 0, 0, 0, 0, implicit $exec
   ; CHECK: bb.2:
   ; CHECK:   S_ENDPGM 0
   bb.0:
     successors: %bb.1, %bb.2
-    SI_MASK_BRANCH %bb.2, implicit $exec
+    S_CBRANCH_EXECZ  %bb.2, implicit $exec
 
   bb.1:
     successors: %bb.2
     $vgpr0 = V_MOV_B32_e32 0, implicit $exec
     BUFFER_STORE_DWORD_OFFSET $vgpr0, undef $sgpr0_sgpr1_sgpr2_sgpr3, undef $sgpr4, 0, 0, 0, 0, 0, 0, 0, implicit $exec
 
   bb.2:
     S_ENDPGM 0
 ...
 
 ---
 
 name: skip_execz_ds
 body: |
   ; CHECK-LABEL: name: skip_execz_ds
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
-  ; CHECK:   SI_MASK_BRANCH %bb.2, implicit $exec
   ; CHECK:   S_CBRANCH_EXECZ %bb.2, implicit $exec
   ; CHECK: bb.1:
   ; CHECK:   successors: %bb.2(0x80000000)
   ; CHECK:   $vgpr0 = V_MOV_B32_e32 0, implicit $exec
   ; CHECK:   DS_WRITE_B32 $vgpr0, $vgpr0, 0, 0, implicit $m0, implicit $exec
   ; CHECK: bb.2:
   ; CHECK:   S_ENDPGM 0
   bb.0:
     successors: %bb.1, %bb.2
-    SI_MASK_BRANCH %bb.2, implicit $exec
+    S_CBRANCH_EXECZ %bb.2, implicit $exec
 
   bb.1:
     successors: %bb.2
     $vgpr0 = V_MOV_B32_e32 0, implicit $exec
     DS_WRITE_B32 $vgpr0, $vgpr0, 0, 0, implicit $m0, implicit $exec
 
   bb.2:
     S_ENDPGM 0
 ...

llvm/test/CodeGen/AMDGPU/insert-skips-gws.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass si-insert-skips -amdgpu-skip-threshold-legacy=1 -verify-machineinstrs  %s -o - | FileCheck %s
+# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass si-remove-short-exec-branches -amdgpu-skip-threshold=1 -verify-machineinstrs  %s -o - | FileCheck %s
 # Make sure mandatory skips are inserted to ensure GWS ops aren't run with exec = 0
 
 ---
 
 name: skip_gws_init
 body: |
   ; CHECK-LABEL: name: skip_gws_init
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
-  ; CHECK:   SI_MASK_BRANCH %bb.2, implicit $exec
   ; CHECK:   S_CBRANCH_EXECZ %bb.2, implicit $exec
   ; CHECK: bb.1:
   ; CHECK:   successors: %bb.2(0x80000000)
   ; CHECK:   $vgpr0 = V_MOV_B32_e32 0, implicit $exec
   ; CHECK:   DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
   ; CHECK: bb.2:
   ; CHECK:   S_ENDPGM 0
   bb.0:
     successors: %bb.1, %bb.2
-    SI_MASK_BRANCH %bb.2, implicit $exec
+    S_CBRANCH_EXECZ %bb.2, implicit $exec
 
   bb.1:
     successors: %bb.2
     $vgpr0 = V_MOV_B32_e32 0, implicit $exec
     DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
 
   bb.2:
     S_ENDPGM 0
 ...
 
 ---
 
 name: skip_gws_barrier
 body: |
   ; CHECK-LABEL: name: skip_gws_barrier
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
-  ; CHECK:   SI_MASK_BRANCH %bb.2, implicit $exec
   ; CHECK:   S_CBRANCH_EXECZ %bb.2, implicit $exec
   ; CHECK: bb.1:
   ; CHECK:   successors: %bb.2(0x80000000)
   ; CHECK:   $vgpr0 = V_MOV_B32_e32 0, implicit $exec
   ; CHECK:   DS_GWS_BARRIER $vgpr0, 0, implicit $m0, implicit $exec
   ; CHECK: bb.2:
   ; CHECK:   S_ENDPGM 0
   bb.0:
     successors: %bb.1, %bb.2
-    SI_MASK_BRANCH %bb.2, implicit $exec
+    S_CBRANCH_EXECZ %bb.2, implicit $exec
 
   bb.1:
     successors: %bb.2
     $vgpr0 = V_MOV_B32_e32 0, implicit $exec
     DS_GWS_BARRIER $vgpr0, 0, implicit $m0, implicit $exec
 
   bb.2:
     S_ENDPGM 0
 ...

llvm/test/CodeGen/AMDGPU/insert-skips-ignored-insts.mir

-# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass si-insert-skips -amdgpu-skip-threshold-legacy=2 %s -o - | FileCheck %s
-
----
-
-# CHECK-LABEL: name: no_count_mask_branch_pseudo
-# CHECK: $vgpr1 = V_MOV_B32_e32 7, implicit $exec
-# CHECK-NEXT: SI_MASK_BRANCH
-# CHECK-NOT: S_CBRANCH_EXECZ
-name: no_count_mask_branch_pseudo
-body: |
-  bb.0:
-    successors: %bb.1
-
-    $vgpr1 = V_MOV_B32_e32 7, implicit $exec
-    SI_MASK_BRANCH %bb.2, implicit $exec
-
-  bb.1:
-    successors: %bb.2
-    $vgpr0 = V_MOV_B32_e32 0, implicit $exec
-    SI_MASK_BRANCH %bb.3, implicit $exec
-
-  bb.2:
-    $vgpr0 = V_MOV_B32_e32 1, implicit $exec
-
-  bb.3:
-    S_ENDPGM 0
-...
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass si-remove-short-exec-branches -amdgpu-skip-threshold=3 %s -o - | FileCheck %s
 
 ---
 
+# FIXME: RemoveShortExecBranches should not count dbg_value instructions.
 # CHECK-LABEL: name: no_count_dbg_value
 # CHECK: $vgpr1 = V_MOV_B32_e32 7, implicit $exec
-# CHECK-NEXT: SI_MASK_BRANCH
 # CHECK-NOT: S_CBRANCH_EXECZ
 name: no_count_dbg_value
 body: |
   bb.0:
-    successors: %bb.1
+    successors: %bb.1, %bb.2
 
     $vgpr1 = V_MOV_B32_e32 7, implicit $exec
-    SI_MASK_BRANCH %bb.2, implicit $exec
+    S_CBRANCH_EXECZ %bb.2, implicit $exec
 
   bb.1:
     successors: %bb.2
     $vgpr0 = V_MOV_B32_e32 0, implicit $exec
     DBG_VALUE
 
   bb.2:
     $vgpr0 = V_MOV_B32_e32 1, implicit $exec
 
   bb.3:
     S_ENDPGM 0
 ...
 

llvm/test/CodeGen/AMDGPU/loop_header_nopred.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -march=amdgcn -o - -run-pass=block-placement -mcpu=gfx1010 -mattr=-inst-fwd-prefetch-bug -verify-machineinstrs %s | FileCheck -check-prefix=GCN %s
 
 # Used to fail with
 # Assertion `Out && "Header of loop has no predecessors from outside loop?"
 
 ---
 name:            loop_header_nopred
 body:             |
   ; GCN-LABEL: name: loop_header_nopred
   ; GCN: bb.0:
-  ; GCN:   successors: %bb.1(0x80000000)
-  ; GCN:   S_INST_PREFETCH 1
-  ; GCN:   S_BRANCH %bb.1
-  ; GCN: bb.6 (align 64):
-  ; GCN:   successors: %bb.7(0x04000000), %bb.1(0x7c000000)
-  ; GCN:   S_CBRANCH_VCCNZ %bb.7, implicit $vcc
-  ; GCN: bb.1:
-  ; GCN:   successors: %bb.2(0x40000000), %bb.3(0x40000000)
-  ; GCN:   S_CBRANCH_VCCNZ %bb.2, implicit $vcc
-  ; GCN: bb.3:
-  ; GCN:   successors: %bb.4(0x40000000), %bb.6(0x40000000)
-  ; GCN:   SI_MASK_BRANCH %bb.6, implicit $exec
-  ; GCN:   S_BRANCH %bb.4
-  ; GCN: bb.2 (align 64):
-  ; GCN:   successors: %bb.4(0x40000000), %bb.6(0x40000000)
-  ; GCN:   SI_MASK_BRANCH %bb.6, implicit $exec
-  ; GCN:   S_BRANCH %bb.4
-  ; GCN: bb.4:
-  ; GCN:   successors: %bb.5(0x04000000), %bb.4(0x7c000000)
+  ; GCN:   successors: %bb.2(0x80000000)
+  ; GCN:   S_BRANCH %bb.2
+  ; GCN: bb.1 (align 64):
+  ; GCN:   successors: %bb.7(0x04000000), %bb.2(0x7c000000)
+  ; GCN:   S_CBRANCH_VCCNZ %bb.7, implicit $vcc_lo
+  ; GCN: bb.2:
+  ; GCN:   successors: %bb.5(0x40000000), %bb.1(0x40000000)
+  ; GCN:   S_CBRANCH_EXECZ %bb.1, implicit $exec
+  ; GCN: bb.5:
+  ; GCN:   successors: %bb.1(0x04000000), %bb.5(0x7c000000)
   ; GCN:   S_NOP 0
   ; GCN:   S_NOP 0
   ; GCN:   S_NOP 0
   ; GCN:   S_NOP 0
   ; GCN:   S_NOP 0
   ; GCN:   S_NOP 0
   ; GCN:   S_NOP 0
   ; GCN:   S_NOP 0
   ; GCN:   S_NOP 0
   ; GCN:   S_NOP 0
   ; GCN:   S_NOP 0
-  ; GCN:   S_CBRANCH_EXECZ %bb.4, implicit $exec
-  ; GCN: bb.5:
-  ; GCN:   successors: %bb.6(0x80000000)
-  ; GCN:   S_BRANCH %bb.6
+  ; GCN:   S_CBRANCH_EXECZ %bb.5, implicit $exec
+  ; GCN:   S_BRANCH %bb.1
   ; GCN: bb.7:
   ; GCN:   S_ENDPGM 0
   bb.0:
     successors: %bb.1(0x80000000)
 
   bb.1:
     successors: %bb.2(0x40000000), %bb.3(0x40000000)
 
     S_CBRANCH_VCCZ %bb.3, implicit $vcc
     S_BRANCH %bb.2
 
   bb.2:
     successors: %bb.3(0x80000000)
 
   bb.3:
     successors: %bb.4(0x40000000), %bb.6(0x40000000)
 
-    SI_MASK_BRANCH %bb.6, implicit $exec
+    S_CBRANCH_EXECZ %bb.6, implicit $exec
     S_BRANCH %bb.4
 
   bb.4:
     successors: %bb.5(0x04000000), %bb.4(0x7c000000)
 
     S_NOP 0
     S_NOP 0
     S_NOP 0

llvm/test/CodeGen/AMDGPU/memory-legalizer-atomic-insert-end.mir

bb.0 (%ir-block.0):
     $sgpr7 = S_MOV_B32 61440
     $sgpr6 = S_MOV_B32 0
     S_WAITCNT 127
     $vgpr1_vgpr2 = BUFFER_LOAD_DWORDX2_ADDR64 killed $vgpr1_vgpr2, $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 8 from %ir.tid.gep)
     $vgpr0 = V_XOR_B32_e32 1, killed $vgpr0, implicit $exec
     V_CMP_NE_U32_e32 0, killed $vgpr0, implicit-def $vcc, implicit $exec
     $sgpr2_sgpr3 = S_AND_SAVEEXEC_B64 killed $vcc, implicit-def $exec, implicit-def $scc, implicit $exec
     $sgpr2_sgpr3 = S_XOR_B64 $exec, killed $sgpr2_sgpr3, implicit-def dead $scc
-    SI_MASK_BRANCH %bb.2.exit, implicit $exec
+    S_CBRANCH_EXECZ %bb.2.exit, implicit $exec
 
   bb.1.atomic:
     successors: %bb.2.exit(0x80000000)
     liveins: $sgpr4_sgpr5_sgpr6_sgpr7:0x0000000C, $sgpr0_sgpr1, $sgpr2_sgpr3, $vgpr1_vgpr2_vgpr3_vgpr4:0x00000003
 
     $sgpr0 = S_LOAD_DWORD_IMM killed $sgpr0_sgpr1, 15, 0, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(4)* undef`)
     dead $vgpr0 = V_MOV_B32_e32 -1, implicit $exec
     dead $vgpr0 = V_MOV_B32_e32 61440, implicit $exec

llvm/test/CodeGen/AMDGPU/optimize-exec-masking-pre-ra.mir

body:             |
   ; GCN:   liveins: $vgpr0
   ; GCN:   [[COPY:%[0-9]+]]:sreg_64 = COPY $exec
   ; GCN:   [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
   ; GCN:   [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[DEF]], implicit $exec
   ; GCN:   [[COPY1:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
   ; GCN:   [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY1]], [[V_CMP_NE_U32_e64_]], implicit-def dead $scc
   ; GCN:   [[S_XOR_B64_:%[0-9]+]]:sreg_64 = S_XOR_B64 [[S_AND_B64_]], [[COPY1]], implicit-def dead $scc
   ; GCN:   $exec = S_MOV_B64_term [[S_AND_B64_]]
-  ; GCN:   SI_MASK_BRANCH %bb.2, implicit $exec
+  ; GCN:   S_CBRANCH_EXECZ %bb.2, implicit $exec
   ; GCN:   S_BRANCH %bb.1
   ; GCN: bb.1:
   ; GCN:   successors: %bb.2(0x80000000)
   ; GCN: bb.2:
   ; GCN:   successors: %bb.3(0x40000000), %bb.6(0x40000000)
   ; GCN:   [[S_OR_SAVEEXEC_B64_:%[0-9]+]]:sreg_64 = S_OR_SAVEEXEC_B64 [[S_XOR_B64_]], implicit-def $exec, implicit-def $scc, implicit $exec
   ; GCN:   $exec = S_AND_B64 $exec, [[COPY]], implicit-def dead $scc
   ; GCN:   [[S_AND_B64_1:%[0-9]+]]:sreg_64 = S_AND_B64 $exec, [[S_OR_SAVEEXEC_B64_]], implicit-def $scc
   ; GCN:   $exec = S_XOR_B64_term $exec, [[S_AND_B64_1]], implicit-def $scc
-  ; GCN:   SI_MASK_BRANCH %bb.6, implicit $exec
+  ; GCN:   S_CBRANCH_EXECZ %bb.6, implicit $exec
   ; GCN:   S_BRANCH %bb.3
   ; GCN: bb.3:
   ; GCN:   successors: %bb.4(0x40000000), %bb.5(0x40000000)
   ; GCN:   [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 0, [[DEF]], implicit $exec
   ; GCN:   [[COPY2:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
   ; GCN:   [[S_AND_B64_2:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY2]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc
   ; GCN:   $exec = S_MOV_B64_term [[S_AND_B64_2]]
-  ; GCN:   SI_MASK_BRANCH %bb.5, implicit $exec
+  ; GCN:   S_CBRANCH_EXECZ %bb.5, implicit $exec
   ; GCN:   S_BRANCH %bb.4
   ; GCN: bb.4:
   ; GCN:   successors: %bb.5(0x80000000)
   ; GCN: bb.5:
   ; GCN:   successors: %bb.6(0x80000000)
   ; GCN:   $exec = S_OR_B64 $exec, [[COPY2]], implicit-def $scc
   ; GCN: bb.6:
   ; GCN:   $exec = S_OR_B64 $exec, [[S_AND_B64_1]], implicit-def $scc
   bb.0:
     successors: %bb.1, %bb.2
     liveins: $vgpr0
 
     %0:sreg_64 = COPY $exec
     %1:vgpr_32 = IMPLICIT_DEF
     %2:sreg_64 = V_CMP_NE_U32_e64 0, %1, implicit $exec
     %3:sreg_64 = COPY $exec, implicit-def $exec
     %4:sreg_64 = S_AND_B64 %3, %2, implicit-def dead $scc
     %5:sreg_64 = S_XOR_B64 %4, %3, implicit-def dead $scc
     $exec = S_MOV_B64_term %4
-    SI_MASK_BRANCH %bb.2, implicit $exec
+    S_CBRANCH_EXECZ %bb.2, implicit $exec
     S_BRANCH %bb.1
 
   bb.1:
 
   bb.2:
     successors: %bb.3, %bb.6
 
     %6:sreg_64 = S_OR_SAVEEXEC_B64 %5, implicit-def $exec, implicit-def $scc, implicit $exec
     $exec = S_AND_B64 $exec, %0, implicit-def dead $scc
     %7:sreg_64 = S_AND_B64 $exec, %6, implicit-def $scc
     $exec = S_XOR_B64_term $exec, %7, implicit-def $scc
-    SI_MASK_BRANCH %bb.6, implicit $exec
+    S_CBRANCH_EXECZ %bb.6, implicit $exec
     S_BRANCH %bb.3
 
   bb.3:
     successors: %bb.4, %bb.5
 
     %8:sreg_64 = V_CMP_NE_U32_e64 0, %1, implicit $exec
     %9:sreg_64 = COPY $exec, implicit-def $exec
     %10:sreg_64 = S_AND_B64 %9, %8, implicit-def dead $scc
     $exec = S_MOV_B64_term %10
-    SI_MASK_BRANCH %bb.5, implicit $exec
+    S_CBRANCH_EXECZ %bb.5, implicit $exec
     S_BRANCH %bb.4
 
   bb.4:
 
   bb.5:
     $exec = S_OR_B64 $exec, %9, implicit-def $scc
 
   bb.6:

llvm/test/CodeGen/AMDGPU/optimize-if-exec-masking.mir

end:                                              ; preds = %if, %main_body
     ret void
   }
 
 ...
 ---
 # CHECK-LABEL: name: optimize_if_and_saveexec_xor{{$}}
 # CHECK: $sgpr0_sgpr1 = S_AND_SAVEEXEC_B64 $vcc, implicit-def $exec, implicit-def $scc, implicit $exec
 # CHECK-NEXT: $sgpr0_sgpr1 = S_XOR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
-# CHECK-NEXT: SI_MASK_BRANCH
+# CHECK-NEXT: S_CBRANCH_EXECZ
 
 name:            optimize_if_and_saveexec_xor
 liveins:
   - { reg: '$vgpr0' }
 body:             |
   bb.0.main_body:
     liveins: $vgpr0
 
     $sgpr0_sgpr1 = COPY $exec
     $vcc = V_CMP_EQ_I32_e64 0, killed $vgpr0, implicit $exec
     $vgpr0 = V_MOV_B32_e32 4, implicit $exec
     $sgpr2_sgpr3 = S_AND_B64 $sgpr0_sgpr1, killed $vcc, implicit-def $scc
     $sgpr0_sgpr1 = S_XOR_B64 $sgpr2_sgpr3, killed $sgpr0_sgpr1, implicit-def $scc
     $exec = S_MOV_B64_term killed $sgpr2_sgpr3
-    SI_MASK_BRANCH %bb.2, implicit $exec
+    S_CBRANCH_EXECZ %bb.2, implicit $exec
     S_BRANCH %bb.1
 
   bb.1.if:
     liveins: $sgpr0_sgpr1
 
     $sgpr7 = S_MOV_B32 61440
     $sgpr6 = S_MOV_B32 -1
     $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec
 
   bb.2.end:
     liveins: $vgpr0, $sgpr0_sgpr1
 
     $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
     $sgpr3 = S_MOV_B32 61440
     $sgpr2 = S_MOV_B32 -1
     BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec
     S_ENDPGM 0
 
 ...
 ---
 # CHECK-LABEL: name: optimize_if_and_saveexec{{$}}
 # CHECK: $sgpr0_sgpr1 = S_AND_SAVEEXEC_B64 $vcc, implicit-def $exec, implicit-def $scc, implicit $exec
-# CHECK-NEXT: SI_MASK_BRANCH
+# CHECK-NEXT: S_CBRANCH_EXECZ
 
 name:            optimize_if_and_saveexec
 liveins:
   - { reg: '$vgpr0' }
 body:             |
   bb.0.main_body:
     liveins: $vgpr0
 
     $sgpr0_sgpr1 = COPY $exec
     $vcc = V_CMP_EQ_I32_e64 0, killed $vgpr0, implicit $exec
     $vgpr0 = V_MOV_B32_e32 4, implicit $exec
     $sgpr2_sgpr3 = S_AND_B64 $sgpr0_sgpr1, killed $vcc, implicit-def $scc
     $exec = S_MOV_B64_term killed $sgpr2_sgpr3
-    SI_MASK_BRANCH %bb.2, implicit $exec
+    S_CBRANCH_EXECZ %bb.2, implicit $exec
     S_BRANCH %bb.1
 
   bb.1.if:
     liveins: $sgpr0_sgpr1
 
     $sgpr7 = S_MOV_B32 61440
     $sgpr6 = S_MOV_B32 -1
     $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec
 
   bb.2.end:
     liveins: $vgpr0, $sgpr0_sgpr1
 
     $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
     $sgpr3 = S_MOV_B32 61440
     $sgpr2 = S_MOV_B32 -1
     BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec
     S_ENDPGM 0
 
 ...
 ---
 # CHECK-LABEL: name: optimize_if_or_saveexec{{$}}
 # CHECK: $sgpr0_sgpr1 = S_OR_SAVEEXEC_B64 $vcc, implicit-def $exec, implicit-def $scc, implicit $exec
-# CHECK-NEXT: SI_MASK_BRANCH
+# CHECK-NEXT: S_CBRANCH_EXECZ
 
 name:            optimize_if_or_saveexec
 liveins:
   - { reg: '$vgpr0' }
 body:             |
   bb.0.main_body:
     liveins: $vgpr0
 
     $sgpr0_sgpr1 = COPY $exec
     $vcc = V_CMP_EQ_I32_e64 0, killed $vgpr0, implicit $exec
     $vgpr0 = V_MOV_B32_e32 4, implicit $exec
     $sgpr2_sgpr3 = S_OR_B64 $sgpr0_sgpr1, killed $vcc, implicit-def $scc
     $exec = S_MOV_B64_term killed $sgpr2_sgpr3
-    SI_MASK_BRANCH %bb.2, implicit $exec
+    S_CBRANCH_EXECZ %bb.2, implicit $exec
     S_BRANCH %bb.1
 
   bb.1.if:
     liveins: $sgpr0_sgpr1
 
     $sgpr7 = S_MOV_B32 61440
     $sgpr6 = S_MOV_B32 -1
     $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec

 
 ...
 ---
 # CHECK-LABEL: name: optimize_if_and_saveexec_xor_valu_middle
 # CHECK: $sgpr2_sgpr3 = S_AND_B64 $sgpr0_sgpr1, killed $vcc, implicit-def $scc
 # CHECK-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr0, undef $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec
 # CHECK-NEXT: $sgpr0_sgpr1 = S_XOR_B64 $sgpr2_sgpr3, killed $sgpr0_sgpr1, implicit-def $scc
 # CHECK-NEXT: $exec = COPY killed $sgpr2_sgpr3
-# CHECK-NEXT: SI_MASK_BRANCH
+# CHECK-NEXT: S_CBRANCH_EXECZ
 name:            optimize_if_and_saveexec_xor_valu_middle
 liveins:
   - { reg: '$vgpr0' }
 body:             |
   bb.0.main_body:
     liveins: $vgpr0
 
     $sgpr0_sgpr1 = COPY $exec
     $vcc = V_CMP_EQ_I32_e64 0, killed $vgpr0, implicit $exec
     $vgpr0 = V_MOV_B32_e32 4, implicit $exec
     $sgpr2_sgpr3 = S_AND_B64 $sgpr0_sgpr1, killed $vcc, implicit-def $scc
     BUFFER_STORE_DWORD_OFFSET $vgpr0, undef $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec
     $sgpr0_sgpr1 = S_XOR_B64 $sgpr2_sgpr3, killed $sgpr0_sgpr1, implicit-def $scc
     $exec = S_MOV_B64_term killed $sgpr2_sgpr3
-    SI_MASK_BRANCH %bb.2, implicit $exec
+    S_CBRANCH_EXECZ %bb.2, implicit $exec
     S_BRANCH %bb.1
 
   bb.1.if:
     liveins: $sgpr0_sgpr1
 
     $sgpr7 = S_MOV_B32 61440
     $sgpr6 = S_MOV_B32 -1
     $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec
 
   bb.2.end:
     liveins: $vgpr0, $sgpr0_sgpr1
 
     $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
     $sgpr3 = S_MOV_B32 61440
     $sgpr2 = S_MOV_B32 -1
     BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec
     S_ENDPGM 0
 
 ...
 ---
 # CHECK-LABEL: name: optimize_if_and_saveexec_xor_wrong_reg{{$}}
 # CHECK: $sgpr0_sgpr1 = S_AND_B64 $sgpr0_sgpr1, killed $vcc, implicit-def $scc
 # CHECK-NEXT: $sgpr0_sgpr1 = S_XOR_B64 undef $sgpr2_sgpr3, killed $sgpr0_sgpr1, implicit-def $scc
 # CHECK-NEXT: $exec = COPY $sgpr0_sgpr1
-# CHECK-NEXT: SI_MASK_BRANCH %bb.2, implicit $exec
+# CHECK-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec
 name:            optimize_if_and_saveexec_xor_wrong_reg
 liveins:
   - { reg: '$vgpr0' }
 body:             |
   bb.0.main_body:
     liveins: $vgpr0
 
     $sgpr6 = S_MOV_B32 -1
     $sgpr7 = S_MOV_B32 61440
     $sgpr0_sgpr1 = COPY $exec
     $vcc = V_CMP_EQ_I32_e64 0, killed $vgpr0, implicit $exec
     $vgpr0 = V_MOV_B32_e32 4, implicit $exec
     $sgpr0_sgpr1 = S_AND_B64 $sgpr0_sgpr1, killed $vcc, implicit-def $scc
     $sgpr0_sgpr1 = S_XOR_B64 undef $sgpr2_sgpr3, killed $sgpr0_sgpr1, implicit-def $scc
     $exec = S_MOV_B64_term $sgpr0_sgpr1
-    SI_MASK_BRANCH %bb.2, implicit $exec
+    S_CBRANCH_EXECZ %bb.2, implicit $exec
     S_BRANCH %bb.1
 
   bb.1.if:
     liveins: $sgpr0_sgpr1 , $sgpr4_sgpr5_sgpr6_sgpr7
     $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec
 
   bb.2.end:
     liveins: $vgpr0, $sgpr0_sgpr1, $sgpr4_sgpr5_sgpr6_sgpr7
 
     $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
     $sgpr3 = S_MOV_B32 61440
     $sgpr2 = S_MOV_B32 -1
     BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec
     S_ENDPGM 0
 
 ...
 ---
 # CHECK-LABEL: name: optimize_if_and_saveexec_xor_modify_copy_to_exec{{$}}
 # CHECK: $sgpr2_sgpr3 = S_AND_B64 $sgpr0_sgpr1, killed $vcc, implicit-def $scc
 # CHECK-NEXT: $sgpr2_sgpr3 = S_OR_B64 killed $sgpr2_sgpr3, 1, implicit-def $scc
 # CHECK-NEXT: $sgpr0_sgpr1 = S_XOR_B64 $sgpr2_sgpr3, killed $sgpr0_sgpr1, implicit-def $scc
 # CHECK-NEXT: $exec = COPY killed $sgpr2_sgpr3
-# CHECK-NEXT: SI_MASK_BRANCH %bb.2, implicit $exec
+# CHECK-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec
 
 name:            optimize_if_and_saveexec_xor_modify_copy_to_exec
 liveins:
   - { reg: '$vgpr0' }
 body:             |
   bb.0.main_body:
     liveins: $vgpr0
 
     $sgpr0_sgpr1 = COPY $exec
     $vcc = V_CMP_EQ_I32_e64 0, killed $vgpr0, implicit $exec
     $vgpr0 = V_MOV_B32_e32 4, implicit $exec
     $sgpr2_sgpr3 = S_AND_B64 $sgpr0_sgpr1, killed $vcc, implicit-def $scc
     $sgpr2_sgpr3 = S_OR_B64 killed $sgpr2_sgpr3, 1, implicit-def $scc
     $sgpr0_sgpr1 = S_XOR_B64 $sgpr2_sgpr3, killed $sgpr0_sgpr1, implicit-def $scc
     $exec = S_MOV_B64_term killed $sgpr2_sgpr3
-    SI_MASK_BRANCH %bb.2, implicit $exec
+    S_CBRANCH_EXECZ %bb.2, implicit $exec
     S_BRANCH %bb.1
 
   bb.1.if:
     liveins: $sgpr0_sgpr1
 
     $sgpr7 = S_MOV_B32 61440
     $sgpr6 = S_MOV_B32 -1
     $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec
bb.2.end:
     S_ENDPGM 0
 
 ...
 ---
 # CHECK-LABEL: name: optimize_if_and_saveexec_xor_live_out_setexec{{$}}
 # CHECK: $sgpr2_sgpr3 = S_AND_B64 $sgpr0_sgpr1, killed $vcc, implicit-def $scc
 # CHECK-NEXT: $sgpr0_sgpr1 = S_XOR_B64 $sgpr2_sgpr3, killed $sgpr0_sgpr1, implicit-def $scc
 # CHECK-NEXT: $exec = COPY $sgpr2_sgpr3
-# CHECK-NEXT: SI_MASK_BRANCH
+# CHECK-NEXT: S_CBRANCH_EXECZ
 name:            optimize_if_and_saveexec_xor_live_out_setexec
 liveins:
   - { reg: '$vgpr0' }
 body:             |
   bb.0.main_body:
     liveins: $vgpr0
 
     $sgpr0_sgpr1 = COPY $exec
     $vcc = V_CMP_EQ_I32_e64 0, killed $vgpr0, implicit $exec
     $vgpr0 = V_MOV_B32_e32 4, implicit $exec
     $sgpr2_sgpr3 = S_AND_B64 $sgpr0_sgpr1, killed $vcc, implicit-def $scc
     $sgpr0_sgpr1 = S_XOR_B64 $sgpr2_sgpr3, killed $sgpr0_sgpr1, implicit-def $scc
     $exec = S_MOV_B64_term $sgpr2_sgpr3
-    SI_MASK_BRANCH %bb.2, implicit $exec
+    S_CBRANCH_EXECZ %bb.2, implicit $exec
     S_BRANCH %bb.1
 
   bb.1.if:
     liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
     S_SLEEP 0, implicit $sgpr2_sgpr3
     $sgpr7 = S_MOV_B32 61440
     $sgpr6 = S_MOV_B32 -1
     $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec
 
   bb.2.end:
     liveins: $vgpr0, $sgpr0_sgpr1
 
     $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
     $sgpr3 = S_MOV_B32 61440
     $sgpr2 = S_MOV_B32 -1
     BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec
     S_ENDPGM 0
 
 ...
 
 # CHECK-LABEL: name: optimize_if_unknown_saveexec{{$}}
 # CHECK: $sgpr0_sgpr1 = COPY $exec
 # CHECK: $sgpr2_sgpr3 = S_LSHR_B64 $sgpr0_sgpr1, killed $vcc_lo, implicit-def $scc
 # CHECK-NEXT: $exec = COPY killed $sgpr2_sgpr3
-# CHECK-NEXT: SI_MASK_BRANCH %bb.2, implicit $exec
+# CHECK-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec
 
 name:            optimize_if_unknown_saveexec
 liveins:
   - { reg: '$vgpr0' }
 body:             |
   bb.0.main_body:
     liveins: $vgpr0
 
     $sgpr0_sgpr1 = COPY $exec
     $vcc = V_CMP_EQ_I32_e64 0, killed $vgpr0, implicit $exec
     $vgpr0 = V_MOV_B32_e32 4, implicit $exec
     $sgpr2_sgpr3 = S_LSHR_B64 $sgpr0_sgpr1, killed $vcc_lo, implicit-def $scc
     $exec = S_MOV_B64_term killed $sgpr2_sgpr3
-    SI_MASK_BRANCH %bb.2, implicit $exec
+    S_CBRANCH_EXECZ %bb.2, implicit $exec
     S_BRANCH %bb.1
 
   bb.1.if:
     liveins: $sgpr0_sgpr1
 
     $sgpr7 = S_MOV_B32 61440
     $sgpr6 = S_MOV_B32 -1
     $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec
 
   bb.2.end:
     liveins: $vgpr0, $sgpr0_sgpr1
 
     $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
     $sgpr3 = S_MOV_B32 61440
     $sgpr2 = S_MOV_B32 -1
     BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec
     S_ENDPGM 0
 
 ...
 ---
 # CHECK-LABEL: name: optimize_if_andn2_saveexec{{$}}
 # CHECK: $sgpr0_sgpr1 = S_ANDN2_SAVEEXEC_B64 $vcc, implicit-def $exec, implicit-def $scc, implicit $exec
-# CHECK-NEXT: SI_MASK_BRANCH
+# CHECK-NEXT: S_CBRANCH_EXECZ
 
 name:            optimize_if_andn2_saveexec
 liveins:
   - { reg: '$vgpr0' }
 body:             |
   bb.0.main_body:
     liveins: $vgpr0
 
     $sgpr0_sgpr1 = COPY $exec
     $vcc = V_CMP_EQ_I32_e64 0, killed $vgpr0, implicit $exec
     $vgpr0 = V_MOV_B32_e32 4, implicit $exec
     $sgpr2_sgpr3 = S_ANDN2_B64 $sgpr0_sgpr1, killed $vcc, implicit-def $scc
     $exec = S_MOV_B64_term killed $sgpr2_sgpr3
-    SI_MASK_BRANCH %bb.2, implicit $exec
+    S_CBRANCH_EXECZ %bb.2, implicit $exec
     S_BRANCH %bb.1
 
   bb.1.if:
     liveins: $sgpr0_sgpr1
 
     $sgpr7 = S_MOV_B32 61440
     $sgpr6 = S_MOV_B32 -1
     $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec
 
   bb.2.end:
     liveins: $vgpr0, $sgpr0_sgpr1
 
     $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
     $sgpr3 = S_MOV_B32 61440
     $sgpr2 = S_MOV_B32 -1
     BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec
     S_ENDPGM 0
 
 ...
 ---
 # CHECK-LABEL: name: optimize_if_andn2_saveexec_no_commute{{$}}
 # CHECK: $sgpr2_sgpr3 = S_ANDN2_B64 killed $vcc, $sgpr0_sgpr1, implicit-def $scc
 # CHECK-NEXT: $exec = COPY killed $sgpr2_sgpr3
-# CHECK-NEXT: SI_MASK_BRANCH %bb.2, implicit $exec
+# CHECK-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec
 name:            optimize_if_andn2_saveexec_no_commute
 liveins:
   - { reg: '$vgpr0' }
 body:             |
   bb.0.main_body:
     liveins: $vgpr0
 
     $sgpr0_sgpr1 = COPY $exec
     $vcc = V_CMP_EQ_I32_e64 0, killed $vgpr0, implicit $exec
     $vgpr0 = V_MOV_B32_e32 4, implicit $exec
     $sgpr2_sgpr3 = S_ANDN2_B64 killed $vcc, $sgpr0_sgpr1, implicit-def $scc
     $exec = S_MOV_B64_term killed $sgpr2_sgpr3
-    SI_MASK_BRANCH %bb.2, implicit $exec
+    S_CBRANCH_EXECZ %bb.2, implicit $exec
     S_BRANCH %bb.1
 
   bb.1.if:
     liveins: $sgpr0_sgpr1
 
     $sgpr7 = S_MOV_B32 61440
     $sgpr6 = S_MOV_B32 -1
     $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec
bb.0.main_body:
 
     $sgpr0_sgpr1 = COPY $exec
     $sgpr4 = S_MOV_B32 $sgpr1
     $vcc = V_CMP_EQ_I32_e64 0, killed $vgpr0, implicit $exec
     $vgpr0 = V_MOV_B32_e32 4, implicit $exec
     $sgpr2_sgpr3 = S_AND_B64 $sgpr0_sgpr1, killed $vcc, implicit-def $scc
     $sgpr0_sgpr1 = S_XOR_B64 $sgpr2_sgpr3, killed $sgpr0_sgpr1, implicit-def $scc
     $exec = S_MOV_B64_term killed $sgpr2_sgpr3
-    SI_MASK_BRANCH %bb.2, implicit $exec
+    S_CBRANCH_EXECZ %bb.2, implicit $exec
     S_BRANCH %bb.1
 
   bb.1.if:
     liveins: $sgpr0_sgpr1
 
     $sgpr7 = S_MOV_B32 61440
     $sgpr6 = S_MOV_B32 -1
     $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec

llvm/test/CodeGen/AMDGPU/readlane_exec0.mir

 body:       |
   bb.0:
     successors: %bb.1, %bb.2
     liveins: $vgpr1_vgpr2:0x00000001, $vgpr2_vgpr3:0x00000003
 
     $vgpr4 = V_AND_B32_e32 1, $vgpr1, implicit $exec
     V_CMP_EQ_U32_e32 1, killed $vgpr4, implicit-def $vcc, implicit $exec
     $sgpr0_sgpr1 = S_AND_SAVEEXEC_B64 killed $vcc, implicit-def $exec, implicit-def $scc, implicit $exec
-    SI_MASK_BRANCH %bb.2, implicit $exec
+    S_CBRANCH_EXECZ %bb.2, implicit $exec
     S_BRANCH %bb.1
 
   bb.1:
 
    $sgpr10 = V_READFIRSTLANE_B32 $vgpr2, implicit $exec
    $sgpr11 = V_READFIRSTLANE_B32 $vgpr3, implicit $exec
    $sgpr10 = S_LOAD_DWORD_IMM killed $sgpr10_sgpr11, 0, 0, 0
    S_WAITCNT 127
    $vgpr0 = V_XOR_B32_e32 killed $sgpr10, killed $vgpr0, implicit $exec
 
   bb.2:
 
     $exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
 ...

llvm/test/CodeGen/AMDGPU/skip-branch-taildup-ret.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass=si-insert-skips -amdgpu-skip-threshold-legacy=1000000 -o -  %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass=si-remove-short-exec-branches -amdgpu-skip-threshold=1000000 -o -  %s | FileCheck %s
 
 ---
 name: skip_branch_taildup_endpgm
 machineFunctionInfo:
   isEntryFunction: true
 body:             |
   ; CHECK-LABEL: name: skip_branch_taildup_endpgm
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; CHECK:   renamable $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM renamable $sgpr4_sgpr5, 4, 0, 0 :: (dereferenceable invariant load 8, align 16, addrspace 4)
   ; CHECK:   renamable $vgpr0 = V_LSHLREV_B32_e32 2, killed $vgpr0, implicit $exec
   ; CHECK:   S_WAITCNT 127
   ; CHECK:   $vgpr1 = V_MOV_B32_e32 $sgpr1, implicit $exec, implicit $exec
   ; CHECK:   renamable $vgpr0 = V_ADD_CO_U32_e32 $sgpr0, killed $vgpr0, implicit-def $vcc, implicit $exec
   ; CHECK:   renamable $vgpr1 = V_ADDC_U32_e32 0, killed $vgpr1, implicit-def $vcc, implicit killed $vcc, implicit $exec
   ; CHECK:   renamable $vgpr0 = FLAT_LOAD_DWORD renamable $vgpr0_vgpr1, 0, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4, addrspace 1)
   ; CHECK:   renamable $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed renamable $sgpr4_sgpr5, 0, 0, 0 :: (dereferenceable invariant load 8, align 16, addrspace 4)
   ; CHECK:   S_WAITCNT 112
   ; CHECK:   V_CMP_NE_U32_e32 0, killed $vgpr0, implicit-def $vcc, implicit $exec
   ; CHECK:   $sgpr2_sgpr3 = S_AND_SAVEEXEC_B64 $vcc, implicit-def $exec, implicit-def $scc, implicit $exec
   ; CHECK:   renamable $sgpr2_sgpr3 = S_XOR_B64 $exec, killed renamable $sgpr2_sgpr3, implicit-def dead $scc
-  ; CHECK:   SI_MASK_BRANCH %bb.1, implicit $exec
   ; CHECK:   S_CBRANCH_EXECZ %bb.1, implicit $exec
   ; CHECK:   S_BRANCH %bb.3
   ; CHECK: bb.1:
   ; CHECK:   successors: %bb.4(0x40000000), %bb.2(0x40000000)
   ; CHECK:   renamable $sgpr2_sgpr3 = S_OR_SAVEEXEC_B64 killed renamable $sgpr2_sgpr3, implicit-def $exec, implicit-def $scc, implicit $exec
   ; CHECK:   $exec = S_XOR_B64 $exec, renamable $sgpr2_sgpr3, implicit-def $scc
-  ; CHECK:   SI_MASK_BRANCH %bb.2, implicit $exec
   ; CHECK:   S_CBRANCH_EXECZ %bb.2, implicit $exec
   ; CHECK:   S_BRANCH %bb.4
   ; CHECK: bb.2:
   ; CHECK:   $exec = S_OR_B64 $exec, killed renamable $sgpr2_sgpr3, implicit-def $scc
   ; CHECK:   renamable $vgpr0 = V_MOV_B32_e32 32, implicit $exec
   ; CHECK:   S_ENDPGM 0
   ; CHECK: bb.3:
   ; CHECK:   successors: %bb.4(0x40000000), %bb.2(0x40000000)
   ; CHECK:   renamable $vgpr2 = V_MOV_B32_e32 15, implicit $exec
   ; CHECK:   $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
   ; CHECK:   $vgpr1 = V_MOV_B32_e32 $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
   ; CHECK:   renamable $sgpr2_sgpr3 = S_OR_SAVEEXEC_B64 killed renamable $sgpr2_sgpr3, implicit-def $exec, implicit-def $scc, implicit $exec
   ; CHECK:   $exec = S_XOR_B64 $exec, renamable $sgpr2_sgpr3, implicit-def $scc
-  ; CHECK:   SI_MASK_BRANCH %bb.2, implicit $exec
   ; CHECK:   S_CBRANCH_EXECZ %bb.2, implicit $exec
   ; CHECK: bb.4:
   ; CHECK:   renamable $vgpr2 = V_MOV_B32_e32 8, implicit $exec
   ; CHECK:   $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
   ; CHECK:   $vgpr1 = V_MOV_B32_e32 $sgpr1, implicit $exec, implicit killed $sgpr0_sgpr1, implicit $exec
   ; CHECK:   $exec = S_OR_B64 $exec, killed renamable $sgpr2_sgpr3, implicit-def $scc
   ; CHECK:   renamable $vgpr0 = V_MOV_B32_e32 32, implicit $exec
   ; CHECK:   S_ENDPGM 0
   bb.0:
     successors: %bb.1, %bb.2
     liveins: $vgpr0, $sgpr4_sgpr5, $sgpr7
 
     renamable $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM renamable $sgpr4_sgpr5, 4, 0, 0 :: (dereferenceable invariant load 8, align 16, addrspace 4)
     renamable $vgpr0 = V_LSHLREV_B32_e32 2, killed $vgpr0, implicit $exec
     S_WAITCNT 127
     $vgpr1 = V_MOV_B32_e32 $sgpr1, implicit $exec, implicit $exec
     renamable $vgpr0 = V_ADD_CO_U32_e32 $sgpr0, killed $vgpr0, implicit-def $vcc, implicit $exec
     renamable $vgpr1 = V_ADDC_U32_e32 0, killed $vgpr1, implicit-def $vcc, implicit killed $vcc, implicit $exec
     renamable $vgpr0 = FLAT_LOAD_DWORD renamable $vgpr0_vgpr1, 0, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4, addrspace 1)
     renamable $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed renamable $sgpr4_sgpr5, 0, 0, 0 :: (dereferenceable invariant load 8, align 16, addrspace 4)
     S_WAITCNT 112
     V_CMP_NE_U32_e32 0, killed $vgpr0, implicit-def $vcc, implicit $exec
     $sgpr2_sgpr3 = S_AND_SAVEEXEC_B64 $vcc, implicit-def $exec, implicit-def $scc, implicit $exec
     renamable $sgpr2_sgpr3 = S_XOR_B64 $exec, killed renamable $sgpr2_sgpr3, implicit-def dead $scc
-    SI_MASK_BRANCH %bb.2, implicit $exec
+    S_CBRANCH_EXECZ %bb.2, implicit $exec
     S_BRANCH %bb.1
 
   bb.2:
     successors: %bb.3, %bb.4
     liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
 
     renamable $sgpr2_sgpr3 = S_OR_SAVEEXEC_B64 killed renamable $sgpr2_sgpr3, implicit-def $exec, implicit-def $scc, implicit $exec
     $exec = S_XOR_B64 $exec, renamable $sgpr2_sgpr3, implicit-def $scc
-    SI_MASK_BRANCH %bb.4, implicit $exec
+    S_CBRANCH_EXECZ %bb.4, implicit $exec
     S_BRANCH %bb.3
 
   bb.4:
     liveins: $sgpr2_sgpr3
 
     $exec = S_OR_B64 $exec, killed renamable $sgpr2_sgpr3, implicit-def $scc
     renamable $vgpr0 = V_MOV_B32_e32 32, implicit $exec
     S_ENDPGM 0
 
   bb.1:
     successors: %bb.3, %bb.4
     liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
 
     renamable $vgpr2 = V_MOV_B32_e32 15, implicit $exec
     $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
     $vgpr1 = V_MOV_B32_e32 $sgpr1, implicit $exec, implicit $sgpr0_sgpr1, implicit $exec
     renamable $sgpr2_sgpr3 = S_OR_SAVEEXEC_B64 killed renamable $sgpr2_sgpr3, implicit-def $exec, implicit-def $scc, implicit $exec
     $exec = S_XOR_B64 $exec, renamable $sgpr2_sgpr3, implicit-def $scc
-    SI_MASK_BRANCH %bb.4, implicit $exec
+    S_CBRANCH_EXECZ %bb.4, implicit $exec
     S_BRANCH %bb.3
 
   bb.3:
     liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
 
     renamable $vgpr2 = V_MOV_B32_e32 8, implicit $exec
     $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr0_sgpr1
     $vgpr1 = V_MOV_B32_e32 $sgpr1, implicit $exec, implicit killed $sgpr0_sgpr1, implicit $exec
     $exec = S_OR_B64 $exec, killed renamable $sgpr2_sgpr3, implicit-def $scc
     renamable $vgpr0 = V_MOV_B32_e32 32, implicit $exec
     S_ENDPGM 0
 
 ...
 
 ---
 name: skip_branch_taildup_ret
 body:             |
   ; CHECK-LABEL: name: skip_branch_taildup_ret
   ; CHECK: bb.0:
   ; CHECK:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
   ; CHECK:   S_WAITCNT 0
   ; CHECK:   V_CMP_NE_U32_e32 0, killed $vgpr0, implicit-def $vcc, implicit $exec
   ; CHECK:   $sgpr6_sgpr7 = S_AND_SAVEEXEC_B64 $vcc, implicit-def $exec, implicit-def $scc, implicit $exec
   ; CHECK:   renamable $sgpr6_sgpr7 = S_XOR_B64 $exec, killed renamable $sgpr6_sgpr7, implicit-def dead $scc
-  ; CHECK:   SI_MASK_BRANCH %bb.1, implicit $exec
   ; CHECK:   S_CBRANCH_EXECZ %bb.1, implicit $exec
   ; CHECK:   S_BRANCH %bb.3
   ; CHECK: bb.1:
   ; CHECK:   successors: %bb.4(0x40000000), %bb.2(0x40000000)
   ; CHECK:   renamable $sgpr6_sgpr7 = S_OR_SAVEEXEC_B64 killed renamable $sgpr6_sgpr7, implicit-def $exec, implicit-def $scc, implicit $exec
   ; CHECK:   $exec = S_XOR_B64 $exec, renamable $sgpr6_sgpr7, implicit-def $scc
-  ; CHECK:   SI_MASK_BRANCH %bb.2, implicit $exec
   ; CHECK:   S_CBRANCH_EXECZ %bb.2, implicit $exec
   ; CHECK:   S_BRANCH %bb.4
   ; CHECK: bb.2:
   ; CHECK:   $exec = S_OR_B64 $exec, killed renamable $sgpr6_sgpr7, implicit-def $scc
   ; CHECK:   renamable $vgpr0 = V_MOV_B32_e32 32, implicit $exec
   ; CHECK:   S_SETPC_B64_return $sgpr30_sgpr31
   ; CHECK: bb.3:
   ; CHECK:   successors: %bb.4(0x40000000), %bb.2(0x40000000)
   ; CHECK:   renamable $vgpr0 = V_MOV_B32_e32 15, implicit $exec
   ; CHECK:   renamable $sgpr6_sgpr7 = S_OR_SAVEEXEC_B64 killed renamable $sgpr6_sgpr7, implicit-def $exec, implicit-def $scc, implicit $exec
   ; CHECK:   $exec = S_XOR_B64 $exec, renamable $sgpr6_sgpr7, implicit-def $scc
-  ; CHECK:   SI_MASK_BRANCH %bb.2, implicit $exec
   ; CHECK:   S_CBRANCH_EXECZ %bb.2, implicit $exec
   ; CHECK: bb.4:
   ; CHECK:   renamable $vgpr0 = V_MOV_B32_e32 8, implicit $exec
   ; CHECK:   $exec = S_OR_B64 $exec, killed renamable $sgpr6_sgpr7, implicit-def $scc
   ; CHECK:   renamable $vgpr0 = V_MOV_B32_e32 32, implicit $exec
   ; CHECK:   S_SETPC_B64_return $sgpr30_sgpr31
   bb.0:
     successors: %bb.1, %bb.2
     liveins: $vgpr0, $sgpr30_sgpr31, $vgpr1_vgpr2
 
     S_WAITCNT 0
     V_CMP_NE_U32_e32 0, killed $vgpr0, implicit-def $vcc, implicit $exec
     $sgpr6_sgpr7 = S_AND_SAVEEXEC_B64 $vcc, implicit-def $exec, implicit-def $scc, implicit $exec
     renamable $sgpr6_sgpr7 = S_XOR_B64 $exec, killed renamable $sgpr6_sgpr7, implicit-def dead $scc
-    SI_MASK_BRANCH %bb.2, implicit $exec
+    S_CBRANCH_EXECZ %bb.2, implicit $exec
     S_BRANCH %bb.1
 
   bb.2:
     successors: %bb.3, %bb.4
     liveins: $sgpr6_sgpr7, $sgpr30_sgpr31, $vgpr1_vgpr2
 
     renamable $sgpr6_sgpr7 = S_OR_SAVEEXEC_B64 killed renamable $sgpr6_sgpr7, implicit-def $exec, implicit-def $scc, implicit $exec
     $exec = S_XOR_B64 $exec, renamable $sgpr6_sgpr7, implicit-def $scc
-    SI_MASK_BRANCH %bb.4, implicit $exec
+    S_CBRANCH_EXECZ %bb.4, implicit $exec
     S_BRANCH %bb.3
 
   bb.4:
     liveins: $sgpr6_sgpr7, $sgpr30_sgpr31
 
     $exec = S_OR_B64 $exec, killed renamable $sgpr6_sgpr7, implicit-def $scc
     renamable $vgpr0 = V_MOV_B32_e32 32, implicit $exec
     S_SETPC_B64_return $sgpr30_sgpr31
 
   bb.1:
     successors: %bb.3, %bb.4
     liveins: $sgpr6_sgpr7, $sgpr30_sgpr31, $vgpr1_vgpr2
 
     renamable $vgpr0 = V_MOV_B32_e32 15, implicit $exec
     renamable $sgpr6_sgpr7 = S_OR_SAVEEXEC_B64 killed renamable $sgpr6_sgpr7, implicit-def $exec, implicit-def $scc, implicit $exec
     $exec = S_XOR_B64 $exec, renamable $sgpr6_sgpr7, implicit-def $scc
-    SI_MASK_BRANCH %bb.4, implicit $exec
+    S_CBRANCH_EXECZ %bb.4, implicit $exec
     S_BRANCH %bb.3
 
   bb.3:
     liveins: $sgpr6_sgpr7, $sgpr30_sgpr31, $vgpr1_vgpr2
 
     renamable $vgpr0 = V_MOV_B32_e32 8, implicit $exec
     $exec = S_OR_B64 $exec, killed renamable $sgpr6_sgpr7, implicit-def $scc
     renamable $vgpr0 = V_MOV_B32_e32 32, implicit $exec
     S_SETPC_B64_return $sgpr30_sgpr31
 
 ...

llvm/test/CodeGen/AMDGPU/spill-before-exec.mir

bb.0:
     %26:sgpr_128 = COPY %1
     S_BRANCH %bb.1
 
   bb.1:
     liveins: $sgpr96_sgpr97, $sgpr98_sgpr99, $sgpr102_sgpr103
 
     %0:sreg_64 = S_OR_SAVEEXEC_B64 $sgpr96_sgpr97, implicit-def $exec, implicit-def $scc, implicit $exec
     $exec = S_XOR_B64_term $exec, %0, implicit-def $scc
-    SI_MASK_BRANCH %bb.3, implicit $exec
+    S_CBRANCH_EXECZ %bb.3, implicit $exec
     S_BRANCH %bb.2
 
   bb.2:
     liveins: $sgpr98_sgpr99, $sgpr102_sgpr103
 
     %0:sreg_64 = S_OR_SAVEEXEC_B64 $sgpr98_sgpr99, implicit-def $exec, implicit-def $scc, implicit $exec
     $exec = S_XOR_B64_term $exec, %0, implicit-def $scc
-    SI_MASK_BRANCH %bb.3, implicit $exec
+    S_CBRANCH_EXECZ %bb.3, implicit $exec
     S_BRANCH %bb.4
 
   bb.3:
     liveins: $sgpr102_sgpr103
 
     %0:sreg_64 = S_OR_SAVEEXEC_B64 $sgpr102_sgpr103, implicit-def $exec, implicit-def $scc, implicit $exec
     $exec = S_XOR_B64_term $exec, %0, implicit-def $scc
     S_BRANCH %bb.4

llvm/test/CodeGen/AMDGPU/subreg-split-live-in-error.mir

bb.15:
     %42:sreg_64 = V_CMP_LE_F32_e64 0, 0, 0, %41, 0, implicit $mode, implicit $exec
     %43:sreg_64 = V_CMP_GE_F32_e64 0, 1065353216, 0, %41, 0, implicit $mode, implicit $exec
     %44:sreg_64 = S_AND_B64 %43, %43, implicit-def dead $scc
     %45:sreg_64 = S_AND_B64 %42, %42, implicit-def dead $scc
     %46:sreg_64 = S_AND_B64 %45, %44, implicit-def dead $scc
     %47:sreg_64 = COPY $exec, implicit-def $exec
     %48:sreg_64 = S_AND_B64 %47, %46, implicit-def dead $scc
     $exec = S_MOV_B64_term %48
-    SI_MASK_BRANCH %bb.18, implicit $exec
+    S_CBRANCH_EXECZ %bb.18, implicit $exec
     S_BRANCH %bb.16
 
   bb.16:
     successors: %bb.18(0x80000000)
     S_BRANCH %bb.18
 
   bb.17:
     successors: %bb.21(0x40000000), %bb.23(0x40000000)

llvm/test/CodeGen/AMDGPU/undefined-physreg-sgpr-spill.mir

bb.0:
     $vgpr1 = GLOBAL_LOAD_UBYTE killed $vgpr1_vgpr2, 0, 0, 0, 0, 0, implicit $exec :: (non-temporal dereferenceable invariant load 1 from `i1 addrspace(4)* undef`)
     $vcc = V_CMP_NE_U32_e64 0, $vgpr0, implicit $exec
     $sgpr0_sgpr1 = V_CMP_EQ_U32_e64 1, killed $vgpr1, implicit $exec
     $vgpr1 = V_CNDMASK_B32_e64 0, 0, 0, -1, killed $sgpr0_sgpr1, implicit $exec
     $sgpr0_sgpr1 = COPY $exec, implicit-def $exec
     SI_SPILL_S64_SAVE $sgpr0_sgpr1, %stack.0, implicit $exec, implicit $sgpr8_sgpr9_sgpr10_sgpr11, implicit $sgpr13, implicit-def dead $m0 :: (store 8 into %stack.0, align 4, addrspace 5)
     $sgpr2_sgpr3 = S_AND_B64 killed $sgpr0_sgpr1, killed $vcc, implicit-def dead $scc
     $exec = S_MOV_B64_term killed $sgpr2_sgpr3
-    SI_MASK_BRANCH %bb.2, implicit $exec
+    S_CBRANCH_EXECZ %bb.2, implicit $exec
     S_BRANCH %bb.1
 
   bb.1:
     successors: %bb.3(0x80000000)
     liveins: $vgpr0, $vgpr1
 
     $sgpr2_sgpr3 = S_MOV_B64 0
     $vgpr2 = V_MOV_B32_e32 0, implicit $exec
bb.0:
     $vgpr1 = GLOBAL_LOAD_UBYTE killed $vgpr1_vgpr2, 0, 0, 0, 0, 0, implicit $exec :: (non-temporal dereferenceable invariant load 1 from `i1 addrspace(4)* undef`)
     $vcc = V_CMP_NE_U32_e64 0, $vgpr0, implicit $exec
     $sgpr0_sgpr1 = V_CMP_EQ_U32_e64 1, killed $vgpr1, implicit $exec
     $vgpr1 = V_CNDMASK_B32_e64 0, 0, 0, -1, killed $sgpr0_sgpr1, implicit $exec
     $sgpr0_sgpr1 = COPY $exec, implicit-def $exec
     $sgpr2_sgpr3 = S_AND_B64 $sgpr0_sgpr1, killed $vcc, implicit-def dead $scc
     SI_SPILL_S64_SAVE killed $sgpr0_sgpr1, %stack.0, implicit $exec, implicit $sgpr8_sgpr9_sgpr10_sgpr11, implicit $sgpr13, implicit-def dead $m0 :: (store 8 into %stack.0, align 4, addrspace 5)
     $exec = S_MOV_B64_term killed $sgpr2_sgpr3
-    SI_MASK_BRANCH %bb.2, implicit $exec
+    S_CBRANCH_EXECZ %bb.2, implicit $exec
     S_BRANCH %bb.1
 
   bb.1:
     successors: %bb.3(0x80000000)
     liveins: $vgpr0, $vgpr1
 
     $sgpr2_sgpr3 = S_MOV_B64 0
     $vgpr2 = V_MOV_B32_e32 0, implicit $exec