Split into D94746, D94747 and D94748.

Superseded by D94311.

Superseded by D94311.

LGTM

• Address reviewer comments
• Change tests to use more indicative S_AND_B32

In D88777#2486221, @foad wrote:

Patch looks fine to me. Why is it useful to terminate on scc0 instead of scc1, or is it an arbitrary choice? Could you give a slightly more realistic example of how it would be used? Your tests all have:

S_CMP_EQ_U32 killed $sgpr0, 0, implicit-def $scc
SI_EARLY_TERMINATE_SCC0 implicit $scc, implicit $exec

which will terminate early if sgpr0 is not 0. Is the idea that this would be used when we're just about to AND sgpr0 into exec?

Rebase

Rebase

Rebase

Rebase

Ping

Ping

Heavily rewritten:

• Use/reuse single virtual register for live mask. This removes need for PHIs and live mask register tracking. Assumes WQM is running non-SSA. (Supporting non-SSA and SSA operation would bloat code.)
• Live mask tracks all kills and demotes.
• Live mask manipulations terminate shader if all lanes are killed, even in non-uniform control flow.
• Move all kill lowering to WQM pass, this simplifies later passes and avoids duplication when updating live mask. Removes the need for "clean up" operations.
• WQM pass always modifies shader if it has any kills or demotes, even if there is no WQM.

• Add tests, but these depend on D91066

• Address reviewer comments.
• Rebase.

• Invert condition.
• Add tests against a symbol.

• Remove restrictions on types of shader where early terminate can occur.

Superseded by 419168d9381959ec6850e9e87aff9d062b68ef4b

• Rebase

In D89804#2343814, @Flakebi wrote:

Changed to use TableIdx.

• Rebase
• Fix markDefs to iterate all operands of MI
• Remove fix up for SI_ELSE as this is no longer required
• Remove elimination of trivial SGPR to SGPR WWM copies (this adds cruft in atomic optimizer tests)

Thanks, I was going to make the same change, but you beat me to it.
Slight nit. since we use Width - 1 three times, for readability I think we should just declare a new variable for it (TableIdx?).

• Address review comments

• Consistently use Register type.

• Rebase

• Remove peephole
• Pre-commit test

In D89187#2331204, @nhaehnle wrote:

How about splitting this change into two parts? Limit this change to generating mixes of 64- and 32-bit moves, and then separately consider what to do about those moves of registers where subregisters are overwritten immediately.

• Use std::array for map array.

• Use std::array and tidy up initialisation.
• Fix number of rows in table.

Having addressed the comments could I get a second quick read before I submit?
Thanks.

Address reviews comments:

• Fix initialiser to use AMDGPU::NoSubRegister and not memset.
• Add comment on mapping array.

Address reviewer comments.

This has been superseded by front-end work in graphics compiler.

To motivate the peephole.
This pattern effects 2% of graphics shaders on GFX9, and nearly 7% on GFX10.
On average we save ~1.5 instructions per effected shader.
On some VulkanCTS tests the savings are much higher.
Given the relatively low gain, I assume it was not worth introducing a new peephole pass, and took this approach to address the duplicate s_mov instructions at the point of generation (when they cheapest to spot).

• Merge code generation loops to avoid needing to generate work list
• Fix potential issue when all elements of copy are overwritten
• Fix test file location error

• Fix assumptions about SCC live intervals which are not valid late in compilation.

• Address comments about pass insertion.
• Fix bug in removal of trivial SGPR copies from WWM.