This is an archive of the discontinued LLVM Phabricator instance.

[AArch64] [DFSan] Adding support of AArch64 for DFSan
ClosedPublic

Authored by sdkie on May 10 2015, 10:30 AM.

Details

Reviewers
kcc
pcc
Summary

This patch require enabling DFSan in Clang,
and also adding ShadowPtrMask in LLVM.
I will also submit those patches for review.

Diff Detail

Repository
rL LLVM

Event Timeline

sdkie updated this revision to Diff 25434.May 10 2015, 10:30 AM
sdkie retitled this revision from to [AArch64] [DFSan] Adding support of AArch64 for DFSan.
sdkie updated this object.
sdkie edited the test plan for this revision. (Show Details)
sdkie added reviewers: pcc, kcc.
sdkie set the repository for this revision to rL LLVM.
sdkie added a subscriber: Unknown Object (MLST).May 10 2015, 10:30 AM
sdkie updated this revision to Diff 25567.May 12 2015, 3:27 AM
sdkie removed rL LLVM as the repository for this revision.

AAarch64 has only 39 addressable bits not like MIPS64 which has 40 addressable bits.

In D9649#170955, @sdkie wrote:

AAarch64 has only 39 addressable bits not like MIPS64 which has 40 addressable bits.

Not all AArch64 is 39bits, some are 42bits.

We had this discussion in the ASAN side, and allowing 42bits made it work on those machines while it didn't increase memory footprint that much for 39bits, so assuming 42 was preferred. If here we have the same case, I'd guess taking the same assumption would be the way to go.

Please check with Kostya fist, though.

cheers,
--renato

sdkie added a comment.May 12 2015, 3:41 AM

@rengolin

AAarch64 has only 39 addressable bits not like MIPS64 which has 40 addressable bits.

Not all AArch64 is 39bits, some are 42bits.

We had this discussion in the ASAN side, and allowing 42bits made it work on those machines while it didn't increase memory footprint that much for 39bits, so assuming 42 was preferred. If here we have the same case, I'd guess taking the same assumption would be the way to go.

In ASAN code I see

kAArch64_ShadowOffset64 = 1ULL << 36;

which will limit the upper memory to 0x7fffffffff.

In D9649#170980, @sdkie wrote:

In ASAN code I see
kAArch64_ShadowOffset64 = 1ULL << 36;
which will limit the upper memory to 0x7fffffffff.

Yes, this has been discussed, but not applied. :)

I think it should be safe to assume 39bits for now, and let the discussion flow on all three ASAN/TSAN/DFSAN later to increase that value. Just giving you the heads up.

cheers,
--renato

@kcc @pcc Did you got time to review my patches?

pcc accepted this revision.Jul 6 2015, 2:11 PM
pcc edited edge metadata.

LGTM

This revision is now accepted and ready to land.Jul 6 2015, 2:11 PM
Eugene.Zelenko added a subscriber: Eugene.Zelenko.

Committed in rL243688, probably independent development.