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[RISCV] Add implementation of targetShrinkDemandedConstant to optimize AND immediates.
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Authored by craig.topper on Jan 13 2021, 12:19 PM.

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Summary

SimplifyDemandedBits can remove set bits from immediates from instructions
like AND/OR/XOR. This can prevent them from being efficiently
codegened on RISCV.

This adds an initial version that tries to keep or form 12 bit
sign extended immediates for AND operations to enable use of ANDI.
If that doesn't work we'll try to create a 32 bit sign extended immediate
to use LUI+ADDIW.

More optimizations are possible for different size immediates or
different operations. But this is a good starting point that already
has test coverage.

Diff Detail

Event Timeline

craig.topper created this revision.Jan 13 2021, 12:19 PM
craig.topper requested review of this revision.Jan 13 2021, 12:19 PM
Herald added a project: Restricted Project. · View Herald TranscriptJan 13 2021, 12:19 PM
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Fix typo in comment.

craig.topper edited the summary of this revision. (Show Details)Jan 13 2021, 12:48 PM

-Add support for forming 32 signed immediates as well. That also had good test coverage.

craig.topper edited the summary of this revision. (Show Details)Jan 13 2021, 1:56 PM
lenary resigned from this revision.Jan 14 2021, 9:27 AM
frasercrmck added inline comments.Jan 15 2021, 7:51 AM
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
1904

As the linter above suggests, this code formatting looks off.

craig.topper retitled this revision from [RISCV] Add implementation of targetShrinkDemandeConstant to optimize AND immediates. to [RISCV] Add implementation of targetShrinkDemandedConstant to optimize AND immediates..Jan 15 2021, 9:12 AM

Fix formatting

frasercrmck accepted this revision.Jan 15 2021, 9:19 AM

LGTM. I hadn't come across this function before so thanks for the intro.

This revision is now accepted and ready to land.Jan 15 2021, 9:19 AM