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Differential D94062

[RISCV][NFC] Add new test cases for mul
ClosedPublic

Authored by benshi001 on Jan 4 2021, 10:54 PM.

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Reviewers
craig.topper
asb
lenary
luismarques
MaskRay

Diff Detail

Event Timeline

benshi001 created this revision.Jan 4 2021, 10:54 PM
Herald added subscribers: frasercrmck, NickHung, evandro and 23 others. · View Herald TranscriptJan 4 2021, 10:54 PM
benshi001 requested review of this revision.Jan 4 2021, 10:54 PM
Herald added a project: Restricted Project. · View Herald TranscriptJan 4 2021, 10:54 PM
Herald added subscribers: llvm-commits, MaskRay. · View Herald Transcript
benshi001 mentioned this in D93619: [RISCV] Optimize multiplication with constant.Jan 4 2021, 10:55 PM
benshi001 retitled this revision from [RISCV] Add a new test case of mul to [RISCV][NFC] Add new test cases for mul.Jan 4 2021, 10:58 PM
benshi001 added a reviewer: MaskRay.
Harbormaster completed remote builds in B83983: Diff 314507.Jan 4 2021, 11:31 PM
craig.topper accepted this revision.Jan 5 2021, 8:45 PM

LGTM

This revision is now accepted and ready to land.Jan 5 2021, 8:45 PM
benshi001 closed this revision.Jan 6 2021, 3:09 AM

closed by https://github.com/llvm/llvm-project/commit/351a45ca73de3ec4524d2194674e2a92f8b7d9b5

jrtc27 added a child revision: D93619: [RISCV] Optimize multiplication with constant.Jan 6 2021, 10:01 PM

Revision Contents

PathSize
llvm/
test/
CodeGen/
RISCV/
204 lines

Diff 314507

llvm/test/CodeGen/RISCV/mul.ll

Show First 20 Lines • Show All 966 Lines • ▼ Show 20 Lines
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: lui a1, 1048575 ; RV64IM-NEXT: lui a1, 1048575
; RV64IM-NEXT: addiw a1, a1, 256 ; RV64IM-NEXT: addiw a1, a1, 256
; RV64IM-NEXT: mul a0, a0, a1 ; RV64IM-NEXT: mul a0, a0, a1
; RV64IM-NEXT: ret ; RV64IM-NEXT: ret
%1 = mul i64 %a, -3840 %1 = mul i64 %a, -3840
ret i64 %1 ret i64 %1
} }
define i128 @muli128_m3840(i128 %a) nounwind {
; RV32I-LABEL: muli128_m3840:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -64
; RV32I-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 56(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a3, 0(a1)
; RV32I-NEXT: lw a2, 4(a1)
; RV32I-NEXT: lw a4, 8(a1)
; RV32I-NEXT: lw a1, 12(a1)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: addi a0, zero, -1
; RV32I-NEXT: sw a0, 20(sp)
; RV32I-NEXT: sw a0, 16(sp)
; RV32I-NEXT: sw a0, 12(sp)
; RV32I-NEXT: lui a0, 1048575
; RV32I-NEXT: addi a0, a0, 256
; RV32I-NEXT: sw a0, 8(sp)
; RV32I-NEXT: sw a1, 36(sp)
; RV32I-NEXT: sw a4, 32(sp)
; RV32I-NEXT: sw a2, 28(sp)
; RV32I-NEXT: addi a0, sp, 40
; RV32I-NEXT: addi a1, sp, 24
; RV32I-NEXT: addi a2, sp, 8
; RV32I-NEXT: sw a3, 24(sp)
; RV32I-NEXT: call __multi3@plt
; RV32I-NEXT: lw a0, 52(sp)
; RV32I-NEXT: lw a1, 48(sp)
; RV32I-NEXT: lw a2, 44(sp)
; RV32I-NEXT: lw a3, 40(sp)
; RV32I-NEXT: sw a0, 12(s0)
; RV32I-NEXT: sw a1, 8(s0)
; RV32I-NEXT: sw a2, 4(s0)
; RV32I-NEXT: sw a3, 0(s0)
; RV32I-NEXT: lw s0, 56(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 64
; RV32I-NEXT: ret
;
; RV32IM-LABEL: muli128_m3840:
; RV32IM: # %bb.0:
; RV32IM-NEXT: addi sp, sp, -64
; RV32IM-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
; RV32IM-NEXT: sw s0, 56(sp) # 4-byte Folded Spill
; RV32IM-NEXT: lw a3, 0(a1)
; RV32IM-NEXT: lw a2, 4(a1)
; RV32IM-NEXT: lw a4, 8(a1)
; RV32IM-NEXT: lw a1, 12(a1)
; RV32IM-NEXT: mv s0, a0
; RV32IM-NEXT: addi a0, zero, -1
; RV32IM-NEXT: sw a0, 20(sp)
; RV32IM-NEXT: sw a0, 16(sp)
; RV32IM-NEXT: sw a0, 12(sp)
; RV32IM-NEXT: lui a0, 1048575
; RV32IM-NEXT: addi a0, a0, 256
; RV32IM-NEXT: sw a0, 8(sp)
; RV32IM-NEXT: sw a1, 36(sp)
; RV32IM-NEXT: sw a4, 32(sp)
; RV32IM-NEXT: sw a2, 28(sp)
; RV32IM-NEXT: addi a0, sp, 40
; RV32IM-NEXT: addi a1, sp, 24
; RV32IM-NEXT: addi a2, sp, 8
; RV32IM-NEXT: sw a3, 24(sp)
; RV32IM-NEXT: call __multi3@plt
; RV32IM-NEXT: lw a0, 52(sp)
; RV32IM-NEXT: lw a1, 48(sp)
; RV32IM-NEXT: lw a2, 44(sp)
; RV32IM-NEXT: lw a3, 40(sp)
; RV32IM-NEXT: sw a0, 12(s0)
; RV32IM-NEXT: sw a1, 8(s0)
; RV32IM-NEXT: sw a2, 4(s0)
; RV32IM-NEXT: sw a3, 0(s0)
; RV32IM-NEXT: lw s0, 56(sp) # 4-byte Folded Reload
; RV32IM-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
; RV32IM-NEXT: addi sp, sp, 64
; RV32IM-NEXT: ret
;
; RV64I-LABEL: muli128_m3840:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: lui a2, 1048575
; RV64I-NEXT: addiw a2, a2, 256
; RV64I-NEXT: addi a3, zero, -1
; RV64I-NEXT: call __multi3@plt
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
; RV64IM-LABEL: muli128_m3840:
; RV64IM: # %bb.0:
; RV64IM-NEXT: lui a2, 1048575
; RV64IM-NEXT: addiw a2, a2, 256
; RV64IM-NEXT: mul a1, a1, a2
; RV64IM-NEXT: mulhu a3, a0, a2
; RV64IM-NEXT: sub a3, a3, a0
; RV64IM-NEXT: add a1, a3, a1
; RV64IM-NEXT: mul a0, a0, a2
; RV64IM-NEXT: ret
%1 = mul i128 %a, -3840
ret i128 %1
}
define i128 @muli128_m63(i128 %a) nounwind {
; RV32I-LABEL: muli128_m63:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -64
; RV32I-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 56(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a3, 0(a1)
; RV32I-NEXT: lw a2, 4(a1)
; RV32I-NEXT: lw a4, 8(a1)
; RV32I-NEXT: lw a1, 12(a1)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: addi a0, zero, -1
; RV32I-NEXT: sw a0, 20(sp)
; RV32I-NEXT: sw a0, 16(sp)
; RV32I-NEXT: sw a0, 12(sp)
; RV32I-NEXT: addi a0, zero, -63
; RV32I-NEXT: sw a0, 8(sp)
; RV32I-NEXT: sw a1, 36(sp)
; RV32I-NEXT: sw a4, 32(sp)
; RV32I-NEXT: sw a2, 28(sp)
; RV32I-NEXT: addi a0, sp, 40
; RV32I-NEXT: addi a1, sp, 24
; RV32I-NEXT: addi a2, sp, 8
; RV32I-NEXT: sw a3, 24(sp)
; RV32I-NEXT: call __multi3@plt
; RV32I-NEXT: lw a0, 52(sp)
; RV32I-NEXT: lw a1, 48(sp)
; RV32I-NEXT: lw a2, 44(sp)
; RV32I-NEXT: lw a3, 40(sp)
; RV32I-NEXT: sw a0, 12(s0)
; RV32I-NEXT: sw a1, 8(s0)
; RV32I-NEXT: sw a2, 4(s0)
; RV32I-NEXT: sw a3, 0(s0)
; RV32I-NEXT: lw s0, 56(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 64
; RV32I-NEXT: ret
;
; RV32IM-LABEL: muli128_m63:
; RV32IM: # %bb.0:
; RV32IM-NEXT: addi sp, sp, -64
; RV32IM-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
; RV32IM-NEXT: sw s0, 56(sp) # 4-byte Folded Spill
; RV32IM-NEXT: lw a3, 0(a1)
; RV32IM-NEXT: lw a2, 4(a1)
; RV32IM-NEXT: lw a4, 8(a1)
; RV32IM-NEXT: lw a1, 12(a1)
; RV32IM-NEXT: mv s0, a0
; RV32IM-NEXT: addi a0, zero, -1
; RV32IM-NEXT: sw a0, 20(sp)
; RV32IM-NEXT: sw a0, 16(sp)
; RV32IM-NEXT: sw a0, 12(sp)
; RV32IM-NEXT: addi a0, zero, -63
; RV32IM-NEXT: sw a0, 8(sp)
; RV32IM-NEXT: sw a1, 36(sp)
; RV32IM-NEXT: sw a4, 32(sp)
; RV32IM-NEXT: sw a2, 28(sp)
; RV32IM-NEXT: addi a0, sp, 40
; RV32IM-NEXT: addi a1, sp, 24
; RV32IM-NEXT: addi a2, sp, 8
; RV32IM-NEXT: sw a3, 24(sp)
; RV32IM-NEXT: call __multi3@plt
; RV32IM-NEXT: lw a0, 52(sp)
; RV32IM-NEXT: lw a1, 48(sp)
; RV32IM-NEXT: lw a2, 44(sp)
; RV32IM-NEXT: lw a3, 40(sp)
; RV32IM-NEXT: sw a0, 12(s0)
; RV32IM-NEXT: sw a1, 8(s0)
; RV32IM-NEXT: sw a2, 4(s0)
; RV32IM-NEXT: sw a3, 0(s0)
; RV32IM-NEXT: lw s0, 56(sp) # 4-byte Folded Reload
; RV32IM-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
; RV32IM-NEXT: addi sp, sp, 64
; RV32IM-NEXT: ret
;
; RV64I-LABEL: muli128_m63:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a2, zero, -63
; RV64I-NEXT: addi a3, zero, -1
; RV64I-NEXT: call __multi3@plt
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
; RV64IM-LABEL: muli128_m63:
; RV64IM: # %bb.0:
; RV64IM-NEXT: slli a2, a1, 6
; RV64IM-NEXT: sub a1, a1, a2
; RV64IM-NEXT: addi a2, zero, -63
; RV64IM-NEXT: mulhu a2, a0, a2
; RV64IM-NEXT: sub a2, a2, a0
; RV64IM-NEXT: add a1, a2, a1
; RV64IM-NEXT: slli a2, a0, 6
; RV64IM-NEXT: sub a0, a0, a2
; RV64IM-NEXT: ret
%1 = mul i128 %a, -63
ret i128 %1
}