[ARM] Handle any extend whilst lowering addw/addl/subw/subl

[dmgreen]

Summary

Same as D93833, use zanyext to treat any_extends as zero extends during lowering to create addw/addl/subw/subl nodes.

[RKSimon]

@dmgreen I hit a similar problem on D56387 where certain VMULL patterns failed when SimplifyDemandedBits simplified a zext/sext to just an aext

[dmgreen]

Hello. Yeah those are related. I was using an AND here to get the same effect, but this is more likely to come up from the truncs in that patch in practice. D93834 is the mull part of handling any_extends. (It unfortunately doesn't entirely fix both the cases there because we end up turning one of the any_extends into a zext load, and are left with a smull of a sext load and zext load).

Long story short - I was trying to port the HADD code from AArch64 so it could be used in MVE too, but in a slightly different way to how they are currently done in the aarch64 backend. Instead of starting at a trunk it started at the shift like MULH lowering. Unfortunately llvm loves turning arithmetic shifts into logical shifts, but it's only valid to match to a hadd in that case if the top bits are not demanded. Which is where I saw D56387, to mark the top bits as not demanded. But we don't currently handle the any extends well in either Arm or AArch64.

I may try and do that HADD lowering differently, maybe more like is done at the moment. It needs some MVE fixes first in any rate, But I figured this was worth doing on it's own. And I believe that treating anyextend as a zext is always fine for lowering (if not always optimal, if a sext/anyextend pair could be folded too).

[RKSimon]

LGTM after D93833 has landed

[dmgreen]

Thanks.

llvm/lib/Target/ARM/ARMInstrNEON.td

def  VADDhd   : N3VD<0, 0, 0b01, 0b1101, 0, IIC_VBIND, "vadd", "f16",
                 Requires<[HasNEON,HasFullFP16]>;
 def  VADDhq   : N3VQ<0, 0, 0b01, 0b1101, 0, IIC_VBINQ, "vadd", "f16",
                      v8f16, v8f16, fadd, 1>,
                 Requires<[HasNEON,HasFullFP16]>;
 //   VADDL    : Vector Add Long (Q = D + D)
 defm VADDLs   : N3VLExt_QHS<0,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
                             "vaddl", "s", add, sext, 1>;
 defm VADDLu   : N3VLExt_QHS<1,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
-                            "vaddl", "u", add, zext, 1>;
+                            "vaddl", "u", add, zanyext, 1>;
 //   VADDW    : Vector Add Wide (Q = Q + D)
 defm VADDWs   : N3VW_QHS<0,1,0b0001,0, "vaddw", "s", add, sext, 0>;
-defm VADDWu   : N3VW_QHS<1,1,0b0001,0, "vaddw", "u", add, zext, 0>;
+defm VADDWu   : N3VW_QHS<1,1,0b0001,0, "vaddw", "u", add, zanyext, 0>;
 //   VHADD    : Vector Halving Add
 defm VHADDs   : N3VInt_QHS<0, 0, 0b0000, 0, N3RegFrm,
                            IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
                            "vhadd", "s", int_arm_neon_vhadds, 1>;
 defm VHADDu   : N3VInt_QHS<1, 0, 0b0000, 0, N3RegFrm,
                            IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
                            "vhadd", "u", int_arm_neon_vhaddu, 1>;
 //   VRHADD   : Vector Rounding Halving Add
def  VSUBhd   : N3VD<0, 0, 0b11, 0b1101, 0, IIC_VBIND, "vsub", "f16",
                 Requires<[HasNEON,HasFullFP16]>;
 def  VSUBhq   : N3VQ<0, 0, 0b11, 0b1101, 0, IIC_VBINQ, "vsub", "f16",
                      v8f16, v8f16, fsub, 0>,
                 Requires<[HasNEON,HasFullFP16]>;
 //   VSUBL    : Vector Subtract Long (Q = D - D)
 defm VSUBLs   : N3VLExt_QHS<0,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
                             "vsubl", "s", sub, sext, 0>;
 defm VSUBLu   : N3VLExt_QHS<1,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
-                            "vsubl", "u", sub, zext, 0>;
+                            "vsubl", "u", sub, zanyext, 0>;
 //   VSUBW    : Vector Subtract Wide (Q = Q - D)
 defm VSUBWs   : N3VW_QHS<0,1,0b0011,0, "vsubw", "s", sub, sext, 0>;
-defm VSUBWu   : N3VW_QHS<1,1,0b0011,0, "vsubw", "u", sub, zext, 0>;
+defm VSUBWu   : N3VW_QHS<1,1,0b0011,0, "vsubw", "u", sub, zanyext, 0>;
 //   VHSUB    : Vector Halving Subtract
 defm VHSUBs   : N3VInt_QHS<0, 0, 0b0010, 0, N3RegFrm,
                            IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
                            "vhsub", "s", int_arm_neon_vhsubs, 0>;
 defm VHSUBu   : N3VInt_QHS<1, 0, 0b0010, 0, N3RegFrm,
                            IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
                            "vhsub", "u", int_arm_neon_vhsubu, 0>;
 //   VQSUB    : Vector Saturing Subtract

llvm/test/CodeGen/ARM/vadd.ll

; CHECK-NEXT:    bx lr
   %tmp4 = zext <2 x i32> %B to <2 x i64>
   %tmp5 = add <2 x i64> %tmp3, %tmp4
   ret <2 x i64> %tmp5
 }
 
 define <8 x i16> @vaddla8(<8 x i8> %A, <8 x i8> %B) {
 ; CHECK-LABEL: vaddla8:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    vmovl.u8 q8, d1
-; CHECK-NEXT:    vmovl.u8 q9, d0
-; CHECK-NEXT:    vadd.i16 q0, q9, q8
+; CHECK-NEXT:    vaddl.u8 q0, d0, d1
 ; CHECK-NEXT:    vbic.i16 q0, #0xff00
 ; CHECK-NEXT:    bx lr
   %tmp3 = zext <8 x i8> %A to <8 x i16>
   %tmp4 = zext <8 x i8> %B to <8 x i16>
   %tmp5 = add <8 x i16> %tmp3, %tmp4
   %and = and <8 x i16> %tmp5, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
   ret <8 x i16> %and
 }
 
 define <4 x i32> @vaddla16(<4 x i16> %A, <4 x i16> %B) {
 ; CHECK-LABEL: vaddla16:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    vmovl.u16 q8, d1
-; CHECK-NEXT:    vmovl.u16 q9, d0
-; CHECK-NEXT:    vmov.i32 q10, #0xffff
-; CHECK-NEXT:    vadd.i32 q8, q9, q8
-; CHECK-NEXT:    vand q0, q8, q10
+; CHECK-NEXT:    vmov.i32 q8, #0xffff
+; CHECK-NEXT:    vaddl.u16 q9, d0, d1
+; CHECK-NEXT:    vand q0, q9, q8
 ; CHECK-NEXT:    bx lr
   %tmp3 = zext <4 x i16> %A to <4 x i32>
   %tmp4 = zext <4 x i16> %B to <4 x i32>
   %tmp5 = add <4 x i32> %tmp3, %tmp4
   %and = and <4 x i32> %tmp5, <i32 65535, i32 65535, i32 65535, i32 65535>
   ret <4 x i32> %and
 }
 
 define <2 x i64> @vaddla32(<2 x i32> %A, <2 x i32> %B) {
 ; CHECK-LABEL: vaddla32:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    vmovl.u32 q8, d1
-; CHECK-NEXT:    vmovl.u32 q9, d0
-; CHECK-NEXT:    vmov.i64 q10, #0xffffffff
-; CHECK-NEXT:    vadd.i64 q8, q9, q8
-; CHECK-NEXT:    vand q0, q8, q10
+; CHECK-NEXT:    vmov.i64 q8, #0xffffffff
+; CHECK-NEXT:    vaddl.u32 q9, d0, d1
+; CHECK-NEXT:    vand q0, q9, q8
 ; CHECK-NEXT:    bx lr
   %tmp3 = zext <2 x i32> %A to <2 x i64>
   %tmp4 = zext <2 x i32> %B to <2 x i64>
   %tmp5 = add <2 x i64> %tmp3, %tmp4
   %and = and <2 x i64> %tmp5, <i64 4294967295, i64 4294967295>
   ret <2 x i64> %and
 }
 
; CHECK-NEXT:    bx lr
   %tmp3 = zext <2 x i32> %B to <2 x i64>
   %tmp4 = add <2 x i64> %A, %tmp3
   ret <2 x i64> %tmp4
 }
 
 define <8 x i16> @vaddwa8(<8 x i16> %A, <8 x i8> %B) {
 ; CHECK-LABEL: vaddwa8:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    vmovl.u8 q8, d2
-; CHECK-NEXT:    vadd.i16 q0, q0, q8
+; CHECK-NEXT:    vaddw.u8 q0, q0, d2
 ; CHECK-NEXT:    vbic.i16 q0, #0xff00
 ; CHECK-NEXT:    bx lr
   %tmp3 = zext <8 x i8> %B to <8 x i16>
   %tmp4 = add <8 x i16> %A, %tmp3
   %and = and <8 x i16> %tmp4, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
   ret <8 x i16> %and
 }
 
 define <4 x i32> @vaddwa16(<4 x i32> %A, <4 x i16> %B) {
 ; CHECK-LABEL: vaddwa16:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    vmovl.u16 q8, d2
-; CHECK-NEXT:    vmov.i32 q9, #0xffff
-; CHECK-NEXT:    vadd.i32 q8, q0, q8
-; CHECK-NEXT:    vand q0, q8, q9
+; CHECK-NEXT:    vmov.i32 q8, #0xffff
+; CHECK-NEXT:    vaddw.u16 q9, q0, d2
+; CHECK-NEXT:    vand q0, q9, q8
 ; CHECK-NEXT:    bx lr
   %tmp3 = zext <4 x i16> %B to <4 x i32>
   %tmp4 = add <4 x i32> %A, %tmp3
   %and = and <4 x i32> %tmp4, <i32 65535, i32 65535, i32 65535, i32 65535>
   ret <4 x i32> %and
 }
 
 define <2 x i64> @vaddwa32(<2 x i64> %A, <2 x i32> %B) {
 ; CHECK-LABEL: vaddwa32:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    vmovl.u32 q8, d2
-; CHECK-NEXT:    vmov.i64 q9, #0xffffffff
-; CHECK-NEXT:    vadd.i64 q8, q0, q8
-; CHECK-NEXT:    vand q0, q8, q9
+; CHECK-NEXT:    vmov.i64 q8, #0xffffffff
+; CHECK-NEXT:    vaddw.u32 q9, q0, d2
+; CHECK-NEXT:    vand q0, q9, q8
 ; CHECK-NEXT:    bx lr
   %tmp3 = zext <2 x i32> %B to <2 x i64>
   %tmp4 = add <2 x i64> %A, %tmp3
   %and = and <2 x i64> %tmp4, <i64 4294967295, i64 4294967295>
   ret <2 x i64> %and
 }

llvm/test/CodeGen/ARM/vsub.ll

; CHECK-NEXT:    bx lr
   %tmp4 = zext <2 x i32> %B to <2 x i64>
   %tmp5 = sub <2 x i64> %tmp3, %tmp4
   ret <2 x i64> %tmp5
 }
 
 define <8 x i16> @vsubla8(<8 x i8> %A, <8 x i8> %B) {
 ; CHECK-LABEL: vsubla8:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    vmovl.u8 q8, d1
-; CHECK-NEXT:    vmovl.u8 q9, d0
-; CHECK-NEXT:    vsub.i16 q0, q9, q8
+; CHECK-NEXT:    vsubl.u8 q0, d0, d1
 ; CHECK-NEXT:    vbic.i16 q0, #0xff00
 ; CHECK-NEXT:    bx lr
   %tmp3 = zext <8 x i8> %A to <8 x i16>
   %tmp4 = zext <8 x i8> %B to <8 x i16>
   %tmp5 = sub <8 x i16> %tmp3, %tmp4
   %and = and <8 x i16> %tmp5, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
   ret <8 x i16> %and
 }
 
 define <4 x i32> @vsubla16(<4 x i16> %A, <4 x i16> %B) {
 ; CHECK-LABEL: vsubla16:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    vmovl.u16 q8, d1
-; CHECK-NEXT:    vmovl.u16 q9, d0
-; CHECK-NEXT:    vmov.i32 q10, #0xffff
-; CHECK-NEXT:    vsub.i32 q8, q9, q8
-; CHECK-NEXT:    vand q0, q8, q10
+; CHECK-NEXT:    vmov.i32 q8, #0xffff
+; CHECK-NEXT:    vsubl.u16 q9, d0, d1
+; CHECK-NEXT:    vand q0, q9, q8
 ; CHECK-NEXT:    bx lr
   %tmp3 = zext <4 x i16> %A to <4 x i32>
   %tmp4 = zext <4 x i16> %B to <4 x i32>
   %tmp5 = sub <4 x i32> %tmp3, %tmp4
   %and = and <4 x i32> %tmp5, <i32 65535, i32 65535, i32 65535, i32 65535>
   ret <4 x i32> %and
 }
 
 define <2 x i64> @vsubla32(<2 x i32> %A, <2 x i32> %B) {
 ; CHECK-LABEL: vsubla32:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    vmovl.u32 q8, d1
-; CHECK-NEXT:    vmovl.u32 q9, d0
-; CHECK-NEXT:    vmov.i64 q10, #0xffffffff
-; CHECK-NEXT:    vsub.i64 q8, q9, q8
-; CHECK-NEXT:    vand q0, q8, q10
+; CHECK-NEXT:    vmov.i64 q8, #0xffffffff
+; CHECK-NEXT:    vsubl.u32 q9, d0, d1
+; CHECK-NEXT:    vand q0, q9, q8
 ; CHECK-NEXT:    bx lr
   %tmp3 = zext <2 x i32> %A to <2 x i64>
   %tmp4 = zext <2 x i32> %B to <2 x i64>
   %tmp5 = sub <2 x i64> %tmp3, %tmp4
   %and = and <2 x i64> %tmp5, <i64 4294967295, i64 4294967295>
   ret <2 x i64> %and
 }
 
; CHECK-NEXT:    bx lr
   %tmp3 = zext <2 x i32> %B to <2 x i64>
   %tmp4 = sub <2 x i64> %A, %tmp3
   ret <2 x i64> %tmp4
 }
 
 define <8 x i16> @vsubwa8(<8 x i16> %A, <8 x i8> %B) {
 ; CHECK-LABEL: vsubwa8:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    vmovl.u8 q8, d2
-; CHECK-NEXT:    vsub.i16 q0, q0, q8
+; CHECK-NEXT:    vsubw.u8 q0, q0, d2
 ; CHECK-NEXT:    vbic.i16 q0, #0xff00
 ; CHECK-NEXT:    bx lr
   %tmp3 = zext <8 x i8> %B to <8 x i16>
   %tmp4 = sub <8 x i16> %A, %tmp3
   %and = and <8 x i16> %tmp4, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
   ret <8 x i16> %and
 }
 
 define <4 x i32> @vsubwa16(<4 x i32> %A, <4 x i16> %B) {
 ; CHECK-LABEL: vsubwa16:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    vmovl.u16 q8, d2
-; CHECK-NEXT:    vmov.i32 q9, #0xffff
-; CHECK-NEXT:    vsub.i32 q8, q0, q8
-; CHECK-NEXT:    vand q0, q8, q9
+; CHECK-NEXT:    vmov.i32 q8, #0xffff
+; CHECK-NEXT:    vsubw.u16 q9, q0, d2
+; CHECK-NEXT:    vand q0, q9, q8
 ; CHECK-NEXT:    bx lr
   %tmp3 = zext <4 x i16> %B to <4 x i32>
   %tmp4 = sub <4 x i32> %A, %tmp3
   %and = and <4 x i32> %tmp4, <i32 65535, i32 65535, i32 65535, i32 65535>
   ret <4 x i32> %and
 }
 
 define <2 x i64> @vsubwa32(<2 x i64> %A, <2 x i32> %B) {
 ; CHECK-LABEL: vsubwa32:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    vmovl.u32 q8, d2
-; CHECK-NEXT:    vmov.i64 q9, #0xffffffff
-; CHECK-NEXT:    vsub.i64 q8, q0, q8
-; CHECK-NEXT:    vand q0, q8, q9
+; CHECK-NEXT:    vmov.i64 q8, #0xffffffff
+; CHECK-NEXT:    vsubw.u32 q9, q0, d2
+; CHECK-NEXT:    vand q0, q9, q8
 ; CHECK-NEXT:    bx lr
   %tmp3 = zext <2 x i32> %B to <2 x i64>
   %tmp4 = sub <2 x i64> %A, %tmp3
   %and = and <2 x i64> %tmp4, <i64 4294967295, i64 4294967295>
   ret <2 x i64> %and
 }