[RISCV] Fix rounding mode in lowering of float operations

[sepavloff]

Summary

LLVM IR nodes like 'fadd', 'fmul' and other are assumed to execute in the
default floating-point environment, which in turn assumes rounding to
nearest even. In RISCV these operations were mapped to dynamic rounding
variants. This change fixes this by mapping to instructions with RNE
argument.

[jrtc27]

Doesn't this render fesetround useless?

llvm/test/CodeGen/RISCV/double-arith.ll

40

I don't understand this. Either you're changing CodeGen which should mean the assembly changes or you're changing the assembler which should instead be tested in the MC tests. You should almost never need to disassemble during a CodeGen test.

[sepavloff]

Changed test

[sepavloff]

In D93624#2465776, @jrtc27 wrote:

Doesn't this render fesetround useless?

No. fesetround sets dynamic rounding mode (register frm), which may be any mode. However in the case of non-default rounding mode (all other than RNE), floating operations must be represented by constrained intrinsics, for example llvm.experimental.constrained.fadd should be used instead of fadd.

llvm/test/CodeGen/RISCV/double-arith.ll

40

I see. Changed assertions in the produced assembler.

[jrtc27]

In D93624#2465904, @sepavloff wrote:

In D93624#2465776, @jrtc27 wrote:

Doesn't this render fesetround useless?

No. fesetround sets dynamic rounding mode (register frm), which may be any mode. However in the case of non-default rounding mode (all other than RNE), floating operations must be represented by constrained intrinsics, for example llvm.experimental.constrained.fadd should be used instead of fadd.

Ah, I see, I need -ffp-strict (or an FENV_ACCESS pragma) if I want that behaviour. Though is that something people actually use? I have a feeling that a lot of code out there uses fesetround without changing compiler flags, and probably "works" on x86 because everything uses the dynamic rounding mode. Can we not just always use the dynamic rounding mode to be more friendly to users, and say that if you change the rounding mode you should have told the compiler about it (but you'll get behaviour approximately like what you asked for)? What do other backends do?

FWIW, the Clang documentation just says:

The option -fno-rounding-math allows the compiler to assume that the rounding mode is set to FE_TONEAREST. This is the default.

So this revision should only make a difference when people violate the documented assumptions of their compiler.

[craig.topper]

I don't see a strong reason to change this. Using dynamic is consistent with targets that only have a dynamic mode.

But if we were to change this, shouldn't also update the Zfh extension files half-arith.ll and RISCVInstrInfoZfh.td.

llvm/lib/Target/RISCV/RISCVInstrInfoF.td

402–406

This comment previously said gcc was using dynamic rounding mode. Now it says gcc uses nearest even. Only one of those statements can be true.

[jrtc27]

llvm/lib/Target/RISCV/RISCVInstrInfoF.td

402–406

The former was correct.

[sepavloff]

In D93624#2465934, @jrtc27 wrote:

I have a feeling that a lot of code out there uses fesetround without changing compiler flags, and probably "works" on x86 because everything uses the dynamic rounding mode.

I think you are right. Using dynamic rounding mode, the fact that fesetround is an external function (thus may have side effect which restricts code reordering) and special care taken by compilers to limit optimizations of FP operations allow the generated code to work in many cases. Another possible reason of "working" may be related to previous unavailability of #pragma STDC FENV_ACCESS. People that used fesetround understand that they should use this pragma but it was unsupported, so they try to use workarounds instead of complaining.

Can we not just always use the dynamic rounding mode to be more friendly to users, and say that if you change the rounding mode you should have told the compiler about it (but you'll get behaviour approximately like what you asked for)? What do other backends do?

If only rounding mode was an issue, probably yes. There is however dependency on another FP register, fflags. More detailed consideration is make in D94163.

FWIW, the Clang documentation just says:

The option -fno-rounding-math allows the compiler to assume that the rounding mode is set to FE_TONEAREST. This is the default.

So this revision should only make a difference when people violate the documented assumptions of their compiler.

If only the default mode were needed, this change were useless. This is a step toward support of non-default FP environments.

[sepavloff]

This change is merged into D94163 and subsequent changes.

llvm/lib/Target/RISCV/RISCVInstrInfoD.td

 
 //===----------------------------------------------------------------------===//
 // Pseudo-instructions and codegen patterns
 //===----------------------------------------------------------------------===//
 
 class PatFpr64Fpr64<SDPatternOperator OpNode, RVInstR Inst>
     : Pat<(OpNode FPR64:$rs1, FPR64:$rs2), (Inst $rs1, $rs2)>;
 
-class PatFpr64Fpr64DynFrm<SDPatternOperator OpNode, RVInstRFrm Inst>
-    : Pat<(OpNode FPR64:$rs1, FPR64:$rs2), (Inst $rs1, $rs2, 0b111)>;
+class PatFpr64Fpr64DefFrm<SDPatternOperator OpNode, RVInstRFrm Inst>
+    : Pat<(OpNode FPR64:$rs1, FPR64:$rs2), (Inst $rs1, $rs2, 0b000)>;
 
 let Predicates = [HasStdExtD] in {
 
 /// Float conversion operations
 
 // f64 -> f32, f32 -> f64
-def : Pat<(fpround FPR64:$rs1), (FCVT_S_D FPR64:$rs1, 0b111)>;
+def : Pat<(fpround FPR64:$rs1), (FCVT_S_D FPR64:$rs1, 0b000)>;
 def : Pat<(fpextend FPR32:$rs1), (FCVT_D_S FPR32:$rs1)>;
 
 // [u]int<->double conversion patterns must be gated on IsRV32 or IsRV64, so
 // are defined later.
 
 /// Float arithmetic operations
 
-def : PatFpr64Fpr64DynFrm<fadd, FADD_D>;
-def : PatFpr64Fpr64DynFrm<fsub, FSUB_D>;
-def : PatFpr64Fpr64DynFrm<fmul, FMUL_D>;
-def : PatFpr64Fpr64DynFrm<fdiv, FDIV_D>;
+def : PatFpr64Fpr64DefFrm<fadd, FADD_D>;
+def : PatFpr64Fpr64DefFrm<fsub, FSUB_D>;
+def : PatFpr64Fpr64DefFrm<fmul, FMUL_D>;
+def : PatFpr64Fpr64DefFrm<fdiv, FDIV_D>;
 
-def : Pat<(fsqrt FPR64:$rs1), (FSQRT_D FPR64:$rs1, 0b111)>;
+def : Pat<(fsqrt FPR64:$rs1), (FSQRT_D FPR64:$rs1, 0b000)>;
 
 def : Pat<(fneg FPR64:$rs1), (FSGNJN_D $rs1, $rs1)>;
 def : Pat<(fabs FPR64:$rs1), (FSGNJX_D $rs1, $rs1)>;
 
 def : PatFpr64Fpr64<fcopysign, FSGNJ_D>;
 def : Pat<(fcopysign FPR64:$rs1, (fneg FPR64:$rs2)), (FSGNJN_D $rs1, $rs2)>;
 def : Pat<(fcopysign FPR64:$rs1, FPR32:$rs2), (FSGNJ_D $rs1, (FCVT_D_S $rs2))>;
 def : Pat<(fcopysign FPR32:$rs1, FPR64:$rs2), (FSGNJ_S $rs1, (FCVT_S_D $rs2,
-                                                              0b111))>;
+                                                              0b000))>;
 
 // fmadd: rs1 * rs2 + rs3
 def : Pat<(fma FPR64:$rs1, FPR64:$rs2, FPR64:$rs3),
-          (FMADD_D $rs1, $rs2, $rs3, 0b111)>;
+          (FMADD_D $rs1, $rs2, $rs3, 0b000)>;
 
 // fmsub: rs1 * rs2 - rs3
 def : Pat<(fma FPR64:$rs1, FPR64:$rs2, (fneg FPR64:$rs3)),
-          (FMSUB_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>;
+          (FMSUB_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b000)>;
 
 // fnmsub: -rs1 * rs2 + rs3
 def : Pat<(fma (fneg FPR64:$rs1), FPR64:$rs2, FPR64:$rs3),
-          (FNMSUB_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>;
+          (FNMSUB_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b000)>;
 
 // fnmadd: -rs1 * rs2 - rs3
 def : Pat<(fma (fneg FPR64:$rs1), FPR64:$rs2, (fneg FPR64:$rs3)),
-          (FNMADD_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>;
+          (FNMADD_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b000)>;
 
 // The RISC-V 2.2 user-level ISA spec defines fmin and fmax as returning the
 // canonical NaN when giving a signaling NaN. This doesn't match the LLVM
 // behaviour (see https://bugs.llvm.org/show_bug.cgi?id=27363). However, the
 // draft 2.3 ISA spec changes the definition of fmin and fmax in a way that
 // matches LLVM's fminnum and fmaxnum
 // <https://github.com/riscv/riscv-isa-manual/commit/cd20cee7efd9bac7c5aa127ec3b451749d2b3cce>.
 def : PatFpr64Fpr64<fminnum, FMIN_D>;

 
 // [u]int32->fp
 def : Pat<(sint_to_fp (sexti32 GPR:$rs1)), (FCVT_D_W $rs1)>;
 def : Pat<(uint_to_fp (zexti32 GPR:$rs1)), (FCVT_D_WU $rs1)>;
 
 def : Pat<(fp_to_sint FPR64:$rs1), (FCVT_L_D FPR64:$rs1, 0b001)>;
 def : Pat<(fp_to_uint FPR64:$rs1), (FCVT_LU_D FPR64:$rs1, 0b001)>;
 
-// [u]int64->fp. Match GCC and default to using dynamic rounding mode.
-def : Pat<(sint_to_fp GPR:$rs1), (FCVT_D_L GPR:$rs1, 0b111)>;
-def : Pat<(uint_to_fp GPR:$rs1), (FCVT_D_LU GPR:$rs1, 0b111)>;
+// [u]int64->fp. Match GCC and default to using rounding mode to nearest even.
+def : Pat<(sint_to_fp GPR:$rs1), (FCVT_D_L GPR:$rs1, 0b000)>;
+def : Pat<(uint_to_fp GPR:$rs1), (FCVT_D_LU GPR:$rs1, 0b000)>;
 } // Predicates = [HasStdExtD, IsRV64]

llvm/lib/Target/RISCV/RISCVInstrInfoF.td

 
 /// Floating point constants
 def fpimm0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(+0.0); }]>;
 
 /// Generic pattern classes
 class PatFpr32Fpr32<SDPatternOperator OpNode, RVInstR Inst>
     : Pat<(OpNode FPR32:$rs1, FPR32:$rs2), (Inst $rs1, $rs2)>;
 
-class PatFpr32Fpr32DynFrm<SDPatternOperator OpNode, RVInstRFrm Inst>
-    : Pat<(OpNode FPR32:$rs1, FPR32:$rs2), (Inst $rs1, $rs2, 0b111)>;
+class PatFpr32Fpr32DefFrm<SDPatternOperator OpNode, RVInstRFrm Inst>
+    : Pat<(OpNode FPR32:$rs1, FPR32:$rs2), (Inst $rs1, $rs2, 0b000)>;
 
 let Predicates = [HasStdExtF] in {
 
 /// Float constants
 def : Pat<(f32 (fpimm0)), (FMV_W_X X0)>;
 
 /// Float conversion operations
 
 // [u]int32<->float conversion patterns must be gated on IsRV32 or IsRV64, so
 // are defined later.
 
 /// Float arithmetic operations
 
-def : PatFpr32Fpr32DynFrm<fadd, FADD_S>;
-def : PatFpr32Fpr32DynFrm<fsub, FSUB_S>;
-def : PatFpr32Fpr32DynFrm<fmul, FMUL_S>;
-def : PatFpr32Fpr32DynFrm<fdiv, FDIV_S>;
+def : PatFpr32Fpr32DefFrm<fadd, FADD_S>;
+def : PatFpr32Fpr32DefFrm<fsub, FSUB_S>;
+def : PatFpr32Fpr32DefFrm<fmul, FMUL_S>;
+def : PatFpr32Fpr32DefFrm<fdiv, FDIV_S>;
 
-def : Pat<(fsqrt FPR32:$rs1), (FSQRT_S FPR32:$rs1, 0b111)>;
+def : Pat<(fsqrt FPR32:$rs1), (FSQRT_S FPR32:$rs1, 0b000)>;
 
 def : Pat<(fneg FPR32:$rs1), (FSGNJN_S $rs1, $rs1)>;
 def : Pat<(fabs FPR32:$rs1), (FSGNJX_S $rs1, $rs1)>;
 
 def : PatFpr32Fpr32<fcopysign, FSGNJ_S>;
 def : Pat<(fcopysign FPR32:$rs1, (fneg FPR32:$rs2)), (FSGNJN_S $rs1, $rs2)>;
 
 // fmadd: rs1 * rs2 + rs3
 def : Pat<(fma FPR32:$rs1, FPR32:$rs2, FPR32:$rs3),
-          (FMADD_S $rs1, $rs2, $rs3, 0b111)>;
+          (FMADD_S $rs1, $rs2, $rs3, 0b000)>;
 
 // fmsub: rs1 * rs2 - rs3
 def : Pat<(fma FPR32:$rs1, FPR32:$rs2, (fneg FPR32:$rs3)),
-          (FMSUB_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>;
+          (FMSUB_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b000)>;
 
 // fnmsub: -rs1 * rs2 + rs3
 def : Pat<(fma (fneg FPR32:$rs1), FPR32:$rs2, FPR32:$rs3),
-          (FNMSUB_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>;
+          (FNMSUB_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b000)>;
 
 // fnmadd: -rs1 * rs2 - rs3
 def : Pat<(fma (fneg FPR32:$rs1), FPR32:$rs2, (fneg FPR32:$rs3)),
-          (FNMADD_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>;
+          (FNMADD_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b000)>;
 
 // The RISC-V 2.2 user-level ISA spec defines fmin and fmax as returning the
 // canonical NaN when given a signaling NaN. This doesn't match the LLVM
 // behaviour (see https://bugs.llvm.org/show_bug.cgi?id=27363). However, the
 // draft 2.3 ISA spec changes the definition of fmin and fmax in a way that
 // matches LLVM's fminnum and fmaxnum
 // <https://github.com/riscv/riscv-isa-manual/commit/cd20cee7efd9bac7c5aa127ec3b451749d2b3cce>.
 def : PatFpr32Fpr32<fminnum, FMIN_S>;

 // Moves (no conversion)
 def : Pat<(bitconvert GPR:$rs1), (FMV_W_X GPR:$rs1)>;
 def : Pat<(bitconvert FPR32:$rs1), (FMV_X_W FPR32:$rs1)>;
 
 // float->[u]int. Round-to-zero must be used.
 def : Pat<(fp_to_sint FPR32:$rs1), (FCVT_W_S $rs1, 0b001)>;
 def : Pat<(fp_to_uint FPR32:$rs1), (FCVT_WU_S $rs1, 0b001)>;
 
-// [u]int->float. Match GCC and default to using dynamic rounding mode.
-def : Pat<(sint_to_fp GPR:$rs1), (FCVT_S_W $rs1, 0b111)>;
-def : Pat<(uint_to_fp GPR:$rs1), (FCVT_S_WU $rs1, 0b111)>;
+// [u]int->float. Match GCC and default to using rounding mode to nearest even.
+def : Pat<(sint_to_fp GPR:$rs1), (FCVT_S_W $rs1, 0b000)>;
+def : Pat<(uint_to_fp GPR:$rs1), (FCVT_S_WU $rs1, 0b000)>;
 } // Predicates = [HasStdExtF, IsRV32]
 
 let Predicates = [HasStdExtF, IsRV64] in {
 // Moves (no conversion)
 def : Pat<(riscv_fmv_w_x_rv64 GPR:$src), (FMV_W_X GPR:$src)>;
 def : Pat<(riscv_fmv_x_anyextw_rv64 FPR32:$src), (FMV_X_W FPR32:$src)>;
 def : Pat<(sext_inreg (riscv_fmv_x_anyextw_rv64 FPR32:$src), i32),
           (FMV_X_W FPR32:$src)>;
 
 // FP->[u]int32 is mostly handled by the FP->[u]int64 patterns. This is safe
 // because fpto[u|s]i produces poison if the value can't fit into the target.
 // We match the single case below because fcvt.wu.s sign-extends its result so
 // is cheaper than fcvt.lu.s+sext.w.
 def : Pat<(sext_inreg (assertzexti32 (fp_to_uint FPR32:$rs1)), i32),
           (FCVT_WU_S $rs1, 0b001)>;
 
 // FP->[u]int64
 def : Pat<(fp_to_sint FPR32:$rs1), (FCVT_L_S $rs1, 0b001)>;
 def : Pat<(fp_to_uint FPR32:$rs1), (FCVT_LU_S $rs1, 0b001)>;
 
-// [u]int->fp. Match GCC and default to using dynamic rounding mode.
-def : Pat<(sint_to_fp (sexti32 GPR:$rs1)), (FCVT_S_W $rs1, 0b111)>;
-def : Pat<(uint_to_fp (zexti32 GPR:$rs1)), (FCVT_S_WU $rs1, 0b111)>;
-def : Pat<(sint_to_fp GPR:$rs1), (FCVT_S_L $rs1, 0b111)>;
-def : Pat<(uint_to_fp GPR:$rs1), (FCVT_S_LU $rs1, 0b111)>;
+// [u]int->fp. Match GCC and default to using rounding mode to nearest even.
+def : Pat<(sint_to_fp (sexti32 GPR:$rs1)), (FCVT_S_W $rs1, 0b000)>;
+def : Pat<(uint_to_fp (zexti32 GPR:$rs1)), (FCVT_S_WU $rs1, 0b000)>;
+def : Pat<(sint_to_fp GPR:$rs1), (FCVT_S_L $rs1, 0b000)>;
+def : Pat<(uint_to_fp GPR:$rs1), (FCVT_S_LU $rs1, 0b000)>;
 } // Predicates = [HasStdExtF, IsRV64]

llvm/test/CodeGen/RISCV/double-arith.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32IFD %s
 ; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV64IFD %s
+; RUN: llc -mtriple=riscv32 -mattr=+d -filetype=obj < %s \
+; RUN:   | llvm-objdump -d --triple=riscv32 --mattr=+d - \
+; RUN:   | FileCheck -check-prefix=RV32IFDIS %s
 
 ; These tests are each targeted at a particular RISC-V FPU instruction. Most
 ; other files in this folder exercise LLVM IR instructions that don't directly
 ; match a RISC-V instruction.
 
 define double @fadd_d(double %a, double %b) nounwind {
 ; RV32IFD-LABEL: fadd_d:
 ; RV32IFD:       # %bb.0:

 ;
 ; RV64IFD-LABEL: fadd_d:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    fmv.d.x ft0, a1
 ; RV64IFD-NEXT:    fmv.d.x ft1, a0
 ; RV64IFD-NEXT:    fadd.d ft0, ft1, ft0
 ; RV64IFD-NEXT:    fmv.x.d a0, ft0
 ; RV64IFD-NEXT:    ret
+
+; RV32IFDIS-LABEL: <fadd_d>:
+; RV32IFDIS:      fadd.d ft0, ft1, ft0, rne
   %1 = fadd double %a, %b
   ret double %1
 }
 
 define double @fsub_d(double %a, double %b) nounwind {
 ; RV32IFD-LABEL: fsub_d:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    addi sp, sp, -16

 ;
 ; RV64IFD-LABEL: fsub_d:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    fmv.d.x ft0, a1
 ; RV64IFD-NEXT:    fmv.d.x ft1, a0
 ; RV64IFD-NEXT:    fsub.d ft0, ft1, ft0
 ; RV64IFD-NEXT:    fmv.x.d a0, ft0
 ; RV64IFD-NEXT:    ret
+
+; RV32IFDIS-LABEL: <fsub_d>:
+; RV32IFDIS:      fsub.d ft0, ft1, ft0, rne
   %1 = fsub double %a, %b
   ret double %1
 }
 
 define double @fmul_d(double %a, double %b) nounwind {
 ; RV32IFD-LABEL: fmul_d:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    addi sp, sp, -16

 ;
 ; RV64IFD-LABEL: fmul_d:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    fmv.d.x ft0, a1
 ; RV64IFD-NEXT:    fmv.d.x ft1, a0
 ; RV64IFD-NEXT:    fmul.d ft0, ft1, ft0
 ; RV64IFD-NEXT:    fmv.x.d a0, ft0
 ; RV64IFD-NEXT:    ret
+
+; RV32IFDIS-LABEL: <fmul_d>:
+; RV32IFDIS:      fmul.d ft0, ft1, ft0, rne
   %1 = fmul double %a, %b
   ret double %1
 }
 
 define double @fdiv_d(double %a, double %b) nounwind {
 ; RV32IFD-LABEL: fdiv_d:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    addi sp, sp, -16

 ;
 ; RV64IFD-LABEL: fdiv_d:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    fmv.d.x ft0, a1
 ; RV64IFD-NEXT:    fmv.d.x ft1, a0
 ; RV64IFD-NEXT:    fdiv.d ft0, ft1, ft0
 ; RV64IFD-NEXT:    fmv.x.d a0, ft0
 ; RV64IFD-NEXT:    ret
+
+; RV32IFDIS-LABEL: <fdiv_d>:
+; RV32IFDIS:      fdiv.d ft0, ft1, ft0, rne
   %1 = fdiv double %a, %b
   ret double %1
 }
 
 declare double @llvm.sqrt.f64(double)
 
 define double @fsqrt_d(double %a) nounwind {
 ; RV32IFD-LABEL: fsqrt_d:

 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fsqrt_d:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    fmv.d.x ft0, a0
 ; RV64IFD-NEXT:    fsqrt.d ft0, ft0
 ; RV64IFD-NEXT:    fmv.x.d a0, ft0
 ; RV64IFD-NEXT:    ret
+
+; RV32IFDIS-LABEL: <fsqrt_d>:
+; RV32IFDIS:      fsqrt.d ft0, ft0, rne
   %1 = call double @llvm.sqrt.f64(double %a)
   ret double %1
 }
 
 declare double @llvm.copysign.f64(double, double)
 
 define double @fsgnj_d(double %a, double %b) nounwind {
 ; RV32IFD-LABEL: fsgnj_d:

 ;
 ; RV64IFD-LABEL: fneg_d:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    fmv.d.x ft0, a0
 ; RV64IFD-NEXT:    fadd.d ft0, ft0, ft0
 ; RV64IFD-NEXT:    fneg.d ft1, ft0
 ; RV64IFD-NEXT:    feq.d a0, ft0, ft1
 ; RV64IFD-NEXT:    ret
+
+; RV32IFDIS-LABEL: <fneg_d>:
+; RV32IFDIS:      fadd.d ft0, ft0, ft0, rne
   %1 = fadd double %a, %a
   %2 = fneg double %1
   %3 = fcmp oeq double %1, %2
   %4 = zext i1 %3 to i32
   ret i32 %4
 }
 
 define double @fsgnjn_d(double %a, double %b) nounwind {

 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    fmv.d.x ft0, a1
 ; RV64IFD-NEXT:    fmv.d.x ft1, a0
 ; RV64IFD-NEXT:    fadd.d ft0, ft1, ft0
 ; RV64IFD-NEXT:    fabs.d ft1, ft0
 ; RV64IFD-NEXT:    fadd.d ft0, ft1, ft0
 ; RV64IFD-NEXT:    fmv.x.d a0, ft0
 ; RV64IFD-NEXT:    ret
+
+; RV32IFDIS-LABEL: <fabs_d>:
+; RV32IFDIS:      fadd.d ft0, ft1, ft0, rne
   %1 = fadd double %a, %b
   %2 = call double @llvm.fabs.f64(double %1)
   %3 = fadd double %2, %1
   ret double %3
 }
 
 declare double @llvm.minnum.f64(double, double)
 

 ; RV64IFD-LABEL: fmadd_d:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    fmv.d.x ft0, a2
 ; RV64IFD-NEXT:    fmv.d.x ft1, a1
 ; RV64IFD-NEXT:    fmv.d.x ft2, a0
 ; RV64IFD-NEXT:    fmadd.d ft0, ft2, ft1, ft0
 ; RV64IFD-NEXT:    fmv.x.d a0, ft0
 ; RV64IFD-NEXT:    ret
+
+; RV32IFDIS-LABEL: <fmadd_d>:
+; RV32IFDIS:      fmadd.d ft0, ft2, ft1, ft0, rne
   %1 = call double @llvm.fma.f64(double %a, double %b, double %c)
   ret double %1
 }
 
 define double @fmsub_d(double %a, double %b, double %c) nounwind {
 ; RV32IFD-LABEL: fmsub_d:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    addi sp, sp, -16

 ; RV64IFD-NEXT:    fmv.d.x ft0, a1
 ; RV64IFD-NEXT:    fmv.d.x ft1, a0
 ; RV64IFD-NEXT:    fmv.d.x ft2, a2
 ; RV64IFD-NEXT:    fmv.d.x ft3, zero
 ; RV64IFD-NEXT:    fadd.d ft2, ft2, ft3
 ; RV64IFD-NEXT:    fmsub.d ft0, ft1, ft0, ft2
 ; RV64IFD-NEXT:    fmv.x.d a0, ft0
 ; RV64IFD-NEXT:    ret
+
+; RV32IFDIS-LABEL: <fmsub_d>:
+; RV32IFDIS:      fmsub.d ft0, ft1, ft0, ft2, rne
   %c_ = fadd double 0.0, %c ; avoid negation using xor
   %negc = fsub double -0.0, %c_
   %1 = call double @llvm.fma.f64(double %a, double %b, double %negc)
   ret double %1
 }
 
 define double @fnmadd_d(double %a, double %b, double %c) nounwind {
 ; RV32IFD-LABEL: fnmadd_d:

 ; RV64IFD-NEXT:    fmv.d.x ft1, a2
 ; RV64IFD-NEXT:    fmv.d.x ft2, a0
 ; RV64IFD-NEXT:    fmv.d.x ft3, zero
 ; RV64IFD-NEXT:    fadd.d ft2, ft2, ft3
 ; RV64IFD-NEXT:    fadd.d ft1, ft1, ft3
 ; RV64IFD-NEXT:    fnmadd.d ft0, ft2, ft0, ft1
 ; RV64IFD-NEXT:    fmv.x.d a0, ft0
 ; RV64IFD-NEXT:    ret
+
+; RV32IFDIS-LABEL: <fnmadd_d>:
+; RV32IFDIS:      fadd.d ft2, ft2, ft3, rne
+; RV32IFDIS:      fadd.d ft1, ft1, ft3, rne
+; RV32IFDIS:      fnmadd.d ft0, ft2, ft0, ft1, rne
   %a_ = fadd double 0.0, %a
   %c_ = fadd double 0.0, %c
   %nega = fsub double -0.0, %a_
   %negc = fsub double -0.0, %c_
   %1 = call double @llvm.fma.f64(double %nega, double %b, double %negc)
   ret double %1
 }
 

 ; RV64IFD-NEXT:    fmv.d.x ft1, a2
 ; RV64IFD-NEXT:    fmv.d.x ft2, a1
 ; RV64IFD-NEXT:    fmv.d.x ft3, zero
 ; RV64IFD-NEXT:    fadd.d ft2, ft2, ft3
 ; RV64IFD-NEXT:    fadd.d ft1, ft1, ft3
 ; RV64IFD-NEXT:    fnmadd.d ft0, ft2, ft0, ft1
 ; RV64IFD-NEXT:    fmv.x.d a0, ft0
 ; RV64IFD-NEXT:    ret
+
+; RV32IFDIS-LABEL: <fnmadd_d_2>:
+; RV32IFDIS:      fadd.d ft2, ft2, ft3, rne
+; RV32IFDIS:      fadd.d ft1, ft1, ft3, rne
+; RV32IFDIS:      fnmadd.d ft0, ft2, ft0, ft1, rne
   %b_ = fadd double 0.0, %b
   %c_ = fadd double 0.0, %c
   %negb = fsub double -0.0, %b_
   %negc = fsub double -0.0, %c_
   %1 = call double @llvm.fma.f64(double %a, double %negb, double %negc)
   ret double %1
 }
 

 ; RV64IFD-NEXT:    fmv.d.x ft0, a2
 ; RV64IFD-NEXT:    fmv.d.x ft1, a1
 ; RV64IFD-NEXT:    fmv.d.x ft2, a0
 ; RV64IFD-NEXT:    fmv.d.x ft3, zero
 ; RV64IFD-NEXT:    fadd.d ft2, ft2, ft3
 ; RV64IFD-NEXT:    fnmsub.d ft0, ft2, ft1, ft0
 ; RV64IFD-NEXT:    fmv.x.d a0, ft0
 ; RV64IFD-NEXT:    ret
+
+; RV32IFDIS-LABEL: <fnmsub_d>:
+; RV32IFDIS:      fadd.d ft2, ft2, ft3, rne
+; RV32IFDIS:      fnmsub.d ft0, ft2, ft1, ft0, rne
   %a_ = fadd double 0.0, %a
   %nega = fsub double -0.0, %a_
   %1 = call double @llvm.fma.f64(double %nega, double %b, double %c)
   ret double %1
 }
 
 define double @fnmsub_d_2(double %a, double %b, double %c) nounwind {
 ; RV32IFD-LABEL: fnmsub_d_2:

 ; RV64IFD-NEXT:    fmv.d.x ft0, a2
 ; RV64IFD-NEXT:    fmv.d.x ft1, a0
 ; RV64IFD-NEXT:    fmv.d.x ft2, a1
 ; RV64IFD-NEXT:    fmv.d.x ft3, zero
 ; RV64IFD-NEXT:    fadd.d ft2, ft2, ft3
 ; RV64IFD-NEXT:    fnmsub.d ft0, ft2, ft1, ft0
 ; RV64IFD-NEXT:    fmv.x.d a0, ft0
 ; RV64IFD-NEXT:    ret
+
+; RV32IFDIS-LABEL: <fnmsub_d_2>:
+; RV32IFDIS:      fadd.d ft2, ft2, ft3, rne
+; RV32IFDIS:      fnmsub.d ft0, ft2, ft1, ft0, rne
   %b_ = fadd double 0.0, %b
   %negb = fsub double -0.0, %b_
   %1 = call double @llvm.fma.f64(double %a, double %negb, double %c)
   ret double %1
 }
 
 define double @fmadd_d_contract(double %a, double %b, double %c) nounwind {
 ; RV32IFD-LABEL: fmadd_d_contract:

 ; RV64IFD-LABEL: fmadd_d_contract:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    fmv.d.x ft0, a2
 ; RV64IFD-NEXT:    fmv.d.x ft1, a1
 ; RV64IFD-NEXT:    fmv.d.x ft2, a0
 ; RV64IFD-NEXT:    fmadd.d ft0, ft2, ft1, ft0
 ; RV64IFD-NEXT:    fmv.x.d a0, ft0
 ; RV64IFD-NEXT:    ret
+
+; RV32IFDIS-LABEL: <fmadd_d_contract>:
+; RV32IFDIS:      fmadd.d ft0, ft2, ft1, ft0, rne
   %1 = fmul contract double %a, %b
   %2 = fadd contract double %1, %c
   ret double %2
 }
 
 define double @fmsub_d_contract(double %a, double %b, double %c) nounwind {
 ; RV32IFD-LABEL: fmsub_d_contract:
 ; RV32IFD:       # %bb.0:

 ; RV64IFD-NEXT:    fmv.d.x ft0, a1
 ; RV64IFD-NEXT:    fmv.d.x ft1, a0
 ; RV64IFD-NEXT:    fmv.d.x ft2, a2
 ; RV64IFD-NEXT:    fmv.d.x ft3, zero
 ; RV64IFD-NEXT:    fadd.d ft2, ft2, ft3
 ; RV64IFD-NEXT:    fmsub.d ft0, ft1, ft0, ft2
 ; RV64IFD-NEXT:    fmv.x.d a0, ft0
 ; RV64IFD-NEXT:    ret
+
+; RV32IFDIS-LABEL: <fmsub_d_contract>:
+; RV32IFDIS:      fadd.d ft2, ft2, ft3, rne
+; RV32IFDIS:      fmsub.d ft0, ft1, ft0, ft2, rne
   %c_ = fadd double 0.0, %c ; avoid negation using xor
   %1 = fmul contract double %a, %b
   %2 = fsub contract double %1, %c_
   ret double %2
 }
 
 define double @fnmadd_d_contract(double %a, double %b, double %c) nounwind {
 ; RV32IFD-LABEL: fnmadd_d_contract:

 ; RV64IFD-NEXT:    fmv.d.x ft2, a0
 ; RV64IFD-NEXT:    fmv.d.x ft3, zero
 ; RV64IFD-NEXT:    fadd.d ft2, ft2, ft3
 ; RV64IFD-NEXT:    fadd.d ft1, ft1, ft3
 ; RV64IFD-NEXT:    fadd.d ft0, ft0, ft3
 ; RV64IFD-NEXT:    fnmadd.d ft0, ft2, ft1, ft0
 ; RV64IFD-NEXT:    fmv.x.d a0, ft0
 ; RV64IFD-NEXT:    ret
+
+; RV32IFDIS-LABEL: <fnmadd_d_contract>:
+; RV32IFDIS:      fadd.d ft2, ft2, ft3, rne
+; RV32IFDIS:      fadd.d ft1, ft1, ft3, rne
+; RV32IFDIS:      fadd.d ft0, ft0, ft3, rne
+; RV32IFDIS:      fnmadd.d ft0, ft2, ft1, ft0, rne
   %a_ = fadd double 0.0, %a ; avoid negation using xor
   %b_ = fadd double 0.0, %b ; avoid negation using xor
   %c_ = fadd double 0.0, %c ; avoid negation using xor
   %1 = fmul contract double %a_, %b_
   %2 = fneg double %1
   %3 = fsub contract double %2, %c_
   ret double %3
 }

 ; RV64IFD-NEXT:    fmv.d.x ft1, a1
 ; RV64IFD-NEXT:    fmv.d.x ft2, a0
 ; RV64IFD-NEXT:    fmv.d.x ft3, zero
 ; RV64IFD-NEXT:    fadd.d ft2, ft2, ft3
 ; RV64IFD-NEXT:    fadd.d ft1, ft1, ft3
 ; RV64IFD-NEXT:    fnmsub.d ft0, ft2, ft1, ft0
 ; RV64IFD-NEXT:    fmv.x.d a0, ft0
 ; RV64IFD-NEXT:    ret
+
+; RV32IFDIS-LABEL: <fnmsub_d_contract>:
+; RV32IFDIS:      fadd.d ft2, ft2, ft3, rne
+; RV32IFDIS:      fadd.d ft1, ft1, ft3, rne
+; RV32IFDIS:      fnmsub.d ft0, ft2, ft1, ft0, rne
   %a_ = fadd double 0.0, %a ; avoid negation using xor
   %b_ = fadd double 0.0, %b ; avoid negation using xor
   %1 = fmul contract double %a_, %b_
   %2 = fsub contract double %c, %1
   ret double %2
 }

llvm/test/CodeGen/RISCV/float-arith.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32IF %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV64IF %s
+; RUN: llc -mtriple=riscv32 -mattr=+f -filetype=obj < %s \
+; RUN:   | llvm-objdump -d --triple=riscv32 --mattr=+f - \
+; RUN:   | FileCheck -check-prefix=RV32IFDIS %s
 
 ; These tests are each targeted at a particular RISC-V FPU instruction. Most
 ; other files in this folder exercise LLVM IR instructions that don't directly
 ; match a RISC-V instruction.
 
 define float @fadd_s(float %a, float %b) nounwind {
 ; RV32IF-LABEL: fadd_s:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fmv.w.x ft0, a1
 ; RV32IF-NEXT:    fmv.w.x ft1, a0
 ; RV32IF-NEXT:    fadd.s ft0, ft1, ft0
 ; RV32IF-NEXT:    fmv.x.w a0, ft0
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fadd_s:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fmv.w.x ft0, a1
 ; RV64IF-NEXT:    fmv.w.x ft1, a0
 ; RV64IF-NEXT:    fadd.s ft0, ft1, ft0
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    ret
+
+; RV32IFDIS-LABEL: <fadd_s>:
+; RV32IFDIS:      fadd.s ft0, ft1, ft0, rne
   %1 = fadd float %a, %b
   ret float %1
 }
 
 define float @fsub_s(float %a, float %b) nounwind {
 ; RV32IF-LABEL: fsub_s:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fmv.w.x ft0, a1
 ; RV32IF-NEXT:    fmv.w.x ft1, a0
 ; RV32IF-NEXT:    fsub.s ft0, ft1, ft0
 ; RV32IF-NEXT:    fmv.x.w a0, ft0
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fsub_s:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fmv.w.x ft0, a1
 ; RV64IF-NEXT:    fmv.w.x ft1, a0
 ; RV64IF-NEXT:    fsub.s ft0, ft1, ft0
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    ret
+
+; RV32IFDIS-LABEL: <fsub_s>:
+; RV32IFDIS:      fsub.s ft0, ft1, ft0, rne
   %1 = fsub float %a, %b
   ret float %1
 }
 
 define float @fmul_s(float %a, float %b) nounwind {
 ; RV32IF-LABEL: fmul_s:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fmv.w.x ft0, a1
 ; RV32IF-NEXT:    fmv.w.x ft1, a0
 ; RV32IF-NEXT:    fmul.s ft0, ft1, ft0
 ; RV32IF-NEXT:    fmv.x.w a0, ft0
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fmul_s:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fmv.w.x ft0, a1
 ; RV64IF-NEXT:    fmv.w.x ft1, a0
 ; RV64IF-NEXT:    fmul.s ft0, ft1, ft0
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    ret
+
+; RV32IFDIS-LABEL: <fmul_s>:
+; RV32IFDIS:      fmul.s ft0, ft1, ft0, rne
   %1 = fmul float %a, %b
   ret float %1
 }
 
 define float @fdiv_s(float %a, float %b) nounwind {
 ; RV32IF-LABEL: fdiv_s:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fmv.w.x ft0, a1
 ; RV32IF-NEXT:    fmv.w.x ft1, a0
 ; RV32IF-NEXT:    fdiv.s ft0, ft1, ft0
 ; RV32IF-NEXT:    fmv.x.w a0, ft0
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fdiv_s:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fmv.w.x ft0, a1
 ; RV64IF-NEXT:    fmv.w.x ft1, a0
 ; RV64IF-NEXT:    fdiv.s ft0, ft1, ft0
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    ret
+
+; RV32IFDIS-LABEL: <fdiv_s>:
+; RV32IFDIS:      fdiv.s ft0, ft1, ft0, rne
   %1 = fdiv float %a, %b
   ret float %1
 }
 
 declare float @llvm.sqrt.f32(float)
 
 define float @fsqrt_s(float %a) nounwind {
 ; RV32IF-LABEL: fsqrt_s:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fmv.w.x ft0, a0
 ; RV32IF-NEXT:    fsqrt.s ft0, ft0
 ; RV32IF-NEXT:    fmv.x.w a0, ft0
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fsqrt_s:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fmv.w.x ft0, a0
 ; RV64IF-NEXT:    fsqrt.s ft0, ft0
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    ret
+
+; RV32IFDIS-LABEL: <fsqrt_s>:
+; RV32IFDIS:      fsqrt.s ft0, ft0, rne
   %1 = call float @llvm.sqrt.f32(float %a)
   ret float %1
 }
 
 declare float @llvm.copysign.f32(float, float)
 
 define float @fsgnj_s(float %a, float %b) nounwind {
 ; RV32IF-LABEL: fsgnj_s:

 ; RV64IF-LABEL: fsgnjn_s:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fmv.w.x ft0, a1
 ; RV64IF-NEXT:    fmv.w.x ft1, a0
 ; RV64IF-NEXT:    fadd.s ft0, ft1, ft0
 ; RV64IF-NEXT:    fsgnjn.s ft0, ft1, ft0
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    ret
+
+; RV32IFDIS-LABEL: <fsgnjn_s>:
+; RV32IFDIS:      fadd.s ft0, ft1, ft0, rne
   %1 = fadd float %a, %b
   %2 = fneg float %1
   %3 = call float @llvm.copysign.f32(float %a, float %2)
   ret float %3
 }
 
 declare float @llvm.fabs.f32(float)
 

 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fmv.w.x ft0, a1
 ; RV64IF-NEXT:    fmv.w.x ft1, a0
 ; RV64IF-NEXT:    fadd.s ft0, ft1, ft0
 ; RV64IF-NEXT:    fabs.s ft1, ft0
 ; RV64IF-NEXT:    fadd.s ft0, ft1, ft0
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    ret
+
+; RV32IFDIS-LABEL: <fabs_s>:
+; RV32IFDIS:      fadd.s ft0, ft1, ft0, rne
+; RV32IFDIS:      fadd.s ft0, ft1, ft0, rne
   %1 = fadd float %a, %b
   %2 = call float @llvm.fabs.f32(float %1)
   %3 = fadd float %2, %1
   ret float %3
 }
 
 declare float @llvm.minnum.f32(float, float)
 

 ; RV64IF-LABEL: fmadd_s:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fmv.w.x ft0, a2
 ; RV64IF-NEXT:    fmv.w.x ft1, a1
 ; RV64IF-NEXT:    fmv.w.x ft2, a0
 ; RV64IF-NEXT:    fmadd.s ft0, ft2, ft1, ft0
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    ret
+
+; RV32IFDIS-LABEL: <fmadd_s>:
+; RV32IFDIS:      fmadd.s ft0, ft2, ft1, ft0, rne
   %1 = call float @llvm.fma.f32(float %a, float %b, float %c)
   ret float %1
 }
 
 define float @fmsub_s(float %a, float %b, float %c) nounwind {
 ; RV32IF-LABEL: fmsub_s:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fmv.w.x ft0, a1

 ; RV64IF-NEXT:    fmv.w.x ft0, a1
 ; RV64IF-NEXT:    fmv.w.x ft1, a0
 ; RV64IF-NEXT:    fmv.w.x ft2, a2
 ; RV64IF-NEXT:    fmv.w.x ft3, zero
 ; RV64IF-NEXT:    fadd.s ft2, ft2, ft3
 ; RV64IF-NEXT:    fmsub.s ft0, ft1, ft0, ft2
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    ret
+
+; RV32IFDIS-LABEL: <fmsub_s>:
+; RV32IFDIS:      fadd.s ft2, ft2, ft3, rne
+; RV32IFDIS:      fmsub.s ft0, ft1, ft0, ft2, rne
   %c_ = fadd float 0.0, %c ; avoid negation using xor
   %negc = fsub float -0.0, %c_
   %1 = call float @llvm.fma.f32(float %a, float %b, float %negc)
   ret float %1
 }
 
 define float @fnmadd_s(float %a, float %b, float %c) nounwind {
 ; RV32IF-LABEL: fnmadd_s:

 ; RV64IF-NEXT:    fmv.w.x ft1, a2
 ; RV64IF-NEXT:    fmv.w.x ft2, a0
 ; RV64IF-NEXT:    fmv.w.x ft3, zero
 ; RV64IF-NEXT:    fadd.s ft2, ft2, ft3
 ; RV64IF-NEXT:    fadd.s ft1, ft1, ft3
 ; RV64IF-NEXT:    fnmadd.s ft0, ft2, ft0, ft1
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    ret
+
+; RV32IFDIS-LABEL: <fnmadd_s>:
+; RV32IFDIS:      fadd.s ft2, ft2, ft3, rne
+; RV32IFDIS:      fadd.s ft1, ft1, ft3, rne
+; RV32IFDIS:      fnmadd.s ft0, ft2, ft0, ft1, rne
   %a_ = fadd float 0.0, %a
   %c_ = fadd float 0.0, %c
   %nega = fsub float -0.0, %a_
   %negc = fsub float -0.0, %c_
   %1 = call float @llvm.fma.f32(float %nega, float %b, float %negc)
   ret float %1
 }
 

 ; RV64IF-NEXT:    fmv.w.x ft1, a2
 ; RV64IF-NEXT:    fmv.w.x ft2, a1
 ; RV64IF-NEXT:    fmv.w.x ft3, zero
 ; RV64IF-NEXT:    fadd.s ft2, ft2, ft3
 ; RV64IF-NEXT:    fadd.s ft1, ft1, ft3
 ; RV64IF-NEXT:    fnmadd.s ft0, ft2, ft0, ft1
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    ret
+
+; RV32IFDIS-LABEL: <fnmadd_s_2>:
+; RV32IFDIS:      fadd.s ft2, ft2, ft3, rne
+; RV32IFDIS:      fadd.s ft1, ft1, ft3, rne
+; RV32IFDIS:      fnmadd.s ft0, ft2, ft0, ft1, rne
   %b_ = fadd float 0.0, %b
   %c_ = fadd float 0.0, %c
   %negb = fsub float -0.0, %b_
   %negc = fsub float -0.0, %c_
   %1 = call float @llvm.fma.f32(float %a, float %negb, float %negc)
   ret float %1
 }
 

 ; RV64IF-NEXT:    fmv.w.x ft0, a2
 ; RV64IF-NEXT:    fmv.w.x ft1, a1
 ; RV64IF-NEXT:    fmv.w.x ft2, a0
 ; RV64IF-NEXT:    fmv.w.x ft3, zero
 ; RV64IF-NEXT:    fadd.s ft2, ft2, ft3
 ; RV64IF-NEXT:    fnmsub.s ft0, ft2, ft1, ft0
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    ret
+
+; RV32IFDIS-LABEL: <fnmsub_s>:
+; RV32IFDIS:      fadd.s ft2, ft2, ft3, rne
+; RV32IFDIS:      fnmsub.s ft0, ft2, ft1, ft0, rne
   %a_ = fadd float 0.0, %a
   %nega = fsub float -0.0, %a_
   %1 = call float @llvm.fma.f32(float %nega, float %b, float %c)
   ret float %1
 }
 
 define float @fnmsub_s_2(float %a, float %b, float %c) nounwind {
 ; RV32IF-LABEL: fnmsub_s_2:

 ; RV64IF-NEXT:    fmv.w.x ft0, a2
 ; RV64IF-NEXT:    fmv.w.x ft1, a0
 ; RV64IF-NEXT:    fmv.w.x ft2, a1
 ; RV64IF-NEXT:    fmv.w.x ft3, zero
 ; RV64IF-NEXT:    fadd.s ft2, ft2, ft3
 ; RV64IF-NEXT:    fnmsub.s ft0, ft2, ft1, ft0
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    ret
+
+; RV32IFDIS-LABEL: <fnmsub_s_2>:
+; RV32IFDIS:      fadd.s ft2, ft2, ft3, rne
+; RV32IFDIS:      fnmsub.s ft0, ft2, ft1, ft0, rne
   %b_ = fadd float 0.0, %b
   %negb = fsub float -0.0, %b_
   %1 = call float @llvm.fma.f32(float %a, float %negb, float %c)
   ret float %1
 }
 
 define float @fmadd_s_contract(float %a, float %b, float %c) nounwind {
 ; RV32IF-LABEL: fmadd_s_contract:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fmv.w.x ft0, a2
 ; RV32IF-NEXT:    fmv.w.x ft1, a1
 ; RV32IF-NEXT:    fmv.w.x ft2, a0
 ; RV32IF-NEXT:    fmadd.s ft0, ft2, ft1, ft0
 ; RV32IF-NEXT:    fmv.x.w a0, ft0
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fmadd_s_contract:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fmv.w.x ft0, a2
 ; RV64IF-NEXT:    fmv.w.x ft1, a1
 ; RV64IF-NEXT:    fmv.w.x ft2, a0
 ; RV64IF-NEXT:    fmadd.s ft0, ft2, ft1, ft0
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    ret
+
+; RV32IFDIS-LABEL: <fmadd_s_contract>:
+; RV32IFDIS:      fmadd.s ft0, ft2, ft1, ft0, rne
   %1 = fmul contract float %a, %b
   %2 = fadd contract float %1, %c
   ret float %2
 }
 
 define float @fmsub_s_contract(float %a, float %b, float %c) nounwind {
 ; RV32IF-LABEL: fmsub_s_contract:
 ; RV32IF:       # %bb.0:

 ; RV64IF-NEXT:    fmv.w.x ft0, a1
 ; RV64IF-NEXT:    fmv.w.x ft1, a0
 ; RV64IF-NEXT:    fmv.w.x ft2, a2
 ; RV64IF-NEXT:    fmv.w.x ft3, zero
 ; RV64IF-NEXT:    fadd.s ft2, ft2, ft3
 ; RV64IF-NEXT:    fmsub.s ft0, ft1, ft0, ft2
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    ret
+
+; RV32IFDIS-LABEL: <fmsub_s_contract>:
+; RV32IFDIS:      fadd.s ft2, ft2, ft3, rne
+; RV32IFDIS:      fmsub.s ft0, ft1, ft0, ft2, rne
   %c_ = fadd float 0.0, %c ; avoid negation using xor
   %1 = fmul contract float %a, %b
   %2 = fsub contract float %1, %c_
   ret float %2
 }
 
 define float @fnmadd_s_contract(float %a, float %b, float %c) nounwind {
 ; RV32IF-LABEL: fnmadd_s_contract:

 ; RV64IF-NEXT:    fmv.w.x ft2, a0
 ; RV64IF-NEXT:    fmv.w.x ft3, zero
 ; RV64IF-NEXT:    fadd.s ft2, ft2, ft3
 ; RV64IF-NEXT:    fadd.s ft1, ft1, ft3
 ; RV64IF-NEXT:    fadd.s ft0, ft0, ft3
 ; RV64IF-NEXT:    fnmadd.s ft0, ft2, ft1, ft0
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    ret
+
+; RV32IFDIS-LABEL: <fnmadd_s_contract>:
+; RV32IFDIS:      fadd.s ft2, ft2, ft3, rne
+; RV32IFDIS:      fadd.s ft1, ft1, ft3, rne
+; RV32IFDIS:      fadd.s ft0, ft0, ft3, rne
+; RV32IFDIS:      fnmadd.s ft0, ft2, ft1, ft0, rne
   %a_ = fadd float 0.0, %a ; avoid negation using xor
   %b_ = fadd float 0.0, %b ; avoid negation using xor
   %c_ = fadd float 0.0, %c ; avoid negation using xor
   %1 = fmul contract float %a_, %b_
   %2 = fneg float %1
   %3 = fsub contract float %2, %c_
   ret float %3
 }

 ; RV64IF-NEXT:    fmv.w.x ft1, a1
 ; RV64IF-NEXT:    fmv.w.x ft2, a0
 ; RV64IF-NEXT:    fmv.w.x ft3, zero
 ; RV64IF-NEXT:    fadd.s ft2, ft2, ft3
 ; RV64IF-NEXT:    fadd.s ft1, ft1, ft3
 ; RV64IF-NEXT:    fnmsub.s ft0, ft2, ft1, ft0
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    ret
+
+; RV32IFDIS-LABEL: <fnmsub_s_contract>:
+; RV32IFDIS:      fadd.s ft2, ft2, ft3, rne
+; RV32IFDIS:      fadd.s ft1, ft1, ft3, rne
+; RV32IFDIS:      fnmsub.s ft0, ft2, ft1, ft0, rne
   %a_ = fadd float 0.0, %a ; avoid negation using xor
   %b_ = fadd float 0.0, %b ; avoid negation using xor
   %1 = fmul contract float %a_, %b_
   %2 = fsub contract float %c, %1
   ret float %2
 }