MVE has a dual lane vector move instruction, capable of moving two general purpose registers into lanes of a vector register. They look like one of:
vmov q0, q0, r2, r0 vmov q0, q0, r3, r1
They only accept these lane indices though (and only insert into an i32), either moving lanes 1 and 3, or 0 and 2.
This patch adds some tablegen patterns for them, selecting from vector inserts elements. Because the insert_elements are knows to be canonicalized to ascending order there are several patterns that we need to select. These lane indices are:
3 2 1 0 -> vmovqrr 31; vmovqrr 20 3 2 1 -> vmovqrr 31; vmov 2 3 1 -> vmovqrr 31 2 1 0 -> vmovqrr 20; vmov 1 2 0 -> vmovqrr 20
With the top one being the most common. All other potential patterns of lane indices will be matched by a combination of these and the individual vmov pattern already present. This does mean that we are selecting several machine instructions at once due to the need to re-arrange the inserts, but in this case there is at least nothing else that will attempt to match an insert_vector_elt node.