OpaquePtr: Require byval on x86_intrcc parameter 0

[arsenm]

Summary

Currently the backend special cases x86_intrcc and treats the first
parameter as byval. Make the IR require byval for this parameter to
remove this special case, and avoid the dependence on the pointee
element type.

Fixes bug 46672.

I'm not sure the IR is enforcing all the calling convention
constraints. clang seems to ignore the attribute for empty parameter
lists, but the IR tolerates it.

[craig.topper]

llvm/test/Bitcode/compatibility-6.0.ll

439

Why do we need to change arguments here? Isn't no arguments allowed?

441

What's this extra parenthese for?

[arsenm]

llvm/test/Bitcode/compatibility-6.0.ll

439

It is allowed, although I'm not sure if it should be. Clang just ignores the attribute on functions with no arguments

441

To surprise us that this actually parses

[arsenm]

Fix bitcode upgrade after rebase

[rnk]

lgtm

Thanks for removing that special case.

[dblaikie]

(generally I'd suggest splitting the clangc and llvm patches if at all possible - in this case I'm guessing the clang patch could go first (adding the attribute which would be redundant/unused initially), then the LLVM one?)

[arsenm]

ef4da3c2ba8a812a695361d786e3de8a8b2cd482+2e0e03c6a089da39039ec3f464f7cee5df86646b

clang/lib/CodeGen/TargetInfo.cpp

bool X86_32TargetCodeGenInfo::isStructReturnInRegABI(
   case llvm::Triple::OpenBSD:
   case llvm::Triple::Win32:
     return true;
   default:
     return false;
   }
 }
 
+static void addX86InterruptAttrs(const FunctionDecl *FD, llvm::GlobalValue *GV,
+                                 CodeGen::CodeGenModule &CGM) {
+  if (!FD->hasAttr<AnyX86InterruptAttr>())
+    return;
+
+  llvm::Function *Fn = cast<llvm::Function>(GV);
+  Fn->setCallingConv(llvm::CallingConv::X86_INTR);
+  if (FD->getNumParams() == 0)
+    return;
+
+  auto PtrTy = cast<PointerType>(FD->getParamDecl(0)->getType());
+  llvm::Type *ByValTy = CGM.getTypes().ConvertType(PtrTy->getPointeeType());
+  llvm::Attribute NewAttr = llvm::Attribute::getWithByValType(
+    Fn->getContext(), ByValTy);
+  Fn->addParamAttr(0, NewAttr);
+}
+
 void X86_32TargetCodeGenInfo::setTargetAttributes(
     const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const {
   if (GV->isDeclaration())
     return;
   if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
     if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) {
       llvm::Function *Fn = cast<llvm::Function>(GV);
       Fn->addFnAttr("stackrealign");
     }
-    if (FD->hasAttr<AnyX86InterruptAttr>()) {
-      llvm::Function *Fn = cast<llvm::Function>(GV);
-      Fn->setCallingConv(llvm::CallingConv::X86_INTR);
-    }
+
+    addX86InterruptAttrs(FD, GV, CGM);
   }
 }
 
 bool X86_32TargetCodeGenInfo::initDwarfEHRegSizeTable(
                                                CodeGen::CodeGenFunction &CGF,
                                                llvm::Value *Address) const {
   CodeGen::CGBuilderTy &Builder = CGF.Builder;
 
void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
                            CodeGen::CodeGenModule &CGM) const override {
     if (GV->isDeclaration())
       return;
     if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
       if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) {
         llvm::Function *Fn = cast<llvm::Function>(GV);
         Fn->addFnAttr("stackrealign");
       }
-      if (FD->hasAttr<AnyX86InterruptAttr>()) {
-        llvm::Function *Fn = cast<llvm::Function>(GV);
-        Fn->setCallingConv(llvm::CallingConv::X86_INTR);
-      }
+
+      addX86InterruptAttrs(FD, GV, CGM);
     }
   }
 
   void checkFunctionCallABI(CodeGenModule &CGM, SourceLocation CallLoc,
                             const FunctionDecl *Caller,
                             const FunctionDecl *Callee,
                             const CallArgList &Args) const override;
 };
void WinX86_64TargetCodeGenInfo::setTargetAttributes(
   TargetCodeGenInfo::setTargetAttributes(D, GV, CGM);
   if (GV->isDeclaration())
     return;
   if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) {
     if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) {
       llvm::Function *Fn = cast<llvm::Function>(GV);
       Fn->addFnAttr("stackrealign");
     }
-    if (FD->hasAttr<AnyX86InterruptAttr>()) {
-      llvm::Function *Fn = cast<llvm::Function>(GV);
-      Fn->setCallingConv(llvm::CallingConv::X86_INTR);
-    }
+
+    addX86InterruptAttrs(FD, GV, CGM);
   }
 
   addStackProbeTargetAttributes(D, GV, CGM);
 }
 }
 
 void X86_64ABIInfo::postMerge(unsigned AggregateSize, Class &Lo,
                               Class &Hi) const {

clang/test/CodeGen/attr-x86-interrupt.c

 // RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu %s -emit-llvm -o - | FileCheck %s --check-prefix=X86_64_LINUX
 // RUN: %clang_cc1 -triple i386-unknown-linux-gnu %s -emit-llvm -o - | FileCheck %s --check-prefix=X86_LINUX
 // RUN: %clang_cc1 -triple x86_64-pc-win32 %s -emit-llvm -o - | FileCheck %s --check-prefix=X86_64_WIN
 // RUN: %clang_cc1 -triple i386-pc-win32 %s -emit-llvm -o - | FileCheck %s --check-prefix=X86_WIN
 // RUN: %clang_cc1 -triple x86_64-unknown-linux-gnux32 %s -emit-llvm -o - | FileCheck %s --check-prefix=X86_64_LINUX
 
 #ifdef __x86_64__
 typedef __UINT64_TYPE__ uword;
 #else
 typedef __UINT32_TYPE__ uword;
 #endif
 
 __attribute__((interrupt)) void foo7(int *a, uword b) {}
 __attribute__((interrupt)) void foo8(int *a) {}
+
+
 // X86_64_LINUX: @llvm.used = appending global [2 x i8*] [i8* bitcast (void (i32*, i64)* @foo7 to i8*), i8* bitcast (void (i32*)* @foo8 to i8*)], section "llvm.metadata"
-// X86_64_LINUX: define x86_intrcc void @foo7(i32* %{{.+}}, i64 %{{.+}})
-// X86_64_LINUX: define x86_intrcc void @foo8(i32* %{{.+}})
+// X86_64_LINUX: define x86_intrcc void @foo7(i32* byval(i32) %{{.+}}, i64 %{{.+}})
+// X86_64_LINUX: define x86_intrcc void @foo8(i32* byval(i32) %{{.+}})
 // X86_64_LINUX: "disable-tail-calls"="true"
 // X86_64_LINUX-NOT: "disable-tail-calls"="false"
 // X86_LINUX: @llvm.used = appending global [2 x i8*] [i8* bitcast (void (i32*, i32)* @foo7 to i8*), i8* bitcast (void (i32*)* @foo8 to i8*)], section "llvm.metadata"
-// X86_LINUX: define x86_intrcc void @foo7(i32* %{{.+}}, i32 %{{.+}})
-// X86_LINUX: define x86_intrcc void @foo8(i32* %{{.+}})
+// X86_LINUX: define x86_intrcc void @foo7(i32* byval(i32) %{{.+}}, i32 %{{.+}})
+// X86_LINUX: define x86_intrcc void @foo8(i32* byval(i32) %{{.+}})
 // X86_LINUX: "disable-tail-calls"="true"
 // X86_LINUX-NOT: "disable-tail-calls"="false"
 // X86_64_WIN: @llvm.used = appending global [2 x i8*] [i8* bitcast (void (i32*, i64)* @foo7 to i8*), i8* bitcast (void (i32*)* @foo8 to i8*)], section "llvm.metadata"
-// X86_64_WIN: define dso_local x86_intrcc void @foo7(i32* %{{.+}}, i64 %{{.+}})
-// X86_64_WIN: define dso_local x86_intrcc void @foo8(i32* %{{.+}})
-// X86_64_Win: "disable-tail-calls"="true"
-// X86_64_Win-NOT: "disable-tail-calls"="false"
+// X86_64_WIN: define dso_local x86_intrcc void @foo7(i32* byval(i32) %{{.+}}, i64 %{{.+}})
+// X86_64_WIN: define dso_local x86_intrcc void @foo8(i32* byval(i32) %{{.+}})
+// X86_64_WIN: "disable-tail-calls"="true"
+// X86_64_WIN-NOT: "disable-tail-calls"="false"
 // X86_WIN: @llvm.used = appending global [2 x i8*] [i8* bitcast (void (i32*, i32)* @foo7 to i8*), i8* bitcast (void (i32*)* @foo8 to i8*)], section "llvm.metadata"
-// X86_WIN: define dso_local x86_intrcc void @foo7(i32* %{{.+}}, i32 %{{.+}})
-// X86_WIN: define dso_local x86_intrcc void @foo8(i32* %{{.+}})
-// X86_Win: "disable-tail-calls"="true"
-// X86_Win-NOT: "disable-tail-calls"="false"
+// X86_WIN: define dso_local x86_intrcc void @foo7(i32* byval(i32) %{{.+}}, i32 %{{.+}})
+// X86_WIN: define dso_local x86_intrcc void @foo8(i32* byval(i32) %{{.+}})
+// X86_WIN: "disable-tail-calls"="true"
+// X86_WIN-NOT: "disable-tail-calls"="false"

clang/test/CodeGenCXX/attr-x86-interrupt.cpp

 __attribute__((interrupt)) void foo7(int *a, uword b) {}
 namespace S {
 __attribute__((interrupt)) void foo8(int *a) {}
 }
 struct St {
 static void foo9(int *a) __attribute__((interrupt)) {}
 };
 // X86_64_LINUX: @llvm.used = appending global [3 x i8*] [i8* bitcast (void (i32*, i64)* @{{.*}}foo7{{.*}} to i8*), i8* bitcast (void (i32*)* @{{.*}}foo8{{.*}} to i8*), i8* bitcast (void (i32*)* @{{.*}}foo9{{.*}} to i8*)], section "llvm.metadata"
-// X86_64_LINUX: define x86_intrcc void @{{.*}}foo7{{.*}}(i32* %{{.+}}, i64 %{{.+}})
-// X86_64_LINUX: define x86_intrcc void @{{.*}}foo8{{.*}}(i32* %{{.+}})
-// X86_64_LINUX: define linkonce_odr x86_intrcc void @{{.*}}foo9{{.*}}(i32* %{{.+}})
+// X86_64_LINUX: define x86_intrcc void @{{.*}}foo7{{.*}}(i32* byval(i32) %{{.+}}, i64 %{{.+}})
+// X86_64_LINUX: define x86_intrcc void @{{.*}}foo8{{.*}}(i32* byval(i32) %{{.+}})
+// X86_64_LINUX: define linkonce_odr x86_intrcc void @{{.*}}foo9{{.*}}(i32* byval(i32) %{{.+}})
 // X86_LINUX: @llvm.used = appending global [3 x i8*] [i8* bitcast (void (i32*, i32)* @{{.*}}foo7{{.*}} to i8*), i8* bitcast (void (i32*)* @{{.*}}foo8{{.*}} to i8*), i8* bitcast (void (i32*)* @{{.*}}foo9{{.*}} to i8*)], section "llvm.metadata"
-// X86_LINUX: define x86_intrcc void @{{.*}}foo7{{.*}}(i32* %{{.+}}, i32 %{{.+}})
-// X86_LINUX: define x86_intrcc void @{{.*}}foo8{{.*}}(i32* %{{.+}})
-// X86_LINUX: define linkonce_odr x86_intrcc void @{{.*}}foo9{{.*}}(i32* %{{.+}})
+// X86_LINUX: define x86_intrcc void @{{.*}}foo7{{.*}}(i32* byval(i32) %{{.+}}, i32 %{{.+}})
+// X86_LINUX: define x86_intrcc void @{{.*}}foo8{{.*}}(i32* byval(i32) %{{.+}})
+// X86_LINUX: define linkonce_odr x86_intrcc void @{{.*}}foo9{{.*}}(i32* byval(i32) %{{.+}})
 // X86_64_WIN: @llvm.used = appending global [3 x i8*] [i8* bitcast (void (i32*, i64)* @{{.*}}foo7{{.*}} to i8*), i8* bitcast (void (i32*)* @{{.*}}foo8{{.*}} to i8*), i8* bitcast (void (i32*)* @{{.*}}foo9{{.*}} to i8*)], section "llvm.metadata"
-// X86_64_WIN: define dso_local x86_intrcc void @{{.*}}foo7{{.*}}(i32* %{{.+}}, i64 %{{.+}})
-// X86_64_WIN: define dso_local x86_intrcc void @{{.*}}foo8{{.*}}(i32* %{{.+}})
-// X86_64_WIN: define linkonce_odr dso_local x86_intrcc void @{{.*}}foo9{{.*}}(i32* %{{.+}})
+// X86_64_WIN: define dso_local x86_intrcc void @{{.*}}foo7{{.*}}(i32* byval(i32) %{{.+}}, i64 %{{.+}})
+// X86_64_WIN: define dso_local x86_intrcc void @{{.*}}foo8{{.*}}(i32* byval(i32) %{{.+}})
+// X86_64_WIN: define linkonce_odr dso_local x86_intrcc void @{{.*}}foo9{{.*}}(i32* byval(i32) %{{.+}})
 // X86_WIN: @llvm.used = appending global [3 x i8*] [i8* bitcast (void (i32*, i32)* @{{.*}}foo7{{.*}} to i8*), i8* bitcast (void (i32*)* @{{.*}}foo8{{.*}} to i8*), i8* bitcast (void (i32*)* @{{.*}}foo9{{.*}} to i8*)], section "llvm.metadata"
-// X86_WIN: define dso_local x86_intrcc void @{{.*}}foo7{{.*}}(i32* %{{.+}}, i32 %{{.+}})
-// X86_WIN: define dso_local x86_intrcc void @{{.*}}foo8{{.*}}(i32* %{{.+}})
-// X86_WIN: define linkonce_odr dso_local x86_intrcc void @{{.*}}foo9{{.*}}(i32* %{{.+}})
+// X86_WIN: define dso_local x86_intrcc void @{{.*}}foo7{{.*}}(i32* byval(i32) %{{.+}}, i32 %{{.+}})
+// X86_WIN: define dso_local x86_intrcc void @{{.*}}foo8{{.*}}(i32* byval(i32) %{{.+}})
+// X86_WIN: define linkonce_odr dso_local x86_intrcc void @{{.*}}foo9{{.*}}(i32* byval(i32) %{{.+}})

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

for (unsigned Value = 0, NumValues = ValueVTs.size();
         // preallocated.  This way we can know how many bytes we should've
         // allocated and how many bytes a callee cleanup function will pop.  If
         // we port preallocated to more targets, we'll have to add custom
         // preallocated handling in the various CC lowering callbacks.
         Flags.setByVal();
       }
 
       Type *ArgMemTy = nullptr;
-      if (F.getCallingConv() == CallingConv::X86_INTR) {
-        // IA Interrupt passes frame (1st parameter) by value in the stack.
-        if (ArgNo == 0) {
-          Flags.setByVal();
-          // FIXME: Dependence on pointee element type. See bug 46672.
-          ArgMemTy = Arg.getType()->getPointerElementType();
-        }
-      }
       if (Flags.isByVal() || Flags.isInAlloca() || Flags.isPreallocated() ||
           Flags.isByRef()) {
         if (!ArgMemTy)
           ArgMemTy = Arg.getPointeeInMemoryValueType();
 
         uint64_t MemSize = DL.getTypeAllocSize(ArgMemTy);
 
         // For in-memory arguments, size and alignment should be passed from FE.

llvm/lib/IR/AutoUpgrade.cpp

 
 void llvm::UpgradeFunctionAttributes(Function &F) {
   // If a function definition doesn't have the strictfp attribute,
   // convert any callsite strictfp attributes to nobuiltin.
   if (!F.isDeclaration() && !F.hasFnAttribute(Attribute::StrictFP)) {
     StrictFPUpgradeVisitor SFPV;
     SFPV.visit(F);
   }
+
+  if (F.getCallingConv() == CallingConv::X86_INTR &&
+      !F.arg_empty() && !F.hasParamAttribute(0, Attribute::ByVal)) {
+    Type *ByValTy = F.getParamByValType(0);
+    Attribute NewAttr = Attribute::getWithByValType(F.getContext(), ByValTy);
+    F.addParamAttr(0, NewAttr);
+  }
 }
 
 static bool isOldLoopArgument(Metadata *MD) {
   auto *T = dyn_cast_or_null<MDTuple>(MD);
   if (!T)
     return false;
   if (T->getNumOperands() < 1)
     return false;

llvm/lib/IR/Verifier.cpp

void Verifier::visitFunction(const Function &F) {
 
   // Check that this function meets the restrictions on this calling convention.
   // Sometimes varargs is used for perfectly forwarding thunks, so some of these
   // restrictions can be lifted.
   switch (F.getCallingConv()) {
   default:
   case CallingConv::C:
     break;
+  case CallingConv::X86_INTR: {
+    Assert(F.arg_empty() || Attrs.hasParamAttribute(0, Attribute::ByVal),
+           "Calling convention parameter requires byval", &F);
+    break;
+  }
   case CallingConv::AMDGPU_KERNEL:
   case CallingConv::SPIR_KERNEL:
     Assert(F.getReturnType()->isVoidTy(),
            "Calling convention requires void return type", &F);
     LLVM_FALLTHROUGH;
   case CallingConv::AMDGPU_VS:
   case CallingConv::AMDGPU_HS:
   case CallingConv::AMDGPU_GS:

llvm/test/Assembler/x86_intrcc.ll

+; RUN: llvm-as < %s | llvm-dis | FileCheck %s
+; RUN: verify-uselistorder %s
+
+; Make sure no arguments is accepted
+; CHECK: define x86_intrcc void @no_args() {
+define x86_intrcc void @no_args() {
+  ret void
+}
+
+; CHECK: define x86_intrcc void @byval_arg(i32* byval(i32) %0) {
+define x86_intrcc void @byval_arg(i32* byval(i32)) {
+  ret void
+}

llvm/test/Bitcode/compatibility-6.0.ll

 declare cc81 void @f.cc81()
 ; CHECK: declare hhvmcc void @f.cc81()
 declare hhvmcc void @f.hhvmcc()
 ; CHECK: declare hhvmcc void @f.hhvmcc()
 declare cc82 void @f.cc82()
 ; CHECK: declare hhvm_ccc void @f.cc82()
 declare hhvm_ccc void @f.hhvm_ccc()
 ; CHECK: declare hhvm_ccc void @f.hhvm_ccc()
-declare cc83 void @f.cc83()
+declare cc83 void @f.cc83(i8* byval(i8))
 ; CHECK: declare x86_intrcc void @f.cc83()
-declare x86_intrcc void @f.x86_intrcc()
+declare x86_intrcc void @f.x86_intrcc())
 ; CHECK: declare x86_intrcc void @f.x86_intrcc()
 declare cc84 void @f.cc84()
 ; CHECK: declare avr_intrcc void @f.cc84()
 declare avr_intrcc void @f.avr_intrcc()
 ; CHECK: declare avr_intrcc void @f.avr_intrcc()
 declare cc85 void @f.cc85()
 ; CHECK: declare avr_signalcc void @f.cc85()
 declare avr_signalcc void @f.avr_signalcc()

llvm/test/Bitcode/compatibility.ll

 declare cc81 void @f.cc81()
 ; CHECK: declare hhvmcc void @f.cc81()
 declare hhvmcc void @f.hhvmcc()
 ; CHECK: declare hhvmcc void @f.hhvmcc()
 declare cc82 void @f.cc82()
 ; CHECK: declare hhvm_ccc void @f.cc82()
 declare hhvm_ccc void @f.hhvm_ccc()
 ; CHECK: declare hhvm_ccc void @f.hhvm_ccc()
-declare cc83 void @f.cc83()
-; CHECK: declare x86_intrcc void @f.cc83()
-declare x86_intrcc void @f.x86_intrcc()
-; CHECK: declare x86_intrcc void @f.x86_intrcc()
+declare cc83 void @f.cc83(i8* byval(i8))
+; CHECK: declare x86_intrcc void @f.cc83(i8* byval(i8))
+declare x86_intrcc void @f.x86_intrcc(i8* byval(i8))
+; CHECK: declare x86_intrcc void @f.x86_intrcc(i8* byval(i8))
 declare cc84 void @f.cc84()
 ; CHECK: declare avr_intrcc void @f.cc84()
 declare avr_intrcc void @f.avr_intrcc()
 ; CHECK: declare avr_intrcc void @f.avr_intrcc()
 declare cc85 void @f.cc85()
 ; CHECK: declare avr_signalcc void @f.cc85()
 declare avr_signalcc void @f.avr_signalcc()
 ; CHECK: declare avr_signalcc void @f.avr_signalcc()

llvm/test/Bitcode/x86_intr-upgrade.test

+RUN: llvm-dis %p/Inputs/x86_intrcc_upgrade.bc -o - | FileCheck %s
+
+Make sure we upgrade x86_intrcc to a byval with explicit type
+
+CHECK: define x86_intrcc void @no_args() {
+CHECK: define x86_intrcc void @non_byval_ptr_arg0(i32* byval(i32) %0)
+CHECK: define x86_intrcc void @non_byval_ptr_struct(%struct* byval(%struct) %0)
+
+CHECK: declare x86_intrcc void @no_args_decl()
+CHECK: declare x86_intrcc void @non_byval_ptr_arg0_decl(i32* byval(i32))
+CHECK: declare x86_intrcc void @non_byval_ptr_struct_decl(%struct* byval(%struct))

llvm/test/CodeGen/X86/x86-32-intrcc.ll

 ; RUN: llc -mtriple=i686-unknown-unknown < %s | FileCheck %s
 ; RUN: llc -mtriple=i686-unknown-unknown -O0 < %s | FileCheck %s -check-prefix=CHECK0
 
 %struct.interrupt_frame = type { i32, i32, i32, i32, i32 }
 
 @sink_address = global i32* null
 @sink_i32 = global i32 0
 
 
 ; Spills eax, putting original esp at +4.
 ; No stack adjustment if declared with no error code
-define x86_intrcc void @test_isr_no_ecode(%struct.interrupt_frame* %frame) {
+define x86_intrcc void @test_isr_no_ecode(%struct.interrupt_frame* byval(%struct.interrupt_frame) %frame) {
   ; CHECK-LABEL: test_isr_no_ecode:
   ; CHECK: pushl %eax
   ; CHECK: movl 12(%esp), %eax
   ; CHECK: popl %eax
   ; CHECK: iretl
   ; CHECK0-LABEL: test_isr_no_ecode:
   ; CHECK0: pushl %eax
   ; CHECK0: leal 4(%esp), %eax
   ; CHECK0: movl 8(%eax), %eax
   ; CHECK0: popl %eax
   ; CHECK0: iretl
   %pflags = getelementptr inbounds %struct.interrupt_frame, %struct.interrupt_frame* %frame, i32 0, i32 2
   %flags = load i32, i32* %pflags, align 4
   call void asm sideeffect "", "r"(i32 %flags)
   ret void
 }
 
 ; Spills eax and ecx, putting original esp at +8. Stack is adjusted up another 4 bytes
 ; before return, popping the error code.
-define x86_intrcc void @test_isr_ecode(%struct.interrupt_frame* %frame, i32 %ecode) {
+define x86_intrcc void @test_isr_ecode(%struct.interrupt_frame* byval(%struct.interrupt_frame) %frame, i32 %ecode) {
   ; CHECK-LABEL: test_isr_ecode
   ; CHECK: pushl %ecx
   ; CHECK: pushl %eax
   ; CHECK: movl 8(%esp), %eax
   ; CHECK: movl 20(%esp), %ecx
   ; CHECK: popl %eax
   ; CHECK: popl %ecx
   ; CHECK: addl $4, %esp
define x86_intrcc void @test_isr_ecode(%struct.interrupt_frame* byval(%struct.interrupt_frame) %frame, i32 %ecode) {
   ; CHECK0: iretl
   %pflags = getelementptr inbounds %struct.interrupt_frame, %struct.interrupt_frame* %frame, i32 0, i32 2
   %flags = load i32, i32* %pflags, align 4
   call x86_fastcallcc void asm sideeffect "", "r,r"(i32 %flags, i32 %ecode)
   ret void
 }
 
 ; All clobbered registers must be saved
-define x86_intrcc void @test_isr_clobbers(%struct.interrupt_frame* %frame, i32 %ecode) {
+define x86_intrcc void @test_isr_clobbers(%struct.interrupt_frame* byval(%struct.interrupt_frame) %frame, i32 %ecode) {
   call void asm sideeffect "", "~{eax},~{ebx},~{ebp}"()
   ; CHECK-LABEL: test_isr_clobbers
   ; CHECK: pushl %ebp
   ; CHECK: pushl %ebx
   ; CHECK: pushl %eax
   ; CHECK: popl %eax
   ; CHECK: popl %ebx
   ; CHECK: popl %ebp
define x86_intrcc void @test_isr_clobbers(%struct.interrupt_frame* byval(%struct.interrupt_frame) %frame, i32 %ecode) {
   ; CHECK0: addl $4, %esp
   ; CHECK0: iretl
   ret void
 }
 
 @f80 = common global x86_fp80 0xK00000000000000000000, align 4
 
 ; Test that the presence of x87 does not crash the FP stackifier
-define x86_intrcc void @test_isr_x87(%struct.interrupt_frame* %frame) {
+define x86_intrcc void @test_isr_x87(%struct.interrupt_frame* byval(%struct.interrupt_frame) %frame) {
   ; CHECK-LABEL: test_isr_x87
   ; CHECK-DAG: fldt f80
   ; CHECK-DAG: fld1
   ; CHECK: faddp
   ; CHECK-NEXT: fstpt f80
   ; CHECK-NEXT: iretl
 entry:
   %ld = load x86_fp80, x86_fp80* @f80, align 4
   %add = fadd x86_fp80 %ld, 0xK3FFF8000000000000000
   store x86_fp80 %add, x86_fp80* @f80, align 4
   ret void
 }
 
 ; Use a frame pointer to check the offsets. No return address, arguments start
 ; at EBP+4.
-define dso_local x86_intrcc void @test_fp_1(%struct.interrupt_frame* %p) #0 {
+define dso_local x86_intrcc void @test_fp_1(%struct.interrupt_frame* byval(%struct.interrupt_frame) %p) #0 {
   ; CHECK-LABEL: test_fp_1:
   ; CHECK: # %bb.0: # %entry
   ; CHECK-NEXT: pushl %ebp
   ; CHECK-NEXT: movl %esp, %ebp
   ; CHECK: cld
   ; CHECK-DAG: leal 4(%ebp), %[[R1:[^ ]*]]
   ; CHECK-DAG: leal 20(%ebp), %[[R2:[^ ]*]]
   ; CHECK: movl %[[R1]], sink_address
   ; CHECK: movl %[[R2]], sink_address
   ; CHECK: popl %ebp
   ; CHECK: iretl
 entry:
   %arrayidx = getelementptr inbounds %struct.interrupt_frame, %struct.interrupt_frame* %p, i32 0, i32 0
   %arrayidx2 = getelementptr inbounds %struct.interrupt_frame, %struct.interrupt_frame* %p, i32 0, i32 4
   store volatile i32* %arrayidx, i32** @sink_address
   store volatile i32* %arrayidx2, i32** @sink_address
   ret void
 }
 
 ; The error code is between EBP and the interrupt_frame.
-define dso_local x86_intrcc void @test_fp_2(%struct.interrupt_frame* %p, i32 %err) #0 {
+define dso_local x86_intrcc void @test_fp_2(%struct.interrupt_frame* byval(%struct.interrupt_frame) %p, i32 %err) #0 {
   ; CHECK-LABEL: test_fp_2:
   ; CHECK: # %bb.0: # %entry
   ; CHECK-NEXT: pushl %ebp
   ; CHECK-NEXT: movl %esp, %ebp
   ; CHECK: cld
   ; CHECK-DAG: movl 4(%ebp), %[[R3:[^ ]*]]
   ; CHECK-DAG: leal 8(%ebp), %[[R1:[^ ]*]]
   ; CHECK-DAG: leal 24(%ebp), %[[R2:[^ ]*]]
   ; CHECK: movl %[[R1]], sink_address
   ; CHECK: movl %[[R2]], sink_address
   ; CHECK: movl %[[R3]], sink_i32
   ; CHECK: popl %ebp
   ; CHECK: iretl
 entry:
   %arrayidx = getelementptr inbounds %struct.interrupt_frame, %struct.interrupt_frame* %p, i32 0, i32 0
   %arrayidx2 = getelementptr inbounds %struct.interrupt_frame, %struct.interrupt_frame* %p, i32 0, i32 4
   store volatile i32* %arrayidx, i32** @sink_address
   store volatile i32* %arrayidx2, i32** @sink_address
   store volatile i32 %err, i32* @sink_i32
   ret void
 }
 
 ; Test argument copy elision when copied to a local alloca.
-define x86_intrcc void @test_copy_elide(%struct.interrupt_frame* %frame, i32 %err) #0 {
+define x86_intrcc void @test_copy_elide(%struct.interrupt_frame* byval(%struct.interrupt_frame) %frame, i32 %err) #0 {
   ; CHECK-LABEL: test_copy_elide:
   ; CHECK: # %bb.0: # %entry
   ; CHECK-NEXT: pushl %ebp
   ; CHECK-NEXT: movl %esp, %ebp
   ; CHECK: cld
   ; CHECK: leal 4(%ebp), %[[R1:[^ ]*]]
   ; CHECK: movl %[[R1]], sink_address
 entry:
   %err.addr = alloca i32, align 4
   store i32 %err, i32* %err.addr, align 4
   store volatile i32* %err.addr, i32** @sink_address
   ret void
 }
 
 attributes #0 = { nounwind "frame-pointer"="all" }

llvm/test/CodeGen/X86/x86-64-intrcc-nosse.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=-sse < %s | FileCheck %s
 
 %struct.interrupt_frame = type { i64, i64, i64, i64, i64 }
 
 @llvm.used = appending global [1 x i8*] [i8* bitcast (void (%struct.interrupt_frame*, i64)* @test_isr_sse_clobbers to i8*)], section "llvm.metadata"
 
 ; Clobbered SSE must not be saved when the target doesn't support SSE
-define x86_intrcc void @test_isr_sse_clobbers(%struct.interrupt_frame* %frame, i64 %ecode) {
+define x86_intrcc void @test_isr_sse_clobbers(%struct.interrupt_frame* byval(%struct.interrupt_frame) %frame, i64 %ecode) {
   ; CHECK-LABEL: test_isr_sse_clobbers:
   ; CHECK:       # %bb.0:
   ; CHECK-NEXT:    pushq %rax
   ; CHECK-NEXT:    cld
   ; CHECK-NEXT:    #APP
   ; CHECK-NEXT:    #NO_APP
   ; CHECK-NEXT:    addq $16, %rsp
   ; CHECK-NEXT:    iretq
   call void asm sideeffect "", "~{xmm0},~{xmm6}"()
   ret void
 }

llvm/test/CodeGen/X86/x86-64-intrcc.ll

 ; RUN: llc -mtriple=x86_64-unknown-unknown < %s | FileCheck %s
 ; RUN: llc -mtriple=x86_64-unknown-unknown -O0 < %s | FileCheck %s -check-prefix=CHECK0
 
 %struct.interrupt_frame = type { i64, i64, i64, i64, i64 }
 
 @sink_address = global i64* null
 @sink_i32 = global i64 0
 
 ; Spills rax, putting original esp at +8.
 ; No stack adjustment if declared with no error code
-define x86_intrcc void @test_isr_no_ecode(%struct.interrupt_frame* %frame) {
+define x86_intrcc void @test_isr_no_ecode(%struct.interrupt_frame* byval(%struct.interrupt_frame) %frame) {
   ; CHECK-LABEL: test_isr_no_ecode:
   ; CHECK: pushq %rax
   ; CHECK: movq 24(%rsp), %rax
   ; CHECK: popq %rax
   ; CHECK: iretq
   ; CHECK0-LABEL: test_isr_no_ecode:
   ; CHECK0: pushq %rax
   ; CHECK0: leaq 8(%rsp), %rax
   ; CHECK0: movq 16(%rax), %rax
   ; CHECK0: popq %rax
   ; CHECK0: iretq
   %pflags = getelementptr inbounds %struct.interrupt_frame, %struct.interrupt_frame* %frame, i32 0, i32 2
   %flags = load i64, i64* %pflags, align 4
   call void asm sideeffect "", "r"(i64 %flags)
   ret void
 }
 
 ; Spills rax and rcx, putting original rsp at +16. Stack is adjusted up another 8 bytes
 ; before return, popping the error code.
-define x86_intrcc void @test_isr_ecode(%struct.interrupt_frame* %frame, i64 %ecode) {
+define x86_intrcc void @test_isr_ecode(%struct.interrupt_frame* byval(%struct.interrupt_frame) %frame, i64 %ecode) {
   ; CHECK-LABEL: test_isr_ecode
   ; CHECK: pushq %rax
   ; CHECK: pushq %rax
   ; CHECK: pushq %rcx
   ; CHECK: movq 24(%rsp), %rax
   ; CHECK: movq 48(%rsp), %rcx
   ; CHECK: popq %rcx
   ; CHECK: popq %rax
define x86_intrcc void @test_isr_ecode(%struct.interrupt_frame* byval(%struct.interrupt_frame) %frame, i64 %ecode) {
   ; CHECK0: iretq
   %pflags = getelementptr inbounds %struct.interrupt_frame, %struct.interrupt_frame* %frame, i32 0, i32 2
   %flags = load i64, i64* %pflags, align 4
   call void asm sideeffect "", "r,r"(i64 %flags, i64 %ecode)
   ret void
 }
 
 ; All clobbered registers must be saved
-define x86_intrcc void @test_isr_clobbers(%struct.interrupt_frame* %frame, i64 %ecode) {
+define x86_intrcc void @test_isr_clobbers(%struct.interrupt_frame* byval(%struct.interrupt_frame) %frame, i64 %ecode) {
   call void asm sideeffect "", "~{rax},~{rbx},~{rbp},~{r11},~{xmm0}"()
   ; CHECK-LABEL: test_isr_clobbers
 
   ; CHECK: pushq %rax
   ; CHECK: pushq %rbp
   ; CHECK: pushq %r11
   ; CHECK: pushq %rbx
   ; CHECK: movaps %xmm0
define x86_intrcc void @test_isr_clobbers(%struct.interrupt_frame* byval(%struct.interrupt_frame) %frame, i64 %ecode) {
   ; CHECK0: addq $16, %rsp
   ; CHECK0: iretq
   ret void
 }
 
 @f80 = common global x86_fp80 0xK00000000000000000000, align 4
 
 ; Test that the presence of x87 does not crash the FP stackifier
-define x86_intrcc void @test_isr_x87(%struct.interrupt_frame* %frame) {
+define x86_intrcc void @test_isr_x87(%struct.interrupt_frame* byval(%struct.interrupt_frame) %frame) {
   ; CHECK-LABEL: test_isr_x87
   ; CHECK-DAG: fldt f80
   ; CHECK-DAG: fld1
   ; CHECK: faddp
   ; CHECK-NEXT: fstpt f80
   ; CHECK-NEXT: iretq
 entry:
   %ld = load x86_fp80, x86_fp80* @f80, align 4
   %add = fadd x86_fp80 %ld, 0xK3FFF8000000000000000
   store x86_fp80 %add, x86_fp80* @f80, align 4
   ret void
 }
 
 ; Use a frame pointer to check the offsets. No return address, arguments start
 ; at RBP+4.
-define dso_local x86_intrcc void @test_fp_1(%struct.interrupt_frame* %p) #0 {
+define dso_local x86_intrcc void @test_fp_1(%struct.interrupt_frame* byval(%struct.interrupt_frame) %p) #0 {
   ; CHECK-LABEL: test_fp_1:
   ; CHECK: # %bb.0: # %entry
   ; CHECK-NEXT: pushq %rbp
   ; CHECK-NEXT: movq %rsp, %rbp
   ; CHECK: cld
   ; CHECK-DAG: leaq 8(%rbp), %[[R1:[^ ]*]]
   ; CHECK-DAG: leaq 40(%rbp), %[[R2:[^ ]*]]
   ; CHECK: movq %[[R1]], sink_address
   ; CHECK: movq %[[R2]], sink_address
   ; CHECK: popq %rbp
   ; CHECK: iretq
 entry:
   %arrayidx = getelementptr inbounds %struct.interrupt_frame, %struct.interrupt_frame* %p, i64 0, i32 0
   %arrayidx2 = getelementptr inbounds %struct.interrupt_frame, %struct.interrupt_frame* %p, i64 0, i32 4
   store volatile i64* %arrayidx, i64** @sink_address
   store volatile i64* %arrayidx2, i64** @sink_address
   ret void
 }
 
 ; The error code is between RBP and the interrupt_frame.
-define dso_local x86_intrcc void @test_fp_2(%struct.interrupt_frame* %p, i64 %err) #0 {
+define dso_local x86_intrcc void @test_fp_2(%struct.interrupt_frame* byval(%struct.interrupt_frame) %p, i64 %err) #0 {
   ; CHECK-LABEL: test_fp_2:
   ; CHECK: # %bb.0: # %entry
   ; This RAX push is just to align the stack.
   ; CHECK-NEXT: pushq %rax
   ; CHECK-NEXT: pushq %rbp
   ; CHECK-NEXT: movq %rsp, %rbp
   ; CHECK: cld
   ; CHECK-DAG: movq 16(%rbp), %[[R3:[^ ]*]]
entry:
   %arrayidx2 = getelementptr inbounds %struct.interrupt_frame, %struct.interrupt_frame* %p, i64 0, i32 4
   store volatile i64* %arrayidx, i64** @sink_address
   store volatile i64* %arrayidx2, i64** @sink_address
   store volatile i64 %err, i64* @sink_i32
   ret void
 }
 
 ; Test argument copy elision when copied to a local alloca.
-define x86_intrcc void @test_copy_elide(%struct.interrupt_frame* %frame, i64 %err) #0 {
+define x86_intrcc void @test_copy_elide(%struct.interrupt_frame* byval(%struct.interrupt_frame) %frame, i64 %err) #0 {
   ; CHECK-LABEL: test_copy_elide:
   ; CHECK: # %bb.0: # %entry
   ; This RAX push is just to align the stack.
   ; CHECK-NEXT: pushq %rax
   ; CHECK-NEXT: pushq %rbp
   ; CHECK-NEXT: movq %rsp, %rbp
   ; CHECK: cld
   ; CHECK: leaq 16(%rbp), %[[R1:[^ ]*]]

llvm/test/CodeGen/X86/x86-interrupt_cc.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=x86_64-apple-macosx -show-mc-encoding -mcpu=knl < %s | FileCheck %s -check-prefix=CHECK64-KNL
 ; RUN: llc -verify-machineinstrs -mtriple=x86_64-apple-macosx -show-mc-encoding -mcpu=skx < %s | FileCheck %s -check-prefix=CHECK64-SKX
 ; RUN: llc -verify-machineinstrs -mtriple=i386-apple-macosx -show-mc-encoding -mcpu=knl < %s | FileCheck %s -check-prefix=CHECK32-KNL
 ; RUN: llc -verify-machineinstrs -mtriple=i386-apple-macosx -show-mc-encoding -mcpu=skx < %s | FileCheck %s -check-prefix=CHECK32-SKX
 
 ; Make sure we spill the high numbered zmm registers and K registers with the right encoding.
 
-define x86_intrcc void @foo(i8* %frame) {
+define x86_intrcc void @foo(i8* byval(i8) %frame) {
 ; CHECK64-KNL-LABEL: foo:
 ; CHECK64-KNL:       ## %bb.0:
 ; CHECK64-KNL-NEXT:    pushq %rax ## encoding: [0x50]
 ; CHECK64-KNL-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK64-KNL-NEXT:    pushq %r11 ## encoding: [0x41,0x53]
 ; CHECK64-KNL-NEXT:    .cfi_def_cfa_offset 24
 ; CHECK64-KNL-NEXT:    pushq %r10 ## encoding: [0x41,0x52]
 ; CHECK64-KNL-NEXT:    .cfi_def_cfa_offset 32

llvm/test/CodeGen/X86/x86-interrupt_cld.ll

 ; RUN: llc -mtriple=x86_64-unknown-unknown < %s | FileCheck %s
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;; Checks that interrupt handler code calls cld before calling an external
 ;; function.
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 ; CHECK: cld
 ; CHECK: call
 
-define x86_intrcc void @foo(i8* %frame) {
+define x86_intrcc void @foo(i8* byval(i8) %frame) {
   call void @bar()
   ret void
 }
 
 declare void @bar()
 

llvm/test/CodeGen/X86/x86-interrupt_vzeroupper.ll

 ; RUN: llc -verify-machineinstrs -mtriple=x86_64-unknown-unknown -mattr=+avx < %s | FileCheck %s
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;; Checks that interrupt handler code does not call "vzeroupper" instruction
 ;; before iret.
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 ; CHECK: vzeroupper
 ; CHECK-NEXT: call
 ; CHECK-NOT: vzeroupper
 ; CHECK: iret
 
-define x86_intrcc void @foo(i8* %frame) {
+define x86_intrcc void @foo(i8* byval(i8) %frame) {
   call void @bar()
   ret void
 }
 
 declare void @bar()
 

llvm/test/CodeGen/X86/x86-no_caller_saved_registers.ll

 ; RUN: llc -mtriple=x86_64-unknown-unknown < %s | FileCheck %s
 ; RUN: llc -mtriple=x86_64-unknown-unknown -O0 < %s | FileCheck %s
 ; RUN: llc -mtriple=i686-unknown-unknown -mattr=+sse2 < %s | FileCheck %s
 ; RUN: llc -mtriple=i686-unknown-unknown -mattr=+sse2 -O0 < %s | FileCheck %s
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;; In functions with 'no_caller_saved_registers' attribute, all registers should
 ;; be preserved except for registers used for passing/returning arguments.
 ;; The test checks that function "bar" preserves xmm0 register.
-;; It also checks that caller function "foo" does not store registers for callee 
+;; It also checks that caller function "foo" does not store registers for callee
 ;; "bar". For example, there is no store/load/access to xmm registers.
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 define i32 @bar(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6, i32 %a7, i32 %a8) #0 {
 ; CHECK-LABEL: bar
 ; CHECK:       mov{{.*}}  %xmm0
 ; CHECK:       mov{{.*}} {{.*}}, %xmm0
 ; CHECK:       ret
   call void asm sideeffect "", "~{xmm0}"()
   ret i32 1
 }
 
-define x86_intrcc void @foo(i8* nocapture readnone %c) {
+define x86_intrcc void @foo(i8* byval(i8) nocapture readnone %c) {
 ; CHECK-LABEL: foo
 ; CHECK-NOT: xmm
 entry:
   tail call i32 @bar(i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8) #0
   ret void
 }
 
 attributes #0 = { "no_caller_saved_registers" }

llvm/test/Verifier/x86_intr.ll

+; RUN: not llvm-as < %s 2>&1 | FileCheck %s
+
+; CHECK: Calling convention parameter requires byval
+; CHECK-NEXT: void (i32)* @non_ptr_arg0
+define x86_intrcc void @non_ptr_arg0(i32) {
+  ret void
+}
+
+; CHECK: Calling convention parameter requires byval
+; CHECK-NEXT: void (i32*)* @non_byval_ptr_arg0
+define x86_intrcc void @non_byval_ptr_arg0(i32*) {
+  ret void
+}
+
+; CHECK: Calling convention parameter requires byval
+; CHECK-NEXT: void (i32)* @non_ptr_arg0_decl
+declare x86_intrcc void @non_ptr_arg0_decl(i32)
+
+; CHECK: Calling convention parameter requires byval
+; CHECK-NEXT: void (i32*)* @non_byval_ptr_arg0_decl
+declare x86_intrcc void @non_byval_ptr_arg0_decl(i32*)