This is an archive of the discontinued LLVM Phabricator instance.

[RISCV] Custom type legalize i32 fshl/fshr on RV64 with Zbt.
ClosedPublic

Authored by craig.topper on Nov 14 2020, 12:18 AM.

Details

Summary

This adds custom opcodes for FSLW/FSRW so we can type legalize
fshl/fshr without needing to match a sign_extend_inreg.

I've used the operand order from fshl/fshr to make the isel
pattern similar to the non-W form. It was also hard to decide
another order since the register instruction has the shift amount
as the second operand, but the immediate instruction has it as
the third operand.

Diff Detail

Event Timeline

craig.topper created this revision.Nov 14 2020, 12:18 AM
Herald added a project: Restricted Project. · View Herald TranscriptNov 14 2020, 12:18 AM
craig.topper requested review of this revision.Nov 14 2020, 12:18 AM
frasercrmck added inline comments.Nov 23 2020, 3:23 AM
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
1100

I think it's worth introducing a scope here, so someone adding a case after this won't have to.

craig.topper added inline comments.Nov 23 2020, 11:53 AM
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
1100

Good catch. Thanks!

Address review comment

This revision is now accepted and ready to land.Nov 25 2020, 1:33 AM