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[lldb] [Process/FreeBSDRemote] Support YMM reg via PT_*XSTATE
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Authored by mgorny on Oct 10 2020, 11:13 AM.

Details

Summary

Add a framework for reading/writing extended register sets via
PT_GETXSTATE/PT_GETXSTATE_INFO/PT_SETXSTATE, and use it to support
YMM0..YMM15. The code is prepared to handle arbitrary XSAVE extensions,
including correct offset handling.

This fixes Shell/Register/*ymm* tests.

Diff Detail

Event Timeline

mgorny requested review of this revision.Oct 10 2020, 11:13 AM
mgorny created this revision.
mgorny added inline comments.
lldb/source/Plugins/Process/FreeBSDRemote/NativeRegisterContextFreeBSD_x86_64.cpp
479

@labath, is this a safe assumption to make? Generally, if ReadRegisterSet() is not called, m_xsave will be zero-sized.

krytarowski added a subscriber: bsdjhb.

+ @bsdjhb John, could you have a look?

mgorny updated this revision to Diff 297431.Oct 10 2020, 1:41 PM

Remove accidental reformatting.

I assume this fixes some of the tests we have already, but it would be good to mention that in the description.

lldb/source/Plugins/Process/FreeBSDRemote/NativeRegisterContextFreeBSD_x86_64.cpp
479

Interesting question. I don't really have an answer to that. Somebody obviously should fill out m_xsave before calling this function, but maybe it doesn't have to be ReadRegisterSet()? What will happen if the client sends a G packet before reading any registers?

That said, I'm not particularly troubled by this assertion. I wouldn't be surprised if we already had code making that assumption without even realizing it.

Looks OK

lldb/source/Plugins/Process/FreeBSDRemote/NativeRegisterContextFreeBSD_x86_64.cpp
448–449

I wonder if these should be an error rather than assertion?

mgorny added inline comments.Oct 13 2020, 9:54 AM
lldb/source/Plugins/Process/FreeBSDRemote/NativeRegisterContextFreeBSD_x86_64.cpp
448–449

I suppose the question is if they ever happen in real use. If they do, we should probably handle them gracefully. Otherwise, assertion should be sufficient.

mgorny added inline comments.Oct 13 2020, 9:58 AM
lldb/source/Plugins/Process/FreeBSDRemote/NativeRegisterContextFreeBSD_x86_64.cpp
448–449

I can actually answer the first question myself. According to Intel's manual, it is impossible to disable x87 bit. IIRC attempt to unset it on XCR0 will raise some fault.

The second question is basically whether under any circumstances can FreeBSD kernel disable SSE on XCR0 (this code is only used on systems supporting XSAVE).

emaste added inline comments.Oct 13 2020, 11:04 AM
lldb/source/Plugins/Process/FreeBSDRemote/NativeRegisterContextFreeBSD_x86_64.cpp
448–449

I guess my point is that having these bits unset would indicate a kernel issue or bug, or maybe hardware issue, but never indicate an error or invalid operation in lldb itself.

Either way I think there is no practical impact, it's not actually going to happen.

krytarowski added inline comments.Oct 13 2020, 11:08 AM
lldb/source/Plugins/Process/FreeBSDRemote/NativeRegisterContextFreeBSD_x86_64.cpp
448–449

If we assert on this code we more trigger software bug in lldb rather than a hardware specifics.

mgorny marked 4 inline comments as done.Oct 13 2020, 12:33 PM
mgorny added inline comments.
lldb/source/Plugins/Process/FreeBSDRemote/NativeRegisterContextFreeBSD_x86_64.cpp
448–449

I think that's roughly the purpose assertions serve. If something is terribly broken, it will blow up on the developers but it will be optimized away in normal work.

479

Actually, I didn't realize WriteRegisterSet() is local to the plugin. In this case, I can easily verify it's never called like this, so I'll just update the comment and leave the assert so that we don't break it in the future.

mgorny updated this revision to Diff 297932.Oct 13 2020, 12:34 PM
mgorny marked an inline comment as done.
mgorny edited the summary of this revision. (Show Details)

Updated the comment above assertion, and indicated fixed tests in the description.

krytarowski accepted this revision.Oct 14 2020, 6:47 AM
This revision is now accepted and ready to land.Oct 14 2020, 6:47 AM
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