RegAllocFast: Add extra DBG_VALUE for live out spills

[arsenm]

Summary

This allows LiveDebugValues to insert the proper DBG_VALUEs in live
out blocks if a spill is inserted before the use of a
register. Previously, this would see the register use as the last
DBG_VALUE, even though the stack slot should be treated as the live
out value.

This avoids an lldb test regression when D52010 is re-applied.

[aprantl]

This looks really promising!

llvm/test/DebugInfo/X86/subreg.ll

13

what's up here? Did we regress?

[arsenm]

llvm/test/DebugInfo/X86/subreg.ll

13

No, this is reverting a previous change to this test to ensure it's still checking the subregister, and not the spill slot as it seems intended to stress

[arsenm]

7fccb42cc62da93dbf79de9e6464a975bf5b37bc

llvm/lib/CodeGen/RegAllocFast.cpp

#endif
     void reloadAtBegin(MachineBasicBlock &MBB);
     void setPhysReg(MachineInstr &MI, MachineOperand &MO, MCPhysReg PhysReg);
 
     Register traceCopies(Register VirtReg) const;
     Register traceCopyChain(Register Reg) const;
 
     int getStackSpaceFor(Register VirtReg);
     void spill(MachineBasicBlock::iterator Before, Register VirtReg,
-               MCPhysReg AssignedReg, bool Kill);
+               MCPhysReg AssignedReg, bool Kill, bool LiveOut);
     void reload(MachineBasicBlock::iterator Before, Register VirtReg,
                 MCPhysReg PhysReg);
 
     bool mayLiveOut(Register VirtReg);
     bool mayLiveIn(Register VirtReg);
 
     void dumpState() const;
   };
bool RegAllocFast::mayLiveIn(Register VirtReg) {
   }
 
   return false;
 }
 
 /// Insert spill instruction for \p AssignedReg before \p Before. Update
 /// DBG_VALUEs with \p VirtReg operands with the stack slot.
 void RegAllocFast::spill(MachineBasicBlock::iterator Before, Register VirtReg,
-                         MCPhysReg AssignedReg, bool Kill) {
+                         MCPhysReg AssignedReg, bool Kill, bool LiveOut) {
   LLVM_DEBUG(dbgs() << "Spilling " << printReg(VirtReg, TRI)
                     << " in " << printReg(AssignedReg, TRI));
   int FI = getStackSpaceFor(VirtReg);
   LLVM_DEBUG(dbgs() << " to stack slot #" << FI << '\n');
 
   const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg);
   TII->storeRegToStackSlot(*MBB, Before, AssignedReg, Kill, FI, &RC, TRI);
   ++NumStores;
 
+  MachineBasicBlock::iterator FirstTerm = MBB->getFirstTerminator();
+
   // When we spill a virtual register, we will have spill instructions behind
   // every definition of it, meaning we can switch all the DBG_VALUEs over
   // to just reference the stack slot.
   SmallVectorImpl<MachineInstr *> &LRIDbgValues = LiveDbgValueMap[VirtReg];
   for (MachineInstr *DBG : LRIDbgValues) {
     MachineInstr *NewDV = buildDbgValueForSpill(*MBB, Before, *DBG, FI);
     assert(NewDV->getParent() == MBB && "dangling parent pointer");
     (void)NewDV;
     LLVM_DEBUG(dbgs() << "Inserting debug info due to spill:\n" << *NewDV);
+
+    if (LiveOut) {
+      // We need to insert a DBG_VALUE at the end of the block if the spill slot
+      // is live out, but there is another use of the value after the
+      // spill. This will allow LiveDebugValues to see the correct live out
+      // value to propagate to the successors.
+      MachineInstr *ClonedDV = MBB->getParent()->CloneMachineInstr(NewDV);
+      MBB->insert(FirstTerm, ClonedDV);
+      LLVM_DEBUG(dbgs() << "Cloning debug info due to live out spill\n");
+    }
+
     // Rewrite unassigned dbg_values to use the stack slot.
     MachineOperand &MO = DBG->getOperand(0);
     if (MO.isReg() && MO.getReg() == 0)
       updateDbgValueForSpill(*DBG, FI);
   }
   // Now this register is spilled there is should not be any DBG_VALUE
   // pointing to this register because they are all pointing to spilled value
   // now.
void RegAllocFast::defineVirtReg(MachineInstr &MI, unsigned OpNum,
   assert(PhysReg != 0 && "Register not assigned");
   if (LRI->Reloaded || LRI->LiveOut) {
     if (!MI.isImplicitDef()) {
       MachineBasicBlock::iterator SpillBefore =
           std::next((MachineBasicBlock::iterator)MI.getIterator());
       LLVM_DEBUG(dbgs() << "Spill Reason: LO: " << LRI->LiveOut << " RL: "
                         << LRI->Reloaded << '\n');
       bool Kill = LRI->LastUse == nullptr;
-      spill(SpillBefore, VirtReg, PhysReg, Kill);
+      spill(SpillBefore, VirtReg, PhysReg, Kill, LRI->LiveOut);
       LRI->LastUse = nullptr;
     }
     LRI->LiveOut = false;
     LRI->Reloaded = false;
   }
   markRegUsedInInstr(PhysReg);
   setPhysReg(MI, MO, PhysReg);
 }

llvm/test/CodeGen/X86/fast-regalloc-live-out-debug-values.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=x86_64-unknown-linux-gnu -start-before=regallocfast -stop-after=livedebugvalues -verify-machineinstrs -o - %s | FileCheck %s
+# DBG_VALUEs for %0 should be present in the use blocks
+
+--- |
+  define dso_local i32 @foo(i32 %a) #0 !dbg !6 {
+  entry:
+    %a.addr = alloca i32, align 4
+    %saved_stack = alloca i8*, align 8
+    %__vla_expr0 = alloca i64, align 8
+    %i = alloca i32, align 4
+    store i32 %a, i32* %a.addr, align 4
+    call void @llvm.dbg.declare(metadata i32* %a.addr, metadata !11, metadata !DIExpression()), !dbg !12
+    %0 = load i32, i32* %a.addr, align 4, !dbg !13
+    %1 = zext i32 %0 to i64, !dbg !14
+    %2 = call i8* @llvm.stacksave(), !dbg !14
+    store i8* %2, i8** %saved_stack, align 8, !dbg !14
+    %vla = alloca i32, i64 %1, align 16, !dbg !14
+    store i64 %1, i64* %__vla_expr0, align 8, !dbg !14
+    call void @llvm.dbg.declare(metadata i64* %__vla_expr0, metadata !15, metadata !DIExpression()), !dbg !17
+    call void @llvm.dbg.declare(metadata i32* %vla, metadata !18, metadata !DIExpression()), !dbg !22
+    call void @llvm.dbg.declare(metadata i32* %i, metadata !23, metadata !DIExpression()), !dbg !25
+    store i32 0, i32* %i, align 4, !dbg !25
+    br label %for.cond, !dbg !26
+
+  for.cond:                                         ; preds = %for.inc, %entry
+    %3 = load i32, i32* %i, align 4, !dbg !27
+    %4 = load i32, i32* %a.addr, align 4, !dbg !29
+    %cmp = icmp slt i32 %3, %4, !dbg !30
+    br i1 %cmp, label %for.body, label %for.end, !dbg !31
+
+  for.body:                                         ; preds = %for.cond
+    %5 = load i32, i32* %a.addr, align 4, !dbg !32
+    %6 = load i32, i32* %i, align 4, !dbg !33
+    %sub = sub nsw i32 %5, %6, !dbg !34
+    %7 = load i32, i32* %i, align 4, !dbg !35
+    %idxprom = sext i32 %7 to i64, !dbg !36
+    %arrayidx = getelementptr inbounds i32, i32* %vla, i64 %idxprom, !dbg !36
+    store i32 %sub, i32* %arrayidx, align 4, !dbg !37
+    br label %for.inc, !dbg !36
+
+  for.inc:                                          ; preds = %for.body
+    %8 = load i32, i32* %i, align 4, !dbg !38
+    %inc = add nsw i32 %8, 1, !dbg !38
+    store i32 %inc, i32* %i, align 4, !dbg !38
+    br label %for.cond, !dbg !39, !llvm.loop !40
+
+  for.end:                                          ; preds = %for.cond
+    %9 = load i32, i32* %a.addr, align 4, !dbg !42
+    %sub1 = sub nsw i32 %9, 1, !dbg !43
+    %idxprom2 = sext i32 %sub1 to i64, !dbg !44
+    %arrayidx3 = getelementptr inbounds i32, i32* %vla, i64 %idxprom2, !dbg !44
+    %10 = load i32, i32* %arrayidx3, align 4, !dbg !44
+    %11 = load i8*, i8** %saved_stack, align 8, !dbg !45
+    call void @llvm.stackrestore(i8* %11), !dbg !45
+    ret i32 %10, !dbg !45
+  }
+
+  declare void @llvm.dbg.declare(metadata, metadata, metadata) #1
+  declare i8* @llvm.stacksave() #2
+  declare void @llvm.stackrestore(i8*) #2
+
+  attributes #0 = { noinline nounwind optnone uwtable }
+  attributes #1 = { nounwind readnone speculatable willreturn }
+  attributes #2 = { nounwind }
+
+  !llvm.dbg.cu = !{!0}
+  !llvm.module.flags = !{!3, !4, !5}
+
+  !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 12.0.0 ([e-mail]:llvm/llvm-project.git 954995d0a45729c7935b82258c166524ee87ad3f)", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, splitDebugInlining: false, nameTableKind: None)
+  !1 = !DIFile(filename: "/home/matt/src/llvm-project/lldb/test/API/lang/c/vla/main.c", directory: "/home/matt/src/llvm-project/build_debug_lldbg")
+  !2 = !{}
+  !3 = !{i32 7, !"Dwarf Version", i32 4}
+  !4 = !{i32 2, !"Debug Info Version", i32 3}
+  !5 = !{i32 1, !"wchar_size", i32 4}
+  !6 = distinct !DISubprogram(name: "foo", scope: !7, file: !7, line: 3, type: !8, scopeLine: 3, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !2)
+  !7 = !DIFile(filename: "lldb/test/API/lang/c/vla/main.c", directory: "/home/matt/src/llvm-project")
+  !8 = !DISubroutineType(types: !9)
+  !9 = !{!10, !10}
+  !10 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed)
+  !11 = !DILocalVariable(name: "a", arg: 1, scope: !6, file: !7, line: 3, type: !10)
+  !12 = !DILocation(line: 3, column: 13, scope: !6)
+  !13 = !DILocation(line: 4, column: 11, scope: !6)
+  !14 = !DILocation(line: 4, column: 3, scope: !6)
+  !15 = !DILocalVariable(name: "__vla_expr0", scope: !6, type: !16, flags: DIFlagArtificial)
+  !16 = !DIBasicType(name: "long unsigned int", size: 64, encoding: DW_ATE_unsigned)
+  !17 = !DILocation(line: 0, scope: !6)
+  !18 = !DILocalVariable(name: "vla", scope: !6, file: !7, line: 4, type: !19)
+  !19 = !DICompositeType(tag: DW_TAG_array_type, baseType: !10, elements: !20)
+  !20 = !{!21}
+  !21 = !DISubrange(count: !15)
+  !22 = !DILocation(line: 4, column: 7, scope: !6)
+  !23 = !DILocalVariable(name: "i", scope: !24, file: !7, line: 6, type: !10)
+  !24 = distinct !DILexicalBlock(scope: !6, file: !7, line: 6, column: 3)
+  !25 = !DILocation(line: 6, column: 12, scope: !24)
+  !26 = !DILocation(line: 6, column: 8, scope: !24)
+  !27 = !DILocation(line: 6, column: 19, scope: !28)
+  !28 = distinct !DILexicalBlock(scope: !24, file: !7, line: 6, column: 3)
+  !29 = !DILocation(line: 6, column: 23, scope: !28)
+  !30 = !DILocation(line: 6, column: 21, scope: !28)
+  !31 = !DILocation(line: 6, column: 3, scope: !24)
+  !32 = !DILocation(line: 7, column: 14, scope: !28)
+  !33 = !DILocation(line: 7, column: 16, scope: !28)
+  !34 = !DILocation(line: 7, column: 15, scope: !28)
+  !35 = !DILocation(line: 7, column: 9, scope: !28)
+  !36 = !DILocation(line: 7, column: 5, scope: !28)
+  !37 = !DILocation(line: 7, column: 12, scope: !28)
+  !38 = !DILocation(line: 6, column: 26, scope: !28)
+  !39 = !DILocation(line: 6, column: 3, scope: !28)
+  !40 = distinct !{!40, !31, !41}
+  !41 = !DILocation(line: 7, column: 16, scope: !24)
+  !42 = !DILocation(line: 10, column: 14, scope: !6)
+  !43 = !DILocation(line: 10, column: 15, scope: !6)
+  !44 = !DILocation(line: 10, column: 10, scope: !6)
+  !45 = !DILocation(line: 11, column: 1, scope: !6)
+
+...
+---
+name:            foo
+tracksRegLiveness: true
+frameInfo:
+  hasCalls:        true
+stack:
+  - { id: 0, name: a.addr, size: 4, alignment: 4, debug-info-variable: '!11',
+      debug-info-expression: '!DIExpression()', debug-info-location: '!12' }
+  - { id: 1, name: __vla_expr0, size: 8, alignment: 8, debug-info-variable: '!15',
+      debug-info-expression: '!DIExpression()', debug-info-location: '!17' }
+  - { id: 2, name: i, size: 4, alignment: 4, debug-info-variable: '!23',
+      debug-info-expression: '!DIExpression()', debug-info-location: '!25' }
+  - { id: 3, name: vla, type: variable-sized, alignment: 1 }
+body:             |
+  ; CHECK-LABEL: name: foo
+  ; CHECK: bb.0.entry:
+  ; CHECK:   successors: %bb.1(0x80000000)
+  ; CHECK:   liveins: $edi, $rbx
+  ; CHECK:   frame-setup PUSH64r killed $rbp, implicit-def $rsp, implicit $rsp
+  ; CHECK:   CFI_INSTRUCTION def_cfa_offset 16
+  ; CHECK:   CFI_INSTRUCTION offset $rbp, -16
+  ; CHECK:   $rbp = frame-setup MOV64rr $rsp
+  ; CHECK:   CFI_INSTRUCTION def_cfa_register $rbp
+  ; CHECK:   frame-setup PUSH64r killed $rbx, implicit-def $rsp, implicit $rsp, debug-location !13
+  ; CHECK:   $rsp = frame-setup SUB64ri8 $rsp, 40, implicit-def dead $eflags
+  ; CHECK:   CFI_INSTRUCTION offset $rbx, -24
+  ; CHECK:   renamable $eax = MOV32rm $rbp, 1, $noreg, -12, $noreg, debug-location !13 :: (dereferenceable load 4 from %ir.a.addr)
+  ; CHECK:   renamable $rax = KILL killed renamable $eax, debug-location !13
+  ; CHECK:   $rcx = MOV64rr $rsp, debug-location !14
+  ; CHECK:   MOV64mr $rbp, 1, $noreg, -40, $noreg, $rcx :: (store 8 into %stack.4)
+  ; CHECK:   DBG_VALUE $rbp, 0, !18, !DIExpression(DW_OP_constu, 40, DW_OP_minus, DW_OP_deref), debug-location !22
+  ; CHECK:   $rsp = MOV64rr $rcx, debug-location !14
+  ; CHECK:   MOV64mr $rbp, 1, $noreg, -24, $noreg, killed renamable $rax, debug-location !14 :: (store 8 into %ir.__vla_expr0)
+  ; CHECK:   DBG_VALUE renamable $rcx, 0, !18, !DIExpression(), debug-location !22
+  ; CHECK:   MOV32mi $rbp, 1, $noreg, -28, $noreg, 0, debug-location !25 :: (store 4 into %ir.i)
+  ; CHECK:   DBG_VALUE $rbp, 0, !18, !DIExpression(DW_OP_constu, 40, DW_OP_minus, DW_OP_deref), debug-location !22
+  ; CHECK: bb.1.for.cond:
+  ; CHECK:   successors: %bb.4(0x40000000), %bb.2(0x40000000)
+  ; CHECK:   DBG_VALUE $rbp, 0, !18, !DIExpression(DW_OP_constu, 40, DW_OP_minus, DW_OP_deref), debug-location !22
+  ; CHECK:   renamable $eax = MOV32rm $rbp, 1, $noreg, -28, $noreg, debug-location !27 :: (load 4 from %ir.i)
+  ; CHECK:   CMP32rm killed renamable $eax, $rbp, 1, $noreg, -12, $noreg, implicit-def $eflags, debug-location !30 :: (load 4 from %ir.a.addr)
+  ; CHECK:   JCC_1 %bb.4, 13, implicit killed $eflags, debug-location !31
+  ; CHECK: bb.2.for.body:
+  ; CHECK:   successors: %bb.3(0x80000000)
+  ; CHECK:   DBG_VALUE $rbp, 0, !18, !DIExpression(DW_OP_constu, 40, DW_OP_minus, DW_OP_deref), debug-location !22
+  ; CHECK:   $rax = MOV64rm $rbp, 1, $noreg, -40, $noreg :: (load 8 from %stack.4)
+  ; CHECK:   renamable $edx = MOV32rm $rbp, 1, $noreg, -12, $noreg, debug-location !32 :: (load 4 from %ir.a.addr)
+  ; CHECK:   renamable $rcx = MOVSX64rm32 $rbp, 1, $noreg, -28, $noreg, debug-location !36 :: (load 4 from %ir.i)
+  ; CHECK:   MOV32mr renamable $rax, 4, killed renamable $rcx, 0, $noreg, killed renamable $edx, debug-location !37 :: (store 4 into %ir.arrayidx)
+  ; CHECK: bb.3.for.inc:
+  ; CHECK:   successors: %bb.1(0x80000000)
+  ; CHECK:   DBG_VALUE $rbp, 0, !18, !DIExpression(DW_OP_constu, 40, DW_OP_minus, DW_OP_deref), debug-location !22
+  ; CHECK:   JMP_1 %bb.1, debug-location !39
+  ; CHECK: bb.4.for.end:
+  ; CHECK:   DBG_VALUE $rbp, 0, !18, !DIExpression(DW_OP_constu, 40, DW_OP_minus, DW_OP_deref), debug-location !22
+  ; CHECK:   $rax = IMPLICIT_DEF
+  ; CHECK:   $rax = MOV64rm $rbp, 1, $noreg, -40, $noreg :: (load 8 from %stack.4)
+  ; CHECK:   dead $rbx = IMPLICIT_DEF
+  ; CHECK:   dead $rcx = IMPLICIT_DEF
+  ; CHECK:   dead $rdx = IMPLICIT_DEF
+  ; CHECK:   renamable $rcx = IMPLICIT_DEF
+  ; CHECK:   renamable $eax = MOV32rm killed renamable $rax, 4, killed renamable $rcx, 0, $noreg, debug-location !44 :: (load 4 from %ir.arrayidx3)
+  ; CHECK:   $rsp = LEA64r $rbp, 1, $noreg, -8, $noreg, debug-location !45
+  ; CHECK:   $rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !45
+  ; CHECK:   $rbp = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !45
+  ; CHECK:   CFI_INSTRUCTION def_cfa $rsp, 8, debug-location !45
+  ; CHECK:   RETQ implicit killed $eax, debug-location !45
+  bb.0.entry:
+    liveins: $edi
+
+    %0:gr32 = COPY $edi
+    %1:gr32 = MOV32rm %stack.0.a.addr, 1, $noreg, 0, $noreg, debug-location !13 :: (dereferenceable load 4 from %ir.a.addr)
+    %2:gr64_nosp = SUBREG_TO_REG 0, killed %1, %subreg.sub_32bit, debug-location !13
+    ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp, debug-location !14
+    %3:gr64 = COPY $rsp, debug-location !14
+    $rsp = COPY %3, debug-location !14
+    ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp, debug-location !14
+    MOV64mr %stack.1.__vla_expr0, 1, $noreg, 0, $noreg, %2, debug-location !14 :: (store 8 into %ir.__vla_expr0)
+    DBG_VALUE %3, 0, !18, !DIExpression(), debug-location !22
+    MOV32mi %stack.2.i, 1, $noreg, 0, $noreg, 0, debug-location !25 :: (store 4 into %ir.i)
+
+  bb.1.for.cond:
+    %4:gr32 = MOV32rm %stack.2.i, 1, $noreg, 0, $noreg, debug-location !27 :: (load 4 from %ir.i)
+    CMP32rm %4, %stack.0.a.addr, 1, $noreg, 0, $noreg, implicit-def $eflags, debug-location !30 :: (load 4 from %ir.a.addr)
+    JCC_1 %bb.4, 13, implicit $eflags, debug-location !31
+
+  bb.2.for.body:
+    %5:gr32 = MOV32rm %stack.0.a.addr, 1, $noreg, 0, $noreg, debug-location !32 :: (load 4 from %ir.a.addr)
+    %6:gr64_nosp = MOVSX64rm32 %stack.2.i, 1, $noreg, 0, $noreg, debug-location !36 :: (load 4 from %ir.i)
+    MOV32mr %3, 4, %6, 0, $noreg, killed %5, debug-location !37 :: (store 4 into %ir.arrayidx)
+
+  bb.3.for.inc:
+    JMP_1 %bb.1, debug-location !39
+
+  bb.4.for.end:
+    $rax = IMPLICIT_DEF
+    $rbx = IMPLICIT_DEF
+    $rcx = IMPLICIT_DEF
+    $rdx = IMPLICIT_DEF
+    %7:gr64_nosp = IMPLICIT_DEF
+    %8:gr32 = MOV32rm %3, 4, %7, 0, $noreg, debug-location !44 :: (load 4 from %ir.arrayidx3)
+    $eax = COPY %8, debug-location !45
+    RETQ implicit $eax, debug-location !45
+
+...

llvm/test/DebugInfo/X86/fission-ranges.ll

 
 ; CHECK:      [[A]]:
 ; CHECK-NEXT:   DW_LLE_startx_length (0x00000002, 0x0000000f): DW_OP_consts +0, DW_OP_stack_value
 ; CHECK-NEXT:   DW_LLE_startx_length (0x00000003, 0x0000000b): DW_OP_reg0 RAX
 ; CHECK-NEXT:   DW_LLE_startx_length (0x00000004, 0x00000012): DW_OP_breg7 RSP-4
 ; CHECK-NEXT:   DW_LLE_end_of_list   ()
 ; CHECK:      [[E]]:
 ; CHECK-NEXT:   DW_LLE_startx_length (0x00000005, 0x0000000b): DW_OP_reg0 RAX
-; CHECK-NEXT:   DW_LLE_startx_length (0x00000006, 0x0000005a): DW_OP_breg7 RSP-36
+; CHECK-NEXT:   DW_LLE_startx_length (0x00000006, 0x0000005a): DW_OP_breg7 RSP-48
 ; CHECK-NEXT:   DW_LLE_end_of_list   ()
 ; CHECK:      [[B]]:
 ; CHECK-NEXT:   DW_LLE_startx_length (0x00000007, 0x0000000b): DW_OP_reg0 RAX
 ; CHECK-NEXT:   DW_LLE_startx_length (0x00000008, 0x00000042): DW_OP_breg7 RSP-24
 ; CHECK-NEXT:   DW_LLE_end_of_list   ()
 ; CHECK:      [[D]]:
 ; CHECK-NEXT:   DW_LLE_startx_length (0x00000009, 0x0000000b): DW_OP_reg0 RAX
 ; CHECK-NEXT:   DW_LLE_startx_length (0x0000000a, 0x0000002a): DW_OP_breg7 RSP-12

llvm/test/DebugInfo/X86/op_deref.ll

 ; RUN: llc -O0 -mtriple=x86_64-apple-darwin < %s -filetype=obj \
 ; RUN:     | llvm-dwarfdump -v -debug-info - \
 ; RUN:     | FileCheck %s -check-prefix=CHECK -check-prefix=DWARF4
 ; RUN: llc -O0 -mtriple=x86_64-apple-darwin < %s -filetype=obj -dwarf-version=3 \
 ; RUN:     | llvm-dwarfdump -v -debug-info - \
 ; RUN:     | FileCheck %s -check-prefix=CHECK -check-prefix=DWARF3
 
 ; DWARF4: DW_AT_location [DW_FORM_sec_offset]                      (0x00000000
 ; DWARF4-NEXT:  {{.*}}: DW_OP_breg6 RBP-40, DW_OP_deref, DW_OP_deref
-; DWARF4-NEXT:  {{.*}}: DW_OP_breg0 RAX+0, DW_OP_deref)
+; DWARF4-NEXT:  {{.*}}: DW_OP_breg0 RAX+0, DW_OP_deref
+; DWARF4-NEXT:  {{.*}}: DW_OP_breg6 RBP-40, DW_OP_deref, DW_OP_deref)
 
 ; DWARF3: DW_AT_location [DW_FORM_data4]                      (0x00000000
 ; DWARF3-NEXT:  {{.*}}: DW_OP_breg6 RBP-40, DW_OP_deref, DW_OP_deref
 ; DWARF3-NEXT:  {{.*}}: DW_OP_breg0 RAX+0, DW_OP_deref
 
 ; CHECK-NOT: DW_TAG
 ; CHECK: DW_AT_name [DW_FORM_strp]  ( .debug_str[0x00000067] = "vla")
 

llvm/test/DebugInfo/X86/parameters.ll

 
 ; CHECK: DW_TAG_subprogram
 ; CHECK: DW_AT_name{{.*}} = "func2"
 ; CHECK: DW_TAG_formal_parameter
 ; CHECK: DW_AT_location{{.*}}(DW_OP_fbreg +23)
 ; CHECK: DW_TAG_formal_parameter
 ; CHECK: DW_AT_location{{.*}}(
 ; CHECK-NEXT: {{.*}}: DW_OP_breg7 RSP+8, DW_OP_deref, DW_OP_deref
-; CHECK-NEXT: {{.*}}: DW_OP_breg4 RSI+0, DW_OP_deref)
+; CHECK-NEXT: {{.*}}: DW_OP_breg4 RSI+0, DW_OP_deref
+; CHECK-NEXT: {{.*}}: DW_OP_breg7 RSP+8, DW_OP_deref, DW_OP_deref)
 ; CHECK-NOT: DW_TAG
 ; CHECK: DW_AT_name{{.*}} = "g"
 
 %"struct.pr14763::foo" = type { i8 }
 
 ; Function Attrs: uwtable
 define void @_ZN7pr147634funcENS_3fooE(%"struct.pr14763::foo"* noalias sret %agg.result, %"struct.pr14763::foo"* %f) #0 !dbg !4 {
 entry:

llvm/test/DebugInfo/X86/sret.ll

 ; RUN: llc -split-dwarf-file=foo.dwo -O0 %s -mtriple=x86_64-unknown-linux-gnu -filetype=obj -o %t
 ; RUN: llvm-dwarfdump -debug-info %t | FileCheck %s --check-prefix=CHECK-DWO
 
 ; Based on the debuginfo-tests/sret.cpp code.
 
-; CHECK-DWO: DW_AT_GNU_dwo_id (0x409e35dbb641730e)
-; CHECK-DWO: DW_AT_GNU_dwo_id (0x409e35dbb641730e)
+; CHECK-DWO: DW_AT_GNU_dwo_id (0xa58a336e896549f1)
+; CHECK-DWO: DW_AT_GNU_dwo_id (0xa58a336e896549f1)
 
 ; RUN: llc -O0 -fast-isel=true -mtriple=x86_64-apple-darwin -filetype=obj -o - %s | llvm-dwarfdump -debug-info - | FileCheck -check-prefixes=CHECK,FASTISEL %s
 ; RUN: llc -O0 -fast-isel=false -mtriple=x86_64-apple-darwin -filetype=obj -o - %s | llvm-dwarfdump -debug-info - | FileCheck -check-prefixes=CHECK,SDAG %s
 ; CHECK: _ZN1B9AInstanceEv
 ; CHECK: DW_TAG_variable
 ; CHECK-NEXT:   DW_AT_location (0x00000000
 ; FASTISEL-NEXT:     [{{.*}}, {{.*}}): DW_OP_breg6 RBP-32, DW_OP_deref
-; FASTISEL-NEXT:     [{{.*}}, {{.*}}): DW_OP_breg5 RDI+0)
-; SDAG-NEXT:     [{{.*}}, {{.*}}): DW_OP_breg5 RDI+0)
+; FASTISEL-NEXT:     [{{.*}}, {{.*}}): DW_OP_breg5 RDI+0
+; FASTISEL-NEXT:     [{{.*}}, {{.*}}): DW_OP_breg6 RBP-32, DW_OP_deref)
+; SDAG-NEXT:     [{{.*}}, {{.*}}): DW_OP_breg5 RDI+0
+; SDAG-NEXT:     [{{.*}}, {{.*}}): DW_OP_breg6 RBP-32, DW_OP_deref)
 ; CHECK-NEXT:   DW_AT_name {{.*}}"a"
 
 %class.A = type { i32 (...)**, i32 }
 %class.B = type { i8 }
 
 @_ZTV1A = linkonce_odr unnamed_addr constant [4 x i8*] [i8* null, i8* bitcast ({ i8*, i8* }* @_ZTI1A to i8*), i8* bitcast (void (%class.A*)* @_ZN1AD2Ev to i8*), i8* bitcast (void (%class.A*)* @_ZN1AD0Ev to i8*)]
 @_ZTVN10__cxxabiv117__class_type_infoE = external global i8*
 @_ZTS1A = linkonce_odr constant [3 x i8] c"1A\00"

llvm/test/DebugInfo/X86/subreg.ll

 ; RUN: llc %s -mtriple=x86_64-pc-linux-gnu -O0 -o - | FileCheck %s
 
 ; We are testing that a value in a 16 bit register gets reported as
 ; being in its superregister.
 
 ; CHECK: .byte   80                      # super-register DW_OP_reg0
 ; No need to a piece at offset 0.
 ; CHECK-NOT: DW_OP_piece
 ; CHECK-NOT: DW_OP_bit_piece
 
 define i16 @f(i16 signext %zzz) nounwind !dbg !1 {
 entry:
   call void @llvm.dbg.value(metadata i16 %zzz, metadata !0, metadata !DIExpression()), !dbg !DILocation(scope: !1)
-  br label %exit
-
-exit:
   %conv = sext i16 %zzz to i32, !dbg !7
   %conv1 = trunc i32 %conv to i16
   ret i16 %conv1
 }
 
 declare void @llvm.dbg.value(metadata, metadata, metadata) nounwind readnone
 
 !llvm.dbg.cu = !{!3}