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AMDGPU: Don't sometimes allow instructions before lowered si_end_cf
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Authored by arsenm on Fri, Sep 11, 12:33 PM.

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Summary

Since 6524a7a2b9ca072bd7f7b4355d1230e70c679d2f, this would sometimes
not emit the or to exec at the beginning of the block, where it really
has to be. If there is an instruction that defines one of the source
operands, split the block and turn the si_end_cf into a terminator.

This avoids regressions when regalloc fast is switched to inserting
reloads at the beginning of the block, instead of spills at the end of
the block.

In a future change, this should always split the block.

Diff Detail

Event Timeline

arsenm created this revision.Fri, Sep 11, 12:33 PM
Herald added a project: Restricted Project. · View Herald TranscriptFri, Sep 11, 12:33 PM
arsenm requested review of this revision.Fri, Sep 11, 12:33 PM
critson added inline comments.Sun, Sep 13, 12:36 AM
llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
496

I wonder if we can place splitBlock somewhere that the code can be shared between multiple passes? Feels like we end up needing to do this in a few places.

arsenm added inline comments.
llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
496

Moved this in D87760

rampitec accepted this revision.Fri, Sep 18, 10:30 AM
This revision is now accepted and ready to land.Fri, Sep 18, 10:30 AM