[ARM] Mark VMINNMA/VMAXNMA as commutative

[dmgreen]

Summary

These operations take Qda and Rn register operands, which are commutative so long as the instruction is not predicated.

[SjoerdMeijer]

LGTM

llvm/lib/Target/ARM/ARMInstrMVE.td

class MVE_VMAXMINNMA<string iname, string suffix, bit size, bit bit_12,
   let Inst{21-16} = 0b111111;
   let Inst{15-13} = Qd{2-0};
   let Inst{12} = bit_12;
   let Inst{11-6} = 0b111010;
   let Inst{5} = Qm{3};
   let Inst{4} = 0b0;
   let Inst{3-1} = Qm{2-0};
   let Inst{0} = 0b1;
+
+  let isCommutable = 1;
 }
 
 multiclass MVE_VMAXMINNMA_m<string iname, MVEVectorVTInfo VTI,
                       SDNode unpred_op, Intrinsic pred_int,
                       bit bit_12> {
   def "" : MVE_VMAXMINNMA<iname, VTI.Suffix, VTI.Size{0}, bit_12>;
   defvar Inst = !cast<Instruction>(NAME);
 

llvm/lib/Target/ARM/Thumb2InstrInfo.h

public:
   /// always be able to get register info as well (through this method).
   ///
   const ThumbRegisterInfo &getRegisterInfo() const override { return RI; }
 
   MachineInstr *optimizeSelect(MachineInstr &MI,
                                SmallPtrSetImpl<MachineInstr *> &SeenMIs,
                                bool) const override;
 
+  MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
+                                       unsigned OpIdx1,
+                                       unsigned OpIdx2) const override;
+
 private:
   void expandLoadStackGuard(MachineBasicBlock::iterator MI) const override;
 };
 
 /// getITInstrPredicate - Valid only in Thumb2 mode. This function is identical
 /// to llvm::getInstrPredicate except it returns AL for conditional branch
 /// instructions which are "predicated", but are not in IT blocks.
 ARMCC::CondCodes getITInstrPredicate(const MachineInstr &MI, Register &PredReg);

llvm/lib/Target/ARM/Thumb2InstrInfo.cpp

void Thumb2InstrInfo::expandLoadStackGuard(
     MachineBasicBlock::iterator MI) const {
   MachineFunction &MF = *MI->getParent()->getParent();
   if (MF.getTarget().isPositionIndependent())
     expandLoadStackGuardBase(MI, ARM::t2MOV_ga_pcrel, ARM::t2LDRi12);
   else
     expandLoadStackGuardBase(MI, ARM::t2MOVi32imm, ARM::t2LDRi12);
 }
 
+MachineInstr *Thumb2InstrInfo::commuteInstructionImpl(MachineInstr &MI,
+                                                      bool NewMI,
+                                                      unsigned OpIdx1,
+                                                      unsigned OpIdx2) const {
+  switch (MI.getOpcode()) {
+  case ARM::MVE_VMAXNMAf16:
+  case ARM::MVE_VMAXNMAf32:
+  case ARM::MVE_VMINNMAf16:
+  case ARM::MVE_VMINNMAf32:
+    // Don't allow predicated instructions to be commuted.
+    if (getVPTInstrPredicate(MI) != ARMVCC::None)
+      return nullptr;
+  }
+  return ARMBaseInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
+}
+
 void llvm::emitT2RegPlusImmediate(MachineBasicBlock &MBB,
                                   MachineBasicBlock::iterator &MBBI,
                                   const DebugLoc &dl, Register DestReg,
                                   Register BaseReg, int NumBytes,
                                   ARMCC::CondCodes Pred, Register PredReg,
                                   const ARMBaseInstrInfo &TII,
                                   unsigned MIFlags) {
   if (NumBytes == 0 && DestReg != BaseReg) {

llvm/test/CodeGen/Thumb2/mve-vmaxnma-commute.ll

; CHECK-NEXT:    bx lr
   %bb = tail call fast <4 x float> @llvm.fabs.v4f32(<4 x float> %b)
   %c = tail call fast <4 x float> @llvm.maxnum.v4f32(<4 x float> %aa, <4 x float> %bb)
   ret <4 x float> %c
 }
 
 define arm_aapcs_vfpcc <4 x float> @maxf32_c(<4 x float> %a, <4 x float> %b) {
 ; CHECK-LABEL: maxf32_c:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    vmaxnma.f32 q1, q0
-; CHECK-NEXT:    vmov q0, q1
+; CHECK-NEXT:    vmaxnma.f32 q0, q1
 ; CHECK-NEXT:    bx lr
   %aa = tail call fast <4 x float> @llvm.fabs.v4f32(<4 x float> %a)
   %bb = tail call fast <4 x float> @llvm.fabs.v4f32(<4 x float> %b)
   %c = tail call fast <4 x float> @llvm.maxnum.v4f32(<4 x float> %bb, <4 x float> %aa)
   ret <4 x float> %c
 }
 
 define arm_aapcs_vfpcc <4 x float> @minf32(<4 x float> %a, <4 x float> %b) {
 ; CHECK-LABEL: minf32:
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    vminnma.f32 q0, q1
 ; CHECK-NEXT:    bx lr
   %aa = tail call fast <4 x float> @llvm.fabs.v4f32(<4 x float> %a)
   %bb = tail call fast <4 x float> @llvm.fabs.v4f32(<4 x float> %b)
   %c = tail call fast <4 x float> @llvm.minnum.v4f32(<4 x float> %aa, <4 x float> %bb)
   ret <4 x float> %c
 }
 
 define arm_aapcs_vfpcc <4 x float> @minf32_c(<4 x float> %a, <4 x float> %b) {
 ; CHECK-LABEL: minf32_c:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    vminnma.f32 q1, q0
-; CHECK-NEXT:    vmov q0, q1
+; CHECK-NEXT:    vminnma.f32 q0, q1
 ; CHECK-NEXT:    bx lr
   %aa = tail call fast <4 x float> @llvm.fabs.v4f32(<4 x float> %a)
   %bb = tail call fast <4 x float> @llvm.fabs.v4f32(<4 x float> %b)
   %c = tail call fast <4 x float> @llvm.minnum.v4f32(<4 x float> %bb, <4 x float> %aa)
   ret <4 x float> %c
 }
 
 
; CHECK-NEXT:    bx lr
   %bb = tail call fast <8 x half> @llvm.fabs.v8f16(<8 x half> %b)
   %c = tail call fast <8 x half> @llvm.maxnum.v8f16(<8 x half> %aa, <8 x half> %bb)
   ret <8 x half> %c
 }
 
 define arm_aapcs_vfpcc <8 x half> @maxf16_c(<8 x half> %a, <8 x half> %b) {
 ; CHECK-LABEL: maxf16_c:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    vmaxnma.f16 q1, q0
-; CHECK-NEXT:    vmov q0, q1
+; CHECK-NEXT:    vmaxnma.f16 q0, q1
 ; CHECK-NEXT:    bx lr
   %aa = tail call fast <8 x half> @llvm.fabs.v8f16(<8 x half> %a)
   %bb = tail call fast <8 x half> @llvm.fabs.v8f16(<8 x half> %b)
   %c = tail call fast <8 x half> @llvm.maxnum.v8f16(<8 x half> %bb, <8 x half> %aa)
   ret <8 x half> %c
 }
 
 define arm_aapcs_vfpcc <8 x half> @minf16(<8 x half> %a, <8 x half> %b) {
 ; CHECK-LABEL: minf16:
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    vminnma.f16 q0, q1
 ; CHECK-NEXT:    bx lr
   %aa = tail call fast <8 x half> @llvm.fabs.v8f16(<8 x half> %a)
   %bb = tail call fast <8 x half> @llvm.fabs.v8f16(<8 x half> %b)
   %c = tail call fast <8 x half> @llvm.minnum.v8f16(<8 x half> %aa, <8 x half> %bb)
   ret <8 x half> %c
 }
 
 define arm_aapcs_vfpcc <8 x half> @minf16_c(<8 x half> %a, <8 x half> %b) {
 ; CHECK-LABEL: minf16_c:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    vminnma.f16 q1, q0
-; CHECK-NEXT:    vmov q0, q1
+; CHECK-NEXT:    vminnma.f16 q0, q1
 ; CHECK-NEXT:    bx lr
   %aa = tail call fast <8 x half> @llvm.fabs.v8f16(<8 x half> %a)
   %bb = tail call fast <8 x half> @llvm.fabs.v8f16(<8 x half> %b)
   %c = tail call fast <8 x half> @llvm.minnum.v8f16(<8 x half> %bb, <8 x half> %aa)
   ret <8 x half> %c
 }
 
 define arm_aapcs_vfpcc <8 x half> @maxpredf16(<8 x half> %a, <8 x half> %b) {

 ; CHECK-LABEL: loop_absmax32_c:
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    .save {r7, lr}
 ; CHECK-NEXT:    push {r7, lr}
 ; CHECK-NEXT:    vmov.i32 q0, #0x0
 ; CHECK-NEXT:    lsr.w lr, r1, #3
 ; CHECK-NEXT:    wls lr, lr, .LBB17_3
 ; CHECK-NEXT:  @ %bb.1: @ %.preheader
-; CHECK-NEXT:    vmov.i32 q1, #0x0
+; CHECK-NEXT:    vmov.i32 q0, #0x0
 ; CHECK-NEXT:  .LBB17_2: @ =>This Inner Loop Header: Depth=1
-; CHECK-NEXT:    vldrw.u32 q0, [r0], #16
+; CHECK-NEXT:    vldrw.u32 q1, [r0], #16
 ; CHECK-NEXT:    vmaxnma.f32 q0, q1
-; CHECK-NEXT:    vmov q1, q0
 ; CHECK-NEXT:    le lr, .LBB17_2
 ; CHECK-NEXT:  .LBB17_3:
 ; CHECK-NEXT:    vldr s4, .LCPI17_0
 ; CHECK-NEXT:    vmov r0, s4
 ; CHECK-NEXT:    vmaxnmav.f32 r0, q0
 ; CHECK-NEXT:    vmov s0, r0
 ; CHECK-NEXT:    vstr s0, [r2]
 ; CHECK-NEXT:    pop {r7, pc}

 ; CHECK-LABEL: loop_absmax16_c:
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    .save {r7, lr}
 ; CHECK-NEXT:    push {r7, lr}
 ; CHECK-NEXT:    vmov.i32 q0, #0x0
 ; CHECK-NEXT:    lsr.w lr, r1, #3
 ; CHECK-NEXT:    wls lr, lr, .LBB21_3
 ; CHECK-NEXT:  @ %bb.1: @ %.preheader
-; CHECK-NEXT:    vmov.i32 q1, #0x0
+; CHECK-NEXT:    vmov.i32 q0, #0x0
 ; CHECK-NEXT:  .LBB21_2: @ =>This Inner Loop Header: Depth=1
-; CHECK-NEXT:    vldrw.u32 q0, [r0], #8
+; CHECK-NEXT:    vldrw.u32 q1, [r0], #8
 ; CHECK-NEXT:    vmaxnma.f16 q0, q1
-; CHECK-NEXT:    vmov q1, q0
 ; CHECK-NEXT:    le lr, .LBB21_2
 ; CHECK-NEXT:  .LBB21_3:
 ; CHECK-NEXT:    vldr.16 s4, .LCPI21_0
 ; CHECK-NEXT:    vmov r0, s4
 ; CHECK-NEXT:    vmaxnmav.f16 r0, q0
 ; CHECK-NEXT:    vmov s0, r0
 ; CHECK-NEXT:    vstr.16 s0, [r2]
 ; CHECK-NEXT:    pop {r7, pc}