[AArch64][GlobalISel] Handle rtcGPR64RegClassID in AArch64RegisterBankInfo::getRegBankFromRegClass()

[tambre]

Summary

TargetRegisterInfo::getMinimalPhysRegClass() returns rtcGPR64RegClassID for X16 and X17, as it's the last matching class.
This in turn gets passed to AArch64RegisterBankInfo::getRegBankFromRegClass(), which hits an unreachable.

It seems sensible to handle this case, so copies from X16 and X17 work.
Copying from X17 is used in inline assembly in libunwind for pointer authentication.

[tambre]

Per usual, if it looks good please land this for me.

[tambre]

Re-generate test checks

[tambre]

paquette: ping

[paquette]

LGTM

[tambre]

Please land this for me (as "Raul Tambre <[e-mail]>"). I lack commit privileges. :)

[tambre]

paquette: ping for landing

[paquette]

Oh whoops, sorry! Landing now.

Also, if you need commit access, you can e-mail Chris Lattner. He usually responds pretty quickly. :)

[kemurphy]

Will this go to the 11.x release branch? We hit the crash that this fixes on 11.0.0.

[tambre]

In D85720#2398588, @kemurphy wrote:

Will this go to the 11.x release branch? We hit the crash that this fixes on 11.0.0.

I've requested for this fix to be merged into 11.0.1:
https://bugs.llvm.org/show_bug.cgi?id=48198

llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp

AArch64RegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC,
   case AArch64::GPR64spRegClassID:
   case AArch64::GPR64sponlyRegClassID:
   case AArch64::GPR64argRegClassID:
   case AArch64::GPR64allRegClassID:
   case AArch64::GPR64noipRegClassID:
   case AArch64::GPR64common_and_GPR64noipRegClassID:
   case AArch64::GPR64noip_and_tcGPR64RegClassID:
   case AArch64::tcGPR64RegClassID:
+  case AArch64::rtcGPR64RegClassID:
   case AArch64::WSeqPairsClassRegClassID:
   case AArch64::XSeqPairsClassRegClassID:
     return getRegBank(AArch64::GPRRegBankID);
   case AArch64::CCRRegClassID:
     return getRegBank(AArch64::CCRegBankID);
   default:
     llvm_unreachable("Register class not supported");
   }

llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir

--- |
 
   define void @test_fptosi_s64_s32() { ret void }
   define void @test_fptosi_v4s32() { ret void }
   define void @test_fptoui_s32_s64() { ret void }
   define void @test_fptoui_v4s32() { ret void }
 
   define void @test_gphi_ptr() { ret void }
 
+  define void @test_restricted_tail_call() { ret void }
+
 ...
 
 ---
 name:            test_add_s32
 legalized:       true
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
body:             |
 
 
   bb.2:
     %3(p0) = G_PHI %0(p0), %bb.0, %1(p0), %bb.1
     $x0 = COPY %3(p0)
     RET_ReallyLR implicit $x0
 
 ...
+
+---
+name:            test_restricted_tail_call
+legalized:       true
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $x16, $x17
+    ; CHECK-LABEL: name: test_restricted_tail_call
+    ; CHECK: liveins: $x16, $x17
+    ; CHECK: [[COPY:%[0-9]+]]:gpr(s64) = COPY $x16
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr(s64) = COPY $x17
+    ; CHECK: RET_ReallyLR
+    %0:_(s64) = COPY $x16
+    %1:_(s64) = COPY $x17
+    RET_ReallyLR
+...