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GlobalISel: Augment addsat/subsat lowering with an optional type
Needs ReviewPublic

Authored by arsenm on Jul 16 2020, 9:58 AM.

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Details

Reviewers

foad
dsanders
paquette
aemerson
aditya_nandakumar

Summary

Extend and perform the lowering in the wider type if provided. This
provides a sort of lower with combined widen scalar action.
widenScalar will always widen and produce the original opcode in a
wider type, whereas this will use different opcodes.

This ends up saving an instruction in the uaddsat case. If you know
you are widening, the add in the wider result can't overflow so only
the clamp of the maximum value is needed. In other cases, it can avoid
introducing more instructions that need further widening, saving
avoiding intermediate legalization artifacts.

Use this to handle the sub-32 bit cases for AMDGPU when the clamp
modifier isn't available. This brings the results closer to
SelectionDAG, which duplicates nearly identical expansions of these in
both LegalizeIntegerTypes and LegalizeDAG.

Diff Detail

Event Timeline

arsenm created this revision.Jul 16 2020, 9:58 AM

Herald added a project: Restricted Project. · View Herald TranscriptJul 16 2020, 9:58 AM

Herald added subscribers: kerbowa, hiraditya, tpr and 4 others. · View Herald Transcript

arsenm added parent revisions: D83715: AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat, D83884: GlobalISel: Make type for lower action more consistently optional, D73051: [GlobalISel][AMDGPU] Legalize saturating add/subtract.Jul 16 2020, 9:59 AM

Looks OK technically. As an alternative, would it be possible to widen, and then have the lowering spot that the operands are both extended from a smaller type, so they're known to have a small range, so we can use the more efficient lowering? That would avoid the need for this new "optional type" concept.

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
5883–5884	Could use getLowBitsSet and getOneBitSet, but I suppose it would be annoyingly asymmetrical.
5883–5884	Surely we should take advantage of DoPromote to simplify this? You can do a normal add/sub and then clamp the result to MinVal and MaxVal.
5899–5900	Use APInt::getLowBitsSet?

In D83964#2199356, @foad wrote:

Looks OK technically. As an alternative, would it be possible to widen, and then have the lowering spot that the operands are both extended from a smaller type, so they're known to have a small range, so we can use the more efficient lowering? That would avoid the need for this new "optional type" concept.

I tried this, but it complicates the heuristic for which lowering strategy to use. If we need to promote, the isLegalOrCustom check for min/max won't work for the narrower type

Handle promotion signed case. Avoiding the explicit hint is trickier

Revision Contents

Path

Size

llvm/

include/

llvm/

CodeGen/

GlobalISel/

LegalizerHelper.h

2 lines

LegalizerInfo.h

11 lines

lib/

CodeGen/

GlobalISel/

LegalizerHelper.cpp

178 lines

Target/

AMDGPU/

AMDGPULegalizerInfo.cpp

4 lines

test/

CodeGen/

AMDGPU/

GlobalISel/

370 lines

358 lines

275 lines

230 lines

1208 lines

1206 lines

732 lines

984 lines

Diff 287500

llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h

Show First 20 Lines • Show All 355 Lines • ▼ Show 20 Lines	public:
LegalizeResult lowerMergeValues(MachineInstr &MI);		LegalizeResult lowerMergeValues(MachineInstr &MI);
LegalizeResult lowerUnmergeValues(MachineInstr &MI);		LegalizeResult lowerUnmergeValues(MachineInstr &MI);
LegalizeResult lowerExtractInsertVectorElt(MachineInstr &MI);		LegalizeResult lowerExtractInsertVectorElt(MachineInstr &MI);
LegalizeResult lowerShuffleVector(MachineInstr &MI);		LegalizeResult lowerShuffleVector(MachineInstr &MI);
LegalizeResult lowerDynStackAlloc(MachineInstr &MI);		LegalizeResult lowerDynStackAlloc(MachineInstr &MI);
LegalizeResult lowerExtract(MachineInstr &MI);		LegalizeResult lowerExtract(MachineInstr &MI);
LegalizeResult lowerInsert(MachineInstr &MI);		LegalizeResult lowerInsert(MachineInstr &MI);
LegalizeResult lowerSADDO_SSUBO(MachineInstr &MI);		LegalizeResult lowerSADDO_SSUBO(MachineInstr &MI);
LegalizeResult lowerAddSubSatToMinMax(MachineInstr &MI);		LegalizeResult lowerAddSubSatToMinMax(MachineInstr &MI, LLT WideTy = LLT());
LegalizeResult lowerAddSubSatToAddoSubo(MachineInstr &MI);		LegalizeResult lowerAddSubSatToAddoSubo(MachineInstr &MI);
LegalizeResult lowerShlSat(MachineInstr &MI);		LegalizeResult lowerShlSat(MachineInstr &MI);
LegalizeResult lowerBswap(MachineInstr &MI);		LegalizeResult lowerBswap(MachineInstr &MI);
LegalizeResult lowerBitreverse(MachineInstr &MI);		LegalizeResult lowerBitreverse(MachineInstr &MI);
LegalizeResult lowerReadWriteRegister(MachineInstr &MI);		LegalizeResult lowerReadWriteRegister(MachineInstr &MI);
};		};

/// Helper function that creates a libcall to the given \p Name using the given		/// Helper function that creates a libcall to the given \p Name using the given
Show All 20 Lines

llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h

Show First 20 Lines • Show All 850 Lines • ▼ Show 20 Lines	public:
LegalizeRuleSet &minScalar(unsigned TypeIdx, const LLT Ty) {		LegalizeRuleSet &minScalar(unsigned TypeIdx, const LLT Ty) {
using namespace LegalityPredicates;		using namespace LegalityPredicates;
using namespace LegalizeMutations;		using namespace LegalizeMutations;
return actionIf(LegalizeAction::WidenScalar,		return actionIf(LegalizeAction::WidenScalar,
scalarNarrowerThan(TypeIdx, Ty.getSizeInBits()),		scalarNarrowerThan(TypeIdx, Ty.getSizeInBits()),
changeTo(typeIdx(TypeIdx), Ty));		changeTo(typeIdx(TypeIdx), Ty));
}		}

		/// Lower the instruction, and prefer to perform the expansion in \p Ty. This
		/// type is treated as an optimization hint, and the type request may not be
		/// respected for all lowerings.
		LegalizeRuleSet &lowerMinScalar(unsigned TypeIdx, const LLT Ty) {
		using namespace LegalityPredicates;
		using namespace LegalizeMutations;
		return actionIf(LegalizeAction::Lower,
		scalarNarrowerThan(TypeIdx, Ty.getSizeInBits()),
		changeTo(typeIdx(TypeIdx), Ty));
		}

/// Ensure the scalar is at most as wide as Ty.		/// Ensure the scalar is at most as wide as Ty.
LegalizeRuleSet &maxScalarOrElt(unsigned TypeIdx, const LLT Ty) {		LegalizeRuleSet &maxScalarOrElt(unsigned TypeIdx, const LLT Ty) {
using namespace LegalityPredicates;		using namespace LegalityPredicates;
using namespace LegalizeMutations;		using namespace LegalizeMutations;
return actionIf(LegalizeAction::NarrowScalar,		return actionIf(LegalizeAction::NarrowScalar,
scalarOrEltWiderThan(TypeIdx, Ty.getScalarSizeInBits()),		scalarOrEltWiderThan(TypeIdx, Ty.getScalarSizeInBits()),
changeElementTo(typeIdx(TypeIdx), Ty));		changeElementTo(typeIdx(TypeIdx), Ty));
}		}
▲ Show 20 Lines • Show All 615 Lines • Show Last 20 Lines

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

Show First 20 Lines • Show All 3,059 Lines • ▼ Show 20 Lines	case G_BSWAP:
return lowerBswap(MI);		return lowerBswap(MI);
case G_BITREVERSE:		case G_BITREVERSE:
return lowerBitreverse(MI);		return lowerBitreverse(MI);
case G_READ_REGISTER:		case G_READ_REGISTER:
case G_WRITE_REGISTER:		case G_WRITE_REGISTER:
return lowerReadWriteRegister(MI);		return lowerReadWriteRegister(MI);
case G_UADDSAT:		case G_UADDSAT:
case G_USUBSAT: {		case G_USUBSAT: {
		LLT Ty = LowerHintTy.isValid() ? LowerHintTy :
		MRI.getType(MI.getOperand(0).getReg());

// Try to make a reasonable guess about which lowering strategy to use. The		// Try to make a reasonable guess about which lowering strategy to use. The
// target can override this with custom lowering and calling the		// target can override this with custom lowering and calling the
// implementation functions.		// implementation functions.
LLT Ty = MRI.getType(MI.getOperand(0).getReg());
if (LI.isLegalOrCustom({G_UMIN, Ty}))		if (LI.isLegalOrCustom({G_UMIN, Ty}))
return lowerAddSubSatToMinMax(MI);		return lowerAddSubSatToMinMax(MI, Ty);
return lowerAddSubSatToAddoSubo(MI);		return lowerAddSubSatToAddoSubo(MI);
}		}
case G_SADDSAT:		case G_SADDSAT:
case G_SSUBSAT: {		case G_SSUBSAT: {
LLT Ty = MRI.getType(MI.getOperand(0).getReg());		LLT Ty = LowerHintTy.isValid() ? LowerHintTy :
		MRI.getType(MI.getOperand(0).getReg());

// FIXME: It would probably make more sense to see if G_SADDO is preferred,		// FIXME: It would probably make more sense to see if G_SADDO is preferred,
// since it's a shorter expansion. However, we would need to figure out the		// since it's a shorter expansion. However, we would need to figure out the
// preferred boolean type for the carry out for the query.		// preferred boolean type for the carry out for the query.
if (LI.isLegalOrCustom({G_SMIN, Ty}) && LI.isLegalOrCustom({G_SMAX, Ty}))		if (LI.isLegalOrCustom({G_SMIN, Ty}) && LI.isLegalOrCustom({G_SMAX, Ty}))
return lowerAddSubSatToMinMax(MI);		return lowerAddSubSatToMinMax(MI, Ty);
return lowerAddSubSatToAddoSubo(MI);		return lowerAddSubSatToAddoSubo(MI);
}		}
case G_SSHLSAT:		case G_SSHLSAT:
case G_USHLSAT:		case G_USHLSAT:
return lowerShlSat(MI);		return lowerShlSat(MI);
}		}
}		}

▲ Show 20 Lines • Show All 2,752 Lines • ▼ Show 20 Lines	LegalizerHelper::lowerSADDO_SSUBO(MachineInstr &MI) {
auto ConditionRHS = MIRBuilder.buildICmp(		auto ConditionRHS = MIRBuilder.buildICmp(
IsAdd ? CmpInst::ICMP_SLT : CmpInst::ICMP_SGT, BoolTy, RHS, Zero);		IsAdd ? CmpInst::ICMP_SLT : CmpInst::ICMP_SGT, BoolTy, RHS, Zero);

MIRBuilder.buildXor(Dst1, ConditionRHS, ResultLowerThanLHS);		MIRBuilder.buildXor(Dst1, ConditionRHS, ResultLowerThanLHS);
MI.eraseFromParent();		MI.eraseFromParent();
return Legalized;		return Legalized;
}		}

		/// Expand saturating add/sub which uses min/max instructions. If \p WideTy is
		/// provided, this will perform the expansion in a wider bitwidth.
LegalizerHelper::LegalizeResult		LegalizerHelper::LegalizeResult
LegalizerHelper::lowerAddSubSatToMinMax(MachineInstr &MI) {		LegalizerHelper::lowerAddSubSatToMinMax(MachineInstr &MI, LLT WideTy) {
		const unsigned Opc = MI.getOpcode();
Register Res = MI.getOperand(0).getReg();		Register Res = MI.getOperand(0).getReg();
Register LHS = MI.getOperand(1).getReg();		Register LHS = MI.getOperand(1).getReg();
Register RHS = MI.getOperand(2).getReg();		Register RHS = MI.getOperand(2).getReg();
LLT Ty = MRI.getType(Res);
bool IsSigned;
bool IsAdd;
unsigned BaseOp;
switch (MI.getOpcode()) {
default:
llvm_unreachable("unexpected addsat/subsat opcode");
case TargetOpcode::G_UADDSAT:
IsSigned = false;
IsAdd = true;
BaseOp = TargetOpcode::G_ADD;
break;
case TargetOpcode::G_SADDSAT:
IsSigned = true;
IsAdd = true;
BaseOp = TargetOpcode::G_ADD;
break;
case TargetOpcode::G_USUBSAT:
IsSigned = false;
IsAdd = false;
BaseOp = TargetOpcode::G_SUB;
break;
case TargetOpcode::G_SSUBSAT:
IsSigned = true;
IsAdd = false;
BaseOp = TargetOpcode::G_SUB;
break;
}

		Register OrigRes = Res;
		LLT OrigTy = MRI.getType(Res);
		LLT Ty = OrigTy;
		bool DoPromote = WideTy.isValid() && WideTy != OrigTy;

		if (DoPromote) {
		bool IsSigned = Opc == TargetOpcode::G_SADDSAT \|\|
		Opc == TargetOpcode::G_SSUBSAT;
		Res = MRI.createGenericVirtualRegister(WideTy);
		Ty = WideTy;
if (IsSigned) {		if (IsSigned) {
		LHS = MIRBuilder.buildSExt(WideTy, LHS).getReg(0);
		RHS = MIRBuilder.buildSExt(WideTy, RHS).getReg(0);
		} else {
		LHS = MIRBuilder.buildZExt(WideTy, LHS).getReg(0);
		RHS = MIRBuilder.buildZExt(WideTy, RHS).getReg(0);
		}
		}

		// usub.sat(a, b) -> umax(a, b) - b
		foadUnsubmitted Not Done Reply Inline Actions Could use getLowBitsSet and getOneBitSet, but I suppose it would be annoyingly asymmetrical. foad: Could use getLowBitsSet and getOneBitSet, but I suppose it would be annoyingly asymmetrical.
		foadUnsubmitted Not Done Reply Inline Actions Surely we should take advantage of DoPromote to simplify this? You can do a normal add/sub and then clamp the result to MinVal and MaxVal. foad: Surely we should take advantage of DoPromote to simplify this? You can do a normal add/sub and…
		//
		// TODO: If the target had umin, and not umax an alternative would be
		// usub.sat(a, b) -> a - umin(a, b)
		if (Opc == TargetOpcode::G_USUBSAT) {
		auto Max = MIRBuilder.buildUMax(Ty, LHS, RHS);
		MIRBuilder.buildSub(Res, Max, RHS);
		} else if (Opc == TargetOpcode::G_UADDSAT) {
		if (DoPromote) {
		// uadd.sat(a, b) -> umin(zext(a) + zext(b), max_val)
		//
		// If we're promoting, we know the wider add won't overflow, so do a
		// simple clamp on the wider result.

		unsigned OrigNumBits = OrigTy.getScalarSizeInBits();
		unsigned NewNumBits = Ty.getScalarSizeInBits();
		APInt MaxVal = APInt::getLowBitsSet(NewNumBits, OrigNumBits);
		foadUnsubmitted Not Done Reply Inline Actions Use APInt::getLowBitsSet? foad: Use APInt::getLowBitsSet?
		auto SatMax = MIRBuilder.buildConstant(Ty, MaxVal);
		auto Add = MIRBuilder.buildAdd(Ty, LHS, RHS);
		MIRBuilder.buildUMin(Res, Add, SatMax);
		} else {
		// uadd.sat(a, b) -> a + umin(~a, b)
		Register Not = MIRBuilder.buildNot(Ty, LHS).getReg(0);
		auto Min = MIRBuilder.buildUMin(Ty, Not, RHS);
		MIRBuilder.buildAdd(Res, LHS, Min);
		}
		} else {
		const bool IsAdd = Opc == TargetOpcode::G_SADDSAT;
		unsigned OrigNumBits = OrigTy.getScalarSizeInBits();
		unsigned NewNumBits = Ty.getScalarSizeInBits();
		const APInt MinSignedVal =
		APInt::getSignedMinValue(OrigNumBits).sextOrSelf(NewNumBits);
		const APInt MaxSignedVal =
		APInt::getSignedMaxValue(OrigNumBits).sextOrSelf(NewNumBits);

		if (DoPromote) {
		// sadd.sat(a, b) -> smin(smax(sext(a) + sext(b), min_val), max_val)
		// ssub.sat(a, b) -> smin(smax(sext(a) - sext(b), min_val), max_val)
		//
		// If we're promoting, we know the wider add won't overflow, so do a
		// simple clamp on the wider result.

		auto Op = IsAdd ? MIRBuilder.buildAdd(Ty, LHS, RHS)
		: MIRBuilder.buildSub(Ty, LHS, RHS);
		auto MinVal = MIRBuilder.buildConstant(Ty, MinSignedVal);
		auto ClampMin = MIRBuilder.buildSMax(Ty, Op, MinVal);

		auto MaxVal = MIRBuilder.buildConstant(Ty, MaxSignedVal);
		MIRBuilder.buildSMin(Res, ClampMin, MaxVal);
		} else {
// sadd.sat(a, b) ->		// sadd.sat(a, b) ->
// hi = 0x7fffffff - smax(a, 0)		// hi = 0x7fffffff - smax(a, 0)
// lo = 0x80000000 - smin(a, 0)		// lo = 0x80000000 - smin(a, 0)
// a + smin(smax(lo, b), hi)		// a + smin(smax(lo, b), hi)
// ssub.sat(a, b) ->		// ssub.sat(a, b) ->
// lo = smax(a, -1) - 0x7fffffff		// lo = smax(a, -1) - 0x7fffffff
// hi = smin(a, -1) - 0x80000000		// hi = smin(a, -1) - 0x80000000
// a - smin(smax(lo, b), hi)		// a - smin(smax(lo, b), hi)
// TODO: AMDGPU can use a "median of 3" instruction here:		// TODO: AMDGPU can use a "median of 3" instruction here:
// a +/- med3(lo, b, hi)		// a +/- med3(lo, b, hi)
uint64_t NumBits = Ty.getScalarSizeInBits();		auto MaxVal = MIRBuilder.buildConstant(Ty, MaxSignedVal);
auto MaxVal =		auto MinVal = MIRBuilder.buildConstant(Ty, MinSignedVal);
MIRBuilder.buildConstant(Ty, APInt::getSignedMaxValue(NumBits));
auto MinVal =
MIRBuilder.buildConstant(Ty, APInt::getSignedMinValue(NumBits));
MachineInstrBuilder Hi, Lo;		MachineInstrBuilder Hi, Lo;
if (IsAdd) {		if (IsAdd) {
auto Zero = MIRBuilder.buildConstant(Ty, 0);		auto Zero = MIRBuilder.buildConstant(Ty, 0);
Hi = MIRBuilder.buildSub(Ty, MaxVal, MIRBuilder.buildSMax(Ty, LHS, Zero));		Hi = MIRBuilder.buildSub(Ty, MaxVal,
Lo = MIRBuilder.buildSub(Ty, MinVal, MIRBuilder.buildSMin(Ty, LHS, Zero));		MIRBuilder.buildSMax(Ty, LHS, Zero));
		Lo = MIRBuilder.buildSub(Ty, MinVal,
		MIRBuilder.buildSMin(Ty, LHS, Zero));
} else {		} else {
auto NegOne = MIRBuilder.buildConstant(Ty, -1);		auto NegOne = MIRBuilder.buildConstant(Ty, -1);
Lo = MIRBuilder.buildSub(Ty, MIRBuilder.buildSMax(Ty, LHS, NegOne),		Lo = MIRBuilder.buildSub(Ty, MIRBuilder.buildSMax(Ty, LHS, NegOne),
MaxVal);		MaxVal);
Hi = MIRBuilder.buildSub(Ty, MIRBuilder.buildSMin(Ty, LHS, NegOne),		Hi = MIRBuilder.buildSub(Ty, MIRBuilder.buildSMin(Ty, LHS, NegOne),
MinVal);		MinVal);
}		}
auto RHSClamped =		auto RHSClamped =
MIRBuilder.buildSMin(Ty, MIRBuilder.buildSMax(Ty, Lo, RHS), Hi);		MIRBuilder.buildSMin(Ty, MIRBuilder.buildSMax(Ty, Lo, RHS), Hi);

		unsigned BaseOp = IsAdd ? TargetOpcode::G_ADD : TargetOpcode::G_SUB;
MIRBuilder.buildInstr(BaseOp, {Res}, {LHS, RHSClamped});		MIRBuilder.buildInstr(BaseOp, {Res}, {LHS, RHSClamped});
} else {
// uadd.sat(a, b) -> a + umin(~a, b)
// usub.sat(a, b) -> a - umin(a, b)
Register Not = IsAdd ? MIRBuilder.buildNot(Ty, LHS).getReg(0) : LHS;
auto Min = MIRBuilder.buildUMin(Ty, Not, RHS);
MIRBuilder.buildInstr(BaseOp, {Res}, {LHS, Min});
}		}
		}

		if (DoPromote)
		MIRBuilder.buildTrunc(OrigRes, Res);

MI.eraseFromParent();		MI.eraseFromParent();
return Legalized;		return Legalized;
}		}

LegalizerHelper::LegalizeResult		LegalizerHelper::LegalizeResult
LegalizerHelper::lowerAddSubSatToAddoSubo(MachineInstr &MI) {		LegalizerHelper::lowerAddSubSatToAddoSubo(MachineInstr &MI) {
Register Res = MI.getOperand(0).getReg();		Register Res = MI.getOperand(0).getReg();
▲ Show 20 Lines • Show All 201 Lines • Show Last 20 Lines

llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Show First 20 Lines • Show All 556 Lines • ▼ Show 20 Lines	if (ST.hasIntClamp()) {
getActionDefinitionsBuilder({G_UADDSAT, G_USUBSAT})		getActionDefinitionsBuilder({G_UADDSAT, G_USUBSAT})
.legalFor({S32}) // Clamp modifier.		.legalFor({S32}) // Clamp modifier.
.scalarize(0)		.scalarize(0)
.minScalarOrElt(0, S32)		.minScalarOrElt(0, S32)
.lower();		.lower();
} else {		} else {
// Clamp bit support was added in VI, along with 16-bit operations.		// Clamp bit support was added in VI, along with 16-bit operations.
getActionDefinitionsBuilder({G_UADDSAT, G_USUBSAT})		getActionDefinitionsBuilder({G_UADDSAT, G_USUBSAT})
.minScalar(0, S32)		.lowerMinScalar(0, S32)
.scalarize(0)		.scalarize(0)
.lower();		.lower();
}		}

// FIXME: DAG expansion gets better results. The widening uses the smaller		// FIXME: DAG expansion gets better results. The widening uses the smaller
// range values and goes for the min/max lowering directly.		// range values and goes for the min/max lowering directly.
getActionDefinitionsBuilder({G_SADDSAT, G_SSUBSAT})		getActionDefinitionsBuilder({G_SADDSAT, G_SSUBSAT})
.minScalar(0, S32)		.lowerMinScalar(0, S32)
.scalarize(0)		.scalarize(0)
.lower();		.lower();
}		}

getActionDefinitionsBuilder({G_SDIV, G_UDIV, G_SREM, G_UREM})		getActionDefinitionsBuilder({G_SDIV, G_UDIV, G_SREM, G_UREM})
.customFor({S32, S64})		.customFor({S32, S64})
.clampScalar(0, S32, S64)		.clampScalar(0, S32, S64)
.widenScalarToNextPow2(0, 32)		.widenScalarToNextPow2(0, 32)
▲ Show 20 Lines • Show All 4,089 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddsat.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py		# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -global-isel-abort=0 -march=amdgcn -mcpu=tahiti -run-pass=legalizer %s -o - \| FileCheck -check-prefix=GFX6 %s		# RUN: llc -global-isel-abort=0 -march=amdgcn -mcpu=tahiti -run-pass=legalizer %s -o - \| FileCheck -check-prefix=GFX6 %s
# RUN: llc -global-isel-abort=0 -march=amdgcn -mcpu=fiji -run-pass=legalizer %s -o - \| FileCheck -check-prefix=GFX8 %s		# RUN: llc -global-isel-abort=0 -march=amdgcn -mcpu=fiji -run-pass=legalizer %s -o - \| FileCheck -check-prefix=GFX8 %s
# RUN: llc -global-isel-abort=0 -march=amdgcn -mcpu=gfx900 -run-pass=legalizer %s -o - \| FileCheck -check-prefix=GFX9 %s		# RUN: llc -global-isel-abort=0 -march=amdgcn -mcpu=gfx900 -run-pass=legalizer %s -o - \| FileCheck -check-prefix=GFX9 %s

---		---
name: saddsat_s7		name: saddsat_s7
body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0, $vgpr1		liveins: $vgpr0, $vgpr1

; GFX6-LABEL: name: saddsat_s7		; GFX6-LABEL: name: saddsat_s7
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0		; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1		; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
		; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 7
; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 25		; GFX6: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 7
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)		; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)		; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -64
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647		; GFX6: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[ADD]], [[C]]
; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648		; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
; GFX6: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0		; GFX6: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SMAX]], [[C1]]
; GFX6: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[SHL]], [[C3]]		; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SMIN]](s32)
; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C1]], [[SMAX]]
; GFX6: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SHL]], [[C3]]
; GFX6: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[SMIN]]
; GFX6: [[SMAX1:%[0-9]+]]:_(s32) = G_SMAX [[SUB1]], [[SHL1]]
; GFX6: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN [[SMAX1]], [[SUB]]
; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SHL]], [[SMIN1]]
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[ADD]], [[C]](s32)
; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
; GFX6: $vgpr0 = COPY [[COPY4]](s32)		; GFX6: $vgpr0 = COPY [[COPY4]](s32)
; GFX8-LABEL: name: saddsat_s7		; GFX8-LABEL: name: saddsat_s7
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1		; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)		; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX8: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)		; GFX8: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX8: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 9		; GFX8: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 9
; GFX8: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16)		; GFX8: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16)
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liveins: $vgpr0, $vgpr1		liveins: $vgpr0, $vgpr1

; GFX6-LABEL: name: saddsat_s8		; GFX6-LABEL: name: saddsat_s8
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0		; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1		; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
		; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 8
; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24		; GFX6: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 8
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)		; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)		; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -128
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647		; GFX6: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[ADD]], [[C]]
; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648		; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
; GFX6: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0		; GFX6: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SMAX]], [[C1]]
; GFX6: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[SHL]], [[C3]]		; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SMIN]](s32)
; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C1]], [[SMAX]]
; GFX6: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SHL]], [[C3]]
; GFX6: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[SMIN]]
; GFX6: [[SMAX1:%[0-9]+]]:_(s32) = G_SMAX [[SUB1]], [[SHL1]]
; GFX6: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN [[SMAX1]], [[SUB]]
; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SHL]], [[SMIN1]]
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[ADD]], [[C]](s32)
; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
; GFX6: $vgpr0 = COPY [[COPY4]](s32)		; GFX6: $vgpr0 = COPY [[COPY4]](s32)
; GFX8-LABEL: name: saddsat_s8		; GFX8-LABEL: name: saddsat_s8
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1		; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)		; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX8: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)		; GFX8: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX8: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 8		; GFX8: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; GFX8: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16)		; GFX8: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16)
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; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16		; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32)		; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32)
; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24		; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX6: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)		; GFX6: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
; GFX6: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32)		; GFX6: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32)
; GFX6: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C1]](s32)		; GFX6: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C1]](s32)
; GFX6: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)		; GFX6: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
		; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 8
; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C2]](s32)		; GFX6: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 8
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C2]](s32)		; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX6: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647		; GFX6: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -128
; GFX6: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648		; GFX6: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[ADD]], [[C3]]
; GFX6: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 0		; GFX6: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
; GFX6: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[SHL]], [[C5]]		; GFX6: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SMAX]], [[C4]]
; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[SMAX]]
; GFX6: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SHL]], [[C5]]
; GFX6: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C4]], [[SMIN]]
; GFX6: [[SMAX1:%[0-9]+]]:_(s32) = G_SMAX [[SUB1]], [[SHL1]]
; GFX6: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN [[SMAX1]], [[SUB]]
; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SHL]], [[SMIN1]]
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[ADD]], [[C2]](s32)
; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)		; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
		; GFX6: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 8
; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)		; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C2]](s32)		; GFX6: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 8
; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C2]](s32)		; GFX6: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[SEXT_INREG2]], [[SEXT_INREG3]]
; GFX6: [[SMAX2:%[0-9]+]]:_(s32) = G_SMAX [[SHL2]], [[C5]]		; GFX6: [[SMAX1:%[0-9]+]]:_(s32) = G_SMAX [[ADD1]], [[C3]]
; GFX6: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[C3]], [[SMAX2]]		; GFX6: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN [[SMAX1]], [[C4]]
; GFX6: [[SMIN2:%[0-9]+]]:_(s32) = G_SMIN [[SHL2]], [[C5]]		; GFX6: [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; GFX6: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C4]], [[SMIN2]]		; GFX6: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SMIN]](s32)
; GFX6: [[SMAX3:%[0-9]+]]:_(s32) = G_SMAX [[SUB3]], [[SHL3]]		; GFX6: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C5]]
; GFX6: [[SMIN3:%[0-9]+]]:_(s32) = G_SMIN [[SMAX3]], [[SUB2]]
; GFX6: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[SHL2]], [[SMIN3]]
; GFX6: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ADD1]], [[C2]](s32)
; GFX6: [[C6:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; GFX6: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR]](s32)
; GFX6: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C6]]
; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C]](s32)		; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX6: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 255		; GFX6: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ASHR1]](s32)		; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SMIN1]](s32)
; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C7]]		; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C6]]
; GFX6: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY6]](s32)		; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY6]](s32)
; GFX6: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL4]](s32)		; GFX6: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; GFX6: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]		; GFX6: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; GFX6: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)		; GFX6: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; GFX6: $vgpr0 = COPY [[ANYEXT]](s32)		; GFX6: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX8-LABEL: name: saddsat_v2s8		; GFX8-LABEL: name: saddsat_v2s8
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1		; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8		; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX8: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)		; GFX8: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
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liveins: $vgpr0, $vgpr1		liveins: $vgpr0, $vgpr1

; GFX6-LABEL: name: saddsat_s16		; GFX6-LABEL: name: saddsat_s16
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0		; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1		; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
		; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16		; GFX6: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)		; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)		; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647		; GFX6: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[ADD]], [[C]]
; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648		; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767
; GFX6: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0		; GFX6: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SMAX]], [[C1]]
; GFX6: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[SHL]], [[C3]]		; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SMIN]](s32)
; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C1]], [[SMAX]]
; GFX6: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SHL]], [[C3]]
; GFX6: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[SMIN]]
; GFX6: [[SMAX1:%[0-9]+]]:_(s32) = G_SMAX [[SUB1]], [[SHL1]]
; GFX6: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN [[SMAX1]], [[SUB]]
; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SHL]], [[SMIN1]]
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[ADD]], [[C]](s32)
; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
; GFX6: $vgpr0 = COPY [[COPY4]](s32)		; GFX6: $vgpr0 = COPY [[COPY4]](s32)
; GFX8-LABEL: name: saddsat_s16		; GFX8-LABEL: name: saddsat_s16
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1		; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)		; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX8: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)		; GFX8: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX8: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767		; GFX8: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767
; GFX8: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768		; GFX8: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768
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; GFX6: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0		; GFX6: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1		; GFX6: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
; GFX6: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)		; GFX6: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16		; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)		; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX6: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)		; GFX6: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)		; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)		; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
		; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)		; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)		; GFX6: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)		; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647		; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768
; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648		; GFX6: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[ADD]], [[C1]]
; GFX6: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0		; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767
; GFX6: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[SHL]], [[C3]]		; GFX6: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SMAX]], [[C2]]
; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C1]], [[SMAX]]
; GFX6: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SHL]], [[C3]]
; GFX6: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[SMIN]]
; GFX6: [[SMAX1:%[0-9]+]]:_(s32) = G_SMAX [[SUB1]], [[SHL1]]
; GFX6: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN [[SMAX1]], [[SUB]]
; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SHL]], [[SMIN1]]
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[ADD]], [[C]](s32)
; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)		; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
		; GFX6: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 16
; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)		; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)		; GFX6: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 16
; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C]](s32)		; GFX6: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[SEXT_INREG2]], [[SEXT_INREG3]]
; GFX6: [[SMAX2:%[0-9]+]]:_(s32) = G_SMAX [[SHL2]], [[C3]]		; GFX6: [[SMAX1:%[0-9]+]]:_(s32) = G_SMAX [[ADD1]], [[C1]]
; GFX6: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[C1]], [[SMAX2]]		; GFX6: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN [[SMAX1]], [[C2]]
; GFX6: [[SMIN2:%[0-9]+]]:_(s32) = G_SMIN [[SHL2]], [[C3]]		; GFX6: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; GFX6: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[SMIN2]]		; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SMIN]](s32)
; GFX6: [[SMAX3:%[0-9]+]]:_(s32) = G_SMAX [[SUB3]], [[SHL3]]		; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
; GFX6: [[SMIN3:%[0-9]+]]:_(s32) = G_SMIN [[SMAX3]], [[SUB2]]		; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SMIN1]](s32)
; GFX6: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[SHL2]], [[SMIN3]]		; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
; GFX6: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ADD1]], [[C]](s32)		; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX6: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535		; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C4]]
; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ASHR1]](s32)
; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C4]]
; GFX6: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL4]]
; GFX6: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)		; GFX6: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX6: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)		; GFX6: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
; GFX8-LABEL: name: saddsat_v2s16		; GFX8-LABEL: name: saddsat_v2s16
; GFX8: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1		; GFX8: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
; GFX8: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)		; GFX8: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)		; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16		; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
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; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)		; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX6: [[INSERT1:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[UV1]](<3 x s16>), 0		; GFX6: [[INSERT1:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[UV1]](<3 x s16>), 0
; GFX6: [[UV4:%[0-9]+]]:_(<2 x s16>), [[UV5:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INSERT1]](<4 x s16>)		; GFX6: [[UV4:%[0-9]+]]:_(<2 x s16>), [[UV5:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INSERT1]](<4 x s16>)
; GFX6: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV4]](<2 x s16>)		; GFX6: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV4]](<2 x s16>)
; GFX6: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)		; GFX6: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX6: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV5]](<2 x s16>)		; GFX6: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV5]](<2 x s16>)
; GFX6: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)		; GFX6: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)		; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
		; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)		; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)		; GFX6: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)		; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647		; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768
; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648		; GFX6: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[ADD]], [[C1]]
; GFX6: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0		; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767
; GFX6: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[SHL]], [[C3]]		; GFX6: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SMAX]], [[C2]]
; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C1]], [[SMAX]]
; GFX6: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SHL]], [[C3]]
; GFX6: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[SMIN]]
; GFX6: [[SMAX1:%[0-9]+]]:_(s32) = G_SMAX [[SUB1]], [[SHL1]]
; GFX6: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN [[SMAX1]], [[SUB]]
; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SHL]], [[SMIN1]]
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[ADD]], [[C]](s32)
; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)		; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
		; GFX6: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)		; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)		; GFX6: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 16
; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)		; GFX6: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[SEXT_INREG2]], [[SEXT_INREG3]]
; GFX6: [[SMAX2:%[0-9]+]]:_(s32) = G_SMAX [[SHL2]], [[C3]]		; GFX6: [[SMAX1:%[0-9]+]]:_(s32) = G_SMAX [[ADD1]], [[C1]]
; GFX6: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[C1]], [[SMAX2]]		; GFX6: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN [[SMAX1]], [[C2]]
; GFX6: [[SMIN2:%[0-9]+]]:_(s32) = G_SMIN [[SHL2]], [[C3]]
; GFX6: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[SMIN2]]
; GFX6: [[SMAX3:%[0-9]+]]:_(s32) = G_SMAX [[SUB3]], [[SHL3]]
; GFX6: [[SMIN3:%[0-9]+]]:_(s32) = G_SMIN [[SMAX3]], [[SUB2]]
; GFX6: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[SHL2]], [[SMIN3]]
; GFX6: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ADD1]], [[C]](s32)
; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)		; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
		; GFX6: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 16
; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)		; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
; GFX6: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C]](s32)		; GFX6: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY6]], 16
; GFX6: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[COPY6]], [[C]](s32)		; GFX6: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[SEXT_INREG4]], [[SEXT_INREG5]]
; GFX6: [[SMAX4:%[0-9]+]]:_(s32) = G_SMAX [[SHL4]], [[C3]]		; GFX6: [[SMAX2:%[0-9]+]]:_(s32) = G_SMAX [[ADD2]], [[C1]]
; GFX6: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[C1]], [[SMAX4]]		; GFX6: [[SMIN2:%[0-9]+]]:_(s32) = G_SMIN [[SMAX2]], [[C2]]
; GFX6: [[SMIN4:%[0-9]+]]:_(s32) = G_SMIN [[SHL4]], [[C3]]		; GFX6: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; GFX6: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[SMIN4]]		; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SMIN]](s32)
; GFX6: [[SMAX5:%[0-9]+]]:_(s32) = G_SMAX [[SUB5]], [[SHL5]]		; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
; GFX6: [[SMIN5:%[0-9]+]]:_(s32) = G_SMIN [[SMAX5]], [[SUB4]]		; GFX6: [[COPY8:%[0-9]+]]:_(s32) = COPY [[SMIN1]](s32)
; GFX6: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[SHL4]], [[SMIN5]]		; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
; GFX6: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[ADD2]], [[C]](s32)		; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX6: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535		; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C4]]
; GFX6: [[COPY8:%[0-9]+]]:_(s32) = COPY [[ASHR1]](s32)
; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C4]]
; GFX6: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL6]]
; GFX6: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)		; GFX6: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX6: [[COPY9:%[0-9]+]]:_(s32) = COPY [[ASHR2]](s32)		; GFX6: [[COPY9:%[0-9]+]]:_(s32) = COPY [[SMIN2]](s32)
; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C4]]		; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
; GFX6: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C3]](s32)		; GFX6: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX6: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[COPY10]], [[C]](s32)		; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C4]], [[C]](s32)
; GFX6: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL7]]		; GFX6: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX6: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)		; GFX6: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; GFX6: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF		; GFX6: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
; GFX6: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>), [[DEF1]](<2 x s16>)		; GFX6: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>), [[DEF1]](<2 x s16>)
; GFX6: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<6 x s16>), 0		; GFX6: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<6 x s16>), 0
; GFX6: [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF		; GFX6: [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
; GFX6: [[CONCAT_VECTORS1:%[0-9]+]]:_(<12 x s16>) = G_CONCAT_VECTORS [[DEF2]](<4 x s16>), [[DEF]](<4 x s16>), [[DEF]](<4 x s16>)		; GFX6: [[CONCAT_VECTORS1:%[0-9]+]]:_(<12 x s16>) = G_CONCAT_VECTORS [[DEF2]](<4 x s16>), [[DEF]](<4 x s16>), [[DEF]](<4 x s16>)
; GFX6: [[UV6:%[0-9]+]]:_(<3 x s16>), [[UV7:%[0-9]+]]:_(<3 x s16>), [[UV8:%[0-9]+]]:_(<3 x s16>), [[UV9:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS1]](<12 x s16>)		; GFX6: [[UV6:%[0-9]+]]:_(<3 x s16>), [[UV7:%[0-9]+]]:_(<3 x s16>), [[UV8:%[0-9]+]]:_(<3 x s16>), [[UV9:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS1]](<12 x s16>)
; GFX6: [[INSERT2:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[EXTRACT]](<3 x s16>), 0		; GFX6: [[INSERT2:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[EXTRACT]](<3 x s16>), 0
; GFX6: [[UV10:%[0-9]+]]:_(<2 x s16>), [[UV11:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INSERT2]](<4 x s16>)		; GFX6: [[UV10:%[0-9]+]]:_(<2 x s16>), [[UV11:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INSERT2]](<4 x s16>)
; GFX6: [[BITCAST6:%[0-9]+]]:_(s32) = G_BITCAST [[UV10]](<2 x s16>)		; GFX6: [[BITCAST6:%[0-9]+]]:_(s32) = G_BITCAST [[UV10]](<2 x s16>)
; GFX6: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST6]], [[C]](s32)		; GFX6: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST6]], [[C]](s32)
; GFX6: [[BITCAST7:%[0-9]+]]:_(s32) = G_BITCAST [[UV11]](<2 x s16>)		; GFX6: [[BITCAST7:%[0-9]+]]:_(s32) = G_BITCAST [[UV11]](<2 x s16>)
; GFX6: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST7]], [[C]](s32)		; GFX6: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST7]], [[C]](s32)
; GFX6: [[INSERT3:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[UV6]](<3 x s16>), 0		; GFX6: [[INSERT3:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[UV6]](<3 x s16>), 0
; GFX6: [[UV12:%[0-9]+]]:_(<2 x s16>), [[UV13:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INSERT3]](<4 x s16>)		; GFX6: [[UV12:%[0-9]+]]:_(<2 x s16>), [[UV13:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INSERT3]](<4 x s16>)
; GFX6: [[BITCAST8:%[0-9]+]]:_(s32) = G_BITCAST [[UV12]](<2 x s16>)		; GFX6: [[BITCAST8:%[0-9]+]]:_(s32) = G_BITCAST [[UV12]](<2 x s16>)
; GFX6: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST8]], [[C]](s32)		; GFX6: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST8]], [[C]](s32)
; GFX6: [[BITCAST9:%[0-9]+]]:_(s32) = G_BITCAST [[UV13]](<2 x s16>)		; GFX6: [[BITCAST9:%[0-9]+]]:_(s32) = G_BITCAST [[UV13]](<2 x s16>)
; GFX6: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST9]], [[C]](s32)		; GFX6: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST9]], [[C]](s32)
; GFX6: [[COPY11:%[0-9]+]]:_(s32) = COPY [[BITCAST6]](s32)		; GFX6: [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST6]](s32)
; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C4]]		; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
; GFX6: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)		; GFX6: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
; GFX6: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C4]]		; GFX6: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
; GFX6: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C]](s32)		; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C]](s32)
; GFX6: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND3]], [[SHL8]]		; GFX6: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND3]], [[SHL2]]
; GFX6: [[BITCAST10:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)		; GFX6: [[BITCAST10:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; GFX6: [[COPY13:%[0-9]+]]:_(s32) = COPY [[BITCAST7]](s32)		; GFX6: [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST7]](s32)
; GFX6: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C4]]		; GFX6: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
; GFX6: [[COPY14:%[0-9]+]]:_(s32) = COPY [[BITCAST8]](s32)		; GFX6: [[COPY13:%[0-9]+]]:_(s32) = COPY [[BITCAST8]](s32)
; GFX6: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C4]]		; GFX6: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
; GFX6: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C]](s32)		; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C]](s32)
; GFX6: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND5]], [[SHL9]]		; GFX6: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND5]], [[SHL3]]
; GFX6: [[BITCAST11:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)		; GFX6: [[BITCAST11:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
; GFX6: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)		; GFX6: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
; GFX6: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C4]]		; GFX6: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
; GFX6: [[COPY16:%[0-9]+]]:_(s32) = COPY [[BITCAST9]](s32)		; GFX6: [[COPY15:%[0-9]+]]:_(s32) = COPY [[BITCAST9]](s32)
; GFX6: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C4]]		; GFX6: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
; GFX6: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C]](s32)		; GFX6: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C]](s32)
; GFX6: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND7]], [[SHL10]]		; GFX6: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND7]], [[SHL4]]
; GFX6: [[BITCAST12:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)		; GFX6: [[BITCAST12:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
; GFX6: [[CONCAT_VECTORS2:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST10]](<2 x s16>), [[BITCAST11]](<2 x s16>), [[BITCAST12]](<2 x s16>)		; GFX6: [[CONCAT_VECTORS2:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST10]](<2 x s16>), [[BITCAST11]](<2 x s16>), [[BITCAST12]](<2 x s16>)
; GFX6: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS2]](<6 x s16>)		; GFX6: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS2]](<6 x s16>)
; GFX8-LABEL: name: saddsat_v3s16		; GFX8-LABEL: name: saddsat_v3s16
; GFX8: [[COPY:%[0-9]+]]:_(<6 x s16>) = COPY $vgpr0_vgpr1_vgpr2		; GFX8: [[COPY:%[0-9]+]]:_(<6 x s16>) = COPY $vgpr0_vgpr1_vgpr2
; GFX8: [[UV:%[0-9]+]]:_(<3 x s16>), [[UV1:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[COPY]](<6 x s16>)		; GFX8: [[UV:%[0-9]+]]:_(<3 x s16>), [[UV1:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[COPY]](<6 x s16>)
; GFX8: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF		; GFX8: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
; GFX8: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[UV]](<3 x s16>), 0		; GFX8: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[UV]](<3 x s16>), 0
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; GFX6: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)		; GFX6: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)		; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX6: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<4 x s16>)		; GFX6: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<4 x s16>)
; GFX6: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV2]](<2 x s16>)		; GFX6: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV2]](<2 x s16>)
; GFX6: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)		; GFX6: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX6: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)		; GFX6: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; GFX6: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)		; GFX6: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)		; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
		; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)		; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)		; GFX6: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)		; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647		; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768
; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648		; GFX6: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[ADD]], [[C1]]
; GFX6: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0		; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767
; GFX6: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[SHL]], [[C3]]		; GFX6: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SMAX]], [[C2]]
; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C1]], [[SMAX]]
; GFX6: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SHL]], [[C3]]
; GFX6: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[SMIN]]
; GFX6: [[SMAX1:%[0-9]+]]:_(s32) = G_SMAX [[SUB1]], [[SHL1]]
; GFX6: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN [[SMAX1]], [[SUB]]
; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SHL]], [[SMIN1]]
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[ADD]], [[C]](s32)
; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)		; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
		; GFX6: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 16
; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)		; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)		; GFX6: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 16
; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C]](s32)		; GFX6: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[SEXT_INREG2]], [[SEXT_INREG3]]
; GFX6: [[SMAX2:%[0-9]+]]:_(s32) = G_SMAX [[SHL2]], [[C3]]		; GFX6: [[SMAX1:%[0-9]+]]:_(s32) = G_SMAX [[ADD1]], [[C1]]
; GFX6: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[C1]], [[SMAX2]]		; GFX6: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN [[SMAX1]], [[C2]]
; GFX6: [[SMIN2:%[0-9]+]]:_(s32) = G_SMIN [[SHL2]], [[C3]]
; GFX6: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[SMIN2]]
; GFX6: [[SMAX3:%[0-9]+]]:_(s32) = G_SMAX [[SUB3]], [[SHL3]]
; GFX6: [[SMIN3:%[0-9]+]]:_(s32) = G_SMIN [[SMAX3]], [[SUB2]]
; GFX6: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[SHL2]], [[SMIN3]]
; GFX6: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ADD1]], [[C]](s32)
; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)		; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
		; GFX6: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY6]], 16
; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)		; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
; GFX6: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[COPY6]], [[C]](s32)		; GFX6: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY7]], 16
; GFX6: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[COPY7]], [[C]](s32)		; GFX6: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[SEXT_INREG4]], [[SEXT_INREG5]]
; GFX6: [[SMAX4:%[0-9]+]]:_(s32) = G_SMAX [[SHL4]], [[C3]]		; GFX6: [[SMAX2:%[0-9]+]]:_(s32) = G_SMAX [[ADD2]], [[C1]]
; GFX6: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[C1]], [[SMAX4]]		; GFX6: [[SMIN2:%[0-9]+]]:_(s32) = G_SMIN [[SMAX2]], [[C2]]
; GFX6: [[SMIN4:%[0-9]+]]:_(s32) = G_SMIN [[SHL4]], [[C3]]
; GFX6: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[SMIN4]]
; GFX6: [[SMAX5:%[0-9]+]]:_(s32) = G_SMAX [[SUB5]], [[SHL5]]
; GFX6: [[SMIN5:%[0-9]+]]:_(s32) = G_SMIN [[SMAX5]], [[SUB4]]
; GFX6: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[SHL4]], [[SMIN5]]
; GFX6: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[ADD2]], [[C]](s32)
; GFX6: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)		; GFX6: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
		; GFX6: [[SEXT_INREG6:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY8]], 16
; GFX6: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)		; GFX6: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
; GFX6: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[COPY8]], [[C]](s32)		; GFX6: [[SEXT_INREG7:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY9]], 16
; GFX6: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[COPY9]], [[C]](s32)		; GFX6: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[SEXT_INREG6]], [[SEXT_INREG7]]
; GFX6: [[SMAX6:%[0-9]+]]:_(s32) = G_SMAX [[SHL6]], [[C3]]		; GFX6: [[SMAX3:%[0-9]+]]:_(s32) = G_SMAX [[ADD3]], [[C1]]
; GFX6: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[C1]], [[SMAX6]]		; GFX6: [[SMIN3:%[0-9]+]]:_(s32) = G_SMIN [[SMAX3]], [[C2]]
; GFX6: [[SMIN6:%[0-9]+]]:_(s32) = G_SMIN [[SHL6]], [[C3]]		; GFX6: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; GFX6: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[SMIN6]]		; GFX6: [[COPY10:%[0-9]+]]:_(s32) = COPY [[SMIN]](s32)
; GFX6: [[SMAX7:%[0-9]+]]:_(s32) = G_SMAX [[SUB7]], [[SHL7]]		; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
; GFX6: [[SMIN7:%[0-9]+]]:_(s32) = G_SMIN [[SMAX7]], [[SUB6]]		; GFX6: [[COPY11:%[0-9]+]]:_(s32) = COPY [[SMIN1]](s32)
; GFX6: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[SHL6]], [[SMIN7]]		; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
; GFX6: [[ASHR3:%[0-9]+]]:_(s32) = G_ASHR [[ADD3]], [[C]](s32)		; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX6: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535		; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX6: [[COPY10:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C4]]
; GFX6: [[COPY11:%[0-9]+]]:_(s32) = COPY [[ASHR1]](s32)
; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C4]]
; GFX6: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL8]]
; GFX6: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)		; GFX6: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX6: [[COPY12:%[0-9]+]]:_(s32) = COPY [[ASHR2]](s32)		; GFX6: [[COPY12:%[0-9]+]]:_(s32) = COPY [[SMIN2]](s32)
; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C4]]		; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
; GFX6: [[COPY13:%[0-9]+]]:_(s32) = COPY [[ASHR3]](s32)		; GFX6: [[COPY13:%[0-9]+]]:_(s32) = COPY [[SMIN3]](s32)
; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C4]]		; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
; GFX6: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)		; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; GFX6: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL9]]		; GFX6: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX6: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)		; GFX6: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; GFX6: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)		; GFX6: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
; GFX6: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)		; GFX6: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
; GFX8-LABEL: name: saddsat_v4s16		; GFX8-LABEL: name: saddsat_v4s16
; GFX8: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1		; GFX8: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
; GFX8: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3		; GFX8: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
; GFX8: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)		; GFX8: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
; GFX8: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>)		; GFX8: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>)
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llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubsat.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py		# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -global-isel-abort=0 -march=amdgcn -mcpu=tahiti -run-pass=legalizer %s -o - \| FileCheck -check-prefix=GFX6 %s		# RUN: llc -global-isel-abort=0 -march=amdgcn -mcpu=tahiti -run-pass=legalizer %s -o - \| FileCheck -check-prefix=GFX6 %s
# RUN: llc -global-isel-abort=0 -march=amdgcn -mcpu=fiji -run-pass=legalizer %s -o - \| FileCheck -check-prefix=GFX8 %s		# RUN: llc -global-isel-abort=0 -march=amdgcn -mcpu=fiji -run-pass=legalizer %s -o - \| FileCheck -check-prefix=GFX8 %s
# RUN: llc -global-isel-abort=0 -march=amdgcn -mcpu=gfx900 -run-pass=legalizer %s -o - \| FileCheck -check-prefix=GFX9 %s		# RUN: llc -global-isel-abort=0 -march=amdgcn -mcpu=gfx900 -run-pass=legalizer %s -o - \| FileCheck -check-prefix=GFX9 %s

---		---
name: ssubsat_s7		name: ssubsat_s7
body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0, $vgpr1		liveins: $vgpr0, $vgpr1

; GFX6-LABEL: name: ssubsat_s7		; GFX6-LABEL: name: ssubsat_s7
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0		; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1		; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
		; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 7
; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 25		; GFX6: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 7
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)		; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)		; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -64
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647		; GFX6: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[SUB]], [[C]]
; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648		; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
; GFX6: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1		; GFX6: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SMAX]], [[C1]]
; GFX6: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[SHL]], [[C3]]		; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SMIN]](s32)
; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SMAX]], [[C1]]
; GFX6: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SHL]], [[C3]]
; GFX6: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[SMIN]], [[C2]]
; GFX6: [[SMAX1:%[0-9]+]]:_(s32) = G_SMAX [[SUB]], [[SHL1]]
; GFX6: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN [[SMAX1]], [[SUB1]]
; GFX6: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SHL]], [[SMIN1]]
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SUB2]], [[C]](s32)
; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
; GFX6: $vgpr0 = COPY [[COPY4]](s32)		; GFX6: $vgpr0 = COPY [[COPY4]](s32)
; GFX8-LABEL: name: ssubsat_s7		; GFX8-LABEL: name: ssubsat_s7
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1		; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)		; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX8: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)		; GFX8: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX8: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 9		; GFX8: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 9
; GFX8: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16)		; GFX8: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16)
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liveins: $vgpr0, $vgpr1		liveins: $vgpr0, $vgpr1

; GFX6-LABEL: name: ssubsat_s8		; GFX6-LABEL: name: ssubsat_s8
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0		; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1		; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
		; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 8
; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24		; GFX6: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 8
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)		; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)		; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -128
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647		; GFX6: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[SUB]], [[C]]
; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648		; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
; GFX6: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1		; GFX6: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SMAX]], [[C1]]
; GFX6: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[SHL]], [[C3]]		; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SMIN]](s32)
; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SMAX]], [[C1]]
; GFX6: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SHL]], [[C3]]
; GFX6: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[SMIN]], [[C2]]
; GFX6: [[SMAX1:%[0-9]+]]:_(s32) = G_SMAX [[SUB]], [[SHL1]]
; GFX6: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN [[SMAX1]], [[SUB1]]
; GFX6: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SHL]], [[SMIN1]]
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SUB2]], [[C]](s32)
; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
; GFX6: $vgpr0 = COPY [[COPY4]](s32)		; GFX6: $vgpr0 = COPY [[COPY4]](s32)
; GFX8-LABEL: name: ssubsat_s8		; GFX8-LABEL: name: ssubsat_s8
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1		; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)		; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX8: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)		; GFX8: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX8: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 8		; GFX8: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; GFX8: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16)		; GFX8: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16)
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; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16		; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32)		; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32)
; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24		; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX6: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)		; GFX6: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
; GFX6: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32)		; GFX6: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32)
; GFX6: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C1]](s32)		; GFX6: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C1]](s32)
; GFX6: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)		; GFX6: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
		; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 8
; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C2]](s32)		; GFX6: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 8
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C2]](s32)		; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX6: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647		; GFX6: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -128
; GFX6: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648		; GFX6: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[SUB]], [[C3]]
; GFX6: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1		; GFX6: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
; GFX6: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[SHL]], [[C5]]		; GFX6: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SMAX]], [[C4]]
; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SMAX]], [[C3]]
; GFX6: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SHL]], [[C5]]
; GFX6: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[SMIN]], [[C4]]
; GFX6: [[SMAX1:%[0-9]+]]:_(s32) = G_SMAX [[SUB]], [[SHL1]]
; GFX6: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN [[SMAX1]], [[SUB1]]
; GFX6: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SHL]], [[SMIN1]]
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SUB2]], [[C2]](s32)
; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)		; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
		; GFX6: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 8
; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)		; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C2]](s32)		; GFX6: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 8
; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C2]](s32)		; GFX6: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[SEXT_INREG2]], [[SEXT_INREG3]]
; GFX6: [[SMAX2:%[0-9]+]]:_(s32) = G_SMAX [[SHL2]], [[C5]]		; GFX6: [[SMAX1:%[0-9]+]]:_(s32) = G_SMAX [[SUB1]], [[C3]]
; GFX6: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SMAX2]], [[C3]]		; GFX6: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN [[SMAX1]], [[C4]]
; GFX6: [[SMIN2:%[0-9]+]]:_(s32) = G_SMIN [[SHL2]], [[C5]]		; GFX6: [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; GFX6: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[SMIN2]], [[C4]]		; GFX6: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SMIN]](s32)
; GFX6: [[SMAX3:%[0-9]+]]:_(s32) = G_SMAX [[SUB3]], [[SHL3]]		; GFX6: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C5]]
; GFX6: [[SMIN3:%[0-9]+]]:_(s32) = G_SMIN [[SMAX3]], [[SUB4]]
; GFX6: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[SHL2]], [[SMIN3]]
; GFX6: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SUB5]], [[C2]](s32)
; GFX6: [[C6:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; GFX6: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ASHR]](s32)
; GFX6: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C6]]
; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C]](s32)		; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX6: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 255		; GFX6: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ASHR1]](s32)		; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SMIN1]](s32)
; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C7]]		; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C6]]
; GFX6: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY6]](s32)		; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY6]](s32)
; GFX6: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL4]](s32)		; GFX6: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; GFX6: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]		; GFX6: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; GFX6: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)		; GFX6: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; GFX6: $vgpr0 = COPY [[ANYEXT]](s32)		; GFX6: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX8-LABEL: name: ssubsat_v2s8		; GFX8-LABEL: name: ssubsat_v2s8
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1		; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8		; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX8: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)		; GFX8: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
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liveins: $vgpr0, $vgpr1		liveins: $vgpr0, $vgpr1

; GFX6-LABEL: name: ssubsat_s16		; GFX6-LABEL: name: ssubsat_s16
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0		; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1		; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
		; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16		; GFX6: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)		; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)		; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647		; GFX6: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[SUB]], [[C]]
; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648		; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767
; GFX6: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1		; GFX6: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SMAX]], [[C1]]
; GFX6: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[SHL]], [[C3]]		; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SMIN]](s32)
; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SMAX]], [[C1]]
; GFX6: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SHL]], [[C3]]
; GFX6: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[SMIN]], [[C2]]
; GFX6: [[SMAX1:%[0-9]+]]:_(s32) = G_SMAX [[SUB]], [[SHL1]]
; GFX6: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN [[SMAX1]], [[SUB1]]
; GFX6: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SHL]], [[SMIN1]]
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SUB2]], [[C]](s32)
; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
; GFX6: $vgpr0 = COPY [[COPY4]](s32)		; GFX6: $vgpr0 = COPY [[COPY4]](s32)
; GFX8-LABEL: name: ssubsat_s16		; GFX8-LABEL: name: ssubsat_s16
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1		; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)		; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX8: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)		; GFX8: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX8: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767		; GFX8: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 32767
; GFX8: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768		; GFX8: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 -32768
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; GFX6: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0		; GFX6: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1		; GFX6: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
; GFX6: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)		; GFX6: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16		; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)		; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX6: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)		; GFX6: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)		; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)		; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
		; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)		; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)		; GFX6: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)		; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647		; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768
; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648		; GFX6: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[SUB]], [[C1]]
; GFX6: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1		; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767
; GFX6: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[SHL]], [[C3]]		; GFX6: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SMAX]], [[C2]]
; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SMAX]], [[C1]]
; GFX6: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SHL]], [[C3]]
; GFX6: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[SMIN]], [[C2]]
; GFX6: [[SMAX1:%[0-9]+]]:_(s32) = G_SMAX [[SUB]], [[SHL1]]
; GFX6: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN [[SMAX1]], [[SUB1]]
; GFX6: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SHL]], [[SMIN1]]
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SUB2]], [[C]](s32)
; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)		; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
		; GFX6: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 16
; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)		; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)		; GFX6: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 16
; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C]](s32)		; GFX6: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[SEXT_INREG2]], [[SEXT_INREG3]]
; GFX6: [[SMAX2:%[0-9]+]]:_(s32) = G_SMAX [[SHL2]], [[C3]]		; GFX6: [[SMAX1:%[0-9]+]]:_(s32) = G_SMAX [[SUB1]], [[C1]]
; GFX6: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SMAX2]], [[C1]]		; GFX6: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN [[SMAX1]], [[C2]]
; GFX6: [[SMIN2:%[0-9]+]]:_(s32) = G_SMIN [[SHL2]], [[C3]]		; GFX6: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; GFX6: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[SMIN2]], [[C2]]		; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SMIN]](s32)
; GFX6: [[SMAX3:%[0-9]+]]:_(s32) = G_SMAX [[SUB3]], [[SHL3]]		; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C3]]
; GFX6: [[SMIN3:%[0-9]+]]:_(s32) = G_SMIN [[SMAX3]], [[SUB4]]		; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SMIN1]](s32)
; GFX6: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[SHL2]], [[SMIN3]]		; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
; GFX6: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SUB5]], [[C]](s32)		; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX6: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535		; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C4]]
; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ASHR1]](s32)
; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C4]]
; GFX6: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL4]]
; GFX6: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)		; GFX6: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX6: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)		; GFX6: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
; GFX8-LABEL: name: ssubsat_v2s16		; GFX8-LABEL: name: ssubsat_v2s16
; GFX8: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1		; GFX8: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
; GFX8: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)		; GFX8: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)		; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16		; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
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; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)		; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX6: [[INSERT1:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[UV1]](<3 x s16>), 0		; GFX6: [[INSERT1:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[UV1]](<3 x s16>), 0
; GFX6: [[UV4:%[0-9]+]]:_(<2 x s16>), [[UV5:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INSERT1]](<4 x s16>)		; GFX6: [[UV4:%[0-9]+]]:_(<2 x s16>), [[UV5:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INSERT1]](<4 x s16>)
; GFX6: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV4]](<2 x s16>)		; GFX6: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV4]](<2 x s16>)
; GFX6: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)		; GFX6: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX6: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV5]](<2 x s16>)		; GFX6: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV5]](<2 x s16>)
; GFX6: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)		; GFX6: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)		; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
		; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)		; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)		; GFX6: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)		; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647		; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768
; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648		; GFX6: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[SUB]], [[C1]]
; GFX6: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1		; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767
; GFX6: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[SHL]], [[C3]]		; GFX6: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SMAX]], [[C2]]
; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SMAX]], [[C1]]
; GFX6: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SHL]], [[C3]]
; GFX6: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[SMIN]], [[C2]]
; GFX6: [[SMAX1:%[0-9]+]]:_(s32) = G_SMAX [[SUB]], [[SHL1]]
; GFX6: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN [[SMAX1]], [[SUB1]]
; GFX6: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SHL]], [[SMIN1]]
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SUB2]], [[C]](s32)
; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)		; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
		; GFX6: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)		; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)		; GFX6: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 16
; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)		; GFX6: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[SEXT_INREG2]], [[SEXT_INREG3]]
; GFX6: [[SMAX2:%[0-9]+]]:_(s32) = G_SMAX [[SHL2]], [[C3]]		; GFX6: [[SMAX1:%[0-9]+]]:_(s32) = G_SMAX [[SUB1]], [[C1]]
; GFX6: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SMAX2]], [[C1]]		; GFX6: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN [[SMAX1]], [[C2]]
; GFX6: [[SMIN2:%[0-9]+]]:_(s32) = G_SMIN [[SHL2]], [[C3]]
; GFX6: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[SMIN2]], [[C2]]
; GFX6: [[SMAX3:%[0-9]+]]:_(s32) = G_SMAX [[SUB3]], [[SHL3]]
; GFX6: [[SMIN3:%[0-9]+]]:_(s32) = G_SMIN [[SMAX3]], [[SUB4]]
; GFX6: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[SHL2]], [[SMIN3]]
; GFX6: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SUB5]], [[C]](s32)
; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)		; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
		; GFX6: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 16
; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)		; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
; GFX6: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C]](s32)		; GFX6: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY6]], 16
; GFX6: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[COPY6]], [[C]](s32)		; GFX6: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SEXT_INREG4]], [[SEXT_INREG5]]
; GFX6: [[SMAX4:%[0-9]+]]:_(s32) = G_SMAX [[SHL4]], [[C3]]		; GFX6: [[SMAX2:%[0-9]+]]:_(s32) = G_SMAX [[SUB2]], [[C1]]
; GFX6: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[SMAX4]], [[C1]]		; GFX6: [[SMIN2:%[0-9]+]]:_(s32) = G_SMIN [[SMAX2]], [[C2]]
; GFX6: [[SMIN4:%[0-9]+]]:_(s32) = G_SMIN [[SHL4]], [[C3]]		; GFX6: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; GFX6: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[SMIN4]], [[C2]]		; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SMIN]](s32)
; GFX6: [[SMAX5:%[0-9]+]]:_(s32) = G_SMAX [[SUB6]], [[SHL5]]		; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
; GFX6: [[SMIN5:%[0-9]+]]:_(s32) = G_SMIN [[SMAX5]], [[SUB7]]		; GFX6: [[COPY8:%[0-9]+]]:_(s32) = COPY [[SMIN1]](s32)
; GFX6: [[SUB8:%[0-9]+]]:_(s32) = G_SUB [[SHL4]], [[SMIN5]]		; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C3]]
; GFX6: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SUB8]], [[C]](s32)		; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX6: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535		; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C4]]
; GFX6: [[COPY8:%[0-9]+]]:_(s32) = COPY [[ASHR1]](s32)
; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C4]]
; GFX6: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL6]]
; GFX6: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)		; GFX6: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX6: [[COPY9:%[0-9]+]]:_(s32) = COPY [[ASHR2]](s32)		; GFX6: [[COPY9:%[0-9]+]]:_(s32) = COPY [[SMIN2]](s32)
; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C4]]		; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
; GFX6: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 0		; GFX6: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX6: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[C5]], [[C]](s32)		; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C4]], [[C]](s32)
; GFX6: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL7]]		; GFX6: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX6: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)		; GFX6: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; GFX6: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF		; GFX6: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
; GFX6: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>), [[DEF1]](<2 x s16>)		; GFX6: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>), [[DEF1]](<2 x s16>)
; GFX6: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<6 x s16>), 0		; GFX6: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<6 x s16>), 0
; GFX6: [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF		; GFX6: [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
; GFX6: [[CONCAT_VECTORS1:%[0-9]+]]:_(<12 x s16>) = G_CONCAT_VECTORS [[DEF2]](<4 x s16>), [[DEF]](<4 x s16>), [[DEF]](<4 x s16>)		; GFX6: [[CONCAT_VECTORS1:%[0-9]+]]:_(<12 x s16>) = G_CONCAT_VECTORS [[DEF2]](<4 x s16>), [[DEF]](<4 x s16>), [[DEF]](<4 x s16>)
; GFX6: [[UV6:%[0-9]+]]:_(<3 x s16>), [[UV7:%[0-9]+]]:_(<3 x s16>), [[UV8:%[0-9]+]]:_(<3 x s16>), [[UV9:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS1]](<12 x s16>)		; GFX6: [[UV6:%[0-9]+]]:_(<3 x s16>), [[UV7:%[0-9]+]]:_(<3 x s16>), [[UV8:%[0-9]+]]:_(<3 x s16>), [[UV9:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS1]](<12 x s16>)
; GFX6: [[INSERT2:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[EXTRACT]](<3 x s16>), 0		; GFX6: [[INSERT2:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[EXTRACT]](<3 x s16>), 0
; GFX6: [[UV10:%[0-9]+]]:_(<2 x s16>), [[UV11:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INSERT2]](<4 x s16>)		; GFX6: [[UV10:%[0-9]+]]:_(<2 x s16>), [[UV11:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INSERT2]](<4 x s16>)
; GFX6: [[BITCAST6:%[0-9]+]]:_(s32) = G_BITCAST [[UV10]](<2 x s16>)		; GFX6: [[BITCAST6:%[0-9]+]]:_(s32) = G_BITCAST [[UV10]](<2 x s16>)
; GFX6: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST6]], [[C]](s32)		; GFX6: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST6]], [[C]](s32)
; GFX6: [[BITCAST7:%[0-9]+]]:_(s32) = G_BITCAST [[UV11]](<2 x s16>)		; GFX6: [[BITCAST7:%[0-9]+]]:_(s32) = G_BITCAST [[UV11]](<2 x s16>)
; GFX6: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST7]], [[C]](s32)		; GFX6: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST7]], [[C]](s32)
; GFX6: [[INSERT3:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[UV6]](<3 x s16>), 0		; GFX6: [[INSERT3:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[UV6]](<3 x s16>), 0
; GFX6: [[UV12:%[0-9]+]]:_(<2 x s16>), [[UV13:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INSERT3]](<4 x s16>)		; GFX6: [[UV12:%[0-9]+]]:_(<2 x s16>), [[UV13:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INSERT3]](<4 x s16>)
; GFX6: [[BITCAST8:%[0-9]+]]:_(s32) = G_BITCAST [[UV12]](<2 x s16>)		; GFX6: [[BITCAST8:%[0-9]+]]:_(s32) = G_BITCAST [[UV12]](<2 x s16>)
; GFX6: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST8]], [[C]](s32)		; GFX6: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST8]], [[C]](s32)
; GFX6: [[BITCAST9:%[0-9]+]]:_(s32) = G_BITCAST [[UV13]](<2 x s16>)		; GFX6: [[BITCAST9:%[0-9]+]]:_(s32) = G_BITCAST [[UV13]](<2 x s16>)
; GFX6: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST9]], [[C]](s32)		; GFX6: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST9]], [[C]](s32)
; GFX6: [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST6]](s32)		; GFX6: [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST6]](s32)
; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C4]]		; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
; GFX6: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)		; GFX6: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
; GFX6: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C4]]		; GFX6: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
; GFX6: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C]](s32)		; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C]](s32)
; GFX6: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND3]], [[SHL8]]		; GFX6: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND3]], [[SHL2]]
; GFX6: [[BITCAST10:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)		; GFX6: [[BITCAST10:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; GFX6: [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST7]](s32)		; GFX6: [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST7]](s32)
; GFX6: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C4]]		; GFX6: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
; GFX6: [[COPY13:%[0-9]+]]:_(s32) = COPY [[BITCAST8]](s32)		; GFX6: [[COPY13:%[0-9]+]]:_(s32) = COPY [[BITCAST8]](s32)
; GFX6: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C4]]		; GFX6: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
; GFX6: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C]](s32)		; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C]](s32)
; GFX6: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND5]], [[SHL9]]		; GFX6: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND5]], [[SHL3]]
; GFX6: [[BITCAST11:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)		; GFX6: [[BITCAST11:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
; GFX6: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)		; GFX6: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
; GFX6: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C4]]		; GFX6: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C3]]
; GFX6: [[COPY15:%[0-9]+]]:_(s32) = COPY [[BITCAST9]](s32)		; GFX6: [[COPY15:%[0-9]+]]:_(s32) = COPY [[BITCAST9]](s32)
; GFX6: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C4]]		; GFX6: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
; GFX6: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C]](s32)		; GFX6: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C]](s32)
; GFX6: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND7]], [[SHL10]]		; GFX6: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND7]], [[SHL4]]
; GFX6: [[BITCAST12:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)		; GFX6: [[BITCAST12:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
; GFX6: [[CONCAT_VECTORS2:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST10]](<2 x s16>), [[BITCAST11]](<2 x s16>), [[BITCAST12]](<2 x s16>)		; GFX6: [[CONCAT_VECTORS2:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST10]](<2 x s16>), [[BITCAST11]](<2 x s16>), [[BITCAST12]](<2 x s16>)
; GFX6: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS2]](<6 x s16>)		; GFX6: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS2]](<6 x s16>)
; GFX8-LABEL: name: ssubsat_v3s16		; GFX8-LABEL: name: ssubsat_v3s16
; GFX8: [[COPY:%[0-9]+]]:_(<6 x s16>) = COPY $vgpr0_vgpr1_vgpr2		; GFX8: [[COPY:%[0-9]+]]:_(<6 x s16>) = COPY $vgpr0_vgpr1_vgpr2
; GFX8: [[UV:%[0-9]+]]:_(<3 x s16>), [[UV1:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[COPY]](<6 x s16>)		; GFX8: [[UV:%[0-9]+]]:_(<3 x s16>), [[UV1:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[COPY]](<6 x s16>)
; GFX8: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF		; GFX8: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
; GFX8: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[UV]](<3 x s16>), 0		; GFX8: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[UV]](<3 x s16>), 0
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; GFX6: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)		; GFX6: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)		; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX6: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<4 x s16>)		; GFX6: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<4 x s16>)
; GFX6: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV2]](<2 x s16>)		; GFX6: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV2]](<2 x s16>)
; GFX6: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)		; GFX6: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX6: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)		; GFX6: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; GFX6: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)		; GFX6: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)		; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
		; GFX6: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)		; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)		; GFX6: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)		; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SEXT_INREG]], [[SEXT_INREG1]]
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2147483647		; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768
; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648		; GFX6: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[SUB]], [[C1]]
; GFX6: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1		; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767
; GFX6: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[SHL]], [[C3]]		; GFX6: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SMAX]], [[C2]]
; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SMAX]], [[C1]]
; GFX6: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SHL]], [[C3]]
; GFX6: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[SMIN]], [[C2]]
; GFX6: [[SMAX1:%[0-9]+]]:_(s32) = G_SMAX [[SUB]], [[SHL1]]
; GFX6: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN [[SMAX1]], [[SUB1]]
; GFX6: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SHL]], [[SMIN1]]
; GFX6: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SUB2]], [[C]](s32)
; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)		; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
		; GFX6: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 16
; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)		; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)		; GFX6: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 16
; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C]](s32)		; GFX6: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[SEXT_INREG2]], [[SEXT_INREG3]]
; GFX6: [[SMAX2:%[0-9]+]]:_(s32) = G_SMAX [[SHL2]], [[C3]]		; GFX6: [[SMAX1:%[0-9]+]]:_(s32) = G_SMAX [[SUB1]], [[C1]]
; GFX6: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SMAX2]], [[C1]]		; GFX6: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN [[SMAX1]], [[C2]]
; GFX6: [[SMIN2:%[0-9]+]]:_(s32) = G_SMIN [[SHL2]], [[C3]]
; GFX6: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[SMIN2]], [[C2]]
; GFX6: [[SMAX3:%[0-9]+]]:_(s32) = G_SMAX [[SUB3]], [[SHL3]]
; GFX6: [[SMIN3:%[0-9]+]]:_(s32) = G_SMIN [[SMAX3]], [[SUB4]]
; GFX6: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[SHL2]], [[SMIN3]]
; GFX6: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SUB5]], [[C]](s32)
; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)		; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
		; GFX6: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY6]], 16
; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)		; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
; GFX6: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[COPY6]], [[C]](s32)		; GFX6: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY7]], 16
; GFX6: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[COPY7]], [[C]](s32)		; GFX6: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SEXT_INREG4]], [[SEXT_INREG5]]
; GFX6: [[SMAX4:%[0-9]+]]:_(s32) = G_SMAX [[SHL4]], [[C3]]		; GFX6: [[SMAX2:%[0-9]+]]:_(s32) = G_SMAX [[SUB2]], [[C1]]
; GFX6: [[SUB6:%[0-9]+]]:_(s32) = G_SUB [[SMAX4]], [[C1]]		; GFX6: [[SMIN2:%[0-9]+]]:_(s32) = G_SMIN [[SMAX2]], [[C2]]
; GFX6: [[SMIN4:%[0-9]+]]:_(s32) = G_SMIN [[SHL4]], [[C3]]
; GFX6: [[SUB7:%[0-9]+]]:_(s32) = G_SUB [[SMIN4]], [[C2]]
; GFX6: [[SMAX5:%[0-9]+]]:_(s32) = G_SMAX [[SUB6]], [[SHL5]]
; GFX6: [[SMIN5:%[0-9]+]]:_(s32) = G_SMIN [[SMAX5]], [[SUB7]]
; GFX6: [[SUB8:%[0-9]+]]:_(s32) = G_SUB [[SHL4]], [[SMIN5]]
; GFX6: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SUB8]], [[C]](s32)
; GFX6: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)		; GFX6: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
		; GFX6: [[SEXT_INREG6:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY8]], 16
; GFX6: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)		; GFX6: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
; GFX6: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[COPY8]], [[C]](s32)		; GFX6: [[SEXT_INREG7:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY9]], 16
; GFX6: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[COPY9]], [[C]](s32)		; GFX6: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SEXT_INREG6]], [[SEXT_INREG7]]
; GFX6: [[SMAX6:%[0-9]+]]:_(s32) = G_SMAX [[SHL6]], [[C3]]		; GFX6: [[SMAX3:%[0-9]+]]:_(s32) = G_SMAX [[SUB3]], [[C1]]
; GFX6: [[SUB9:%[0-9]+]]:_(s32) = G_SUB [[SMAX6]], [[C1]]		; GFX6: [[SMIN3:%[0-9]+]]:_(s32) = G_SMIN [[SMAX3]], [[C2]]
; GFX6: [[SMIN6:%[0-9]+]]:_(s32) = G_SMIN [[SHL6]], [[C3]]		; GFX6: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; GFX6: [[SUB10:%[0-9]+]]:_(s32) = G_SUB [[SMIN6]], [[C2]]		; GFX6: [[COPY10:%[0-9]+]]:_(s32) = COPY [[SMIN]](s32)
; GFX6: [[SMAX7:%[0-9]+]]:_(s32) = G_SMAX [[SUB9]], [[SHL7]]		; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C3]]
; GFX6: [[SMIN7:%[0-9]+]]:_(s32) = G_SMIN [[SMAX7]], [[SUB10]]		; GFX6: [[COPY11:%[0-9]+]]:_(s32) = COPY [[SMIN1]](s32)
; GFX6: [[SUB11:%[0-9]+]]:_(s32) = G_SUB [[SHL6]], [[SMIN7]]		; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
; GFX6: [[ASHR3:%[0-9]+]]:_(s32) = G_ASHR [[SUB11]], [[C]](s32)		; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX6: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535		; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; GFX6: [[COPY10:%[0-9]+]]:_(s32) = COPY [[ASHR]](s32)
; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C4]]
; GFX6: [[COPY11:%[0-9]+]]:_(s32) = COPY [[ASHR1]](s32)
; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C4]]
; GFX6: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL8]]
; GFX6: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)		; GFX6: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX6: [[COPY12:%[0-9]+]]:_(s32) = COPY [[ASHR2]](s32)		; GFX6: [[COPY12:%[0-9]+]]:_(s32) = COPY [[SMIN2]](s32)
; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C4]]		; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C3]]
; GFX6: [[COPY13:%[0-9]+]]:_(s32) = COPY [[ASHR3]](s32)		; GFX6: [[COPY13:%[0-9]+]]:_(s32) = COPY [[SMIN3]](s32)
; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C4]]		; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
; GFX6: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)		; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; GFX6: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL9]]		; GFX6: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; GFX6: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)		; GFX6: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; GFX6: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)		; GFX6: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
; GFX6: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)		; GFX6: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
; GFX8-LABEL: name: ssubsat_v4s16		; GFX8-LABEL: name: ssubsat_v4s16
; GFX8: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1		; GFX8: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
; GFX8: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3		; GFX8: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
; GFX8: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)		; GFX8: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
; GFX8: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>)		; GFX8: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>)
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llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddsat.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py		# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -global-isel-abort=0 -march=amdgcn -mcpu=tahiti -run-pass=legalizer %s -o - \| FileCheck -check-prefix=GFX6 %s		# RUN: llc -global-isel-abort=0 -march=amdgcn -mcpu=tahiti -run-pass=legalizer %s -o - \| FileCheck -check-prefix=GFX6 %s
# RUN: llc -global-isel-abort=0 -march=amdgcn -mcpu=fiji -run-pass=legalizer %s -o - \| FileCheck -check-prefix=GFX8 %s		# RUN: llc -global-isel-abort=0 -march=amdgcn -mcpu=fiji -run-pass=legalizer %s -o - \| FileCheck -check-prefix=GFX8 %s
# RUN: llc -global-isel-abort=0 -march=amdgcn -mcpu=gfx900 -run-pass=legalizer %s -o - \| FileCheck -check-prefix=GFX9 %s		# RUN: llc -global-isel-abort=0 -march=amdgcn -mcpu=gfx900 -run-pass=legalizer %s -o - \| FileCheck -check-prefix=GFX9 %s

---		---
name: uaddsat_s7		name: uaddsat_s7
body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0, $vgpr1		liveins: $vgpr0, $vgpr1

; GFX6-LABEL: name: uaddsat_s7		; GFX6-LABEL: name: uaddsat_s7
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0		; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1		; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
		; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
		; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 25		; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)		; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)		; GFX6: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[ADD]], [[C]]
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1		; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UMIN]](s32)
; GFX6: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[SHL]], [[C1]]
; GFX6: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[XOR]], [[SHL1]]
; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SHL]], [[UMIN]]
; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[ADD]], [[C]](s32)
; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; GFX6: $vgpr0 = COPY [[COPY4]](s32)		; GFX6: $vgpr0 = COPY [[COPY4]](s32)
; GFX8-LABEL: name: uaddsat_s7		; GFX8-LABEL: name: uaddsat_s7
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1		; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)		; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX8: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)		; GFX8: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX8: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 9		; GFX8: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 9
; GFX8: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16)		; GFX8: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16)
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name: uaddsat_s8		name: uaddsat_s8
body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0, $vgpr1		liveins: $vgpr0, $vgpr1

; GFX6-LABEL: name: uaddsat_s8		; GFX6-LABEL: name: uaddsat_s8
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0		; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1		; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
		; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
		; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24		; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)		; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)		; GFX6: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[ADD]], [[C]]
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1		; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UMIN]](s32)
; GFX6: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[SHL]], [[C1]]
; GFX6: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[XOR]], [[SHL1]]
; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SHL]], [[UMIN]]
; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[ADD]], [[C]](s32)
; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; GFX6: $vgpr0 = COPY [[COPY4]](s32)		; GFX6: $vgpr0 = COPY [[COPY4]](s32)
; GFX8-LABEL: name: uaddsat_s8		; GFX8-LABEL: name: uaddsat_s8
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1		; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)		; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX8: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)		; GFX8: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX8: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 8		; GFX8: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; GFX8: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16)		; GFX8: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16)
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; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)		; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16		; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32)		; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32)
; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24		; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX6: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)		; GFX6: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
; GFX6: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32)		; GFX6: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32)
; GFX6: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C1]](s32)		; GFX6: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C1]](s32)
; GFX6: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)		; GFX6: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
		; GFX6: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
		; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C2]](s32)		; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C2]](s32)		; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
; GFX6: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1		; GFX6: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[ADD]], [[C3]]
; GFX6: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[SHL]], [[C3]]
; GFX6: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[XOR]], [[SHL1]]
; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SHL]], [[UMIN]]
; GFX6: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[ADD]], [[C2]](s32)
; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)		; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
		; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)		; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C2]](s32)		; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C2]](s32)		; GFX6: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[AND2]], [[AND3]]
; GFX6: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[SHL2]], [[C3]]		; GFX6: [[UMIN1:%[0-9]+]]:_(s32) = G_UMIN [[ADD1]], [[C3]]
; GFX6: [[UMIN1:%[0-9]+]]:_(s32) = G_UMIN [[XOR1]], [[SHL3]]
; GFX6: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[SHL2]], [[UMIN1]]
; GFX6: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[ADD1]], [[C2]](s32)
; GFX6: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 255		; GFX6: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; GFX6: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR6]](s32)		; GFX6: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UMIN]](s32)
; GFX6: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C4]]		; GFX6: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C4]]
; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C]](s32)		; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX6: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 255		; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[UMIN1]](s32)
; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)		; GFX6: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C5]]		; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY6]](s32)
; GFX6: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY6]](s32)		; GFX6: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; GFX6: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL4]](s32)		; GFX6: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC1]]
; GFX6: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; GFX6: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)		; GFX6: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; GFX6: $vgpr0 = COPY [[ANYEXT]](s32)		; GFX6: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX8-LABEL: name: uaddsat_v2s8		; GFX8-LABEL: name: uaddsat_v2s8
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1		; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8		; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX8: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)		; GFX8: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
; GFX8: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16		; GFX8: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
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name: uaddsat_s16		name: uaddsat_s16
body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0, $vgpr1		liveins: $vgpr0, $vgpr1

; GFX6-LABEL: name: uaddsat_s16		; GFX6-LABEL: name: uaddsat_s16
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0		; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1		; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
		; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
		; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16		; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)		; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)		; GFX6: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[ADD]], [[C]]
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1		; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UMIN]](s32)
; GFX6: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[SHL]], [[C1]]
; GFX6: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[XOR]], [[SHL1]]
; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SHL]], [[UMIN]]
; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[ADD]], [[C]](s32)
; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; GFX6: $vgpr0 = COPY [[COPY4]](s32)		; GFX6: $vgpr0 = COPY [[COPY4]](s32)
; GFX8-LABEL: name: uaddsat_s16		; GFX8-LABEL: name: uaddsat_s16
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1		; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)		; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX8: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)		; GFX8: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX8: [[UADDSAT:%[0-9]+]]:_(s16) = G_UADDSAT [[TRUNC]], [[TRUNC1]]		; GFX8: [[UADDSAT:%[0-9]+]]:_(s16) = G_UADDSAT [[TRUNC]], [[TRUNC1]]
; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UADDSAT]](s16)		; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UADDSAT]](s16)
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; GFX6-LABEL: name: uaddsat_v2s16		; GFX6-LABEL: name: uaddsat_v2s16
; GFX6: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0		; GFX6: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1		; GFX6: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
; GFX6: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)		; GFX6: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16		; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)		; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX6: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)		; GFX6: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)		; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
		; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)		; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
		; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)		; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)		; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)		; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1		; GFX6: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[ADD]], [[C1]]
; GFX6: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[SHL]], [[C1]]
; GFX6: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[XOR]], [[SHL1]]
; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SHL]], [[UMIN]]
; GFX6: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[ADD]], [[C]](s32)
; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)		; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
		; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)		; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)		; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C]](s32)		; GFX6: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[AND2]], [[AND3]]
; GFX6: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[SHL2]], [[C1]]		; GFX6: [[UMIN1:%[0-9]+]]:_(s32) = G_UMIN [[ADD1]], [[C1]]
; GFX6: [[UMIN1:%[0-9]+]]:_(s32) = G_UMIN [[XOR1]], [[SHL3]]		; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UMIN]](s32)
; GFX6: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[SHL2]], [[UMIN1]]		; GFX6: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
; GFX6: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[ADD1]], [[C]](s32)		; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[UMIN1]](s32)
; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535		; GFX6: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)		; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C2]]		; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL]]
; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C2]]
; GFX6: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL4]]
; GFX6: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)		; GFX6: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX6: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)		; GFX6: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
; GFX8-LABEL: name: uaddsat_v2s16		; GFX8-LABEL: name: uaddsat_v2s16
; GFX8: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1		; GFX8: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
; GFX8: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)		; GFX8: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)		; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16		; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
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; GFX6: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)		; GFX6: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)		; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX6: [[INSERT1:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[UV1]](<3 x s16>), 0		; GFX6: [[INSERT1:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[UV1]](<3 x s16>), 0
; GFX6: [[UV4:%[0-9]+]]:_(<2 x s16>), [[UV5:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INSERT1]](<4 x s16>)		; GFX6: [[UV4:%[0-9]+]]:_(<2 x s16>), [[UV5:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INSERT1]](<4 x s16>)
; GFX6: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV4]](<2 x s16>)		; GFX6: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV4]](<2 x s16>)
; GFX6: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)		; GFX6: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX6: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV5]](<2 x s16>)		; GFX6: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV5]](<2 x s16>)
; GFX6: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)		; GFX6: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
		; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)		; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
		; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)		; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)		; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)		; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1		; GFX6: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[ADD]], [[C1]]
; GFX6: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[SHL]], [[C1]]
; GFX6: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[XOR]], [[SHL1]]
; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SHL]], [[UMIN]]
; GFX6: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[ADD]], [[C]](s32)
; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)		; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
		; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)		; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)		; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)		; GFX6: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[AND2]], [[AND3]]
; GFX6: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[SHL2]], [[C1]]		; GFX6: [[UMIN1:%[0-9]+]]:_(s32) = G_UMIN [[ADD1]], [[C1]]
; GFX6: [[UMIN1:%[0-9]+]]:_(s32) = G_UMIN [[XOR1]], [[SHL3]]
; GFX6: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[SHL2]], [[UMIN1]]
; GFX6: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[ADD1]], [[C]](s32)
; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)		; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
		; GFX6: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)		; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
; GFX6: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C]](s32)		; GFX6: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
; GFX6: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[COPY6]], [[C]](s32)		; GFX6: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[AND4]], [[AND5]]
; GFX6: [[XOR2:%[0-9]+]]:_(s32) = G_XOR [[SHL4]], [[C1]]		; GFX6: [[UMIN2:%[0-9]+]]:_(s32) = G_UMIN [[ADD2]], [[C1]]
; GFX6: [[UMIN2:%[0-9]+]]:_(s32) = G_UMIN [[XOR2]], [[SHL5]]		; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[UMIN]](s32)
; GFX6: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[SHL4]], [[UMIN2]]		; GFX6: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
; GFX6: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[ADD2]], [[C]](s32)		; GFX6: [[COPY8:%[0-9]+]]:_(s32) = COPY [[UMIN1]](s32)
; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535		; GFX6: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)		; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C]](s32)
; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C2]]		; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL]]
; GFX6: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C2]]
; GFX6: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL6]]
; GFX6: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)		; GFX6: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX6: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)		; GFX6: [[COPY9:%[0-9]+]]:_(s32) = COPY [[UMIN2]](s32)
; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C2]]		; GFX6: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C1]]
; GFX6: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0		; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX6: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[C3]], [[C]](s32)		; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C]](s32)
; GFX6: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL7]]		; GFX6: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL1]]
; GFX6: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)		; GFX6: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; GFX6: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF		; GFX6: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
; GFX6: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>), [[DEF1]](<2 x s16>)		; GFX6: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>), [[DEF1]](<2 x s16>)
; GFX6: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<6 x s16>), 0		; GFX6: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<6 x s16>), 0
; GFX6: [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF		; GFX6: [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
; GFX6: [[CONCAT_VECTORS1:%[0-9]+]]:_(<12 x s16>) = G_CONCAT_VECTORS [[DEF2]](<4 x s16>), [[DEF]](<4 x s16>), [[DEF]](<4 x s16>)		; GFX6: [[CONCAT_VECTORS1:%[0-9]+]]:_(<12 x s16>) = G_CONCAT_VECTORS [[DEF2]](<4 x s16>), [[DEF]](<4 x s16>), [[DEF]](<4 x s16>)
; GFX6: [[UV6:%[0-9]+]]:_(<3 x s16>), [[UV7:%[0-9]+]]:_(<3 x s16>), [[UV8:%[0-9]+]]:_(<3 x s16>), [[UV9:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS1]](<12 x s16>)		; GFX6: [[UV6:%[0-9]+]]:_(<3 x s16>), [[UV7:%[0-9]+]]:_(<3 x s16>), [[UV8:%[0-9]+]]:_(<3 x s16>), [[UV9:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS1]](<12 x s16>)
; GFX6: [[INSERT2:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[EXTRACT]](<3 x s16>), 0		; GFX6: [[INSERT2:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[EXTRACT]](<3 x s16>), 0
; GFX6: [[UV10:%[0-9]+]]:_(<2 x s16>), [[UV11:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INSERT2]](<4 x s16>)		; GFX6: [[UV10:%[0-9]+]]:_(<2 x s16>), [[UV11:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INSERT2]](<4 x s16>)
; GFX6: [[BITCAST6:%[0-9]+]]:_(s32) = G_BITCAST [[UV10]](<2 x s16>)		; GFX6: [[BITCAST6:%[0-9]+]]:_(s32) = G_BITCAST [[UV10]](<2 x s16>)
; GFX6: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST6]], [[C]](s32)		; GFX6: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST6]], [[C]](s32)
; GFX6: [[BITCAST7:%[0-9]+]]:_(s32) = G_BITCAST [[UV11]](<2 x s16>)		; GFX6: [[BITCAST7:%[0-9]+]]:_(s32) = G_BITCAST [[UV11]](<2 x s16>)
; GFX6: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST7]], [[C]](s32)		; GFX6: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST7]], [[C]](s32)
; GFX6: [[INSERT3:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[UV6]](<3 x s16>), 0		; GFX6: [[INSERT3:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[UV6]](<3 x s16>), 0
; GFX6: [[UV12:%[0-9]+]]:_(<2 x s16>), [[UV13:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INSERT3]](<4 x s16>)		; GFX6: [[UV12:%[0-9]+]]:_(<2 x s16>), [[UV13:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INSERT3]](<4 x s16>)
; GFX6: [[BITCAST8:%[0-9]+]]:_(s32) = G_BITCAST [[UV12]](<2 x s16>)		; GFX6: [[BITCAST8:%[0-9]+]]:_(s32) = G_BITCAST [[UV12]](<2 x s16>)
; GFX6: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST8]], [[C]](s32)		; GFX6: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST8]], [[C]](s32)
; GFX6: [[BITCAST9:%[0-9]+]]:_(s32) = G_BITCAST [[UV13]](<2 x s16>)		; GFX6: [[BITCAST9:%[0-9]+]]:_(s32) = G_BITCAST [[UV13]](<2 x s16>)
; GFX6: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST9]], [[C]](s32)		; GFX6: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST9]], [[C]](s32)
; GFX6: [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST6]](s32)		; GFX6: [[COPY10:%[0-9]+]]:_(s32) = COPY [[BITCAST6]](s32)
; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C2]]		; GFX6: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
; GFX6: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)		; GFX6: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
; GFX6: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C2]]		; GFX6: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
; GFX6: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[C]](s32)		; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[C]](s32)
; GFX6: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND3]], [[SHL8]]		; GFX6: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND9]], [[SHL2]]
; GFX6: [[BITCAST10:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)		; GFX6: [[BITCAST10:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; GFX6: [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST7]](s32)		; GFX6: [[COPY12:%[0-9]+]]:_(s32) = COPY [[BITCAST7]](s32)
; GFX6: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C2]]		; GFX6: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
; GFX6: [[COPY13:%[0-9]+]]:_(s32) = COPY [[BITCAST8]](s32)		; GFX6: [[COPY13:%[0-9]+]]:_(s32) = COPY [[BITCAST8]](s32)
; GFX6: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C2]]		; GFX6: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C1]]
; GFX6: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C]](s32)		; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND12]], [[C]](s32)
; GFX6: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND5]], [[SHL9]]		; GFX6: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND11]], [[SHL3]]
; GFX6: [[BITCAST11:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)		; GFX6: [[BITCAST11:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR3]](s32)
; GFX6: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)		; GFX6: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
; GFX6: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C2]]		; GFX6: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C1]]
; GFX6: [[COPY15:%[0-9]+]]:_(s32) = COPY [[BITCAST9]](s32)		; GFX6: [[COPY15:%[0-9]+]]:_(s32) = COPY [[BITCAST9]](s32)
; GFX6: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C2]]		; GFX6: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C1]]
; GFX6: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[C]](s32)		; GFX6: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[C]](s32)
; GFX6: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND7]], [[SHL10]]		; GFX6: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND13]], [[SHL4]]
; GFX6: [[BITCAST12:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)		; GFX6: [[BITCAST12:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR4]](s32)
; GFX6: [[CONCAT_VECTORS2:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST10]](<2 x s16>), [[BITCAST11]](<2 x s16>), [[BITCAST12]](<2 x s16>)		; GFX6: [[CONCAT_VECTORS2:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST10]](<2 x s16>), [[BITCAST11]](<2 x s16>), [[BITCAST12]](<2 x s16>)
; GFX6: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS2]](<6 x s16>)		; GFX6: $vgpr0_vgpr1_vgpr2 = COPY [[CONCAT_VECTORS2]](<6 x s16>)
; GFX8-LABEL: name: uaddsat_v3s16		; GFX8-LABEL: name: uaddsat_v3s16
; GFX8: [[COPY:%[0-9]+]]:_(<6 x s16>) = COPY $vgpr0_vgpr1_vgpr2		; GFX8: [[COPY:%[0-9]+]]:_(<6 x s16>) = COPY $vgpr0_vgpr1_vgpr2
; GFX8: [[UV:%[0-9]+]]:_(<3 x s16>), [[UV1:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[COPY]](<6 x s16>)		; GFX8: [[UV:%[0-9]+]]:_(<3 x s16>), [[UV1:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[COPY]](<6 x s16>)
; GFX8: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF		; GFX8: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
; GFX8: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[UV]](<3 x s16>), 0		; GFX8: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[UV]](<3 x s16>), 0
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; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)		; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX6: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)		; GFX6: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)		; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX6: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<4 x s16>)		; GFX6: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<4 x s16>)
; GFX6: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV2]](<2 x s16>)		; GFX6: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV2]](<2 x s16>)
; GFX6: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)		; GFX6: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX6: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)		; GFX6: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; GFX6: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)		; GFX6: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
		; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)		; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
		; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)		; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)		; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)		; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1		; GFX6: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[ADD]], [[C1]]
; GFX6: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[SHL]], [[C1]]
; GFX6: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[XOR]], [[SHL1]]
; GFX6: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SHL]], [[UMIN]]
; GFX6: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[ADD]], [[C]](s32)
; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)		; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
		; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)		; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)		; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C]](s32)		; GFX6: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[AND2]], [[AND3]]
; GFX6: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[SHL2]], [[C1]]		; GFX6: [[UMIN1:%[0-9]+]]:_(s32) = G_UMIN [[ADD1]], [[C1]]
; GFX6: [[UMIN1:%[0-9]+]]:_(s32) = G_UMIN [[XOR1]], [[SHL3]]
; GFX6: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[SHL2]], [[UMIN1]]
; GFX6: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[ADD1]], [[C]](s32)
; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)		; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
		; GFX6: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)		; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
; GFX6: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[COPY6]], [[C]](s32)		; GFX6: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
; GFX6: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[COPY7]], [[C]](s32)		; GFX6: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[AND4]], [[AND5]]
; GFX6: [[XOR2:%[0-9]+]]:_(s32) = G_XOR [[SHL4]], [[C1]]		; GFX6: [[UMIN2:%[0-9]+]]:_(s32) = G_UMIN [[ADD2]], [[C1]]
; GFX6: [[UMIN2:%[0-9]+]]:_(s32) = G_UMIN [[XOR2]], [[SHL5]]
; GFX6: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[SHL4]], [[UMIN2]]
; GFX6: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[ADD2]], [[C]](s32)
; GFX6: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)		; GFX6: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
		; GFX6: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
; GFX6: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)		; GFX6: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
; GFX6: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[COPY8]], [[C]](s32)		; GFX6: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C1]]
; GFX6: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[COPY9]], [[C]](s32)		; GFX6: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[AND6]], [[AND7]]
; GFX6: [[XOR3:%[0-9]+]]:_(s32) = G_XOR [[SHL6]], [[C1]]		; GFX6: [[UMIN3:%[0-9]+]]:_(s32) = G_UMIN [[ADD3]], [[C1]]
; GFX6: [[UMIN3:%[0-9]+]]:_(s32) = G_UMIN [[XOR3]], [[SHL7]]		; GFX6: [[COPY10:%[0-9]+]]:_(s32) = COPY [[UMIN]](s32)
; GFX6: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[SHL6]], [[UMIN3]]		; GFX6: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
; GFX6: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[ADD3]], [[C]](s32)		; GFX6: [[COPY11:%[0-9]+]]:_(s32) = COPY [[UMIN1]](s32)
; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535		; GFX6: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
; GFX6: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)		; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C]](s32)
; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C2]]		; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL]]
; GFX6: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C2]]
; GFX6: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL8]]
; GFX6: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)		; GFX6: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX6: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)		; GFX6: [[COPY12:%[0-9]+]]:_(s32) = COPY [[UMIN2]](s32)
; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C2]]		; GFX6: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
; GFX6: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)		; GFX6: [[COPY13:%[0-9]+]]:_(s32) = COPY [[UMIN3]](s32)
; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C2]]		; GFX6: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C1]]
; GFX6: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)		; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C]](s32)
; GFX6: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL9]]		; GFX6: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND10]], [[SHL1]]
; GFX6: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)		; GFX6: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; GFX6: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)		; GFX6: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
; GFX6: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)		; GFX6: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
; GFX8-LABEL: name: uaddsat_v4s16		; GFX8-LABEL: name: uaddsat_v4s16
; GFX8: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1		; GFX8: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
; GFX8: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3		; GFX8: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
; GFX8: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)		; GFX8: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
; GFX8: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>)		; GFX8: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>)
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llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubsat.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py		# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -global-isel-abort=0 -march=amdgcn -mcpu=tahiti -run-pass=legalizer %s -o - \| FileCheck -check-prefix=GFX6 %s		# RUN: llc -global-isel-abort=0 -march=amdgcn -mcpu=tahiti -run-pass=legalizer %s -o - \| FileCheck -check-prefix=GFX6 %s
# RUN: llc -global-isel-abort=0 -march=amdgcn -mcpu=fiji -run-pass=legalizer %s -o - \| FileCheck -check-prefix=GFX8 %s		# RUN: llc -global-isel-abort=0 -march=amdgcn -mcpu=fiji -run-pass=legalizer %s -o - \| FileCheck -check-prefix=GFX8 %s
# RUN: llc -global-isel-abort=0 -march=amdgcn -mcpu=gfx900 -run-pass=legalizer %s -o - \| FileCheck -check-prefix=GFX9 %s		# RUN: llc -global-isel-abort=0 -march=amdgcn -mcpu=gfx900 -run-pass=legalizer %s -o - \| FileCheck -check-prefix=GFX9 %s

---		---
name: usubsat_s7		name: usubsat_s7
body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0, $vgpr1		liveins: $vgpr0, $vgpr1

; GFX6-LABEL: name: usubsat_s7		; GFX6-LABEL: name: usubsat_s7
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0		; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1		; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
		; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
		; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 25		; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)		; GFX6: [[UMAX:%[0-9]+]]:_(s32) = G_UMAX [[AND]], [[AND1]]
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)		; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UMAX]], [[AND1]]
; GFX6: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[SHL]], [[SHL1]]		; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SHL]], [[UMIN]]
; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[SUB]], [[C]](s32)
; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; GFX6: $vgpr0 = COPY [[COPY4]](s32)		; GFX6: $vgpr0 = COPY [[COPY4]](s32)
; GFX8-LABEL: name: usubsat_s7		; GFX8-LABEL: name: usubsat_s7
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1		; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)		; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX8: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)		; GFX8: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX8: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 9		; GFX8: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 9
; GFX8: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16)		; GFX8: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16)
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name: usubsat_s8		name: usubsat_s8
body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0, $vgpr1		liveins: $vgpr0, $vgpr1

; GFX6-LABEL: name: usubsat_s8		; GFX6-LABEL: name: usubsat_s8
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0		; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1		; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
		; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
		; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24		; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)		; GFX6: [[UMAX:%[0-9]+]]:_(s32) = G_UMAX [[AND]], [[AND1]]
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)		; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UMAX]], [[AND1]]
; GFX6: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[SHL]], [[SHL1]]		; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SHL]], [[UMIN]]
; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[SUB]], [[C]](s32)
; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; GFX6: $vgpr0 = COPY [[COPY4]](s32)		; GFX6: $vgpr0 = COPY [[COPY4]](s32)
; GFX8-LABEL: name: usubsat_s8		; GFX8-LABEL: name: usubsat_s8
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1		; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)		; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX8: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)		; GFX8: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX8: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 8		; GFX8: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; GFX8: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16)		; GFX8: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16)
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; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)		; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16		; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32)		; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32)
; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24		; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; GFX6: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)		; GFX6: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
; GFX6: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32)		; GFX6: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32)
; GFX6: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C1]](s32)		; GFX6: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C1]](s32)
; GFX6: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)		; GFX6: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
		; GFX6: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
		; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C2]](s32)		; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C2]](s32)		; GFX6: [[UMAX:%[0-9]+]]:_(s32) = G_UMAX [[AND]], [[AND1]]
; GFX6: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[SHL]], [[SHL1]]		; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UMAX]], [[AND1]]
; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SHL]], [[UMIN]]
; GFX6: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[SUB]], [[C2]](s32)
; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)		; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
		; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C3]]
; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)		; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C2]](s32)		; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C2]](s32)		; GFX6: [[UMAX1:%[0-9]+]]:_(s32) = G_UMAX [[AND2]], [[AND3]]
; GFX6: [[UMIN1:%[0-9]+]]:_(s32) = G_UMIN [[SHL2]], [[SHL3]]		; GFX6: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[UMAX1]], [[AND3]]
; GFX6: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[SHL2]], [[UMIN1]]		; GFX6: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
; GFX6: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[SUB1]], [[C2]](s32)		; GFX6: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SUB]](s32)
; GFX6: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 255		; GFX6: [[AND4:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C4]]
; GFX6: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR6]](s32)
; GFX6: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[C3]]
; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C]](s32)		; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; GFX6: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255		; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SUB1]](s32)
; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)		; GFX6: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C4]]		; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[COPY6]](s32)
; GFX6: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[COPY6]](s32)		; GFX6: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; GFX6: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[SHL4]](s32)		; GFX6: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[TRUNC1]]
; GFX6: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC1]]
; GFX6: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)		; GFX6: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; GFX6: $vgpr0 = COPY [[ANYEXT]](s32)		; GFX6: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX8-LABEL: name: usubsat_v2s8		; GFX8-LABEL: name: usubsat_v2s8
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1		; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8		; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GFX8: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)		; GFX8: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
; GFX8: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16		; GFX8: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
▲ Show 20 Lines • Show All 79 Lines • ▼ Show 20 Lines
name: usubsat_s16		name: usubsat_s16
body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0, $vgpr1		liveins: $vgpr0, $vgpr1

; GFX6-LABEL: name: usubsat_s16		; GFX6-LABEL: name: usubsat_s16
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0		; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1		; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
		; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)		; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
		; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)		; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16		; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)		; GFX6: [[UMAX:%[0-9]+]]:_(s32) = G_UMAX [[AND]], [[AND1]]
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)		; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UMAX]], [[AND1]]
; GFX6: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[SHL]], [[SHL1]]		; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SHL]], [[UMIN]]
; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[SUB]], [[C]](s32)
; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; GFX6: $vgpr0 = COPY [[COPY4]](s32)		; GFX6: $vgpr0 = COPY [[COPY4]](s32)
; GFX8-LABEL: name: usubsat_s16		; GFX8-LABEL: name: usubsat_s16
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1		; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)		; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX8: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)		; GFX8: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; GFX8: [[USUBSAT:%[0-9]+]]:_(s16) = G_USUBSAT [[TRUNC]], [[TRUNC1]]		; GFX8: [[USUBSAT:%[0-9]+]]:_(s16) = G_USUBSAT [[TRUNC]], [[TRUNC1]]
; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[USUBSAT]](s16)		; GFX8: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[USUBSAT]](s16)
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; GFX6-LABEL: name: usubsat_v2s16		; GFX6-LABEL: name: usubsat_v2s16
; GFX6: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0		; GFX6: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1		; GFX6: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
; GFX6: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)		; GFX6: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16		; GFX6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)		; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX6: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)		; GFX6: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>)
; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)		; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
		; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)		; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
		; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)		; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)		; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)		; GFX6: [[UMAX:%[0-9]+]]:_(s32) = G_UMAX [[AND]], [[AND1]]
; GFX6: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[SHL]], [[SHL1]]		; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UMAX]], [[AND1]]
; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SHL]], [[UMIN]]
; GFX6: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[SUB]], [[C]](s32)
; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)		; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
		; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)		; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)		; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C]](s32)		; GFX6: [[UMAX1:%[0-9]+]]:_(s32) = G_UMAX [[AND2]], [[AND3]]
; GFX6: [[UMIN1:%[0-9]+]]:_(s32) = G_UMIN [[SHL2]], [[SHL3]]		; GFX6: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[UMAX1]], [[AND3]]
; GFX6: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[SHL2]], [[UMIN1]]		; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; GFX6: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[SUB1]], [[C]](s32)		; GFX6: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535		; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SUB1]](s32)
; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)		; GFX6: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]		; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C]](s32)
; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)		; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SHL]]
; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
; GFX6: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL4]]
; GFX6: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)		; GFX6: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX6: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)		; GFX6: $vgpr0 = COPY [[BITCAST2]](<2 x s16>)
; GFX8-LABEL: name: usubsat_v2s16		; GFX8-LABEL: name: usubsat_v2s16
; GFX8: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1		; GFX8: [[COPY1:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr1
; GFX8: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)		; GFX8: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)		; GFX8: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16		; GFX8: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
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; GFX6: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)		; GFX6: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)		; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX6: [[INSERT1:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[UV1]](<3 x s16>), 0		; GFX6: [[INSERT1:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[UV1]](<3 x s16>), 0
; GFX6: [[UV4:%[0-9]+]]:_(<2 x s16>), [[UV5:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INSERT1]](<4 x s16>)		; GFX6: [[UV4:%[0-9]+]]:_(<2 x s16>), [[UV5:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INSERT1]](<4 x s16>)
; GFX6: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV4]](<2 x s16>)		; GFX6: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV4]](<2 x s16>)
; GFX6: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)		; GFX6: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX6: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV5]](<2 x s16>)		; GFX6: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV5]](<2 x s16>)
; GFX6: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)		; GFX6: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
		; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)		; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
		; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)		; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)		; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)		; GFX6: [[UMAX:%[0-9]+]]:_(s32) = G_UMAX [[AND]], [[AND1]]
; GFX6: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[SHL]], [[SHL1]]		; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UMAX]], [[AND1]]
; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SHL]], [[UMIN]]
; GFX6: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[SUB]], [[C]](s32)
; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)		; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
		; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)		; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)		; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)		; GFX6: [[UMAX1:%[0-9]+]]:_(s32) = G_UMAX [[AND2]], [[AND3]]
; GFX6: [[UMIN1:%[0-9]+]]:_(s32) = G_UMIN [[SHL2]], [[SHL3]]		; GFX6: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[UMAX1]], [[AND3]]
; GFX6: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[SHL2]], [[UMIN1]]
; GFX6: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[SUB1]], [[C]](s32)
; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)		; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
		; GFX6: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)		; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
; GFX6: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C]](s32)		; GFX6: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
; GFX6: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[COPY6]], [[C]](s32)		; GFX6: [[UMAX2:%[0-9]+]]:_(s32) = G_UMAX [[AND4]], [[AND5]]
; GFX6: [[UMIN2:%[0-9]+]]:_(s32) = G_UMIN [[SHL4]], [[SHL5]]		; GFX6: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[UMAX2]], [[AND5]]
; GFX6: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SHL4]], [[UMIN2]]		; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; GFX6: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[SUB2]], [[C]](s32)		; GFX6: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535		; GFX6: [[COPY8:%[0-9]+]]:_(s32) = COPY [[SUB1]](s32)
; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)		; GFX6: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]		; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C]](s32)
; GFX6: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)		; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[SHL]]
; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
; GFX6: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL6]]
; GFX6: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)		; GFX6: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX6: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)		; GFX6: [[COPY9:%[0-9]+]]:_(s32) = COPY [[SUB2]](s32)
; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C1]]		; GFX6: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C1]]
; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0		; GFX6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GFX6: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C]](s32)		; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C]](s32)
; GFX6: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL7]]		; GFX6: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL1]]
; GFX6: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)		; GFX6: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; GFX6: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF		; GFX6: [[DEF1:%[0-9]+]]:_(<2 x s16>) = G_IMPLICIT_DEF
; GFX6: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>), [[DEF1]](<2 x s16>)		; GFX6: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>), [[DEF1]](<2 x s16>)
; GFX6: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<6 x s16>), 0		; GFX6: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<6 x s16>), 0
; GFX6: [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF		; GFX6: [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
; GFX6: [[CONCAT_VECTORS1:%[0-9]+]]:_(<12 x s16>) = G_CONCAT_VECTORS [[DEF2]](<4 x s16>), [[DEF]](<4 x s16>), [[DEF]](<4 x s16>)		; GFX6: [[CONCAT_VECTORS1:%[0-9]+]]:_(<12 x s16>) = G_CONCAT_VECTORS [[DEF2]](<4 x s16>), [[DEF]](<4 x s16>), [[DEF]](<4 x s16>)
; GFX6: [[UV6:%[0-9]+]]:_(<3 x s16>), [[UV7:%[0-9]+]]:_(<3 x s16>), [[UV8:%[0-9]+]]:_(<3 x s16>), [[UV9:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS1]](<12 x s16>)		; GFX6: [[UV6:%[0-9]+]]:_(<3 x s16>), [[UV7:%[0-9]+]]:_(<3 x s16>), [[UV8:%[0-9]+]]:_(<3 x s16>), [[UV9:%[0-9]+]]:_(<3 x s16>) = G_UNMERGE_VALUES [[CONCAT_VECTORS1]](<12 x s16>)
; GFX6: [[INSERT2:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[EXTRACT]](<3 x s16>), 0		; GFX6: [[INSERT2:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[EXTRACT]](<3 x s16>), 0
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; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)		; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; GFX6: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)		; GFX6: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)		; GFX6: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
; GFX6: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<4 x s16>)		; GFX6: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY1]](<4 x s16>)
; GFX6: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV2]](<2 x s16>)		; GFX6: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV2]](<2 x s16>)
; GFX6: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)		; GFX6: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; GFX6: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)		; GFX6: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; GFX6: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)		; GFX6: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
		; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)		; GFX6: [[COPY2:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
		; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)		; GFX6: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)		; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY3]], [[C]](s32)		; GFX6: [[UMAX:%[0-9]+]]:_(s32) = G_UMAX [[AND]], [[AND1]]
; GFX6: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[SHL]], [[SHL1]]		; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UMAX]], [[AND1]]
; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SHL]], [[UMIN]]
; GFX6: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[SUB]], [[C]](s32)
; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)		; GFX6: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
		; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)		; GFX6: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; GFX6: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY4]], [[C]](s32)		; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
; GFX6: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY5]], [[C]](s32)		; GFX6: [[UMAX1:%[0-9]+]]:_(s32) = G_UMAX [[AND2]], [[AND3]]
; GFX6: [[UMIN1:%[0-9]+]]:_(s32) = G_UMIN [[SHL2]], [[SHL3]]		; GFX6: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[UMAX1]], [[AND3]]
; GFX6: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[SHL2]], [[UMIN1]]
; GFX6: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[SUB1]], [[C]](s32)
; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)		; GFX6: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
		; GFX6: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)		; GFX6: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
; GFX6: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[COPY6]], [[C]](s32)		; GFX6: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C1]]
; GFX6: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[COPY7]], [[C]](s32)		; GFX6: [[UMAX2:%[0-9]+]]:_(s32) = G_UMAX [[AND4]], [[AND5]]
; GFX6: [[UMIN2:%[0-9]+]]:_(s32) = G_UMIN [[SHL4]], [[SHL5]]		; GFX6: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[UMAX2]], [[AND5]]
; GFX6: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SHL4]], [[UMIN2]]
; GFX6: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[SUB2]], [[C]](s32)
; GFX6: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)		; GFX6: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
		; GFX6: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
; GFX6: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)		; GFX6: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
; GFX6: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[COPY8]], [[C]](s32)		; GFX6: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C1]]
; GFX6: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[COPY9]], [[C]](s32)		; GFX6: [[UMAX3:%[0-9]+]]:_(s32) = G_UMAX [[AND6]], [[AND7]]
; GFX6: [[UMIN3:%[0-9]+]]:_(s32) = G_UMIN [[SHL6]], [[SHL7]]		; GFX6: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[UMAX3]], [[AND7]]
; GFX6: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[SHL6]], [[UMIN3]]		; GFX6: [[COPY10:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; GFX6: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[SUB3]], [[C]](s32)		; GFX6: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]
; GFX6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535		; GFX6: [[COPY11:%[0-9]+]]:_(s32) = COPY [[SUB1]](s32)
; GFX6: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)		; GFX6: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
; GFX6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C1]]		; GFX6: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND9]], [[C]](s32)
; GFX6: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)		; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[SHL]]
; GFX6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C1]]
; GFX6: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; GFX6: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL8]]
; GFX6: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)		; GFX6: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; GFX6: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)		; GFX6: [[COPY12:%[0-9]+]]:_(s32) = COPY [[SUB2]](s32)
; GFX6: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]		; GFX6: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
; GFX6: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)		; GFX6: [[COPY13:%[0-9]+]]:_(s32) = COPY [[SUB3]](s32)
; GFX6: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C1]]		; GFX6: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C1]]
; GFX6: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)		; GFX6: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[C]](s32)
; GFX6: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL9]]		; GFX6: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND10]], [[SHL1]]
; GFX6: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)		; GFX6: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; GFX6: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)		; GFX6: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST4]](<2 x s16>), [[BITCAST5]](<2 x s16>)
; GFX6: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)		; GFX6: $vgpr0_vgpr1 = COPY [[CONCAT_VECTORS]](<4 x s16>)
; GFX8-LABEL: name: usubsat_v4s16		; GFX8-LABEL: name: usubsat_v4s16
; GFX8: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1		; GFX8: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
; GFX8: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3		; GFX8: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr2_vgpr3
; GFX8: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)		; GFX8: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
; GFX8: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>)		; GFX8: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>)
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name: usubsat_s32		name: usubsat_s32
body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0, $vgpr1		liveins: $vgpr0, $vgpr1

; GFX6-LABEL: name: usubsat_s32		; GFX6-LABEL: name: usubsat_s32
; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0		; GFX6: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1		; GFX6: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX6: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[COPY]], [[COPY1]]		; GFX6: [[UMAX:%[0-9]+]]:_(s32) = G_UMAX [[COPY]], [[COPY1]]
; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[UMIN]]		; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UMAX]], [[COPY1]]
; GFX6: $vgpr0 = COPY [[SUB]](s32)		; GFX6: $vgpr0 = COPY [[SUB]](s32)
; GFX8-LABEL: name: usubsat_s32		; GFX8-LABEL: name: usubsat_s32
; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0		; GFX8: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1		; GFX8: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX8: [[USUBSAT:%[0-9]+]]:_(s32) = G_USUBSAT [[COPY]], [[COPY1]]		; GFX8: [[USUBSAT:%[0-9]+]]:_(s32) = G_USUBSAT [[COPY]], [[COPY1]]
; GFX8: $vgpr0 = COPY [[USUBSAT]](s32)		; GFX8: $vgpr0 = COPY [[USUBSAT]](s32)
; GFX9-LABEL: name: usubsat_s32		; GFX9-LABEL: name: usubsat_s32
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0		; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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bb.0:		bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3		liveins: $vgpr0_vgpr1, $vgpr2_vgpr3

; GFX6-LABEL: name: usubsat_v2s32		; GFX6-LABEL: name: usubsat_v2s32
; GFX6: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1		; GFX6: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; GFX6: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3		; GFX6: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
; GFX6: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)		; GFX6: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; GFX6: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)		; GFX6: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
; GFX6: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[UV]], [[UV2]]		; GFX6: [[UMAX:%[0-9]+]]:_(s32) = G_UMAX [[UV]], [[UV2]]
; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UV]], [[UMIN]]		; GFX6: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UMAX]], [[UV2]]
; GFX6: [[UMIN1:%[0-9]+]]:_(s32) = G_UMIN [[UV1]], [[UV3]]		; GFX6: [[UMAX1:%[0-9]+]]:_(s32) = G_UMAX [[UV1]], [[UV3]]
; GFX6: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[UV1]], [[UMIN1]]		; GFX6: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[UMAX1]], [[UV3]]
; GFX6: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SUB]](s32), [[SUB1]](s32)		; GFX6: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SUB]](s32), [[SUB1]](s32)
; GFX6: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)		; GFX6: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
; GFX8-LABEL: name: usubsat_v2s32		; GFX8-LABEL: name: usubsat_v2s32
; GFX8: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1		; GFX8: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; GFX8: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3		; GFX8: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3
; GFX8: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)		; GFX8: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; GFX8: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)		; GFX8: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](<2 x s32>)
; GFX8: [[USUBSAT:%[0-9]+]]:_(s32) = G_USUBSAT [[UV]], [[UV2]]		; GFX8: [[USUBSAT:%[0-9]+]]:_(s32) = G_USUBSAT [[UV]], [[UV2]]
▲ Show 20 Lines • Show All 143 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll

This file is larger than 256 KB, so syntax highlighting is disabled by default.

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py		; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=tahiti -o - %s \| FileCheck -check-prefix=GFX6 %s		; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=tahiti -o - %s \| FileCheck -check-prefix=GFX6 %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=fiji -o - %s \| FileCheck -check-prefix=GFX8 %s		; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=fiji -o - %s \| FileCheck -check-prefix=GFX8 %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -o - %s \| FileCheck -check-prefix=GFX9 %s		; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -o - %s \| FileCheck -check-prefix=GFX9 %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -o - %s \| FileCheck -check-prefix=GFX10 %s		; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -o - %s \| FileCheck -check-prefix=GFX10 %s

define i7 @v_saddsat_i7(i7 %lhs, i7 %rhs) {		define i7 @v_saddsat_i7(i7 %lhs, i7 %rhs) {
; GFX6-LABEL: v_saddsat_i7:		; GFX6-LABEL: v_saddsat_i7:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 25, v0		; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 7
; GFX6-NEXT: v_min_i32_e32 v3, 0, v0		; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 7
; GFX6-NEXT: v_max_i32_e32 v2, 0, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 25, v1
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, 0x80000000, v3
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, 0x7fffffff, v2
; GFX6-NEXT: v_max_i32_e32 v1, v3, v1
; GFX6-NEXT: v_min_i32_e32 v1, v1, v2
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1		; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 25, v0		; GFX6-NEXT: v_max_i32_e32 v0, 0xffffffc0, v0
		; GFX6-NEXT: v_min_i32_e32 v0, 63, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]		; GFX6-NEXT: s_setpc_b64 s[30:31]
;		;
; GFX8-LABEL: v_saddsat_i7:		; GFX8-LABEL: v_saddsat_i7:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshlrev_b16_e32 v0, 9, v0		; GFX8-NEXT: v_lshlrev_b16_e32 v0, 9, v0
; GFX8-NEXT: v_min_i16_e32 v3, 0, v0		; GFX8-NEXT: v_min_i16_e32 v3, 0, v0
; GFX8-NEXT: v_max_i16_e32 v2, 0, v0		; GFX8-NEXT: v_max_i16_e32 v2, 0, v0
Show All 27 Lines
; GFX10-NEXT: s_setpc_b64 s[30:31]		; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call i7 @llvm.sadd.sat.i7(i7 %lhs, i7 %rhs)		%result = call i7 @llvm.sadd.sat.i7(i7 %lhs, i7 %rhs)
ret i7 %result		ret i7 %result
}		}

define amdgpu_ps i7 @s_saddsat_i7(i7 inreg %lhs, i7 inreg %rhs) {		define amdgpu_ps i7 @s_saddsat_i7(i7 inreg %lhs, i7 inreg %rhs) {
; GFX6-LABEL: s_saddsat_i7:		; GFX6-LABEL: s_saddsat_i7:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 25		; GFX6-NEXT: s_bfe_i32 s0, s0, 0x70000
; GFX6-NEXT: s_lshl_b32 s1, s1, 25		; GFX6-NEXT: s_bfe_i32 s1, s1, 0x70000
; GFX6-NEXT: s_cmp_gt_i32 s0, 0
; GFX6-NEXT: s_cselect_b32 s2, s0, 0
; GFX6-NEXT: s_sub_i32 s2, 0x7fffffff, s2
; GFX6-NEXT: s_cmp_lt_i32 s0, 0
; GFX6-NEXT: s_cselect_b32 s3, s0, 0
; GFX6-NEXT: s_sub_i32 s3, 0x80000000, s3
; GFX6-NEXT: s_cmp_gt_i32 s3, s1
; GFX6-NEXT: s_cselect_b32 s1, s3, s1
; GFX6-NEXT: s_cmp_lt_i32 s1, s2
; GFX6-NEXT: s_cselect_b32 s1, s1, s2
; GFX6-NEXT: s_add_i32 s0, s0, s1		; GFX6-NEXT: s_add_i32 s0, s0, s1
; GFX6-NEXT: s_ashr_i32 s0, s0, 25		; GFX6-NEXT: s_movk_i32 s1, 0xffc0
		; GFX6-NEXT: s_cmp_gt_i32 s0, s1
		; GFX6-NEXT: s_cselect_b32 s0, s0, s1
		; GFX6-NEXT: s_cmp_lt_i32 s0, 63
		; GFX6-NEXT: s_cselect_b32 s0, s0, 63
; GFX6-NEXT: ; return to shader part epilog		; GFX6-NEXT: ; return to shader part epilog
;		;
; GFX8-LABEL: s_saddsat_i7:		; GFX8-LABEL: s_saddsat_i7:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_bfe_u32 s2, 9, 0x100000		; GFX8-NEXT: s_bfe_u32 s2, 9, 0x100000
; GFX8-NEXT: s_lshl_b32 s0, s0, s2		; GFX8-NEXT: s_lshl_b32 s0, s0, s2
; GFX8-NEXT: s_lshl_b32 s1, s1, s2		; GFX8-NEXT: s_lshl_b32 s1, s1, s2
; GFX8-NEXT: s_sext_i32_i16 s3, s0		; GFX8-NEXT: s_sext_i32_i16 s3, s0
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines	; GFX10-NEXT: ; return to shader part epilog
%result = call i7 @llvm.sadd.sat.i7(i7 %lhs, i7 %rhs)		%result = call i7 @llvm.sadd.sat.i7(i7 %lhs, i7 %rhs)
ret i7 %result		ret i7 %result
}		}

define i8 @v_saddsat_i8(i8 %lhs, i8 %rhs) {		define i8 @v_saddsat_i8(i8 %lhs, i8 %rhs) {
; GFX6-LABEL: v_saddsat_i8:		; GFX6-LABEL: v_saddsat_i8:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 24, v0		; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX6-NEXT: v_min_i32_e32 v3, 0, v0		; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 8
; GFX6-NEXT: v_max_i32_e32 v2, 0, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v1
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, 0x80000000, v3
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, 0x7fffffff, v2
; GFX6-NEXT: v_max_i32_e32 v1, v3, v1
; GFX6-NEXT: v_min_i32_e32 v1, v1, v2
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1		; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 24, v0		; GFX6-NEXT: v_max_i32_e32 v0, 0xffffff80, v0
		; GFX6-NEXT: v_min_i32_e32 v0, 0x7f, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]		; GFX6-NEXT: s_setpc_b64 s[30:31]
;		;
; GFX8-LABEL: v_saddsat_i8:		; GFX8-LABEL: v_saddsat_i8:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshlrev_b16_e32 v0, 8, v0		; GFX8-NEXT: v_lshlrev_b16_e32 v0, 8, v0
; GFX8-NEXT: v_min_i16_e32 v3, 0, v0		; GFX8-NEXT: v_min_i16_e32 v3, 0, v0
; GFX8-NEXT: v_max_i16_e32 v2, 0, v0		; GFX8-NEXT: v_max_i16_e32 v2, 0, v0
Show All 27 Lines
; GFX10-NEXT: s_setpc_b64 s[30:31]		; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call i8 @llvm.sadd.sat.i8(i8 %lhs, i8 %rhs)		%result = call i8 @llvm.sadd.sat.i8(i8 %lhs, i8 %rhs)
ret i8 %result		ret i8 %result
}		}

define amdgpu_ps i8 @s_saddsat_i8(i8 inreg %lhs, i8 inreg %rhs) {		define amdgpu_ps i8 @s_saddsat_i8(i8 inreg %lhs, i8 inreg %rhs) {
; GFX6-LABEL: s_saddsat_i8:		; GFX6-LABEL: s_saddsat_i8:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 24		; GFX6-NEXT: s_sext_i32_i8 s0, s0
; GFX6-NEXT: s_lshl_b32 s1, s1, 24		; GFX6-NEXT: s_sext_i32_i8 s1, s1
; GFX6-NEXT: s_cmp_gt_i32 s0, 0
; GFX6-NEXT: s_cselect_b32 s2, s0, 0
; GFX6-NEXT: s_sub_i32 s2, 0x7fffffff, s2
; GFX6-NEXT: s_cmp_lt_i32 s0, 0
; GFX6-NEXT: s_cselect_b32 s3, s0, 0
; GFX6-NEXT: s_sub_i32 s3, 0x80000000, s3
; GFX6-NEXT: s_cmp_gt_i32 s3, s1
; GFX6-NEXT: s_cselect_b32 s1, s3, s1
; GFX6-NEXT: s_cmp_lt_i32 s1, s2
; GFX6-NEXT: s_cselect_b32 s1, s1, s2
; GFX6-NEXT: s_add_i32 s0, s0, s1		; GFX6-NEXT: s_add_i32 s0, s0, s1
; GFX6-NEXT: s_ashr_i32 s0, s0, 24		; GFX6-NEXT: s_movk_i32 s1, 0xff80
		; GFX6-NEXT: s_cmp_gt_i32 s0, s1
		; GFX6-NEXT: s_cselect_b32 s0, s0, s1
		; GFX6-NEXT: s_movk_i32 s1, 0x7f
		; GFX6-NEXT: s_cmp_lt_i32 s0, s1
		; GFX6-NEXT: s_cselect_b32 s0, s0, s1
; GFX6-NEXT: ; return to shader part epilog		; GFX6-NEXT: ; return to shader part epilog
;		;
; GFX8-LABEL: s_saddsat_i8:		; GFX8-LABEL: s_saddsat_i8:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_bfe_u32 s2, 8, 0x100000		; GFX8-NEXT: s_bfe_u32 s2, 8, 0x100000
; GFX8-NEXT: s_lshl_b32 s0, s0, s2		; GFX8-NEXT: s_lshl_b32 s0, s0, s2
; GFX8-NEXT: s_lshl_b32 s1, s1, s2		; GFX8-NEXT: s_lshl_b32 s1, s1, s2
; GFX8-NEXT: s_sext_i32_i16 s3, s0		; GFX8-NEXT: s_sext_i32_i16 s3, s0
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines	; GFX10-NEXT: ; return to shader part epilog
ret i8 %result		ret i8 %result
}		}

define i16 @v_saddsat_v2i8(i16 %lhs.arg, i16 %rhs.arg) {		define i16 @v_saddsat_v2i8(i16 %lhs.arg, i16 %rhs.arg) {
; GFX6-LABEL: v_saddsat_v2i8:		; GFX6-LABEL: v_saddsat_v2i8:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshrrev_b32_e32 v2, 8, v0		; GFX6-NEXT: v_lshrrev_b32_e32 v2, 8, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 24, v0
; GFX6-NEXT: s_brev_b32 s5, 1
; GFX6-NEXT: v_min_i32_e32 v5, 0, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 8, v1		; GFX6-NEXT: v_lshrrev_b32_e32 v3, 8, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v1		; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX6-NEXT: v_sub_i32_e32 v5, vcc, s5, v5		; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 8
; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_max_i32_e32 v4, 0, v0
; GFX6-NEXT: v_sub_i32_e32 v4, vcc, s4, v4
; GFX6-NEXT: v_max_i32_e32 v1, v5, v1
; GFX6-NEXT: v_min_i32_e32 v1, v1, v4
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1		; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v2		; GFX6-NEXT: v_bfe_i32 v1, v2, 0, 8
; GFX6-NEXT: v_min_i32_e32 v4, 0, v1		; GFX6-NEXT: v_bfe_i32 v2, v3, 0, 8
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 24, v3		; GFX6-NEXT: s_movk_i32 s4, 0xff80
; GFX6-NEXT: v_max_i32_e32 v3, 0, v1
; GFX6-NEXT: v_sub_i32_e32 v4, vcc, s5, v4
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s4, v3
; GFX6-NEXT: v_max_i32_e32 v2, v4, v2
; GFX6-NEXT: v_min_i32_e32 v2, v2, v3
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v2		; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v2
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 24, v1		; GFX6-NEXT: s_movk_i32 s5, 0x7f
		; GFX6-NEXT: v_max_i32_e32 v1, s4, v1
		; GFX6-NEXT: v_max_i32_e32 v0, s4, v0
		; GFX6-NEXT: v_min_i32_e32 v1, s5, v1
; GFX6-NEXT: v_mov_b32_e32 v2, 0xff		; GFX6-NEXT: v_mov_b32_e32 v2, 0xff
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 24, v0		; GFX6-NEXT: v_min_i32_e32 v0, s5, v0
; GFX6-NEXT: v_and_b32_e32 v1, v1, v2		; GFX6-NEXT: v_and_b32_e32 v1, v1, v2
; GFX6-NEXT: v_and_b32_e32 v0, v0, v2		; GFX6-NEXT: v_and_b32_e32 v0, v0, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 8, v1		; GFX6-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1		; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]		; GFX6-NEXT: s_setpc_b64 s[30:31]
;		;
; GFX8-LABEL: v_saddsat_v2i8:		; GFX8-LABEL: v_saddsat_v2i8:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
▲ Show 20 Lines • Show All 69 Lines • ▼ Show 20 Lines	; GFX10-NEXT: s_setpc_b64 s[30:31]
ret i16 %cast.result		ret i16 %cast.result
}		}

define amdgpu_ps i16 @s_saddsat_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg) {		define amdgpu_ps i16 @s_saddsat_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg) {
; GFX6-LABEL: s_saddsat_v2i8:		; GFX6-LABEL: s_saddsat_v2i8:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshr_b32 s2, s0, 8		; GFX6-NEXT: s_lshr_b32 s2, s0, 8
; GFX6-NEXT: s_lshr_b32 s3, s1, 8		; GFX6-NEXT: s_lshr_b32 s3, s1, 8
; GFX6-NEXT: s_lshl_b32 s0, s0, 24		; GFX6-NEXT: s_sext_i32_i8 s0, s0
; GFX6-NEXT: s_lshl_b32 s1, s1, 24		; GFX6-NEXT: s_sext_i32_i8 s1, s1
; GFX6-NEXT: s_cmp_gt_i32 s0, 0
; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: s_cselect_b32 s6, s0, 0
; GFX6-NEXT: s_sub_i32 s6, s4, s6
; GFX6-NEXT: s_cmp_lt_i32 s0, 0
; GFX6-NEXT: s_brev_b32 s5, 1
; GFX6-NEXT: s_cselect_b32 s7, s0, 0
; GFX6-NEXT: s_sub_i32 s7, s5, s7
; GFX6-NEXT: s_cmp_gt_i32 s7, s1
; GFX6-NEXT: s_cselect_b32 s1, s7, s1
; GFX6-NEXT: s_cmp_lt_i32 s1, s6
; GFX6-NEXT: s_cselect_b32 s1, s1, s6
; GFX6-NEXT: s_add_i32 s0, s0, s1		; GFX6-NEXT: s_add_i32 s0, s0, s1
; GFX6-NEXT: s_lshl_b32 s1, s2, 24		; GFX6-NEXT: s_movk_i32 s1, 0xff80
; GFX6-NEXT: s_ashr_i32 s0, s0, 24		; GFX6-NEXT: s_cmp_gt_i32 s0, s1
; GFX6-NEXT: s_lshl_b32 s2, s3, 24		; GFX6-NEXT: s_cselect_b32 s0, s0, s1
; GFX6-NEXT: s_cmp_gt_i32 s1, 0		; GFX6-NEXT: s_movk_i32 s4, 0x7f
; GFX6-NEXT: s_cselect_b32 s3, s1, 0		; GFX6-NEXT: s_cmp_lt_i32 s0, s4
; GFX6-NEXT: s_sub_i32 s3, s4, s3		; GFX6-NEXT: s_sext_i32_i8 s2, s2
; GFX6-NEXT: s_cmp_lt_i32 s1, 0		; GFX6-NEXT: s_sext_i32_i8 s3, s3
; GFX6-NEXT: s_cselect_b32 s4, s1, 0		; GFX6-NEXT: s_cselect_b32 s0, s0, s4
; GFX6-NEXT: s_sub_i32 s4, s5, s4		; GFX6-NEXT: s_add_i32 s2, s2, s3
; GFX6-NEXT: s_cmp_gt_i32 s4, s2		; GFX6-NEXT: s_cmp_gt_i32 s2, s1
; GFX6-NEXT: s_cselect_b32 s2, s4, s2		; GFX6-NEXT: s_cselect_b32 s1, s2, s1
; GFX6-NEXT: s_cmp_lt_i32 s2, s3		; GFX6-NEXT: s_cmp_lt_i32 s1, s4
; GFX6-NEXT: s_cselect_b32 s2, s2, s3		; GFX6-NEXT: s_cselect_b32 s1, s1, s4
; GFX6-NEXT: s_add_i32 s1, s1, s2
; GFX6-NEXT: s_movk_i32 s2, 0xff		; GFX6-NEXT: s_movk_i32 s2, 0xff
; GFX6-NEXT: s_ashr_i32 s1, s1, 24
; GFX6-NEXT: s_and_b32 s1, s1, s2		; GFX6-NEXT: s_and_b32 s1, s1, s2
; GFX6-NEXT: s_and_b32 s0, s0, s2		; GFX6-NEXT: s_and_b32 s0, s0, s2
; GFX6-NEXT: s_lshl_b32 s1, s1, 8		; GFX6-NEXT: s_lshl_b32 s1, s1, 8
; GFX6-NEXT: s_or_b32 s0, s0, s1		; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: ; return to shader part epilog		; GFX6-NEXT: ; return to shader part epilog
;		;
; GFX8-LABEL: s_saddsat_v2i8:		; GFX8-LABEL: s_saddsat_v2i8:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
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define i32 @v_saddsat_v4i8(i32 %lhs.arg, i32 %rhs.arg) {		define i32 @v_saddsat_v4i8(i32 %lhs.arg, i32 %rhs.arg) {
; GFX6-LABEL: v_saddsat_v4i8:		; GFX6-LABEL: v_saddsat_v4i8:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshrrev_b32_e32 v2, 8, v0		; GFX6-NEXT: v_lshrrev_b32_e32 v2, 8, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v0		; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v4, 24, v0		; GFX6-NEXT: v_lshrrev_b32_e32 v4, 24, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 24, v0
; GFX6-NEXT: s_brev_b32 s5, 1
; GFX6-NEXT: v_min_i32_e32 v10, 0, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v5, 8, v1		; GFX6-NEXT: v_lshrrev_b32_e32 v5, 8, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v6, 16, v1		; GFX6-NEXT: v_lshrrev_b32_e32 v6, 16, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v7, 24, v1		; GFX6-NEXT: v_lshrrev_b32_e32 v7, 24, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v1		; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX6-NEXT: v_sub_i32_e32 v10, vcc, s5, v10		; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 8
; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_max_i32_e32 v8, 0, v0
; GFX6-NEXT: v_sub_i32_e32 v8, vcc, s4, v8
; GFX6-NEXT: v_max_i32_e32 v1, v10, v1
; GFX6-NEXT: v_min_i32_e32 v1, v1, v8
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1		; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v2		; GFX6-NEXT: v_bfe_i32 v1, v2, 0, 8
; GFX6-NEXT: v_min_i32_e32 v8, 0, v1		; GFX6-NEXT: v_bfe_i32 v2, v5, 0, 8
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 24, v5
; GFX6-NEXT: v_max_i32_e32 v5, 0, v1
; GFX6-NEXT: v_sub_i32_e32 v8, vcc, s5, v8
; GFX6-NEXT: v_sub_i32_e32 v5, vcc, s4, v5
; GFX6-NEXT: v_max_i32_e32 v2, v8, v2
; GFX6-NEXT: v_min_i32_e32 v2, v2, v5
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v2		; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 24, v3		; GFX6-NEXT: v_bfe_i32 v2, v3, 0, 8
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 24, v6		; GFX6-NEXT: v_bfe_i32 v3, v6, 0, 8
; GFX6-NEXT: v_min_i32_e32 v6, 0, v2		; GFX6-NEXT: s_movk_i32 s4, 0xff80
; GFX6-NEXT: v_sub_i32_e32 v6, vcc, s5, v6
; GFX6-NEXT: v_bfrev_b32_e32 v9, -2
; GFX6-NEXT: v_max_i32_e32 v5, 0, v2
; GFX6-NEXT: v_sub_i32_e32 v5, vcc, v9, v5
; GFX6-NEXT: v_max_i32_e32 v3, v6, v3
; GFX6-NEXT: v_min_i32_e32 v3, v3, v5
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3		; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 24, v4		; GFX6-NEXT: v_bfe_i32 v3, v4, 0, 8
; GFX6-NEXT: v_bfrev_b32_e32 v11, 1		; GFX6-NEXT: v_bfe_i32 v4, v7, 0, 8
; GFX6-NEXT: v_min_i32_e32 v6, 0, v3		; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v4
; GFX6-NEXT: v_max_i32_e32 v5, 0, v3		; GFX6-NEXT: s_movk_i32 s5, 0x7f
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 24, v1		; GFX6-NEXT: v_max_i32_e32 v1, s4, v1
		; GFX6-NEXT: v_max_i32_e32 v0, s4, v0
		; GFX6-NEXT: v_max_i32_e32 v2, s4, v2
		; GFX6-NEXT: v_max_i32_e32 v3, s4, v3
		; GFX6-NEXT: v_min_i32_e32 v1, s5, v1
; GFX6-NEXT: s_movk_i32 s4, 0xff		; GFX6-NEXT: s_movk_i32 s4, 0xff
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 24, v7		; GFX6-NEXT: v_min_i32_e32 v0, s5, v0
; GFX6-NEXT: v_sub_i32_e32 v6, vcc, v11, v6
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 24, v0
; GFX6-NEXT: v_and_b32_e32 v1, s4, v1		; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
; GFX6-NEXT: v_sub_i32_e32 v5, vcc, v9, v5		; GFX6-NEXT: v_min_i32_e32 v2, s5, v2
; GFX6-NEXT: v_max_i32_e32 v4, v6, v4
; GFX6-NEXT: v_min_i32_e32 v4, v4, v5
; GFX6-NEXT: v_ashrrev_i32_e32 v2, 24, v2
; GFX6-NEXT: v_and_b32_e32 v0, s4, v0		; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 8, v1		; GFX6-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v4
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1		; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: v_and_b32_e32 v1, s4, v2		; GFX6-NEXT: v_and_b32_e32 v1, s4, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1		; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_ashrrev_i32_e32 v3, 24, v3		; GFX6-NEXT: v_min_i32_e32 v3, s5, v3
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1		; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: v_and_b32_e32 v1, s4, v3		; GFX6-NEXT: v_and_b32_e32 v1, s4, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v1		; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1		; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]		; GFX6-NEXT: s_setpc_b64 s[30:31]
;		;
; GFX8-LABEL: v_saddsat_v4i8:		; GFX8-LABEL: v_saddsat_v4i8:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
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; GFX6-LABEL: s_saddsat_v4i8:		; GFX6-LABEL: s_saddsat_v4i8:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshr_b32 s2, s0, 8		; GFX6-NEXT: s_lshr_b32 s2, s0, 8
; GFX6-NEXT: s_lshr_b32 s3, s0, 16		; GFX6-NEXT: s_lshr_b32 s3, s0, 16
; GFX6-NEXT: s_lshr_b32 s4, s0, 24		; GFX6-NEXT: s_lshr_b32 s4, s0, 24
; GFX6-NEXT: s_lshr_b32 s5, s1, 8		; GFX6-NEXT: s_lshr_b32 s5, s1, 8
; GFX6-NEXT: s_lshr_b32 s6, s1, 16		; GFX6-NEXT: s_lshr_b32 s6, s1, 16
; GFX6-NEXT: s_lshr_b32 s7, s1, 24		; GFX6-NEXT: s_lshr_b32 s7, s1, 24
; GFX6-NEXT: s_lshl_b32 s0, s0, 24		; GFX6-NEXT: s_sext_i32_i8 s0, s0
; GFX6-NEXT: s_lshl_b32 s1, s1, 24		; GFX6-NEXT: s_sext_i32_i8 s1, s1
; GFX6-NEXT: s_cmp_gt_i32 s0, 0
; GFX6-NEXT: s_brev_b32 s8, -2
; GFX6-NEXT: s_cselect_b32 s10, s0, 0
; GFX6-NEXT: s_sub_i32 s10, s8, s10
; GFX6-NEXT: s_cmp_lt_i32 s0, 0
; GFX6-NEXT: s_brev_b32 s9, 1
; GFX6-NEXT: s_cselect_b32 s11, s0, 0
; GFX6-NEXT: s_sub_i32 s11, s9, s11
; GFX6-NEXT: s_cmp_gt_i32 s11, s1
; GFX6-NEXT: s_cselect_b32 s1, s11, s1
; GFX6-NEXT: s_cmp_lt_i32 s1, s10
; GFX6-NEXT: s_cselect_b32 s1, s1, s10
; GFX6-NEXT: s_add_i32 s0, s0, s1		; GFX6-NEXT: s_add_i32 s0, s0, s1
; GFX6-NEXT: s_lshl_b32 s1, s2, 24		; GFX6-NEXT: s_movk_i32 s1, 0xff80
; GFX6-NEXT: s_ashr_i32 s0, s0, 24		; GFX6-NEXT: s_cmp_gt_i32 s0, s1
; GFX6-NEXT: s_lshl_b32 s2, s5, 24		; GFX6-NEXT: s_cselect_b32 s0, s0, s1
; GFX6-NEXT: s_cmp_gt_i32 s1, 0		; GFX6-NEXT: s_movk_i32 s8, 0x7f
; GFX6-NEXT: s_cselect_b32 s5, s1, 0		; GFX6-NEXT: s_cmp_lt_i32 s0, s8
; GFX6-NEXT: s_sub_i32 s5, s8, s5		; GFX6-NEXT: s_sext_i32_i8 s2, s2
; GFX6-NEXT: s_cmp_lt_i32 s1, 0		; GFX6-NEXT: s_sext_i32_i8 s5, s5
; GFX6-NEXT: s_cselect_b32 s10, s1, 0		; GFX6-NEXT: s_cselect_b32 s0, s0, s8
; GFX6-NEXT: s_sub_i32 s10, s9, s10		; GFX6-NEXT: s_add_i32 s2, s2, s5
; GFX6-NEXT: s_cmp_gt_i32 s10, s2		; GFX6-NEXT: s_cmp_gt_i32 s2, s1
; GFX6-NEXT: s_cselect_b32 s2, s10, s2		; GFX6-NEXT: s_cselect_b32 s2, s2, s1
; GFX6-NEXT: s_cmp_lt_i32 s2, s5		; GFX6-NEXT: s_cmp_lt_i32 s2, s8
; GFX6-NEXT: s_cselect_b32 s2, s2, s5		; GFX6-NEXT: s_sext_i32_i8 s3, s3
; GFX6-NEXT: s_add_i32 s1, s1, s2		; GFX6-NEXT: s_sext_i32_i8 s5, s6
; GFX6-NEXT: s_lshl_b32 s2, s3, 24		; GFX6-NEXT: s_cselect_b32 s2, s2, s8
; GFX6-NEXT: s_ashr_i32 s1, s1, 24		; GFX6-NEXT: s_add_i32 s3, s3, s5
; GFX6-NEXT: s_lshl_b32 s3, s6, 24		; GFX6-NEXT: s_cmp_gt_i32 s3, s1
; GFX6-NEXT: s_cmp_gt_i32 s2, 0		; GFX6-NEXT: s_cselect_b32 s3, s3, s1
; GFX6-NEXT: s_cselect_b32 s5, s2, 0		; GFX6-NEXT: s_cmp_lt_i32 s3, s8
; GFX6-NEXT: s_sub_i32 s5, s8, s5		; GFX6-NEXT: s_sext_i32_i8 s4, s4
; GFX6-NEXT: s_cmp_lt_i32 s2, 0		; GFX6-NEXT: s_sext_i32_i8 s5, s7
; GFX6-NEXT: s_cselect_b32 s6, s2, 0		; GFX6-NEXT: s_cselect_b32 s3, s3, s8
; GFX6-NEXT: s_sub_i32 s6, s9, s6		; GFX6-NEXT: s_add_i32 s4, s4, s5
; GFX6-NEXT: s_cmp_gt_i32 s6, s3		; GFX6-NEXT: s_cmp_gt_i32 s4, s1
; GFX6-NEXT: s_cselect_b32 s3, s6, s3		; GFX6-NEXT: s_cselect_b32 s1, s4, s1
; GFX6-NEXT: s_cmp_lt_i32 s3, s5		; GFX6-NEXT: s_cmp_lt_i32 s1, s8
; GFX6-NEXT: s_cselect_b32 s3, s3, s5
; GFX6-NEXT: s_add_i32 s2, s2, s3
; GFX6-NEXT: s_lshl_b32 s3, s4, 24
; GFX6-NEXT: s_ashr_i32 s2, s2, 24
; GFX6-NEXT: s_lshl_b32 s4, s7, 24
; GFX6-NEXT: s_cmp_gt_i32 s3, 0
; GFX6-NEXT: s_cselect_b32 s5, s3, 0
; GFX6-NEXT: s_sub_i32 s5, s8, s5
; GFX6-NEXT: s_cmp_lt_i32 s3, 0
; GFX6-NEXT: s_cselect_b32 s6, s3, 0
; GFX6-NEXT: s_sub_i32 s6, s9, s6
; GFX6-NEXT: s_cmp_gt_i32 s6, s4
; GFX6-NEXT: s_cselect_b32 s4, s6, s4
; GFX6-NEXT: s_cmp_lt_i32 s4, s5
; GFX6-NEXT: s_cselect_b32 s4, s4, s5
; GFX6-NEXT: s_add_i32 s3, s3, s4
; GFX6-NEXT: s_movk_i32 s4, 0xff		; GFX6-NEXT: s_movk_i32 s4, 0xff
; GFX6-NEXT: s_and_b32 s1, s1, s4		; GFX6-NEXT: s_cselect_b32 s1, s1, s8
		; GFX6-NEXT: s_and_b32 s2, s2, s4
; GFX6-NEXT: s_and_b32 s0, s0, s4		; GFX6-NEXT: s_and_b32 s0, s0, s4
; GFX6-NEXT: s_lshl_b32 s1, s1, 8		; GFX6-NEXT: s_lshl_b32 s2, s2, 8
; GFX6-NEXT: s_or_b32 s0, s0, s1		; GFX6-NEXT: s_or_b32 s0, s0, s2
; GFX6-NEXT: s_and_b32 s1, s2, s4		; GFX6-NEXT: s_and_b32 s2, s3, s4
; GFX6-NEXT: s_lshl_b32 s1, s1, 16		; GFX6-NEXT: s_and_b32 s1, s1, s4
; GFX6-NEXT: s_ashr_i32 s3, s3, 24		; GFX6-NEXT: s_lshl_b32 s2, s2, 16
; GFX6-NEXT: s_or_b32 s0, s0, s1		; GFX6-NEXT: s_or_b32 s0, s0, s2
; GFX6-NEXT: s_and_b32 s1, s3, s4
; GFX6-NEXT: s_lshl_b32 s1, s1, 24		; GFX6-NEXT: s_lshl_b32 s1, s1, 24
; GFX6-NEXT: s_or_b32 s0, s0, s1		; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: ; return to shader part epilog		; GFX6-NEXT: ; return to shader part epilog
;		;
; GFX8-LABEL: s_saddsat_v4i8:		; GFX8-LABEL: s_saddsat_v4i8:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_bfe_u32 s8, 8, 0x100000		; GFX8-NEXT: s_bfe_u32 s8, 8, 0x100000
; GFX8-NEXT: s_lshr_b32 s2, s0, 8		; GFX8-NEXT: s_lshr_b32 s2, s0, 8
▲ Show 20 Lines • Show All 194 Lines • ▼ Show 20 Lines	; GFX10-NEXT: ; return to shader part epilog
%cast.result = bitcast <4 x i8> %result to i32		%cast.result = bitcast <4 x i8> %result to i32
ret i32 %cast.result		ret i32 %cast.result
}		}

define i24 @v_saddsat_i24(i24 %lhs, i24 %rhs) {		define i24 @v_saddsat_i24(i24 %lhs, i24 %rhs) {
; GFX6-LABEL: v_saddsat_i24:		; GFX6-LABEL: v_saddsat_i24:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 8, v0		; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 24
; GFX6-NEXT: v_min_i32_e32 v3, 0, v0		; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 24
; GFX6-NEXT: v_max_i32_e32 v2, 0, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, 0x80000000, v3
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, 0x7fffffff, v2
; GFX6-NEXT: v_max_i32_e32 v1, v3, v1
; GFX6-NEXT: v_min_i32_e32 v1, v1, v2
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1		; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 8, v0		; GFX6-NEXT: v_max_i32_e32 v0, 0xff800000, v0
		; GFX6-NEXT: v_min_i32_e32 v0, 0x7fffff, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]		; GFX6-NEXT: s_setpc_b64 s[30:31]
;		;
; GFX8-LABEL: v_saddsat_i24:		; GFX8-LABEL: v_saddsat_i24:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_add_u32_e32 v2, vcc, v0, v1		; GFX8-NEXT: v_add_u32_e32 v2, vcc, v0, v1
; GFX8-NEXT: v_bfe_i32 v3, v2, 0, 24		; GFX8-NEXT: v_bfe_i32 v3, v2, 0, 24
; GFX8-NEXT: v_bfe_i32 v0, v0, 0, 24		; GFX8-NEXT: v_bfe_i32 v0, v0, 0, 24
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; GFX10-NEXT: s_setpc_b64 s[30:31]		; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call i24 @llvm.sadd.sat.i24(i24 %lhs, i24 %rhs)		%result = call i24 @llvm.sadd.sat.i24(i24 %lhs, i24 %rhs)
ret i24 %result		ret i24 %result
}		}

define amdgpu_ps i24 @s_saddsat_i24(i24 inreg %lhs, i24 inreg %rhs) {		define amdgpu_ps i24 @s_saddsat_i24(i24 inreg %lhs, i24 inreg %rhs) {
; GFX6-LABEL: s_saddsat_i24:		; GFX6-LABEL: s_saddsat_i24:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 8		; GFX6-NEXT: s_bfe_i32 s0, s0, 0x180000
; GFX6-NEXT: s_lshl_b32 s1, s1, 8		; GFX6-NEXT: s_bfe_i32 s1, s1, 0x180000
; GFX6-NEXT: s_cmp_gt_i32 s0, 0
; GFX6-NEXT: s_cselect_b32 s2, s0, 0
; GFX6-NEXT: s_sub_i32 s2, 0x7fffffff, s2
; GFX6-NEXT: s_cmp_lt_i32 s0, 0
; GFX6-NEXT: s_cselect_b32 s3, s0, 0
; GFX6-NEXT: s_sub_i32 s3, 0x80000000, s3
; GFX6-NEXT: s_cmp_gt_i32 s3, s1
; GFX6-NEXT: s_cselect_b32 s1, s3, s1
; GFX6-NEXT: s_cmp_lt_i32 s1, s2
; GFX6-NEXT: s_cselect_b32 s1, s1, s2
; GFX6-NEXT: s_add_i32 s0, s0, s1		; GFX6-NEXT: s_add_i32 s0, s0, s1
; GFX6-NEXT: s_ashr_i32 s0, s0, 8		; GFX6-NEXT: s_mov_b32 s1, 0xff800000
		; GFX6-NEXT: s_cmp_gt_i32 s0, s1
		; GFX6-NEXT: s_cselect_b32 s0, s0, s1
		; GFX6-NEXT: s_mov_b32 s1, 0x7fffff
		; GFX6-NEXT: s_cmp_lt_i32 s0, s1
		; GFX6-NEXT: s_cselect_b32 s0, s0, s1
; GFX6-NEXT: ; return to shader part epilog		; GFX6-NEXT: ; return to shader part epilog
;		;
; GFX8-LABEL: s_saddsat_i24:		; GFX8-LABEL: s_saddsat_i24:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_add_i32 s2, s0, s1		; GFX8-NEXT: s_add_i32 s2, s0, s1
; GFX8-NEXT: s_bfe_i32 s3, s2, 0x180000		; GFX8-NEXT: s_bfe_i32 s3, s2, 0x180000
; GFX8-NEXT: s_bfe_i32 s0, s0, 0x180000		; GFX8-NEXT: s_bfe_i32 s0, s0, 0x180000
; GFX8-NEXT: s_cmp_lt_i32 s3, s0		; GFX8-NEXT: s_cmp_lt_i32 s3, s0
▲ Show 20 Lines • Show All 1,790 Lines • ▼ Show 20 Lines	; GFX10-NEXT: ; return to shader part epilog
%result = call <16 x i32> @llvm.sadd.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)		%result = call <16 x i32> @llvm.sadd.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)
ret <16 x i32> %result		ret <16 x i32> %result
}		}

define i16 @v_saddsat_i16(i16 %lhs, i16 %rhs) {		define i16 @v_saddsat_i16(i16 %lhs, i16 %rhs) {
; GFX6-LABEL: v_saddsat_i16:		; GFX6-LABEL: v_saddsat_i16:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0		; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX6-NEXT: v_min_i32_e32 v3, 0, v0		; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16
; GFX6-NEXT: v_max_i32_e32 v2, 0, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, 0x80000000, v3
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, 0x7fffffff, v2
; GFX6-NEXT: v_max_i32_e32 v1, v3, v1
; GFX6-NEXT: v_min_i32_e32 v1, v1, v2
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1		; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 16, v0		; GFX6-NEXT: v_max_i32_e32 v0, 0xffff8000, v0
		; GFX6-NEXT: v_min_i32_e32 v0, 0x7fff, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]		; GFX6-NEXT: s_setpc_b64 s[30:31]
;		;
; GFX8-LABEL: v_saddsat_i16:		; GFX8-LABEL: v_saddsat_i16:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_min_i16_e32 v3, 0, v0		; GFX8-NEXT: v_min_i16_e32 v3, 0, v0
; GFX8-NEXT: v_max_i16_e32 v2, 0, v0		; GFX8-NEXT: v_max_i16_e32 v2, 0, v0
; GFX8-NEXT: v_sub_u16_e32 v3, 0x8000, v3		; GFX8-NEXT: v_sub_u16_e32 v3, 0x8000, v3
Show All 18 Lines
; GFX10-NEXT: s_setpc_b64 s[30:31]		; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call i16 @llvm.sadd.sat.i16(i16 %lhs, i16 %rhs)		%result = call i16 @llvm.sadd.sat.i16(i16 %lhs, i16 %rhs)
ret i16 %result		ret i16 %result
}		}

define amdgpu_ps i16 @s_saddsat_i16(i16 inreg %lhs, i16 inreg %rhs) {		define amdgpu_ps i16 @s_saddsat_i16(i16 inreg %lhs, i16 inreg %rhs) {
; GFX6-LABEL: s_saddsat_i16:		; GFX6-LABEL: s_saddsat_i16:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 16		; GFX6-NEXT: s_sext_i32_i16 s0, s0
; GFX6-NEXT: s_lshl_b32 s1, s1, 16		; GFX6-NEXT: s_sext_i32_i16 s1, s1
; GFX6-NEXT: s_cmp_gt_i32 s0, 0
; GFX6-NEXT: s_cselect_b32 s2, s0, 0
; GFX6-NEXT: s_sub_i32 s2, 0x7fffffff, s2
; GFX6-NEXT: s_cmp_lt_i32 s0, 0
; GFX6-NEXT: s_cselect_b32 s3, s0, 0
; GFX6-NEXT: s_sub_i32 s3, 0x80000000, s3
; GFX6-NEXT: s_cmp_gt_i32 s3, s1
; GFX6-NEXT: s_cselect_b32 s1, s3, s1
; GFX6-NEXT: s_cmp_lt_i32 s1, s2
; GFX6-NEXT: s_cselect_b32 s1, s1, s2
; GFX6-NEXT: s_add_i32 s0, s0, s1		; GFX6-NEXT: s_add_i32 s0, s0, s1
; GFX6-NEXT: s_ashr_i32 s0, s0, 16		; GFX6-NEXT: s_movk_i32 s1, 0x8000
		; GFX6-NEXT: s_cmp_gt_i32 s0, s1
		; GFX6-NEXT: s_cselect_b32 s0, s0, s1
		; GFX6-NEXT: s_movk_i32 s1, 0x7fff
		; GFX6-NEXT: s_cmp_lt_i32 s0, s1
		; GFX6-NEXT: s_cselect_b32 s0, s0, s1
; GFX6-NEXT: ; return to shader part epilog		; GFX6-NEXT: ; return to shader part epilog
;		;
; GFX8-LABEL: s_saddsat_i16:		; GFX8-LABEL: s_saddsat_i16:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_sext_i32_i16 s2, s0		; GFX8-NEXT: s_sext_i32_i16 s2, s0
; GFX8-NEXT: s_sext_i32_i16 s3, 0		; GFX8-NEXT: s_sext_i32_i16 s3, 0
; GFX8-NEXT: s_cmp_gt_i32 s2, s3		; GFX8-NEXT: s_cmp_gt_i32 s2, s3
; GFX8-NEXT: s_cselect_b32 s4, s2, s3		; GFX8-NEXT: s_cselect_b32 s4, s2, s3
Show All 27 Lines
; GFX10-NEXT: ; return to shader part epilog		; GFX10-NEXT: ; return to shader part epilog
%result = call i16 @llvm.sadd.sat.i16(i16 %lhs, i16 %rhs)		%result = call i16 @llvm.sadd.sat.i16(i16 %lhs, i16 %rhs)
ret i16 %result		ret i16 %result
}		}

define amdgpu_ps half @saddsat_i16_sv(i16 inreg %lhs, i16 %rhs) {		define amdgpu_ps half @saddsat_i16_sv(i16 inreg %lhs, i16 %rhs) {
; GFX6-LABEL: saddsat_i16_sv:		; GFX6-LABEL: saddsat_i16_sv:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 16		; GFX6-NEXT: s_sext_i32_i16 s0, s0
; GFX6-NEXT: s_cmp_gt_i32 s0, 0		; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX6-NEXT: s_cselect_b32 s1, s0, 0
; GFX6-NEXT: s_sub_i32 s1, 0x7fffffff, s1
; GFX6-NEXT: s_cmp_lt_i32 s0, 0
; GFX6-NEXT: s_cselect_b32 s2, s0, 0
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX6-NEXT: s_sub_i32 s2, 0x80000000, s2
; GFX6-NEXT: v_max_i32_e32 v0, s2, v0
; GFX6-NEXT: v_min_i32_e32 v0, s1, v0
; GFX6-NEXT: v_add_i32_e32 v0, vcc, s0, v0		; GFX6-NEXT: v_add_i32_e32 v0, vcc, s0, v0
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 16, v0		; GFX6-NEXT: v_max_i32_e32 v0, 0xffff8000, v0
		; GFX6-NEXT: v_min_i32_e32 v0, 0x7fff, v0
; GFX6-NEXT: ; return to shader part epilog		; GFX6-NEXT: ; return to shader part epilog
;		;
; GFX8-LABEL: saddsat_i16_sv:		; GFX8-LABEL: saddsat_i16_sv:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_sext_i32_i16 s1, s0		; GFX8-NEXT: s_sext_i32_i16 s1, s0
; GFX8-NEXT: s_sext_i32_i16 s2, 0		; GFX8-NEXT: s_sext_i32_i16 s2, 0
; GFX8-NEXT: s_cmp_gt_i32 s1, s2		; GFX8-NEXT: s_cmp_gt_i32 s1, s2
; GFX8-NEXT: s_cselect_b32 s3, s1, s2		; GFX8-NEXT: s_cselect_b32 s3, s1, s2
Show All 19 Lines	; GFX10-NEXT: ; return to shader part epilog
%result = call i16 @llvm.sadd.sat.i16(i16 %lhs, i16 %rhs)		%result = call i16 @llvm.sadd.sat.i16(i16 %lhs, i16 %rhs)
%cast = bitcast i16 %result to half		%cast = bitcast i16 %result to half
ret half %cast		ret half %cast
}		}

define amdgpu_ps half @saddsat_i16_vs(i16 %lhs, i16 inreg %rhs) {		define amdgpu_ps half @saddsat_i16_vs(i16 %lhs, i16 inreg %rhs) {
; GFX6-LABEL: saddsat_i16_vs:		; GFX6-LABEL: saddsat_i16_vs:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0		; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX6-NEXT: v_min_i32_e32 v2, 0, v0		; GFX6-NEXT: s_sext_i32_i16 s0, s0
; GFX6-NEXT: v_max_i32_e32 v1, 0, v0		; GFX6-NEXT: v_add_i32_e32 v0, vcc, s0, v0
; GFX6-NEXT: s_lshl_b32 s0, s0, 16		; GFX6-NEXT: v_max_i32_e32 v0, 0xffff8000, v0
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, 0x80000000, v2		; GFX6-NEXT: v_min_i32_e32 v0, 0x7fff, v0
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, 0x7fffffff, v1
; GFX6-NEXT: v_max_i32_e32 v2, s0, v2
; GFX6-NEXT: v_min_i32_e32 v1, v2, v1
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 16, v0
; GFX6-NEXT: ; return to shader part epilog		; GFX6-NEXT: ; return to shader part epilog
;		;
; GFX8-LABEL: saddsat_i16_vs:		; GFX8-LABEL: saddsat_i16_vs:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: v_min_i16_e32 v2, 0, v0		; GFX8-NEXT: v_min_i16_e32 v2, 0, v0
; GFX8-NEXT: v_max_i16_e32 v1, 0, v0		; GFX8-NEXT: v_max_i16_e32 v1, 0, v0
; GFX8-NEXT: v_sub_u16_e32 v2, 0x8000, v2		; GFX8-NEXT: v_sub_u16_e32 v2, 0x8000, v2
; GFX8-NEXT: v_sub_u16_e32 v1, 0x7fff, v1		; GFX8-NEXT: v_sub_u16_e32 v1, 0x7fff, v1
Show All 16 Lines	; GFX10-NEXT: ; return to shader part epilog
%cast = bitcast i16 %result to half		%cast = bitcast i16 %result to half
ret half %cast		ret half %cast
}		}

define <2 x i16> @v_saddsat_v2i16(<2 x i16> %lhs, <2 x i16> %rhs) {		define <2 x i16> @v_saddsat_v2i16(<2 x i16> %lhs, <2 x i16> %rhs) {
; GFX6-LABEL: v_saddsat_v2i16:		; GFX6-LABEL: v_saddsat_v2i16:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0		; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX6-NEXT: s_brev_b32 s5, 1		; GFX6-NEXT: v_bfe_i32 v2, v2, 0, 16
; GFX6-NEXT: v_min_i32_e32 v5, 0, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX6-NEXT: v_sub_i32_e32 v5, vcc, s5, v5
; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_max_i32_e32 v4, 0, v0
; GFX6-NEXT: v_sub_i32_e32 v4, vcc, s4, v4
; GFX6-NEXT: v_max_i32_e32 v2, v5, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_min_i32_e32 v2, v2, v4
; GFX6-NEXT: v_min_i32_e32 v4, 0, v1
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2		; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v3		; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16
; GFX6-NEXT: v_max_i32_e32 v3, 0, v1		; GFX6-NEXT: v_bfe_i32 v2, v3, 0, 16
; GFX6-NEXT: v_sub_i32_e32 v4, vcc, s5, v4		; GFX6-NEXT: s_movk_i32 s4, 0x8000
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s4, v3
; GFX6-NEXT: v_max_i32_e32 v2, v4, v2
; GFX6-NEXT: v_min_i32_e32 v2, v2, v3
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v2		; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v2
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 16, v0		; GFX6-NEXT: v_max_i32_e32 v0, s4, v0
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 16, v1		; GFX6-NEXT: s_movk_i32 s5, 0x7fff
		; GFX6-NEXT: v_max_i32_e32 v1, s4, v1
		; GFX6-NEXT: v_min_i32_e32 v0, s5, v0
		; GFX6-NEXT: v_min_i32_e32 v1, s5, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]		; GFX6-NEXT: s_setpc_b64 s[30:31]
;		;
; GFX8-LABEL: v_saddsat_v2i16:		; GFX8-LABEL: v_saddsat_v2i16:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: s_movk_i32 s5, 0x8000		; GFX8-NEXT: s_movk_i32 s5, 0x8000
; GFX8-NEXT: v_min_i16_e32 v4, 0, v0		; GFX8-NEXT: v_min_i16_e32 v4, 0, v0
; GFX8-NEXT: v_sub_u16_e32 v4, s5, v4		; GFX8-NEXT: v_sub_u16_e32 v4, s5, v4
Show All 29 Lines
; GFX10-NEXT: s_setpc_b64 s[30:31]		; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)		%result = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
ret <2 x i16> %result		ret <2 x i16> %result
}		}

define amdgpu_ps i32 @s_saddsat_v2i16(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs) {		define amdgpu_ps i32 @s_saddsat_v2i16(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs) {
; GFX6-LABEL: s_saddsat_v2i16:		; GFX6-LABEL: s_saddsat_v2i16:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 16		; GFX6-NEXT: s_sext_i32_i16 s0, s0
; GFX6-NEXT: s_lshl_b32 s2, s2, 16		; GFX6-NEXT: s_sext_i32_i16 s2, s2
; GFX6-NEXT: s_cmp_gt_i32 s0, 0
; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: s_cselect_b32 s6, s0, 0
; GFX6-NEXT: s_sub_i32 s6, s4, s6
; GFX6-NEXT: s_cmp_lt_i32 s0, 0
; GFX6-NEXT: s_brev_b32 s5, 1
; GFX6-NEXT: s_cselect_b32 s7, s0, 0
; GFX6-NEXT: s_sub_i32 s7, s5, s7
; GFX6-NEXT: s_cmp_gt_i32 s7, s2
; GFX6-NEXT: s_cselect_b32 s2, s7, s2
; GFX6-NEXT: s_cmp_lt_i32 s2, s6
; GFX6-NEXT: s_cselect_b32 s2, s2, s6
; GFX6-NEXT: s_add_i32 s0, s0, s2		; GFX6-NEXT: s_add_i32 s0, s0, s2
; GFX6-NEXT: s_ashr_i32 s0, s0, 16		; GFX6-NEXT: s_movk_i32 s2, 0x8000
; GFX6-NEXT: s_lshl_b32 s1, s1, 16		; GFX6-NEXT: s_cmp_gt_i32 s0, s2
; GFX6-NEXT: s_lshl_b32 s2, s3, 16		; GFX6-NEXT: s_cselect_b32 s0, s0, s2
; GFX6-NEXT: s_cmp_gt_i32 s1, 0		; GFX6-NEXT: s_movk_i32 s4, 0x7fff
; GFX6-NEXT: s_cselect_b32 s3, s1, 0		; GFX6-NEXT: s_cmp_lt_i32 s0, s4
; GFX6-NEXT: s_sub_i32 s3, s4, s3		; GFX6-NEXT: s_sext_i32_i16 s1, s1
; GFX6-NEXT: s_cmp_lt_i32 s1, 0		; GFX6-NEXT: s_sext_i32_i16 s3, s3
; GFX6-NEXT: s_cselect_b32 s4, s1, 0		; GFX6-NEXT: s_cselect_b32 s0, s0, s4
; GFX6-NEXT: s_sub_i32 s4, s5, s4		; GFX6-NEXT: s_add_i32 s1, s1, s3
; GFX6-NEXT: s_cmp_gt_i32 s4, s2		; GFX6-NEXT: s_cmp_gt_i32 s1, s2
; GFX6-NEXT: s_cselect_b32 s2, s4, s2		; GFX6-NEXT: s_cselect_b32 s1, s1, s2
; GFX6-NEXT: s_cmp_lt_i32 s2, s3		; GFX6-NEXT: s_cmp_lt_i32 s1, s4
; GFX6-NEXT: s_cselect_b32 s2, s2, s3		; GFX6-NEXT: s_cselect_b32 s1, s1, s4
; GFX6-NEXT: s_add_i32 s1, s1, s2
; GFX6-NEXT: s_mov_b32 s2, 0xffff		; GFX6-NEXT: s_mov_b32 s2, 0xffff
; GFX6-NEXT: s_ashr_i32 s1, s1, 16
; GFX6-NEXT: s_and_b32 s1, s1, s2		; GFX6-NEXT: s_and_b32 s1, s1, s2
; GFX6-NEXT: s_and_b32 s0, s0, s2		; GFX6-NEXT: s_and_b32 s0, s0, s2
; GFX6-NEXT: s_lshl_b32 s1, s1, 16		; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_or_b32 s0, s0, s1		; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: ; return to shader part epilog		; GFX6-NEXT: ; return to shader part epilog
;		;
; GFX8-LABEL: s_saddsat_v2i16:		; GFX8-LABEL: s_saddsat_v2i16:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines	; GFX10-NEXT: ; return to shader part epilog
%result = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)		%result = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
%cast = bitcast <2 x i16> %result to i32		%cast = bitcast <2 x i16> %result to i32
ret i32 %cast		ret i32 %cast
}		}

define amdgpu_ps float @saddsat_v2i16_sv(<2 x i16> inreg %lhs, <2 x i16> %rhs) {		define amdgpu_ps float @saddsat_v2i16_sv(<2 x i16> inreg %lhs, <2 x i16> %rhs) {
; GFX6-LABEL: saddsat_v2i16_sv:		; GFX6-LABEL: saddsat_v2i16_sv:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 16		; GFX6-NEXT: s_sext_i32_i16 s0, s0
; GFX6-NEXT: s_cmp_gt_i32 s0, 0		; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX6-NEXT: s_brev_b32 s2, -2		; GFX6-NEXT: s_sext_i32_i16 s1, s1
; GFX6-NEXT: s_cselect_b32 s4, s0, 0		; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16
; GFX6-NEXT: s_sub_i32 s4, s2, s4
; GFX6-NEXT: s_cmp_lt_i32 s0, 0
; GFX6-NEXT: s_brev_b32 s3, 1
; GFX6-NEXT: s_cselect_b32 s5, s0, 0
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX6-NEXT: s_sub_i32 s5, s3, s5
; GFX6-NEXT: v_max_i32_e32 v0, s5, v0
; GFX6-NEXT: v_min_i32_e32 v0, s4, v0
; GFX6-NEXT: v_add_i32_e32 v0, vcc, s0, v0		; GFX6-NEXT: v_add_i32_e32 v0, vcc, s0, v0
; GFX6-NEXT: s_lshl_b32 s0, s1, 16		; GFX6-NEXT: s_movk_i32 s0, 0x8000
; GFX6-NEXT: s_cmp_gt_i32 s0, 0		; GFX6-NEXT: v_add_i32_e32 v1, vcc, s1, v1
; GFX6-NEXT: s_cselect_b32 s1, s0, 0		; GFX6-NEXT: s_movk_i32 s2, 0x7fff
; GFX6-NEXT: s_sub_i32 s1, s2, s1		; GFX6-NEXT: v_max_i32_e32 v1, s0, v1
; GFX6-NEXT: s_cmp_lt_i32 s0, 0		; GFX6-NEXT: v_max_i32_e32 v0, s0, v0
; GFX6-NEXT: s_cselect_b32 s2, s0, 0		; GFX6-NEXT: v_min_i32_e32 v1, s2, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: s_sub_i32 s2, s3, s2
; GFX6-NEXT: v_max_i32_e32 v1, s2, v1
; GFX6-NEXT: v_min_i32_e32 v1, s1, v1
; GFX6-NEXT: v_add_i32_e32 v1, vcc, s0, v1
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 16, v1
; GFX6-NEXT: s_mov_b32 s0, 0xffff		; GFX6-NEXT: s_mov_b32 s0, 0xffff
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 16, v0		; GFX6-NEXT: v_min_i32_e32 v0, s2, v0
; GFX6-NEXT: v_and_b32_e32 v1, s0, v1		; GFX6-NEXT: v_and_b32_e32 v1, s0, v1
; GFX6-NEXT: v_and_b32_e32 v0, s0, v0		; GFX6-NEXT: v_and_b32_e32 v0, s0, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1		; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1		; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: ; return to shader part epilog		; GFX6-NEXT: ; return to shader part epilog
;		;
; GFX8-LABEL: saddsat_v2i16_sv:		; GFX8-LABEL: saddsat_v2i16_sv:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
Show All 39 Lines	; GFX10-NEXT: ; return to shader part epilog
%result = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)		%result = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
%cast = bitcast <2 x i16> %result to float		%cast = bitcast <2 x i16> %result to float
ret float %cast		ret float %cast
}		}

define amdgpu_ps float @saddsat_v2i16_vs(<2 x i16> %lhs, <2 x i16> inreg %rhs) {		define amdgpu_ps float @saddsat_v2i16_vs(<2 x i16> %lhs, <2 x i16> inreg %rhs) {
; GFX6-LABEL: saddsat_v2i16_vs:		; GFX6-LABEL: saddsat_v2i16_vs:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0		; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX6-NEXT: s_brev_b32 s3, 1		; GFX6-NEXT: s_sext_i32_i16 s0, s0
; GFX6-NEXT: v_min_i32_e32 v3, 0, v0		; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16
; GFX6-NEXT: s_lshl_b32 s0, s0, 16		; GFX6-NEXT: s_sext_i32_i16 s1, s1
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s3, v3		; GFX6-NEXT: v_add_i32_e32 v0, vcc, s0, v0
; GFX6-NEXT: s_brev_b32 s2, -2		; GFX6-NEXT: s_movk_i32 s0, 0x8000
; GFX6-NEXT: v_max_i32_e32 v2, 0, v0		; GFX6-NEXT: v_add_i32_e32 v1, vcc, s1, v1
; GFX6-NEXT: v_max_i32_e32 v3, s0, v3		; GFX6-NEXT: s_movk_i32 s2, 0x7fff
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s2, v2		; GFX6-NEXT: v_max_i32_e32 v1, s0, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1		; GFX6-NEXT: v_max_i32_e32 v0, s0, v0
; GFX6-NEXT: v_min_i32_e32 v2, v3, v2		; GFX6-NEXT: v_min_i32_e32 v1, s2, v1
; GFX6-NEXT: v_min_i32_e32 v3, 0, v1
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GFX6-NEXT: v_max_i32_e32 v2, 0, v1
; GFX6-NEXT: s_lshl_b32 s0, s1, 16
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s3, v3
; GFX6-NEXT: v_max_i32_e32 v3, s0, v3
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s2, v2
; GFX6-NEXT: v_min_i32_e32 v2, v3, v2
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v2
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 16, v1
; GFX6-NEXT: s_mov_b32 s0, 0xffff		; GFX6-NEXT: s_mov_b32 s0, 0xffff
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 16, v0		; GFX6-NEXT: v_min_i32_e32 v0, s2, v0
; GFX6-NEXT: v_and_b32_e32 v1, s0, v1		; GFX6-NEXT: v_and_b32_e32 v1, s0, v1
; GFX6-NEXT: v_and_b32_e32 v0, s0, v0		; GFX6-NEXT: v_and_b32_e32 v0, s0, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1		; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1		; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: ; return to shader part epilog		; GFX6-NEXT: ; return to shader part epilog
;		;
; GFX8-LABEL: saddsat_v2i16_vs:		; GFX8-LABEL: saddsat_v2i16_vs:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; %result = call <3 x i16> @llvm.sadd.sat.v3i16(<3 x i16> %lhs, <3 x i16> %rhs)		; %result = call <3 x i16> @llvm.sadd.sat.v3i16(<3 x i16> %lhs, <3 x i16> %rhs)
; ret <3 x i16> %result		; ret <3 x i16> %result
; }		; }

define <2 x float> @v_saddsat_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {		define <2 x float> @v_saddsat_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
; GFX6-LABEL: v_saddsat_v4i16:		; GFX6-LABEL: v_saddsat_v4i16:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0		; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX6-NEXT: s_brev_b32 s5, 1		; GFX6-NEXT: v_bfe_i32 v4, v4, 0, 16
; GFX6-NEXT: v_min_i32_e32 v10, 0, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX6-NEXT: v_sub_i32_e32 v10, vcc, s5, v10
; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_max_i32_e32 v8, 0, v0
; GFX6-NEXT: v_sub_i32_e32 v8, vcc, s4, v8
; GFX6-NEXT: v_max_i32_e32 v4, v10, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_min_i32_e32 v4, v4, v8
; GFX6-NEXT: v_min_i32_e32 v8, 0, v1
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v4		; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v5		; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16
; GFX6-NEXT: v_max_i32_e32 v5, 0, v1		; GFX6-NEXT: v_bfe_i32 v4, v5, 0, 16
; GFX6-NEXT: v_sub_i32_e32 v8, vcc, s5, v8
; GFX6-NEXT: v_sub_i32_e32 v5, vcc, s4, v5
; GFX6-NEXT: v_max_i32_e32 v4, v8, v4
; GFX6-NEXT: v_min_i32_e32 v4, v4, v5
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v4		; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v6		; GFX6-NEXT: v_bfe_i32 v2, v2, 0, 16
; GFX6-NEXT: v_min_i32_e32 v6, 0, v2		; GFX6-NEXT: v_bfe_i32 v4, v6, 0, 16
; GFX6-NEXT: v_sub_i32_e32 v6, vcc, s5, v6		; GFX6-NEXT: s_movk_i32 s4, 0x8000
; GFX6-NEXT: v_bfrev_b32_e32 v9, -2
; GFX6-NEXT: v_max_i32_e32 v5, 0, v2
; GFX6-NEXT: v_sub_i32_e32 v5, vcc, v9, v5
; GFX6-NEXT: v_max_i32_e32 v4, v6, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX6-NEXT: v_min_i32_e32 v4, v4, v5
; GFX6-NEXT: v_bfrev_b32_e32 v11, 1
; GFX6-NEXT: v_min_i32_e32 v6, 0, v3
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4		; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; GFX6-NEXT: v_max_i32_e32 v5, 0, v3		; GFX6-NEXT: v_bfe_i32 v3, v3, 0, 16
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v7		; GFX6-NEXT: v_bfe_i32 v4, v7, 0, 16
; GFX6-NEXT: v_sub_i32_e32 v6, vcc, v11, v6
; GFX6-NEXT: v_sub_i32_e32 v5, vcc, v9, v5
; GFX6-NEXT: v_max_i32_e32 v4, v6, v4
; GFX6-NEXT: v_min_i32_e32 v4, v4, v5
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 16, v1
; GFX6-NEXT: s_mov_b32 s4, 0xffff
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 16, v0
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v4		; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v4
		; GFX6-NEXT: s_movk_i32 s5, 0x7fff
		; GFX6-NEXT: v_max_i32_e32 v1, s4, v1
		; GFX6-NEXT: v_max_i32_e32 v0, s4, v0
		; GFX6-NEXT: v_max_i32_e32 v2, s4, v2
		; GFX6-NEXT: v_max_i32_e32 v3, s4, v3
		; GFX6-NEXT: v_min_i32_e32 v1, s5, v1
		; GFX6-NEXT: s_mov_b32 s4, 0xffff
		; GFX6-NEXT: v_min_i32_e32 v0, s5, v0
; GFX6-NEXT: v_and_b32_e32 v1, s4, v1		; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
; GFX6-NEXT: v_ashrrev_i32_e32 v2, 16, v2		; GFX6-NEXT: v_min_i32_e32 v2, s5, v2
; GFX6-NEXT: v_ashrrev_i32_e32 v3, 16, v3		; GFX6-NEXT: v_min_i32_e32 v3, s5, v3
; GFX6-NEXT: v_and_b32_e32 v0, s4, v0		; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1		; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1		; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: v_and_b32_e32 v1, s4, v2		; GFX6-NEXT: v_and_b32_e32 v1, s4, v2
; GFX6-NEXT: v_and_b32_e32 v2, s4, v3		; GFX6-NEXT: v_and_b32_e32 v2, s4, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2		; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX6-NEXT: v_or_b32_e32 v1, v1, v2		; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
; GFX6-NEXT: s_setpc_b64 s[30:31]		; GFX6-NEXT: s_setpc_b64 s[30:31]
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines	; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <4 x i16> @llvm.sadd.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)		%result = call <4 x i16> @llvm.sadd.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
%cast = bitcast <4 x i16> %result to <2 x float>		%cast = bitcast <4 x i16> %result to <2 x float>
ret <2 x float> %cast		ret <2 x float> %cast
}		}

define amdgpu_ps <2 x i32> @s_saddsat_v4i16(<4 x i16> inreg %lhs, <4 x i16> inreg %rhs) {		define amdgpu_ps <2 x i32> @s_saddsat_v4i16(<4 x i16> inreg %lhs, <4 x i16> inreg %rhs) {
; GFX6-LABEL: s_saddsat_v4i16:		; GFX6-LABEL: s_saddsat_v4i16:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 16		; GFX6-NEXT: s_sext_i32_i16 s0, s0
; GFX6-NEXT: s_lshl_b32 s4, s4, 16		; GFX6-NEXT: s_sext_i32_i16 s4, s4
; GFX6-NEXT: s_cmp_gt_i32 s0, 0
; GFX6-NEXT: s_brev_b32 s8, -2
; GFX6-NEXT: s_cselect_b32 s10, s0, 0
; GFX6-NEXT: s_sub_i32 s10, s8, s10
; GFX6-NEXT: s_cmp_lt_i32 s0, 0
; GFX6-NEXT: s_brev_b32 s9, 1
; GFX6-NEXT: s_cselect_b32 s11, s0, 0
; GFX6-NEXT: s_sub_i32 s11, s9, s11
; GFX6-NEXT: s_cmp_gt_i32 s11, s4
; GFX6-NEXT: s_cselect_b32 s4, s11, s4
; GFX6-NEXT: s_cmp_lt_i32 s4, s10
; GFX6-NEXT: s_cselect_b32 s4, s4, s10
; GFX6-NEXT: s_add_i32 s0, s0, s4		; GFX6-NEXT: s_add_i32 s0, s0, s4
; GFX6-NEXT: s_ashr_i32 s0, s0, 16		; GFX6-NEXT: s_movk_i32 s4, 0x8000
; GFX6-NEXT: s_lshl_b32 s1, s1, 16		; GFX6-NEXT: s_cmp_gt_i32 s0, s4
; GFX6-NEXT: s_lshl_b32 s4, s5, 16		; GFX6-NEXT: s_cselect_b32 s0, s0, s4
; GFX6-NEXT: s_cmp_gt_i32 s1, 0		; GFX6-NEXT: s_movk_i32 s8, 0x7fff
; GFX6-NEXT: s_cselect_b32 s5, s1, 0		; GFX6-NEXT: s_cmp_lt_i32 s0, s8
; GFX6-NEXT: s_sub_i32 s5, s8, s5		; GFX6-NEXT: s_sext_i32_i16 s1, s1
; GFX6-NEXT: s_cmp_lt_i32 s1, 0		; GFX6-NEXT: s_sext_i32_i16 s5, s5
; GFX6-NEXT: s_cselect_b32 s10, s1, 0		; GFX6-NEXT: s_cselect_b32 s0, s0, s8
; GFX6-NEXT: s_sub_i32 s10, s9, s10		; GFX6-NEXT: s_add_i32 s1, s1, s5
; GFX6-NEXT: s_cmp_gt_i32 s10, s4		; GFX6-NEXT: s_cmp_gt_i32 s1, s4
; GFX6-NEXT: s_cselect_b32 s4, s10, s4		; GFX6-NEXT: s_cselect_b32 s1, s1, s4
; GFX6-NEXT: s_cmp_lt_i32 s4, s5		; GFX6-NEXT: s_cmp_lt_i32 s1, s8
; GFX6-NEXT: s_cselect_b32 s4, s4, s5		; GFX6-NEXT: s_sext_i32_i16 s2, s2
; GFX6-NEXT: s_add_i32 s1, s1, s4		; GFX6-NEXT: s_sext_i32_i16 s5, s6
; GFX6-NEXT: s_ashr_i32 s1, s1, 16		; GFX6-NEXT: s_cselect_b32 s1, s1, s8
; GFX6-NEXT: s_lshl_b32 s2, s2, 16		; GFX6-NEXT: s_add_i32 s2, s2, s5
; GFX6-NEXT: s_lshl_b32 s4, s6, 16		; GFX6-NEXT: s_cmp_gt_i32 s2, s4
; GFX6-NEXT: s_cmp_gt_i32 s2, 0		; GFX6-NEXT: s_cselect_b32 s2, s2, s4
; GFX6-NEXT: s_cselect_b32 s5, s2, 0		; GFX6-NEXT: s_cmp_lt_i32 s2, s8
; GFX6-NEXT: s_sub_i32 s5, s8, s5		; GFX6-NEXT: s_sext_i32_i16 s3, s3
; GFX6-NEXT: s_cmp_lt_i32 s2, 0		; GFX6-NEXT: s_sext_i32_i16 s5, s7
; GFX6-NEXT: s_cselect_b32 s6, s2, 0		; GFX6-NEXT: s_cselect_b32 s2, s2, s8
; GFX6-NEXT: s_sub_i32 s6, s9, s6		; GFX6-NEXT: s_add_i32 s3, s3, s5
; GFX6-NEXT: s_cmp_gt_i32 s6, s4		; GFX6-NEXT: s_cmp_gt_i32 s3, s4
; GFX6-NEXT: s_cselect_b32 s4, s6, s4		; GFX6-NEXT: s_cselect_b32 s3, s3, s4
; GFX6-NEXT: s_cmp_lt_i32 s4, s5		; GFX6-NEXT: s_cmp_lt_i32 s3, s8
; GFX6-NEXT: s_cselect_b32 s4, s4, s5
; GFX6-NEXT: s_add_i32 s2, s2, s4
; GFX6-NEXT: s_ashr_i32 s2, s2, 16
; GFX6-NEXT: s_lshl_b32 s3, s3, 16
; GFX6-NEXT: s_lshl_b32 s4, s7, 16
; GFX6-NEXT: s_cmp_gt_i32 s3, 0
; GFX6-NEXT: s_cselect_b32 s5, s3, 0
; GFX6-NEXT: s_sub_i32 s5, s8, s5
; GFX6-NEXT: s_cmp_lt_i32 s3, 0
; GFX6-NEXT: s_cselect_b32 s6, s3, 0
; GFX6-NEXT: s_sub_i32 s6, s9, s6
; GFX6-NEXT: s_cmp_gt_i32 s6, s4
; GFX6-NEXT: s_cselect_b32 s4, s6, s4
; GFX6-NEXT: s_cmp_lt_i32 s4, s5
; GFX6-NEXT: s_cselect_b32 s4, s4, s5
; GFX6-NEXT: s_add_i32 s3, s3, s4
; GFX6-NEXT: s_mov_b32 s4, 0xffff		; GFX6-NEXT: s_mov_b32 s4, 0xffff
		; GFX6-NEXT: s_cselect_b32 s3, s3, s8
; GFX6-NEXT: s_and_b32 s1, s1, s4		; GFX6-NEXT: s_and_b32 s1, s1, s4
; GFX6-NEXT: s_ashr_i32 s3, s3, 16
; GFX6-NEXT: s_and_b32 s0, s0, s4		; GFX6-NEXT: s_and_b32 s0, s0, s4
; GFX6-NEXT: s_lshl_b32 s1, s1, 16		; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_or_b32 s0, s0, s1		; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: s_and_b32 s1, s2, s4		; GFX6-NEXT: s_and_b32 s1, s2, s4
; GFX6-NEXT: s_and_b32 s2, s3, s4		; GFX6-NEXT: s_and_b32 s2, s3, s4
; GFX6-NEXT: s_lshl_b32 s2, s2, 16		; GFX6-NEXT: s_lshl_b32 s2, s2, 16
; GFX6-NEXT: s_or_b32 s1, s1, s2		; GFX6-NEXT: s_or_b32 s1, s1, s2
; GFX6-NEXT: ; return to shader part epilog		; GFX6-NEXT: ; return to shader part epilog
▲ Show 20 Lines • Show All 114 Lines • ▼ Show 20 Lines
; %result = call <5 x i16> @llvm.sadd.sat.v5i16(<5 x i16> %lhs, <5 x i16> %rhs)		; %result = call <5 x i16> @llvm.sadd.sat.v5i16(<5 x i16> %lhs, <5 x i16> %rhs)
; ret <5 x i16> %result		; ret <5 x i16> %result
; }		; }

define <3 x float> @v_saddsat_v6i16(<6 x i16> %lhs, <6 x i16> %rhs) {		define <3 x float> @v_saddsat_v6i16(<6 x i16> %lhs, <6 x i16> %rhs) {
; GFX6-LABEL: v_saddsat_v6i16:		; GFX6-LABEL: v_saddsat_v6i16:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0		; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16
; GFX6-NEXT: s_brev_b32 s5, 1		; GFX6-NEXT: v_bfe_i32 v7, v7, 0, 16
; GFX6-NEXT: v_min_i32_e32 v14, 0, v0		; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v7
; GFX6-NEXT: v_lshlrev_b32_e32 v6, 16, v6		; GFX6-NEXT: v_bfe_i32 v2, v2, 0, 16
; GFX6-NEXT: v_sub_i32_e32 v14, vcc, s5, v14		; GFX6-NEXT: v_bfe_i32 v7, v8, 0, 16
; GFX6-NEXT: s_brev_b32 s4, -2		; GFX6-NEXT: s_movk_i32 s4, 0x8000
; GFX6-NEXT: v_max_i32_e32 v12, 0, v0		; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v7
; GFX6-NEXT: v_sub_i32_e32 v12, vcc, s4, v12		; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX6-NEXT: v_max_i32_e32 v6, v14, v6		; GFX6-NEXT: v_bfe_i32 v6, v6, 0, 16
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1		; GFX6-NEXT: v_bfe_i32 v3, v3, 0, 16
; GFX6-NEXT: v_min_i32_e32 v6, v6, v12		; GFX6-NEXT: v_bfe_i32 v7, v9, 0, 16
; GFX6-NEXT: v_min_i32_e32 v12, 0, v1
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v6		; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v6
; GFX6-NEXT: v_lshlrev_b32_e32 v6, 16, v7		; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v7
; GFX6-NEXT: v_max_i32_e32 v7, 0, v1		; GFX6-NEXT: s_movk_i32 s5, 0x7fff
; GFX6-NEXT: v_sub_i32_e32 v12, vcc, s5, v12		; GFX6-NEXT: v_max_i32_e32 v1, s4, v1
; GFX6-NEXT: v_sub_i32_e32 v7, vcc, s4, v7		; GFX6-NEXT: v_bfe_i32 v4, v4, 0, 16
; GFX6-NEXT: v_max_i32_e32 v6, v12, v6		; GFX6-NEXT: v_bfe_i32 v7, v10, 0, 16
; GFX6-NEXT: v_min_i32_e32 v6, v6, v7		; GFX6-NEXT: v_max_i32_e32 v0, s4, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2		; GFX6-NEXT: v_max_i32_e32 v2, s4, v2
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v6		; GFX6-NEXT: v_max_i32_e32 v3, s4, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v6, 16, v8		; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v7
; GFX6-NEXT: v_min_i32_e32 v8, 0, v2		; GFX6-NEXT: v_min_i32_e32 v1, s5, v1
; GFX6-NEXT: v_sub_i32_e32 v8, vcc, s5, v8
; GFX6-NEXT: v_bfrev_b32_e32 v13, -2
; GFX6-NEXT: v_max_i32_e32 v7, 0, v2
; GFX6-NEXT: v_sub_i32_e32 v7, vcc, v13, v7
; GFX6-NEXT: v_max_i32_e32 v6, v8, v6
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX6-NEXT: v_min_i32_e32 v6, v6, v7
; GFX6-NEXT: v_bfrev_b32_e32 v15, 1
; GFX6-NEXT: v_min_i32_e32 v8, 0, v3
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v6
; GFX6-NEXT: v_max_i32_e32 v7, 0, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v6, 16, v9
; GFX6-NEXT: v_sub_i32_e32 v8, vcc, v15, v8
; GFX6-NEXT: v_sub_i32_e32 v7, vcc, v13, v7
; GFX6-NEXT: v_max_i32_e32 v6, v8, v6
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX6-NEXT: v_min_i32_e32 v6, v6, v7
; GFX6-NEXT: v_min_i32_e32 v8, 0, v4
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v6
; GFX6-NEXT: v_max_i32_e32 v7, 0, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v6, 16, v10
; GFX6-NEXT: v_sub_i32_e32 v8, vcc, v15, v8
; GFX6-NEXT: v_sub_i32_e32 v7, vcc, v13, v7
; GFX6-NEXT: v_max_i32_e32 v6, v8, v6
; GFX6-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX6-NEXT: v_min_i32_e32 v6, v6, v7
; GFX6-NEXT: v_min_i32_e32 v8, 0, v5
; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v6
; GFX6-NEXT: v_max_i32_e32 v7, 0, v5
; GFX6-NEXT: v_lshlrev_b32_e32 v6, 16, v11
; GFX6-NEXT: v_sub_i32_e32 v8, vcc, v15, v8
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 16, v1
; GFX6-NEXT: s_mov_b32 s4, 0xffff		; GFX6-NEXT: s_mov_b32 s4, 0xffff
; GFX6-NEXT: v_sub_i32_e32 v7, vcc, v13, v7		; GFX6-NEXT: v_bfe_i32 v5, v5, 0, 16
; GFX6-NEXT: v_max_i32_e32 v6, v8, v6		; GFX6-NEXT: v_bfe_i32 v7, v11, 0, 16
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 16, v0		; GFX6-NEXT: v_min_i32_e32 v0, s5, v0
; GFX6-NEXT: v_and_b32_e32 v1, s4, v1		; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
; GFX6-NEXT: v_min_i32_e32 v6, v6, v7		; GFX6-NEXT: v_mov_b32_e32 v6, 0xffff8000
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v6		; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v7
; GFX6-NEXT: v_ashrrev_i32_e32 v2, 16, v2		; GFX6-NEXT: v_max_i32_e32 v5, v5, v6
; GFX6-NEXT: v_ashrrev_i32_e32 v3, 16, v3		; GFX6-NEXT: v_min_i32_e32 v2, s5, v2
		; GFX6-NEXT: v_min_i32_e32 v3, s5, v3
; GFX6-NEXT: v_and_b32_e32 v0, s4, v0		; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1		; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
		; GFX6-NEXT: v_max_i32_e32 v4, v4, v6
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1		; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: v_and_b32_e32 v1, s4, v2		; GFX6-NEXT: v_and_b32_e32 v1, s4, v2
; GFX6-NEXT: v_and_b32_e32 v2, s4, v3		; GFX6-NEXT: v_and_b32_e32 v2, s4, v3
; GFX6-NEXT: v_ashrrev_i32_e32 v5, 16, v5		; GFX6-NEXT: v_min_i32_e32 v5, 0x7fff, v5
; GFX6-NEXT: v_and_b32_e32 v3, s4, v5		; GFX6-NEXT: v_and_b32_e32 v3, s4, v5
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2		; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX6-NEXT: v_ashrrev_i32_e32 v4, 16, v4		; GFX6-NEXT: v_min_i32_e32 v4, s5, v4
; GFX6-NEXT: v_or_b32_e32 v1, v1, v2		; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
; GFX6-NEXT: v_and_b32_e32 v2, s4, v4		; GFX6-NEXT: v_and_b32_e32 v2, s4, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3		; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX6-NEXT: v_or_b32_e32 v2, v2, v3		; GFX6-NEXT: v_or_b32_e32 v2, v2, v3
; GFX6-NEXT: s_setpc_b64 s[30:31]		; GFX6-NEXT: s_setpc_b64 s[30:31]
;		;
; GFX8-LABEL: v_saddsat_v6i16:		; GFX8-LABEL: v_saddsat_v6i16:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
▲ Show 20 Lines • Show All 72 Lines • ▼ Show 20 Lines	; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <6 x i16> @llvm.sadd.sat.v6i16(<6 x i16> %lhs, <6 x i16> %rhs)		%result = call <6 x i16> @llvm.sadd.sat.v6i16(<6 x i16> %lhs, <6 x i16> %rhs)
%cast = bitcast <6 x i16> %result to <3 x float>		%cast = bitcast <6 x i16> %result to <3 x float>
ret <3 x float> %cast		ret <3 x float> %cast
}		}

define amdgpu_ps <3 x i32> @s_saddsat_v6i16(<6 x i16> inreg %lhs, <6 x i16> inreg %rhs) {		define amdgpu_ps <3 x i32> @s_saddsat_v6i16(<6 x i16> inreg %lhs, <6 x i16> inreg %rhs) {
; GFX6-LABEL: s_saddsat_v6i16:		; GFX6-LABEL: s_saddsat_v6i16:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 16		; GFX6-NEXT: s_sext_i32_i16 s0, s0
; GFX6-NEXT: s_lshl_b32 s6, s6, 16		; GFX6-NEXT: s_sext_i32_i16 s6, s6
; GFX6-NEXT: s_cmp_gt_i32 s0, 0
; GFX6-NEXT: s_brev_b32 s12, -2
; GFX6-NEXT: s_cselect_b32 s14, s0, 0
; GFX6-NEXT: s_sub_i32 s14, s12, s14
; GFX6-NEXT: s_cmp_lt_i32 s0, 0
; GFX6-NEXT: s_brev_b32 s13, 1
; GFX6-NEXT: s_cselect_b32 s15, s0, 0
; GFX6-NEXT: s_sub_i32 s15, s13, s15
; GFX6-NEXT: s_cmp_gt_i32 s15, s6
; GFX6-NEXT: s_cselect_b32 s6, s15, s6
; GFX6-NEXT: s_cmp_lt_i32 s6, s14
; GFX6-NEXT: s_cselect_b32 s6, s6, s14
; GFX6-NEXT: s_add_i32 s0, s0, s6		; GFX6-NEXT: s_add_i32 s0, s0, s6
; GFX6-NEXT: s_ashr_i32 s0, s0, 16		; GFX6-NEXT: s_movk_i32 s6, 0x8000
; GFX6-NEXT: s_lshl_b32 s1, s1, 16		; GFX6-NEXT: s_cmp_gt_i32 s0, s6
; GFX6-NEXT: s_lshl_b32 s6, s7, 16		; GFX6-NEXT: s_cselect_b32 s0, s0, s6
; GFX6-NEXT: s_cmp_gt_i32 s1, 0		; GFX6-NEXT: s_movk_i32 s12, 0x7fff
; GFX6-NEXT: s_cselect_b32 s7, s1, 0		; GFX6-NEXT: s_cmp_lt_i32 s0, s12
; GFX6-NEXT: s_sub_i32 s7, s12, s7		; GFX6-NEXT: s_sext_i32_i16 s1, s1
; GFX6-NEXT: s_cmp_lt_i32 s1, 0		; GFX6-NEXT: s_sext_i32_i16 s7, s7
; GFX6-NEXT: s_cselect_b32 s14, s1, 0		; GFX6-NEXT: s_cselect_b32 s0, s0, s12
; GFX6-NEXT: s_sub_i32 s14, s13, s14		; GFX6-NEXT: s_add_i32 s1, s1, s7
; GFX6-NEXT: s_cmp_gt_i32 s14, s6		; GFX6-NEXT: s_cmp_gt_i32 s1, s6
; GFX6-NEXT: s_cselect_b32 s6, s14, s6		; GFX6-NEXT: s_cselect_b32 s1, s1, s6
; GFX6-NEXT: s_cmp_lt_i32 s6, s7		; GFX6-NEXT: s_cmp_lt_i32 s1, s12
; GFX6-NEXT: s_cselect_b32 s6, s6, s7		; GFX6-NEXT: s_sext_i32_i16 s2, s2
; GFX6-NEXT: s_add_i32 s1, s1, s6		; GFX6-NEXT: s_sext_i32_i16 s7, s8
; GFX6-NEXT: s_ashr_i32 s1, s1, 16		; GFX6-NEXT: s_cselect_b32 s1, s1, s12
; GFX6-NEXT: s_lshl_b32 s2, s2, 16		; GFX6-NEXT: s_add_i32 s2, s2, s7
; GFX6-NEXT: s_lshl_b32 s6, s8, 16		; GFX6-NEXT: s_cmp_gt_i32 s2, s6
; GFX6-NEXT: s_cmp_gt_i32 s2, 0		; GFX6-NEXT: s_cselect_b32 s2, s2, s6
; GFX6-NEXT: s_cselect_b32 s7, s2, 0		; GFX6-NEXT: s_cmp_lt_i32 s2, s12
; GFX6-NEXT: s_sub_i32 s7, s12, s7		; GFX6-NEXT: s_sext_i32_i16 s3, s3
; GFX6-NEXT: s_cmp_lt_i32 s2, 0		; GFX6-NEXT: s_sext_i32_i16 s7, s9
; GFX6-NEXT: s_cselect_b32 s8, s2, 0		; GFX6-NEXT: s_cselect_b32 s2, s2, s12
; GFX6-NEXT: s_sub_i32 s8, s13, s8		; GFX6-NEXT: s_add_i32 s3, s3, s7
; GFX6-NEXT: s_cmp_gt_i32 s8, s6		; GFX6-NEXT: s_cmp_gt_i32 s3, s6
; GFX6-NEXT: s_cselect_b32 s6, s8, s6		; GFX6-NEXT: s_cselect_b32 s3, s3, s6
; GFX6-NEXT: s_cmp_lt_i32 s6, s7		; GFX6-NEXT: s_cmp_lt_i32 s3, s12
; GFX6-NEXT: s_cselect_b32 s6, s6, s7		; GFX6-NEXT: s_sext_i32_i16 s4, s4
; GFX6-NEXT: s_add_i32 s2, s2, s6		; GFX6-NEXT: s_sext_i32_i16 s7, s10
; GFX6-NEXT: s_ashr_i32 s2, s2, 16		; GFX6-NEXT: s_cselect_b32 s3, s3, s12
; GFX6-NEXT: s_lshl_b32 s3, s3, 16		; GFX6-NEXT: s_add_i32 s4, s4, s7
; GFX6-NEXT: s_lshl_b32 s6, s9, 16		; GFX6-NEXT: s_cmp_gt_i32 s4, s6
; GFX6-NEXT: s_cmp_gt_i32 s3, 0		; GFX6-NEXT: s_cselect_b32 s4, s4, s6
; GFX6-NEXT: s_cselect_b32 s7, s3, 0		; GFX6-NEXT: s_cmp_lt_i32 s4, s12
; GFX6-NEXT: s_sub_i32 s7, s12, s7		; GFX6-NEXT: s_sext_i32_i16 s5, s5
; GFX6-NEXT: s_cmp_lt_i32 s3, 0		; GFX6-NEXT: s_sext_i32_i16 s7, s11
; GFX6-NEXT: s_cselect_b32 s8, s3, 0		; GFX6-NEXT: s_cselect_b32 s4, s4, s12
; GFX6-NEXT: s_sub_i32 s8, s13, s8		; GFX6-NEXT: s_add_i32 s5, s5, s7
; GFX6-NEXT: s_cmp_gt_i32 s8, s6		; GFX6-NEXT: s_cmp_gt_i32 s5, s6
; GFX6-NEXT: s_cselect_b32 s6, s8, s6		; GFX6-NEXT: s_cselect_b32 s5, s5, s6
; GFX6-NEXT: s_cmp_lt_i32 s6, s7		; GFX6-NEXT: s_cmp_lt_i32 s5, s12
; GFX6-NEXT: s_cselect_b32 s6, s6, s7
; GFX6-NEXT: s_add_i32 s3, s3, s6
; GFX6-NEXT: s_ashr_i32 s3, s3, 16
; GFX6-NEXT: s_lshl_b32 s4, s4, 16
; GFX6-NEXT: s_lshl_b32 s6, s10, 16
; GFX6-NEXT: s_cmp_gt_i32 s4, 0
; GFX6-NEXT: s_cselect_b32 s7, s4, 0
; GFX6-NEXT: s_sub_i32 s7, s12, s7
; GFX6-NEXT: s_cmp_lt_i32 s4, 0
; GFX6-NEXT: s_cselect_b32 s8, s4, 0
; GFX6-NEXT: s_sub_i32 s8, s13, s8
; GFX6-NEXT: s_cmp_gt_i32 s8, s6
; GFX6-NEXT: s_cselect_b32 s6, s8, s6
; GFX6-NEXT: s_cmp_lt_i32 s6, s7
; GFX6-NEXT: s_cselect_b32 s6, s6, s7
; GFX6-NEXT: s_add_i32 s4, s4, s6
; GFX6-NEXT: s_ashr_i32 s4, s4, 16
; GFX6-NEXT: s_lshl_b32 s5, s5, 16
; GFX6-NEXT: s_lshl_b32 s6, s11, 16
; GFX6-NEXT: s_cmp_gt_i32 s5, 0
; GFX6-NEXT: s_cselect_b32 s7, s5, 0
; GFX6-NEXT: s_sub_i32 s7, s12, s7
; GFX6-NEXT: s_cmp_lt_i32 s5, 0
; GFX6-NEXT: s_cselect_b32 s8, s5, 0
; GFX6-NEXT: s_sub_i32 s8, s13, s8
; GFX6-NEXT: s_cmp_gt_i32 s8, s6
; GFX6-NEXT: s_cselect_b32 s6, s8, s6
; GFX6-NEXT: s_cmp_lt_i32 s6, s7
; GFX6-NEXT: s_cselect_b32 s6, s6, s7
; GFX6-NEXT: s_add_i32 s5, s5, s6
; GFX6-NEXT: s_mov_b32 s6, 0xffff		; GFX6-NEXT: s_mov_b32 s6, 0xffff
		; GFX6-NEXT: s_cselect_b32 s5, s5, s12
; GFX6-NEXT: s_and_b32 s1, s1, s6		; GFX6-NEXT: s_and_b32 s1, s1, s6
; GFX6-NEXT: s_and_b32 s0, s0, s6		; GFX6-NEXT: s_and_b32 s0, s0, s6
; GFX6-NEXT: s_lshl_b32 s1, s1, 16		; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_or_b32 s0, s0, s1		; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: s_and_b32 s1, s2, s6		; GFX6-NEXT: s_and_b32 s1, s2, s6
; GFX6-NEXT: s_and_b32 s2, s3, s6		; GFX6-NEXT: s_and_b32 s2, s3, s6
; GFX6-NEXT: s_ashr_i32 s5, s5, 16
; GFX6-NEXT: s_and_b32 s3, s5, s6		; GFX6-NEXT: s_and_b32 s3, s5, s6
; GFX6-NEXT: s_lshl_b32 s2, s2, 16		; GFX6-NEXT: s_lshl_b32 s2, s2, 16
; GFX6-NEXT: s_or_b32 s1, s1, s2		; GFX6-NEXT: s_or_b32 s1, s1, s2
; GFX6-NEXT: s_and_b32 s2, s4, s6		; GFX6-NEXT: s_and_b32 s2, s4, s6
; GFX6-NEXT: s_lshl_b32 s3, s3, 16		; GFX6-NEXT: s_lshl_b32 s3, s3, 16
; GFX6-NEXT: s_or_b32 s2, s2, s3		; GFX6-NEXT: s_or_b32 s2, s2, s3
; GFX6-NEXT: ; return to shader part epilog		; GFX6-NEXT: ; return to shader part epilog
;		;
▲ Show 20 Lines • Show All 145 Lines • ▼ Show 20 Lines	; GFX10-NEXT: ; return to shader part epilog
%cast = bitcast <6 x i16> %result to <3 x i32>		%cast = bitcast <6 x i16> %result to <3 x i32>
ret <3 x i32> %cast		ret <3 x i32> %cast
}		}

define <4 x float> @v_saddsat_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {		define <4 x float> @v_saddsat_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
; GFX6-LABEL: v_saddsat_v8i16:		; GFX6-LABEL: v_saddsat_v8i16:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0		; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16
; GFX6-NEXT: s_brev_b32 s5, 1		; GFX6-NEXT: v_bfe_i32 v9, v9, 0, 16
; GFX6-NEXT: v_min_i32_e32 v18, 0, v0		; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v9
; GFX6-NEXT: v_lshlrev_b32_e32 v8, 16, v8		; GFX6-NEXT: v_bfe_i32 v2, v2, 0, 16
; GFX6-NEXT: v_sub_i32_e32 v18, vcc, s5, v18		; GFX6-NEXT: v_bfe_i32 v9, v10, 0, 16
; GFX6-NEXT: s_brev_b32 s4, -2		; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v9
; GFX6-NEXT: v_max_i32_e32 v16, 0, v0		; GFX6-NEXT: v_bfe_i32 v3, v3, 0, 16
; GFX6-NEXT: v_sub_i32_e32 v16, vcc, s4, v16		; GFX6-NEXT: v_bfe_i32 v9, v11, 0, 16
; GFX6-NEXT: v_max_i32_e32 v8, v18, v8		; GFX6-NEXT: s_movk_i32 s4, 0x8000
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1		; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v9
; GFX6-NEXT: v_min_i32_e32 v8, v8, v16		; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX6-NEXT: v_min_i32_e32 v16, 0, v1		; GFX6-NEXT: v_bfe_i32 v8, v8, 0, 16
		; GFX6-NEXT: v_bfe_i32 v4, v4, 0, 16
		; GFX6-NEXT: v_bfe_i32 v9, v12, 0, 16
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v8		; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v8
; GFX6-NEXT: v_lshlrev_b32_e32 v8, 16, v9		; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v9
; GFX6-NEXT: v_max_i32_e32 v9, 0, v1		; GFX6-NEXT: s_movk_i32 s5, 0x7fff
; GFX6-NEXT: v_sub_i32_e32 v16, vcc, s5, v16		; GFX6-NEXT: v_max_i32_e32 v1, s4, v1
; GFX6-NEXT: v_sub_i32_e32 v9, vcc, s4, v9		; GFX6-NEXT: v_bfe_i32 v5, v5, 0, 16
; GFX6-NEXT: v_max_i32_e32 v8, v16, v8		; GFX6-NEXT: v_bfe_i32 v9, v13, 0, 16
; GFX6-NEXT: v_min_i32_e32 v8, v8, v9		; GFX6-NEXT: v_max_i32_e32 v0, s4, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2		; GFX6-NEXT: v_max_i32_e32 v2, s4, v2
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v8		; GFX6-NEXT: v_max_i32_e32 v3, s4, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v8, 16, v10		; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v9
; GFX6-NEXT: v_min_i32_e32 v10, 0, v2		; GFX6-NEXT: v_min_i32_e32 v1, s5, v1
; GFX6-NEXT: v_sub_i32_e32 v10, vcc, s5, v10
; GFX6-NEXT: v_bfrev_b32_e32 v17, -2
; GFX6-NEXT: v_max_i32_e32 v9, 0, v2
; GFX6-NEXT: v_sub_i32_e32 v9, vcc, v17, v9
; GFX6-NEXT: v_max_i32_e32 v8, v10, v8
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX6-NEXT: v_min_i32_e32 v8, v8, v9
; GFX6-NEXT: v_bfrev_b32_e32 v19, 1
; GFX6-NEXT: v_min_i32_e32 v10, 0, v3
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v8
; GFX6-NEXT: v_max_i32_e32 v9, 0, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v8, 16, v11
; GFX6-NEXT: v_sub_i32_e32 v10, vcc, v19, v10
; GFX6-NEXT: v_sub_i32_e32 v9, vcc, v17, v9
; GFX6-NEXT: v_max_i32_e32 v8, v10, v8
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX6-NEXT: v_min_i32_e32 v8, v8, v9
; GFX6-NEXT: v_min_i32_e32 v10, 0, v4
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v8
; GFX6-NEXT: v_max_i32_e32 v9, 0, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v8, 16, v12
; GFX6-NEXT: v_sub_i32_e32 v10, vcc, v19, v10
; GFX6-NEXT: v_sub_i32_e32 v9, vcc, v17, v9
; GFX6-NEXT: v_max_i32_e32 v8, v10, v8
; GFX6-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX6-NEXT: v_min_i32_e32 v8, v8, v9
; GFX6-NEXT: v_min_i32_e32 v10, 0, v5
; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v8
; GFX6-NEXT: v_max_i32_e32 v9, 0, v5
; GFX6-NEXT: v_lshlrev_b32_e32 v8, 16, v13
; GFX6-NEXT: v_sub_i32_e32 v10, vcc, v19, v10
; GFX6-NEXT: v_sub_i32_e32 v9, vcc, v17, v9
; GFX6-NEXT: v_max_i32_e32 v8, v10, v8
; GFX6-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX6-NEXT: v_min_i32_e32 v8, v8, v9
; GFX6-NEXT: v_min_i32_e32 v10, 0, v6
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; GFX6-NEXT: v_max_i32_e32 v9, 0, v6
; GFX6-NEXT: v_lshlrev_b32_e32 v8, 16, v14
; GFX6-NEXT: v_sub_i32_e32 v10, vcc, v19, v10
; GFX6-NEXT: v_sub_i32_e32 v9, vcc, v17, v9
; GFX6-NEXT: v_max_i32_e32 v8, v10, v8
; GFX6-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX6-NEXT: v_min_i32_e32 v8, v8, v9
; GFX6-NEXT: v_min_i32_e32 v10, 0, v7
; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v8
; GFX6-NEXT: v_max_i32_e32 v9, 0, v7
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 16, v1
; GFX6-NEXT: s_mov_b32 s4, 0xffff		; GFX6-NEXT: s_mov_b32 s4, 0xffff
; GFX6-NEXT: v_lshlrev_b32_e32 v8, 16, v15		; GFX6-NEXT: v_bfe_i32 v6, v6, 0, 16
; GFX6-NEXT: v_sub_i32_e32 v10, vcc, v19, v10		; GFX6-NEXT: v_bfe_i32 v9, v14, 0, 16
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 16, v0		; GFX6-NEXT: v_mov_b32_e32 v8, 0xffff8000
		; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v9
		; GFX6-NEXT: v_min_i32_e32 v0, s5, v0
; GFX6-NEXT: v_and_b32_e32 v1, s4, v1		; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
; GFX6-NEXT: v_sub_i32_e32 v9, vcc, v17, v9		; GFX6-NEXT: v_bfe_i32 v7, v7, 0, 16
; GFX6-NEXT: v_max_i32_e32 v8, v10, v8		; GFX6-NEXT: v_bfe_i32 v9, v15, 0, 16
; GFX6-NEXT: v_min_i32_e32 v8, v8, v9		; GFX6-NEXT: v_add_i32_e32 v7, vcc, v7, v9
; GFX6-NEXT: v_ashrrev_i32_e32 v2, 16, v2		; GFX6-NEXT: v_mov_b32_e32 v16, 0x7fff
; GFX6-NEXT: v_ashrrev_i32_e32 v3, 16, v3		; GFX6-NEXT: v_max_i32_e32 v5, v5, v8
		; GFX6-NEXT: v_min_i32_e32 v2, s5, v2
		; GFX6-NEXT: v_min_i32_e32 v3, s5, v3
; GFX6-NEXT: v_and_b32_e32 v0, s4, v0		; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1		; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_add_i32_e32 v7, vcc, v7, v8		; GFX6-NEXT: v_max_i32_e32 v4, v4, v8
		; GFX6-NEXT: v_max_i32_e32 v7, v7, v8
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1		; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: v_and_b32_e32 v1, s4, v2		; GFX6-NEXT: v_and_b32_e32 v1, s4, v2
; GFX6-NEXT: v_and_b32_e32 v2, s4, v3		; GFX6-NEXT: v_and_b32_e32 v2, s4, v3
; GFX6-NEXT: v_ashrrev_i32_e32 v5, 16, v5		; GFX6-NEXT: v_min_i32_e32 v5, v5, v16
		; GFX6-NEXT: v_max_i32_e32 v6, v6, v8
; GFX6-NEXT: v_and_b32_e32 v3, s4, v5		; GFX6-NEXT: v_and_b32_e32 v3, s4, v5
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2		; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX6-NEXT: v_ashrrev_i32_e32 v4, 16, v4		; GFX6-NEXT: v_min_i32_e32 v4, s5, v4
; GFX6-NEXT: v_ashrrev_i32_e32 v7, 16, v7		; GFX6-NEXT: v_min_i32_e32 v7, v7, v16
; GFX6-NEXT: v_or_b32_e32 v1, v1, v2		; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
; GFX6-NEXT: v_and_b32_e32 v2, s4, v4		; GFX6-NEXT: v_and_b32_e32 v2, s4, v4
; GFX6-NEXT: v_and_b32_e32 v4, s4, v7		; GFX6-NEXT: v_and_b32_e32 v4, s4, v7
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3		; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX6-NEXT: v_ashrrev_i32_e32 v6, 16, v6		; GFX6-NEXT: v_min_i32_e32 v6, v6, v16
; GFX6-NEXT: v_or_b32_e32 v2, v2, v3		; GFX6-NEXT: v_or_b32_e32 v2, v2, v3
; GFX6-NEXT: v_and_b32_e32 v3, s4, v6		; GFX6-NEXT: v_and_b32_e32 v3, s4, v6
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v4		; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX6-NEXT: v_or_b32_e32 v3, v3, v4		; GFX6-NEXT: v_or_b32_e32 v3, v3, v4
; GFX6-NEXT: s_setpc_b64 s[30:31]		; GFX6-NEXT: s_setpc_b64 s[30:31]
;		;
; GFX8-LABEL: v_saddsat_v8i16:		; GFX8-LABEL: v_saddsat_v8i16:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
▲ Show 20 Lines • Show All 90 Lines • ▼ Show 20 Lines	; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)		%result = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
%cast = bitcast <8 x i16> %result to <4 x float>		%cast = bitcast <8 x i16> %result to <4 x float>
ret <4 x float> %cast		ret <4 x float> %cast
}		}

define amdgpu_ps <4 x i32> @s_saddsat_v8i16(<8 x i16> inreg %lhs, <8 x i16> inreg %rhs) {		define amdgpu_ps <4 x i32> @s_saddsat_v8i16(<8 x i16> inreg %lhs, <8 x i16> inreg %rhs) {
; GFX6-LABEL: s_saddsat_v8i16:		; GFX6-LABEL: s_saddsat_v8i16:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 16		; GFX6-NEXT: s_sext_i32_i16 s0, s0
; GFX6-NEXT: s_lshl_b32 s8, s8, 16		; GFX6-NEXT: s_sext_i32_i16 s8, s8
; GFX6-NEXT: s_cmp_gt_i32 s0, 0
; GFX6-NEXT: s_brev_b32 s16, -2
; GFX6-NEXT: s_cselect_b32 s18, s0, 0
; GFX6-NEXT: s_sub_i32 s18, s16, s18
; GFX6-NEXT: s_cmp_lt_i32 s0, 0
; GFX6-NEXT: s_brev_b32 s17, 1
; GFX6-NEXT: s_cselect_b32 s19, s0, 0
; GFX6-NEXT: s_sub_i32 s19, s17, s19
; GFX6-NEXT: s_cmp_gt_i32 s19, s8
; GFX6-NEXT: s_cselect_b32 s8, s19, s8
; GFX6-NEXT: s_cmp_lt_i32 s8, s18
; GFX6-NEXT: s_cselect_b32 s8, s8, s18
; GFX6-NEXT: s_add_i32 s0, s0, s8		; GFX6-NEXT: s_add_i32 s0, s0, s8
; GFX6-NEXT: s_ashr_i32 s0, s0, 16		; GFX6-NEXT: s_movk_i32 s8, 0x8000
; GFX6-NEXT: s_lshl_b32 s1, s1, 16		; GFX6-NEXT: s_cmp_gt_i32 s0, s8
; GFX6-NEXT: s_lshl_b32 s8, s9, 16		; GFX6-NEXT: s_cselect_b32 s0, s0, s8
; GFX6-NEXT: s_cmp_gt_i32 s1, 0		; GFX6-NEXT: s_movk_i32 s16, 0x7fff
; GFX6-NEXT: s_cselect_b32 s9, s1, 0		; GFX6-NEXT: s_cmp_lt_i32 s0, s16
; GFX6-NEXT: s_sub_i32 s9, s16, s9		; GFX6-NEXT: s_sext_i32_i16 s1, s1
; GFX6-NEXT: s_cmp_lt_i32 s1, 0		; GFX6-NEXT: s_sext_i32_i16 s9, s9
; GFX6-NEXT: s_cselect_b32 s18, s1, 0		; GFX6-NEXT: s_cselect_b32 s0, s0, s16
; GFX6-NEXT: s_sub_i32 s18, s17, s18		; GFX6-NEXT: s_add_i32 s1, s1, s9
; GFX6-NEXT: s_cmp_gt_i32 s18, s8		; GFX6-NEXT: s_cmp_gt_i32 s1, s8
; GFX6-NEXT: s_cselect_b32 s8, s18, s8		; GFX6-NEXT: s_cselect_b32 s1, s1, s8
; GFX6-NEXT: s_cmp_lt_i32 s8, s9		; GFX6-NEXT: s_cmp_lt_i32 s1, s16
; GFX6-NEXT: s_cselect_b32 s8, s8, s9		; GFX6-NEXT: s_sext_i32_i16 s2, s2
; GFX6-NEXT: s_add_i32 s1, s1, s8		; GFX6-NEXT: s_sext_i32_i16 s9, s10
; GFX6-NEXT: s_ashr_i32 s1, s1, 16		; GFX6-NEXT: s_cselect_b32 s1, s1, s16
; GFX6-NEXT: s_lshl_b32 s2, s2, 16		; GFX6-NEXT: s_add_i32 s2, s2, s9
; GFX6-NEXT: s_lshl_b32 s8, s10, 16		; GFX6-NEXT: s_cmp_gt_i32 s2, s8
; GFX6-NEXT: s_cmp_gt_i32 s2, 0		; GFX6-NEXT: s_cselect_b32 s2, s2, s8
; GFX6-NEXT: s_cselect_b32 s9, s2, 0		; GFX6-NEXT: s_cmp_lt_i32 s2, s16
; GFX6-NEXT: s_sub_i32 s9, s16, s9		; GFX6-NEXT: s_sext_i32_i16 s3, s3
; GFX6-NEXT: s_cmp_lt_i32 s2, 0		; GFX6-NEXT: s_sext_i32_i16 s9, s11
; GFX6-NEXT: s_cselect_b32 s10, s2, 0		; GFX6-NEXT: s_cselect_b32 s2, s2, s16
; GFX6-NEXT: s_sub_i32 s10, s17, s10		; GFX6-NEXT: s_add_i32 s3, s3, s9
; GFX6-NEXT: s_cmp_gt_i32 s10, s8		; GFX6-NEXT: s_cmp_gt_i32 s3, s8
; GFX6-NEXT: s_cselect_b32 s8, s10, s8		; GFX6-NEXT: s_cselect_b32 s3, s3, s8
; GFX6-NEXT: s_cmp_lt_i32 s8, s9		; GFX6-NEXT: s_cmp_lt_i32 s3, s16
; GFX6-NEXT: s_cselect_b32 s8, s8, s9		; GFX6-NEXT: s_sext_i32_i16 s4, s4
; GFX6-NEXT: s_add_i32 s2, s2, s8		; GFX6-NEXT: s_sext_i32_i16 s9, s12
; GFX6-NEXT: s_ashr_i32 s2, s2, 16		; GFX6-NEXT: s_cselect_b32 s3, s3, s16
; GFX6-NEXT: s_lshl_b32 s3, s3, 16		; GFX6-NEXT: s_add_i32 s4, s4, s9
; GFX6-NEXT: s_lshl_b32 s8, s11, 16		; GFX6-NEXT: s_cmp_gt_i32 s4, s8
; GFX6-NEXT: s_cmp_gt_i32 s3, 0		; GFX6-NEXT: s_cselect_b32 s4, s4, s8
; GFX6-NEXT: s_cselect_b32 s9, s3, 0		; GFX6-NEXT: s_cmp_lt_i32 s4, s16
; GFX6-NEXT: s_sub_i32 s9, s16, s9		; GFX6-NEXT: s_sext_i32_i16 s5, s5
; GFX6-NEXT: s_cmp_lt_i32 s3, 0		; GFX6-NEXT: s_sext_i32_i16 s9, s13
; GFX6-NEXT: s_cselect_b32 s10, s3, 0		; GFX6-NEXT: s_cselect_b32 s4, s4, s16
; GFX6-NEXT: s_sub_i32 s10, s17, s10		; GFX6-NEXT: s_add_i32 s5, s5, s9
; GFX6-NEXT: s_cmp_gt_i32 s10, s8		; GFX6-NEXT: s_cmp_gt_i32 s5, s8
; GFX6-NEXT: s_cselect_b32 s8, s10, s8		; GFX6-NEXT: s_cselect_b32 s5, s5, s8
; GFX6-NEXT: s_cmp_lt_i32 s8, s9		; GFX6-NEXT: s_cmp_lt_i32 s5, s16
; GFX6-NEXT: s_cselect_b32 s8, s8, s9		; GFX6-NEXT: s_sext_i32_i16 s6, s6
; GFX6-NEXT: s_add_i32 s3, s3, s8		; GFX6-NEXT: s_sext_i32_i16 s9, s14
; GFX6-NEXT: s_ashr_i32 s3, s3, 16		; GFX6-NEXT: s_cselect_b32 s5, s5, s16
; GFX6-NEXT: s_lshl_b32 s4, s4, 16		; GFX6-NEXT: s_add_i32 s6, s6, s9
; GFX6-NEXT: s_lshl_b32 s8, s12, 16		; GFX6-NEXT: s_cmp_gt_i32 s6, s8
; GFX6-NEXT: s_cmp_gt_i32 s4, 0		; GFX6-NEXT: s_cselect_b32 s6, s6, s8
; GFX6-NEXT: s_cselect_b32 s9, s4, 0		; GFX6-NEXT: s_cmp_lt_i32 s6, s16
; GFX6-NEXT: s_sub_i32 s9, s16, s9		; GFX6-NEXT: s_sext_i32_i16 s7, s7
; GFX6-NEXT: s_cmp_lt_i32 s4, 0		; GFX6-NEXT: s_sext_i32_i16 s9, s15
; GFX6-NEXT: s_cselect_b32 s10, s4, 0		; GFX6-NEXT: s_cselect_b32 s6, s6, s16
; GFX6-NEXT: s_sub_i32 s10, s17, s10		; GFX6-NEXT: s_add_i32 s7, s7, s9
; GFX6-NEXT: s_cmp_gt_i32 s10, s8		; GFX6-NEXT: s_cmp_gt_i32 s7, s8
; GFX6-NEXT: s_cselect_b32 s8, s10, s8		; GFX6-NEXT: s_cselect_b32 s7, s7, s8
; GFX6-NEXT: s_cmp_lt_i32 s8, s9		; GFX6-NEXT: s_cmp_lt_i32 s7, s16
; GFX6-NEXT: s_cselect_b32 s8, s8, s9
; GFX6-NEXT: s_add_i32 s4, s4, s8
; GFX6-NEXT: s_ashr_i32 s4, s4, 16
; GFX6-NEXT: s_lshl_b32 s5, s5, 16
; GFX6-NEXT: s_lshl_b32 s8, s13, 16
; GFX6-NEXT: s_cmp_gt_i32 s5, 0
; GFX6-NEXT: s_cselect_b32 s9, s5, 0
; GFX6-NEXT: s_sub_i32 s9, s16, s9
; GFX6-NEXT: s_cmp_lt_i32 s5, 0
; GFX6-NEXT: s_cselect_b32 s10, s5, 0
; GFX6-NEXT: s_sub_i32 s10, s17, s10
; GFX6-NEXT: s_cmp_gt_i32 s10, s8
; GFX6-NEXT: s_cselect_b32 s8, s10, s8
; GFX6-NEXT: s_cmp_lt_i32 s8, s9
; GFX6-NEXT: s_cselect_b32 s8, s8, s9
; GFX6-NEXT: s_add_i32 s5, s5, s8
; GFX6-NEXT: s_ashr_i32 s5, s5, 16
; GFX6-NEXT: s_lshl_b32 s6, s6, 16
; GFX6-NEXT: s_lshl_b32 s8, s14, 16
; GFX6-NEXT: s_cmp_gt_i32 s6, 0
; GFX6-NEXT: s_cselect_b32 s9, s6, 0
; GFX6-NEXT: s_sub_i32 s9, s16, s9
; GFX6-NEXT: s_cmp_lt_i32 s6, 0
; GFX6-NEXT: s_cselect_b32 s10, s6, 0
; GFX6-NEXT: s_sub_i32 s10, s17, s10
; GFX6-NEXT: s_cmp_gt_i32 s10, s8
; GFX6-NEXT: s_cselect_b32 s8, s10, s8
; GFX6-NEXT: s_cmp_lt_i32 s8, s9
; GFX6-NEXT: s_cselect_b32 s8, s8, s9
; GFX6-NEXT: s_add_i32 s6, s6, s8
; GFX6-NEXT: s_ashr_i32 s6, s6, 16
; GFX6-NEXT: s_lshl_b32 s7, s7, 16
; GFX6-NEXT: s_lshl_b32 s8, s15, 16
; GFX6-NEXT: s_cmp_gt_i32 s7, 0
; GFX6-NEXT: s_cselect_b32 s9, s7, 0
; GFX6-NEXT: s_sub_i32 s9, s16, s9
; GFX6-NEXT: s_cmp_lt_i32 s7, 0
; GFX6-NEXT: s_cselect_b32 s10, s7, 0
; GFX6-NEXT: s_sub_i32 s10, s17, s10
; GFX6-NEXT: s_cmp_gt_i32 s10, s8
; GFX6-NEXT: s_cselect_b32 s8, s10, s8
; GFX6-NEXT: s_cmp_lt_i32 s8, s9
; GFX6-NEXT: s_cselect_b32 s8, s8, s9
; GFX6-NEXT: s_add_i32 s7, s7, s8
; GFX6-NEXT: s_mov_b32 s8, 0xffff		; GFX6-NEXT: s_mov_b32 s8, 0xffff
		; GFX6-NEXT: s_cselect_b32 s7, s7, s16
; GFX6-NEXT: s_and_b32 s1, s1, s8		; GFX6-NEXT: s_and_b32 s1, s1, s8
; GFX6-NEXT: s_and_b32 s0, s0, s8		; GFX6-NEXT: s_and_b32 s0, s0, s8
; GFX6-NEXT: s_lshl_b32 s1, s1, 16		; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_or_b32 s0, s0, s1		; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: s_and_b32 s1, s2, s8		; GFX6-NEXT: s_and_b32 s1, s2, s8
; GFX6-NEXT: s_and_b32 s2, s3, s8		; GFX6-NEXT: s_and_b32 s2, s3, s8
; GFX6-NEXT: s_and_b32 s3, s5, s8		; GFX6-NEXT: s_and_b32 s3, s5, s8
; GFX6-NEXT: s_lshl_b32 s2, s2, 16		; GFX6-NEXT: s_lshl_b32 s2, s2, 16
; GFX6-NEXT: s_ashr_i32 s7, s7, 16
; GFX6-NEXT: s_or_b32 s1, s1, s2		; GFX6-NEXT: s_or_b32 s1, s1, s2
; GFX6-NEXT: s_and_b32 s2, s4, s8		; GFX6-NEXT: s_and_b32 s2, s4, s8
; GFX6-NEXT: s_and_b32 s4, s7, s8		; GFX6-NEXT: s_and_b32 s4, s7, s8
; GFX6-NEXT: s_lshl_b32 s3, s3, 16		; GFX6-NEXT: s_lshl_b32 s3, s3, 16
; GFX6-NEXT: s_or_b32 s2, s2, s3		; GFX6-NEXT: s_or_b32 s2, s2, s3
; GFX6-NEXT: s_and_b32 s3, s6, s8		; GFX6-NEXT: s_and_b32 s3, s6, s8
; GFX6-NEXT: s_lshl_b32 s4, s4, 16		; GFX6-NEXT: s_lshl_b32 s4, s4, 16
; GFX6-NEXT: s_or_b32 s3, s3, s4		; GFX6-NEXT: s_or_b32 s3, s3, s4
▲ Show 20 Lines • Show All 2,906 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py		; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=tahiti -o - %s \| FileCheck -check-prefix=GFX6 %s		; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=tahiti -o - %s \| FileCheck -check-prefix=GFX6 %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=fiji -o - %s \| FileCheck -check-prefix=GFX8 %s		; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=fiji -o - %s \| FileCheck -check-prefix=GFX8 %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -o - %s \| FileCheck -check-prefix=GFX9 %s		; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -o - %s \| FileCheck -check-prefix=GFX9 %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -o - %s \| FileCheck -check-prefix=GFX10 %s		; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -o - %s \| FileCheck -check-prefix=GFX10 %s

define i7 @v_ssubsat_i7(i7 %lhs, i7 %rhs) {		define i7 @v_ssubsat_i7(i7 %lhs, i7 %rhs) {
; GFX6-LABEL: v_ssubsat_i7:		; GFX6-LABEL: v_ssubsat_i7:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 25, v0		; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 7
; GFX6-NEXT: v_max_i32_e32 v2, -1, v0		; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 7
; GFX6-NEXT: v_min_i32_e32 v3, -1, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 25, v1
; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, 0x7fffffff, v2
; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, 0x80000000, v3
; GFX6-NEXT: v_max_i32_e32 v1, v2, v1
; GFX6-NEXT: v_min_i32_e32 v1, v1, v3
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1		; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 25, v0		; GFX6-NEXT: v_max_i32_e32 v0, 0xffffffc0, v0
		; GFX6-NEXT: v_min_i32_e32 v0, 63, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]		; GFX6-NEXT: s_setpc_b64 s[30:31]
;		;
; GFX8-LABEL: v_ssubsat_i7:		; GFX8-LABEL: v_ssubsat_i7:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshlrev_b16_e32 v0, 9, v0		; GFX8-NEXT: v_lshlrev_b16_e32 v0, 9, v0
; GFX8-NEXT: v_max_i16_e32 v2, -1, v0		; GFX8-NEXT: v_max_i16_e32 v2, -1, v0
; GFX8-NEXT: v_min_i16_e32 v3, -1, v0		; GFX8-NEXT: v_min_i16_e32 v3, -1, v0
Show All 27 Lines
; GFX10-NEXT: s_setpc_b64 s[30:31]		; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call i7 @llvm.ssub.sat.i7(i7 %lhs, i7 %rhs)		%result = call i7 @llvm.ssub.sat.i7(i7 %lhs, i7 %rhs)
ret i7 %result		ret i7 %result
}		}

define amdgpu_ps i7 @s_ssubsat_i7(i7 inreg %lhs, i7 inreg %rhs) {		define amdgpu_ps i7 @s_ssubsat_i7(i7 inreg %lhs, i7 inreg %rhs) {
; GFX6-LABEL: s_ssubsat_i7:		; GFX6-LABEL: s_ssubsat_i7:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 25		; GFX6-NEXT: s_bfe_i32 s0, s0, 0x70000
; GFX6-NEXT: s_lshl_b32 s1, s1, 25		; GFX6-NEXT: s_bfe_i32 s1, s1, 0x70000
; GFX6-NEXT: s_cmp_gt_i32 s0, -1
; GFX6-NEXT: s_cselect_b32 s2, s0, -1
; GFX6-NEXT: s_sub_i32 s2, s2, 0x7fffffff
; GFX6-NEXT: s_cmp_lt_i32 s0, -1
; GFX6-NEXT: s_cselect_b32 s3, s0, -1
; GFX6-NEXT: s_sub_i32 s3, s3, 0x80000000
; GFX6-NEXT: s_cmp_gt_i32 s2, s1
; GFX6-NEXT: s_cselect_b32 s1, s2, s1
; GFX6-NEXT: s_cmp_lt_i32 s1, s3
; GFX6-NEXT: s_cselect_b32 s1, s1, s3
; GFX6-NEXT: s_sub_i32 s0, s0, s1		; GFX6-NEXT: s_sub_i32 s0, s0, s1
; GFX6-NEXT: s_ashr_i32 s0, s0, 25		; GFX6-NEXT: s_movk_i32 s1, 0xffc0
		; GFX6-NEXT: s_cmp_gt_i32 s0, s1
		; GFX6-NEXT: s_cselect_b32 s0, s0, s1
		; GFX6-NEXT: s_cmp_lt_i32 s0, 63
		; GFX6-NEXT: s_cselect_b32 s0, s0, 63
; GFX6-NEXT: ; return to shader part epilog		; GFX6-NEXT: ; return to shader part epilog
;		;
; GFX8-LABEL: s_ssubsat_i7:		; GFX8-LABEL: s_ssubsat_i7:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_bfe_u32 s2, 9, 0x100000		; GFX8-NEXT: s_bfe_u32 s2, 9, 0x100000
; GFX8-NEXT: s_lshl_b32 s0, s0, s2		; GFX8-NEXT: s_lshl_b32 s0, s0, s2
; GFX8-NEXT: s_lshl_b32 s1, s1, s2		; GFX8-NEXT: s_lshl_b32 s1, s1, s2
; GFX8-NEXT: s_sext_i32_i16 s3, s0		; GFX8-NEXT: s_sext_i32_i16 s3, s0
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines	; GFX10-NEXT: ; return to shader part epilog
%result = call i7 @llvm.ssub.sat.i7(i7 %lhs, i7 %rhs)		%result = call i7 @llvm.ssub.sat.i7(i7 %lhs, i7 %rhs)
ret i7 %result		ret i7 %result
}		}

define i8 @v_ssubsat_i8(i8 %lhs, i8 %rhs) {		define i8 @v_ssubsat_i8(i8 %lhs, i8 %rhs) {
; GFX6-LABEL: v_ssubsat_i8:		; GFX6-LABEL: v_ssubsat_i8:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 24, v0		; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX6-NEXT: v_max_i32_e32 v2, -1, v0		; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 8
; GFX6-NEXT: v_min_i32_e32 v3, -1, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v1
; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, 0x7fffffff, v2
; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, 0x80000000, v3
; GFX6-NEXT: v_max_i32_e32 v1, v2, v1
; GFX6-NEXT: v_min_i32_e32 v1, v1, v3
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1		; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 24, v0		; GFX6-NEXT: v_max_i32_e32 v0, 0xffffff80, v0
		; GFX6-NEXT: v_min_i32_e32 v0, 0x7f, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]		; GFX6-NEXT: s_setpc_b64 s[30:31]
;		;
; GFX8-LABEL: v_ssubsat_i8:		; GFX8-LABEL: v_ssubsat_i8:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshlrev_b16_e32 v0, 8, v0		; GFX8-NEXT: v_lshlrev_b16_e32 v0, 8, v0
; GFX8-NEXT: v_max_i16_e32 v2, -1, v0		; GFX8-NEXT: v_max_i16_e32 v2, -1, v0
; GFX8-NEXT: v_min_i16_e32 v3, -1, v0		; GFX8-NEXT: v_min_i16_e32 v3, -1, v0
Show All 27 Lines
; GFX10-NEXT: s_setpc_b64 s[30:31]		; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call i8 @llvm.ssub.sat.i8(i8 %lhs, i8 %rhs)		%result = call i8 @llvm.ssub.sat.i8(i8 %lhs, i8 %rhs)
ret i8 %result		ret i8 %result
}		}

define amdgpu_ps i8 @s_ssubsat_i8(i8 inreg %lhs, i8 inreg %rhs) {		define amdgpu_ps i8 @s_ssubsat_i8(i8 inreg %lhs, i8 inreg %rhs) {
; GFX6-LABEL: s_ssubsat_i8:		; GFX6-LABEL: s_ssubsat_i8:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 24		; GFX6-NEXT: s_sext_i32_i8 s0, s0
; GFX6-NEXT: s_lshl_b32 s1, s1, 24		; GFX6-NEXT: s_sext_i32_i8 s1, s1
; GFX6-NEXT: s_cmp_gt_i32 s0, -1
; GFX6-NEXT: s_cselect_b32 s2, s0, -1
; GFX6-NEXT: s_sub_i32 s2, s2, 0x7fffffff
; GFX6-NEXT: s_cmp_lt_i32 s0, -1
; GFX6-NEXT: s_cselect_b32 s3, s0, -1
; GFX6-NEXT: s_sub_i32 s3, s3, 0x80000000
; GFX6-NEXT: s_cmp_gt_i32 s2, s1
; GFX6-NEXT: s_cselect_b32 s1, s2, s1
; GFX6-NEXT: s_cmp_lt_i32 s1, s3
; GFX6-NEXT: s_cselect_b32 s1, s1, s3
; GFX6-NEXT: s_sub_i32 s0, s0, s1		; GFX6-NEXT: s_sub_i32 s0, s0, s1
; GFX6-NEXT: s_ashr_i32 s0, s0, 24		; GFX6-NEXT: s_movk_i32 s1, 0xff80
		; GFX6-NEXT: s_cmp_gt_i32 s0, s1
		; GFX6-NEXT: s_cselect_b32 s0, s0, s1
		; GFX6-NEXT: s_movk_i32 s1, 0x7f
		; GFX6-NEXT: s_cmp_lt_i32 s0, s1
		; GFX6-NEXT: s_cselect_b32 s0, s0, s1
; GFX6-NEXT: ; return to shader part epilog		; GFX6-NEXT: ; return to shader part epilog
;		;
; GFX8-LABEL: s_ssubsat_i8:		; GFX8-LABEL: s_ssubsat_i8:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_bfe_u32 s2, 8, 0x100000		; GFX8-NEXT: s_bfe_u32 s2, 8, 0x100000
; GFX8-NEXT: s_lshl_b32 s0, s0, s2		; GFX8-NEXT: s_lshl_b32 s0, s0, s2
; GFX8-NEXT: s_lshl_b32 s1, s1, s2		; GFX8-NEXT: s_lshl_b32 s1, s1, s2
; GFX8-NEXT: s_sext_i32_i16 s3, s0		; GFX8-NEXT: s_sext_i32_i16 s3, s0
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines	; GFX10-NEXT: ; return to shader part epilog
ret i8 %result		ret i8 %result
}		}

define i16 @v_ssubsat_v2i8(i16 %lhs.arg, i16 %rhs.arg) {		define i16 @v_ssubsat_v2i8(i16 %lhs.arg, i16 %rhs.arg) {
; GFX6-LABEL: v_ssubsat_v2i8:		; GFX6-LABEL: v_ssubsat_v2i8:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshrrev_b32_e32 v2, 8, v0		; GFX6-NEXT: v_lshrrev_b32_e32 v2, 8, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 24, v0
; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_max_i32_e32 v4, -1, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 8, v1		; GFX6-NEXT: v_lshrrev_b32_e32 v3, 8, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v1		; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s4, v4		; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 8
; GFX6-NEXT: s_brev_b32 s5, 1
; GFX6-NEXT: v_min_i32_e32 v5, -1, v0
; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s5, v5
; GFX6-NEXT: v_max_i32_e32 v1, v4, v1
; GFX6-NEXT: v_min_i32_e32 v1, v1, v5
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1		; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v2		; GFX6-NEXT: v_bfe_i32 v1, v2, 0, 8
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 24, v3		; GFX6-NEXT: v_bfe_i32 v2, v3, 0, 8
; GFX6-NEXT: v_max_i32_e32 v3, -1, v1		; GFX6-NEXT: s_movk_i32 s4, 0xff80
; GFX6-NEXT: v_min_i32_e32 v4, -1, v1
; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s4, v3
; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s5, v4
; GFX6-NEXT: v_max_i32_e32 v2, v3, v2
; GFX6-NEXT: v_min_i32_e32 v2, v2, v4
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v2		; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v2
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 24, v1		; GFX6-NEXT: s_movk_i32 s5, 0x7f
		; GFX6-NEXT: v_max_i32_e32 v1, s4, v1
		; GFX6-NEXT: v_max_i32_e32 v0, s4, v0
		; GFX6-NEXT: v_min_i32_e32 v1, s5, v1
; GFX6-NEXT: v_mov_b32_e32 v2, 0xff		; GFX6-NEXT: v_mov_b32_e32 v2, 0xff
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 24, v0		; GFX6-NEXT: v_min_i32_e32 v0, s5, v0
; GFX6-NEXT: v_and_b32_e32 v1, v1, v2		; GFX6-NEXT: v_and_b32_e32 v1, v1, v2
; GFX6-NEXT: v_and_b32_e32 v0, v0, v2		; GFX6-NEXT: v_and_b32_e32 v0, v0, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 8, v1		; GFX6-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1		; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]		; GFX6-NEXT: s_setpc_b64 s[30:31]
;		;
; GFX8-LABEL: v_ssubsat_v2i8:		; GFX8-LABEL: v_ssubsat_v2i8:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
▲ Show 20 Lines • Show All 69 Lines • ▼ Show 20 Lines	; GFX10-NEXT: s_setpc_b64 s[30:31]
ret i16 %cast.result		ret i16 %cast.result
}		}

define amdgpu_ps i16 @s_ssubsat_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg) {		define amdgpu_ps i16 @s_ssubsat_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg) {
; GFX6-LABEL: s_ssubsat_v2i8:		; GFX6-LABEL: s_ssubsat_v2i8:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshr_b32 s2, s0, 8		; GFX6-NEXT: s_lshr_b32 s2, s0, 8
; GFX6-NEXT: s_lshr_b32 s3, s1, 8		; GFX6-NEXT: s_lshr_b32 s3, s1, 8
; GFX6-NEXT: s_lshl_b32 s0, s0, 24		; GFX6-NEXT: s_sext_i32_i8 s0, s0
; GFX6-NEXT: s_lshl_b32 s1, s1, 24		; GFX6-NEXT: s_sext_i32_i8 s1, s1
; GFX6-NEXT: s_cmp_gt_i32 s0, -1
; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: s_cselect_b32 s6, s0, -1
; GFX6-NEXT: s_sub_i32 s6, s6, s4
; GFX6-NEXT: s_cmp_lt_i32 s0, -1
; GFX6-NEXT: s_brev_b32 s5, 1
; GFX6-NEXT: s_cselect_b32 s7, s0, -1
; GFX6-NEXT: s_sub_i32 s7, s7, s5
; GFX6-NEXT: s_cmp_gt_i32 s6, s1
; GFX6-NEXT: s_cselect_b32 s1, s6, s1
; GFX6-NEXT: s_cmp_lt_i32 s1, s7
; GFX6-NEXT: s_cselect_b32 s1, s1, s7
; GFX6-NEXT: s_sub_i32 s0, s0, s1		; GFX6-NEXT: s_sub_i32 s0, s0, s1
; GFX6-NEXT: s_lshl_b32 s1, s2, 24		; GFX6-NEXT: s_movk_i32 s1, 0xff80
; GFX6-NEXT: s_ashr_i32 s0, s0, 24		; GFX6-NEXT: s_cmp_gt_i32 s0, s1
; GFX6-NEXT: s_lshl_b32 s2, s3, 24		; GFX6-NEXT: s_cselect_b32 s0, s0, s1
; GFX6-NEXT: s_cmp_gt_i32 s1, -1		; GFX6-NEXT: s_movk_i32 s4, 0x7f
; GFX6-NEXT: s_cselect_b32 s3, s1, -1		; GFX6-NEXT: s_cmp_lt_i32 s0, s4
; GFX6-NEXT: s_sub_i32 s3, s3, s4		; GFX6-NEXT: s_sext_i32_i8 s2, s2
; GFX6-NEXT: s_cmp_lt_i32 s1, -1		; GFX6-NEXT: s_sext_i32_i8 s3, s3
; GFX6-NEXT: s_cselect_b32 s4, s1, -1		; GFX6-NEXT: s_cselect_b32 s0, s0, s4
; GFX6-NEXT: s_sub_i32 s4, s4, s5		; GFX6-NEXT: s_sub_i32 s2, s2, s3
; GFX6-NEXT: s_cmp_gt_i32 s3, s2		; GFX6-NEXT: s_cmp_gt_i32 s2, s1
; GFX6-NEXT: s_cselect_b32 s2, s3, s2		; GFX6-NEXT: s_cselect_b32 s1, s2, s1
; GFX6-NEXT: s_cmp_lt_i32 s2, s4		; GFX6-NEXT: s_cmp_lt_i32 s1, s4
; GFX6-NEXT: s_cselect_b32 s2, s2, s4		; GFX6-NEXT: s_cselect_b32 s1, s1, s4
; GFX6-NEXT: s_sub_i32 s1, s1, s2
; GFX6-NEXT: s_movk_i32 s2, 0xff		; GFX6-NEXT: s_movk_i32 s2, 0xff
; GFX6-NEXT: s_ashr_i32 s1, s1, 24
; GFX6-NEXT: s_and_b32 s1, s1, s2		; GFX6-NEXT: s_and_b32 s1, s1, s2
; GFX6-NEXT: s_and_b32 s0, s0, s2		; GFX6-NEXT: s_and_b32 s0, s0, s2
; GFX6-NEXT: s_lshl_b32 s1, s1, 8		; GFX6-NEXT: s_lshl_b32 s1, s1, 8
; GFX6-NEXT: s_or_b32 s0, s0, s1		; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: ; return to shader part epilog		; GFX6-NEXT: ; return to shader part epilog
;		;
; GFX8-LABEL: s_ssubsat_v2i8:		; GFX8-LABEL: s_ssubsat_v2i8:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
▲ Show 20 Lines • Show All 106 Lines • ▼ Show 20 Lines

define i32 @v_ssubsat_v4i8(i32 %lhs.arg, i32 %rhs.arg) {		define i32 @v_ssubsat_v4i8(i32 %lhs.arg, i32 %rhs.arg) {
; GFX6-LABEL: v_ssubsat_v4i8:		; GFX6-LABEL: v_ssubsat_v4i8:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshrrev_b32_e32 v2, 8, v0		; GFX6-NEXT: v_lshrrev_b32_e32 v2, 8, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v0		; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v4, 24, v0		; GFX6-NEXT: v_lshrrev_b32_e32 v4, 24, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 24, v0
; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_max_i32_e32 v8, -1, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v5, 8, v1		; GFX6-NEXT: v_lshrrev_b32_e32 v5, 8, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v6, 16, v1		; GFX6-NEXT: v_lshrrev_b32_e32 v6, 16, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v7, 24, v1		; GFX6-NEXT: v_lshrrev_b32_e32 v7, 24, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v1		; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX6-NEXT: v_subrev_i32_e32 v8, vcc, s4, v8		; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 8
; GFX6-NEXT: s_brev_b32 s5, 1
; GFX6-NEXT: v_min_i32_e32 v10, -1, v0
; GFX6-NEXT: v_subrev_i32_e32 v10, vcc, s5, v10
; GFX6-NEXT: v_max_i32_e32 v1, v8, v1
; GFX6-NEXT: v_min_i32_e32 v1, v1, v10
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1		; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v2		; GFX6-NEXT: v_bfe_i32 v1, v2, 0, 8
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 24, v5		; GFX6-NEXT: v_bfe_i32 v2, v5, 0, 8
; GFX6-NEXT: v_max_i32_e32 v5, -1, v1
; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s4, v5
; GFX6-NEXT: v_min_i32_e32 v8, -1, v1
; GFX6-NEXT: v_subrev_i32_e32 v8, vcc, s5, v8
; GFX6-NEXT: v_max_i32_e32 v2, v5, v2
; GFX6-NEXT: v_min_i32_e32 v2, v2, v8
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v2		; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 24, v3		; GFX6-NEXT: v_bfe_i32 v2, v3, 0, 8
; GFX6-NEXT: v_bfrev_b32_e32 v9, -2		; GFX6-NEXT: v_bfe_i32 v3, v6, 0, 8
; GFX6-NEXT: v_max_i32_e32 v5, -1, v2		; GFX6-NEXT: s_movk_i32 s4, 0xff80
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 24, v6
; GFX6-NEXT: v_min_i32_e32 v6, -1, v2
; GFX6-NEXT: v_sub_i32_e32 v5, vcc, v5, v9
; GFX6-NEXT: v_subrev_i32_e32 v6, vcc, s5, v6
; GFX6-NEXT: v_max_i32_e32 v3, v5, v3
; GFX6-NEXT: v_min_i32_e32 v3, v3, v6
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v3		; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 24, v4		; GFX6-NEXT: v_bfe_i32 v3, v4, 0, 8
; GFX6-NEXT: v_max_i32_e32 v5, -1, v3		; GFX6-NEXT: v_bfe_i32 v4, v7, 0, 8
; GFX6-NEXT: v_bfrev_b32_e32 v11, 1		; GFX6-NEXT: v_sub_i32_e32 v3, vcc, v3, v4
; GFX6-NEXT: v_min_i32_e32 v6, -1, v3		; GFX6-NEXT: s_movk_i32 s5, 0x7f
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 24, v1		; GFX6-NEXT: v_max_i32_e32 v1, s4, v1
		; GFX6-NEXT: v_max_i32_e32 v0, s4, v0
		; GFX6-NEXT: v_max_i32_e32 v2, s4, v2
		; GFX6-NEXT: v_max_i32_e32 v3, s4, v3
		; GFX6-NEXT: v_min_i32_e32 v1, s5, v1
; GFX6-NEXT: s_movk_i32 s4, 0xff		; GFX6-NEXT: s_movk_i32 s4, 0xff
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 24, v7		; GFX6-NEXT: v_min_i32_e32 v0, s5, v0
; GFX6-NEXT: v_sub_i32_e32 v5, vcc, v5, v9
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 24, v0
; GFX6-NEXT: v_and_b32_e32 v1, s4, v1		; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
; GFX6-NEXT: v_sub_i32_e32 v6, vcc, v6, v11		; GFX6-NEXT: v_min_i32_e32 v2, s5, v2
; GFX6-NEXT: v_max_i32_e32 v4, v5, v4
; GFX6-NEXT: v_min_i32_e32 v4, v4, v6
; GFX6-NEXT: v_ashrrev_i32_e32 v2, 24, v2
; GFX6-NEXT: v_and_b32_e32 v0, s4, v0		; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 8, v1		; GFX6-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, v3, v4
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1		; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: v_and_b32_e32 v1, s4, v2		; GFX6-NEXT: v_and_b32_e32 v1, s4, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1		; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_ashrrev_i32_e32 v3, 24, v3		; GFX6-NEXT: v_min_i32_e32 v3, s5, v3
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1		; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: v_and_b32_e32 v1, s4, v3		; GFX6-NEXT: v_and_b32_e32 v1, s4, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v1		; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1		; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]		; GFX6-NEXT: s_setpc_b64 s[30:31]
;		;
; GFX8-LABEL: v_ssubsat_v4i8:		; GFX8-LABEL: v_ssubsat_v4i8:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
▲ Show 20 Lines • Show All 135 Lines • ▼ Show 20 Lines
; GFX6-LABEL: s_ssubsat_v4i8:		; GFX6-LABEL: s_ssubsat_v4i8:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshr_b32 s2, s0, 8		; GFX6-NEXT: s_lshr_b32 s2, s0, 8
; GFX6-NEXT: s_lshr_b32 s3, s0, 16		; GFX6-NEXT: s_lshr_b32 s3, s0, 16
; GFX6-NEXT: s_lshr_b32 s4, s0, 24		; GFX6-NEXT: s_lshr_b32 s4, s0, 24
; GFX6-NEXT: s_lshr_b32 s5, s1, 8		; GFX6-NEXT: s_lshr_b32 s5, s1, 8
; GFX6-NEXT: s_lshr_b32 s6, s1, 16		; GFX6-NEXT: s_lshr_b32 s6, s1, 16
; GFX6-NEXT: s_lshr_b32 s7, s1, 24		; GFX6-NEXT: s_lshr_b32 s7, s1, 24
; GFX6-NEXT: s_lshl_b32 s0, s0, 24		; GFX6-NEXT: s_sext_i32_i8 s0, s0
; GFX6-NEXT: s_lshl_b32 s1, s1, 24		; GFX6-NEXT: s_sext_i32_i8 s1, s1
; GFX6-NEXT: s_cmp_gt_i32 s0, -1
; GFX6-NEXT: s_brev_b32 s8, -2
; GFX6-NEXT: s_cselect_b32 s10, s0, -1
; GFX6-NEXT: s_sub_i32 s10, s10, s8
; GFX6-NEXT: s_cmp_lt_i32 s0, -1
; GFX6-NEXT: s_brev_b32 s9, 1
; GFX6-NEXT: s_cselect_b32 s11, s0, -1
; GFX6-NEXT: s_sub_i32 s11, s11, s9
; GFX6-NEXT: s_cmp_gt_i32 s10, s1
; GFX6-NEXT: s_cselect_b32 s1, s10, s1
; GFX6-NEXT: s_cmp_lt_i32 s1, s11
; GFX6-NEXT: s_cselect_b32 s1, s1, s11
; GFX6-NEXT: s_sub_i32 s0, s0, s1		; GFX6-NEXT: s_sub_i32 s0, s0, s1
; GFX6-NEXT: s_lshl_b32 s1, s2, 24		; GFX6-NEXT: s_movk_i32 s1, 0xff80
; GFX6-NEXT: s_ashr_i32 s0, s0, 24		; GFX6-NEXT: s_cmp_gt_i32 s0, s1
; GFX6-NEXT: s_lshl_b32 s2, s5, 24		; GFX6-NEXT: s_cselect_b32 s0, s0, s1
; GFX6-NEXT: s_cmp_gt_i32 s1, -1		; GFX6-NEXT: s_movk_i32 s8, 0x7f
; GFX6-NEXT: s_cselect_b32 s5, s1, -1		; GFX6-NEXT: s_cmp_lt_i32 s0, s8
; GFX6-NEXT: s_sub_i32 s5, s5, s8		; GFX6-NEXT: s_sext_i32_i8 s2, s2
; GFX6-NEXT: s_cmp_lt_i32 s1, -1		; GFX6-NEXT: s_sext_i32_i8 s5, s5
; GFX6-NEXT: s_cselect_b32 s10, s1, -1		; GFX6-NEXT: s_cselect_b32 s0, s0, s8
; GFX6-NEXT: s_sub_i32 s10, s10, s9		; GFX6-NEXT: s_sub_i32 s2, s2, s5
; GFX6-NEXT: s_cmp_gt_i32 s5, s2		; GFX6-NEXT: s_cmp_gt_i32 s2, s1
; GFX6-NEXT: s_cselect_b32 s2, s5, s2		; GFX6-NEXT: s_cselect_b32 s2, s2, s1
; GFX6-NEXT: s_cmp_lt_i32 s2, s10		; GFX6-NEXT: s_cmp_lt_i32 s2, s8
; GFX6-NEXT: s_cselect_b32 s2, s2, s10		; GFX6-NEXT: s_sext_i32_i8 s3, s3
; GFX6-NEXT: s_sub_i32 s1, s1, s2		; GFX6-NEXT: s_sext_i32_i8 s5, s6
; GFX6-NEXT: s_lshl_b32 s2, s3, 24		; GFX6-NEXT: s_cselect_b32 s2, s2, s8
; GFX6-NEXT: s_ashr_i32 s1, s1, 24		; GFX6-NEXT: s_sub_i32 s3, s3, s5
; GFX6-NEXT: s_lshl_b32 s3, s6, 24		; GFX6-NEXT: s_cmp_gt_i32 s3, s1
; GFX6-NEXT: s_cmp_gt_i32 s2, -1		; GFX6-NEXT: s_cselect_b32 s3, s3, s1
; GFX6-NEXT: s_cselect_b32 s5, s2, -1		; GFX6-NEXT: s_cmp_lt_i32 s3, s8
; GFX6-NEXT: s_sub_i32 s5, s5, s8		; GFX6-NEXT: s_sext_i32_i8 s4, s4
; GFX6-NEXT: s_cmp_lt_i32 s2, -1		; GFX6-NEXT: s_sext_i32_i8 s5, s7
; GFX6-NEXT: s_cselect_b32 s6, s2, -1		; GFX6-NEXT: s_cselect_b32 s3, s3, s8
; GFX6-NEXT: s_sub_i32 s6, s6, s9		; GFX6-NEXT: s_sub_i32 s4, s4, s5
; GFX6-NEXT: s_cmp_gt_i32 s5, s3		; GFX6-NEXT: s_cmp_gt_i32 s4, s1
; GFX6-NEXT: s_cselect_b32 s3, s5, s3		; GFX6-NEXT: s_cselect_b32 s1, s4, s1
; GFX6-NEXT: s_cmp_lt_i32 s3, s6		; GFX6-NEXT: s_cmp_lt_i32 s1, s8
; GFX6-NEXT: s_cselect_b32 s3, s3, s6
; GFX6-NEXT: s_sub_i32 s2, s2, s3
; GFX6-NEXT: s_lshl_b32 s3, s4, 24
; GFX6-NEXT: s_ashr_i32 s2, s2, 24
; GFX6-NEXT: s_lshl_b32 s4, s7, 24
; GFX6-NEXT: s_cmp_gt_i32 s3, -1
; GFX6-NEXT: s_cselect_b32 s5, s3, -1
; GFX6-NEXT: s_sub_i32 s5, s5, s8
; GFX6-NEXT: s_cmp_lt_i32 s3, -1
; GFX6-NEXT: s_cselect_b32 s6, s3, -1
; GFX6-NEXT: s_sub_i32 s6, s6, s9
; GFX6-NEXT: s_cmp_gt_i32 s5, s4
; GFX6-NEXT: s_cselect_b32 s4, s5, s4
; GFX6-NEXT: s_cmp_lt_i32 s4, s6
; GFX6-NEXT: s_cselect_b32 s4, s4, s6
; GFX6-NEXT: s_sub_i32 s3, s3, s4
; GFX6-NEXT: s_movk_i32 s4, 0xff		; GFX6-NEXT: s_movk_i32 s4, 0xff
; GFX6-NEXT: s_and_b32 s1, s1, s4		; GFX6-NEXT: s_cselect_b32 s1, s1, s8
		; GFX6-NEXT: s_and_b32 s2, s2, s4
; GFX6-NEXT: s_and_b32 s0, s0, s4		; GFX6-NEXT: s_and_b32 s0, s0, s4
; GFX6-NEXT: s_lshl_b32 s1, s1, 8		; GFX6-NEXT: s_lshl_b32 s2, s2, 8
; GFX6-NEXT: s_or_b32 s0, s0, s1		; GFX6-NEXT: s_or_b32 s0, s0, s2
; GFX6-NEXT: s_and_b32 s1, s2, s4		; GFX6-NEXT: s_and_b32 s2, s3, s4
; GFX6-NEXT: s_lshl_b32 s1, s1, 16		; GFX6-NEXT: s_and_b32 s1, s1, s4
; GFX6-NEXT: s_ashr_i32 s3, s3, 24		; GFX6-NEXT: s_lshl_b32 s2, s2, 16
; GFX6-NEXT: s_or_b32 s0, s0, s1		; GFX6-NEXT: s_or_b32 s0, s0, s2
; GFX6-NEXT: s_and_b32 s1, s3, s4
; GFX6-NEXT: s_lshl_b32 s1, s1, 24		; GFX6-NEXT: s_lshl_b32 s1, s1, 24
; GFX6-NEXT: s_or_b32 s0, s0, s1		; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: ; return to shader part epilog		; GFX6-NEXT: ; return to shader part epilog
;		;
; GFX8-LABEL: s_ssubsat_v4i8:		; GFX8-LABEL: s_ssubsat_v4i8:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_bfe_u32 s8, 8, 0x100000		; GFX8-NEXT: s_bfe_u32 s8, 8, 0x100000
; GFX8-NEXT: s_lshr_b32 s2, s0, 8		; GFX8-NEXT: s_lshr_b32 s2, s0, 8
▲ Show 20 Lines • Show All 194 Lines • ▼ Show 20 Lines	; GFX10-NEXT: ; return to shader part epilog
%cast.result = bitcast <4 x i8> %result to i32		%cast.result = bitcast <4 x i8> %result to i32
ret i32 %cast.result		ret i32 %cast.result
}		}

define i24 @v_ssubsat_i24(i24 %lhs, i24 %rhs) {		define i24 @v_ssubsat_i24(i24 %lhs, i24 %rhs) {
; GFX6-LABEL: v_ssubsat_i24:		; GFX6-LABEL: v_ssubsat_i24:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 8, v0		; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 24
; GFX6-NEXT: v_max_i32_e32 v2, -1, v0		; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 24
; GFX6-NEXT: v_min_i32_e32 v3, -1, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, 0x7fffffff, v2
; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, 0x80000000, v3
; GFX6-NEXT: v_max_i32_e32 v1, v2, v1
; GFX6-NEXT: v_min_i32_e32 v1, v1, v3
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1		; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 8, v0		; GFX6-NEXT: v_max_i32_e32 v0, 0xff800000, v0
		; GFX6-NEXT: v_min_i32_e32 v0, 0x7fffff, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]		; GFX6-NEXT: s_setpc_b64 s[30:31]
;		;
; GFX8-LABEL: v_ssubsat_i24:		; GFX8-LABEL: v_ssubsat_i24:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_sub_u32_e32 v2, vcc, v0, v1		; GFX8-NEXT: v_sub_u32_e32 v2, vcc, v0, v1
; GFX8-NEXT: v_bfe_i32 v3, v2, 0, 24		; GFX8-NEXT: v_bfe_i32 v3, v2, 0, 24
; GFX8-NEXT: v_bfe_i32 v0, v0, 0, 24		; GFX8-NEXT: v_bfe_i32 v0, v0, 0, 24
Show All 28 Lines
; GFX10-NEXT: s_setpc_b64 s[30:31]		; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call i24 @llvm.ssub.sat.i24(i24 %lhs, i24 %rhs)		%result = call i24 @llvm.ssub.sat.i24(i24 %lhs, i24 %rhs)
ret i24 %result		ret i24 %result
}		}

define amdgpu_ps i24 @s_ssubsat_i24(i24 inreg %lhs, i24 inreg %rhs) {		define amdgpu_ps i24 @s_ssubsat_i24(i24 inreg %lhs, i24 inreg %rhs) {
; GFX6-LABEL: s_ssubsat_i24:		; GFX6-LABEL: s_ssubsat_i24:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 8		; GFX6-NEXT: s_bfe_i32 s0, s0, 0x180000
; GFX6-NEXT: s_lshl_b32 s1, s1, 8		; GFX6-NEXT: s_bfe_i32 s1, s1, 0x180000
; GFX6-NEXT: s_cmp_gt_i32 s0, -1
; GFX6-NEXT: s_cselect_b32 s2, s0, -1
; GFX6-NEXT: s_sub_i32 s2, s2, 0x7fffffff
; GFX6-NEXT: s_cmp_lt_i32 s0, -1
; GFX6-NEXT: s_cselect_b32 s3, s0, -1
; GFX6-NEXT: s_sub_i32 s3, s3, 0x80000000
; GFX6-NEXT: s_cmp_gt_i32 s2, s1
; GFX6-NEXT: s_cselect_b32 s1, s2, s1
; GFX6-NEXT: s_cmp_lt_i32 s1, s3
; GFX6-NEXT: s_cselect_b32 s1, s1, s3
; GFX6-NEXT: s_sub_i32 s0, s0, s1		; GFX6-NEXT: s_sub_i32 s0, s0, s1
; GFX6-NEXT: s_ashr_i32 s0, s0, 8		; GFX6-NEXT: s_mov_b32 s1, 0xff800000
		; GFX6-NEXT: s_cmp_gt_i32 s0, s1
		; GFX6-NEXT: s_cselect_b32 s0, s0, s1
		; GFX6-NEXT: s_mov_b32 s1, 0x7fffff
		; GFX6-NEXT: s_cmp_lt_i32 s0, s1
		; GFX6-NEXT: s_cselect_b32 s0, s0, s1
; GFX6-NEXT: ; return to shader part epilog		; GFX6-NEXT: ; return to shader part epilog
;		;
; GFX8-LABEL: s_ssubsat_i24:		; GFX8-LABEL: s_ssubsat_i24:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_sub_i32 s2, s0, s1		; GFX8-NEXT: s_sub_i32 s2, s0, s1
; GFX8-NEXT: s_bfe_i32 s3, s2, 0x180000		; GFX8-NEXT: s_bfe_i32 s3, s2, 0x180000
; GFX8-NEXT: s_bfe_i32 s0, s0, 0x180000		; GFX8-NEXT: s_bfe_i32 s0, s0, 0x180000
; GFX8-NEXT: s_cmp_lt_i32 s3, s0		; GFX8-NEXT: s_cmp_lt_i32 s3, s0
▲ Show 20 Lines • Show All 1,775 Lines • ▼ Show 20 Lines	; GFX10-NEXT: ; return to shader part epilog
%result = call <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)		%result = call <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)
ret <16 x i32> %result		ret <16 x i32> %result
}		}

define i16 @v_ssubsat_i16(i16 %lhs, i16 %rhs) {		define i16 @v_ssubsat_i16(i16 %lhs, i16 %rhs) {
; GFX6-LABEL: v_ssubsat_i16:		; GFX6-LABEL: v_ssubsat_i16:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0		; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX6-NEXT: v_max_i32_e32 v2, -1, v0		; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16
; GFX6-NEXT: v_min_i32_e32 v3, -1, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, 0x7fffffff, v2
; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, 0x80000000, v3
; GFX6-NEXT: v_max_i32_e32 v1, v2, v1
; GFX6-NEXT: v_min_i32_e32 v1, v1, v3
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1		; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 16, v0		; GFX6-NEXT: v_max_i32_e32 v0, 0xffff8000, v0
		; GFX6-NEXT: v_min_i32_e32 v0, 0x7fff, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]		; GFX6-NEXT: s_setpc_b64 s[30:31]
;		;
; GFX8-LABEL: v_ssubsat_i16:		; GFX8-LABEL: v_ssubsat_i16:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_max_i16_e32 v2, -1, v0		; GFX8-NEXT: v_max_i16_e32 v2, -1, v0
; GFX8-NEXT: v_min_i16_e32 v3, -1, v0		; GFX8-NEXT: v_min_i16_e32 v3, -1, v0
; GFX8-NEXT: v_subrev_u16_e32 v2, 0x7fff, v2		; GFX8-NEXT: v_subrev_u16_e32 v2, 0x7fff, v2
Show All 18 Lines
; GFX10-NEXT: s_setpc_b64 s[30:31]		; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call i16 @llvm.ssub.sat.i16(i16 %lhs, i16 %rhs)		%result = call i16 @llvm.ssub.sat.i16(i16 %lhs, i16 %rhs)
ret i16 %result		ret i16 %result
}		}

define amdgpu_ps i16 @s_ssubsat_i16(i16 inreg %lhs, i16 inreg %rhs) {		define amdgpu_ps i16 @s_ssubsat_i16(i16 inreg %lhs, i16 inreg %rhs) {
; GFX6-LABEL: s_ssubsat_i16:		; GFX6-LABEL: s_ssubsat_i16:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 16		; GFX6-NEXT: s_sext_i32_i16 s0, s0
; GFX6-NEXT: s_lshl_b32 s1, s1, 16		; GFX6-NEXT: s_sext_i32_i16 s1, s1
; GFX6-NEXT: s_cmp_gt_i32 s0, -1
; GFX6-NEXT: s_cselect_b32 s2, s0, -1
; GFX6-NEXT: s_sub_i32 s2, s2, 0x7fffffff
; GFX6-NEXT: s_cmp_lt_i32 s0, -1
; GFX6-NEXT: s_cselect_b32 s3, s0, -1
; GFX6-NEXT: s_sub_i32 s3, s3, 0x80000000
; GFX6-NEXT: s_cmp_gt_i32 s2, s1
; GFX6-NEXT: s_cselect_b32 s1, s2, s1
; GFX6-NEXT: s_cmp_lt_i32 s1, s3
; GFX6-NEXT: s_cselect_b32 s1, s1, s3
; GFX6-NEXT: s_sub_i32 s0, s0, s1		; GFX6-NEXT: s_sub_i32 s0, s0, s1
; GFX6-NEXT: s_ashr_i32 s0, s0, 16		; GFX6-NEXT: s_movk_i32 s1, 0x8000
		; GFX6-NEXT: s_cmp_gt_i32 s0, s1
		; GFX6-NEXT: s_cselect_b32 s0, s0, s1
		; GFX6-NEXT: s_movk_i32 s1, 0x7fff
		; GFX6-NEXT: s_cmp_lt_i32 s0, s1
		; GFX6-NEXT: s_cselect_b32 s0, s0, s1
; GFX6-NEXT: ; return to shader part epilog		; GFX6-NEXT: ; return to shader part epilog
;		;
; GFX8-LABEL: s_ssubsat_i16:		; GFX8-LABEL: s_ssubsat_i16:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_sext_i32_i16 s2, s0		; GFX8-NEXT: s_sext_i32_i16 s2, s0
; GFX8-NEXT: s_sext_i32_i16 s3, -1		; GFX8-NEXT: s_sext_i32_i16 s3, -1
; GFX8-NEXT: s_cmp_gt_i32 s2, s3		; GFX8-NEXT: s_cmp_gt_i32 s2, s3
; GFX8-NEXT: s_cselect_b32 s4, s2, s3		; GFX8-NEXT: s_cselect_b32 s4, s2, s3
Show All 27 Lines
; GFX10-NEXT: ; return to shader part epilog		; GFX10-NEXT: ; return to shader part epilog
%result = call i16 @llvm.ssub.sat.i16(i16 %lhs, i16 %rhs)		%result = call i16 @llvm.ssub.sat.i16(i16 %lhs, i16 %rhs)
ret i16 %result		ret i16 %result
}		}

define amdgpu_ps half @ssubsat_i16_sv(i16 inreg %lhs, i16 %rhs) {		define amdgpu_ps half @ssubsat_i16_sv(i16 inreg %lhs, i16 %rhs) {
; GFX6-LABEL: ssubsat_i16_sv:		; GFX6-LABEL: ssubsat_i16_sv:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 16		; GFX6-NEXT: s_sext_i32_i16 s0, s0
; GFX6-NEXT: s_cmp_gt_i32 s0, -1		; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX6-NEXT: s_cselect_b32 s1, s0, -1
; GFX6-NEXT: s_sub_i32 s1, s1, 0x7fffffff
; GFX6-NEXT: s_cmp_lt_i32 s0, -1
; GFX6-NEXT: s_cselect_b32 s2, s0, -1
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX6-NEXT: s_sub_i32 s2, s2, 0x80000000
; GFX6-NEXT: v_max_i32_e32 v0, s1, v0
; GFX6-NEXT: v_min_i32_e32 v0, s2, v0
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s0, v0		; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s0, v0
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 16, v0		; GFX6-NEXT: v_max_i32_e32 v0, 0xffff8000, v0
		; GFX6-NEXT: v_min_i32_e32 v0, 0x7fff, v0
; GFX6-NEXT: ; return to shader part epilog		; GFX6-NEXT: ; return to shader part epilog
;		;
; GFX8-LABEL: ssubsat_i16_sv:		; GFX8-LABEL: ssubsat_i16_sv:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_sext_i32_i16 s1, s0		; GFX8-NEXT: s_sext_i32_i16 s1, s0
; GFX8-NEXT: s_sext_i32_i16 s2, -1		; GFX8-NEXT: s_sext_i32_i16 s2, -1
; GFX8-NEXT: s_cmp_gt_i32 s1, s2		; GFX8-NEXT: s_cmp_gt_i32 s1, s2
; GFX8-NEXT: s_cselect_b32 s3, s1, s2		; GFX8-NEXT: s_cselect_b32 s3, s1, s2
Show All 19 Lines	; GFX10-NEXT: ; return to shader part epilog
%result = call i16 @llvm.ssub.sat.i16(i16 %lhs, i16 %rhs)		%result = call i16 @llvm.ssub.sat.i16(i16 %lhs, i16 %rhs)
%cast = bitcast i16 %result to half		%cast = bitcast i16 %result to half
ret half %cast		ret half %cast
}		}

define amdgpu_ps half @ssubsat_i16_vs(i16 %lhs, i16 inreg %rhs) {		define amdgpu_ps half @ssubsat_i16_vs(i16 %lhs, i16 inreg %rhs) {
; GFX6-LABEL: ssubsat_i16_vs:		; GFX6-LABEL: ssubsat_i16_vs:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0		; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX6-NEXT: v_max_i32_e32 v1, -1, v0		; GFX6-NEXT: s_sext_i32_i16 s0, s0
; GFX6-NEXT: v_min_i32_e32 v2, -1, v0		; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s0, v0
; GFX6-NEXT: s_lshl_b32 s0, s0, 16		; GFX6-NEXT: v_max_i32_e32 v0, 0xffff8000, v0
; GFX6-NEXT: v_subrev_i32_e32 v1, vcc, 0x7fffffff, v1		; GFX6-NEXT: v_min_i32_e32 v0, 0x7fff, v0
; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, 0x80000000, v2
; GFX6-NEXT: v_max_i32_e32 v1, s0, v1
; GFX6-NEXT: v_min_i32_e32 v1, v1, v2
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 16, v0
; GFX6-NEXT: ; return to shader part epilog		; GFX6-NEXT: ; return to shader part epilog
;		;
; GFX8-LABEL: ssubsat_i16_vs:		; GFX8-LABEL: ssubsat_i16_vs:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: v_max_i16_e32 v1, -1, v0		; GFX8-NEXT: v_max_i16_e32 v1, -1, v0
; GFX8-NEXT: v_subrev_u16_e32 v1, 0x7fff, v1		; GFX8-NEXT: v_subrev_u16_e32 v1, 0x7fff, v1
; GFX8-NEXT: v_min_i16_e32 v2, -1, v0		; GFX8-NEXT: v_min_i16_e32 v2, -1, v0
; GFX8-NEXT: v_subrev_u16_e32 v2, 0x8000, v2		; GFX8-NEXT: v_subrev_u16_e32 v2, 0x8000, v2
Show All 16 Lines	; GFX10-NEXT: ; return to shader part epilog
%cast = bitcast i16 %result to half		%cast = bitcast i16 %result to half
ret half %cast		ret half %cast
}		}

define <2 x i16> @v_ssubsat_v2i16(<2 x i16> %lhs, <2 x i16> %rhs) {		define <2 x i16> @v_ssubsat_v2i16(<2 x i16> %lhs, <2 x i16> %rhs) {
; GFX6-LABEL: v_ssubsat_v2i16:		; GFX6-LABEL: v_ssubsat_v2i16:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0		; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX6-NEXT: s_brev_b32 s4, -2		; GFX6-NEXT: v_bfe_i32 v2, v2, 0, 16
; GFX6-NEXT: v_max_i32_e32 v4, -1, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s4, v4
; GFX6-NEXT: s_brev_b32 s5, 1
; GFX6-NEXT: v_min_i32_e32 v5, -1, v0
; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s5, v5
; GFX6-NEXT: v_max_i32_e32 v2, v4, v2
; GFX6-NEXT: v_min_i32_e32 v2, v2, v5
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v2		; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v3		; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16
; GFX6-NEXT: v_max_i32_e32 v3, -1, v1		; GFX6-NEXT: v_bfe_i32 v2, v3, 0, 16
; GFX6-NEXT: v_min_i32_e32 v4, -1, v1		; GFX6-NEXT: s_movk_i32 s4, 0x8000
; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s4, v3
; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s5, v4
; GFX6-NEXT: v_max_i32_e32 v2, v3, v2
; GFX6-NEXT: v_min_i32_e32 v2, v2, v4
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v2		; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v2
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 16, v0		; GFX6-NEXT: v_max_i32_e32 v0, s4, v0
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 16, v1		; GFX6-NEXT: s_movk_i32 s5, 0x7fff
		; GFX6-NEXT: v_max_i32_e32 v1, s4, v1
		; GFX6-NEXT: v_min_i32_e32 v0, s5, v0
		; GFX6-NEXT: v_min_i32_e32 v1, s5, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]		; GFX6-NEXT: s_setpc_b64 s[30:31]
;		;
; GFX8-LABEL: v_ssubsat_v2i16:		; GFX8-LABEL: v_ssubsat_v2i16:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: s_movk_i32 s4, 0x7fff		; GFX8-NEXT: s_movk_i32 s4, 0x7fff
; GFX8-NEXT: v_max_i16_e32 v3, -1, v0		; GFX8-NEXT: v_max_i16_e32 v3, -1, v0
; GFX8-NEXT: v_subrev_u16_e32 v3, s4, v3		; GFX8-NEXT: v_subrev_u16_e32 v3, s4, v3
Show All 29 Lines
; GFX10-NEXT: s_setpc_b64 s[30:31]		; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)		%result = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
ret <2 x i16> %result		ret <2 x i16> %result
}		}

define amdgpu_ps i32 @s_ssubsat_v2i16(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs) {		define amdgpu_ps i32 @s_ssubsat_v2i16(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs) {
; GFX6-LABEL: s_ssubsat_v2i16:		; GFX6-LABEL: s_ssubsat_v2i16:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 16		; GFX6-NEXT: s_sext_i32_i16 s0, s0
; GFX6-NEXT: s_lshl_b32 s2, s2, 16		; GFX6-NEXT: s_sext_i32_i16 s2, s2
; GFX6-NEXT: s_cmp_gt_i32 s0, -1
; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: s_cselect_b32 s6, s0, -1
; GFX6-NEXT: s_sub_i32 s6, s6, s4
; GFX6-NEXT: s_cmp_lt_i32 s0, -1
; GFX6-NEXT: s_brev_b32 s5, 1
; GFX6-NEXT: s_cselect_b32 s7, s0, -1
; GFX6-NEXT: s_sub_i32 s7, s7, s5
; GFX6-NEXT: s_cmp_gt_i32 s6, s2
; GFX6-NEXT: s_cselect_b32 s2, s6, s2
; GFX6-NEXT: s_cmp_lt_i32 s2, s7
; GFX6-NEXT: s_cselect_b32 s2, s2, s7
; GFX6-NEXT: s_sub_i32 s0, s0, s2		; GFX6-NEXT: s_sub_i32 s0, s0, s2
; GFX6-NEXT: s_ashr_i32 s0, s0, 16		; GFX6-NEXT: s_movk_i32 s2, 0x8000
; GFX6-NEXT: s_lshl_b32 s1, s1, 16		; GFX6-NEXT: s_cmp_gt_i32 s0, s2
; GFX6-NEXT: s_lshl_b32 s2, s3, 16		; GFX6-NEXT: s_cselect_b32 s0, s0, s2
; GFX6-NEXT: s_cmp_gt_i32 s1, -1		; GFX6-NEXT: s_movk_i32 s4, 0x7fff
; GFX6-NEXT: s_cselect_b32 s3, s1, -1		; GFX6-NEXT: s_cmp_lt_i32 s0, s4
; GFX6-NEXT: s_sub_i32 s3, s3, s4		; GFX6-NEXT: s_sext_i32_i16 s1, s1
; GFX6-NEXT: s_cmp_lt_i32 s1, -1		; GFX6-NEXT: s_sext_i32_i16 s3, s3
; GFX6-NEXT: s_cselect_b32 s4, s1, -1		; GFX6-NEXT: s_cselect_b32 s0, s0, s4
; GFX6-NEXT: s_sub_i32 s4, s4, s5		; GFX6-NEXT: s_sub_i32 s1, s1, s3
; GFX6-NEXT: s_cmp_gt_i32 s3, s2		; GFX6-NEXT: s_cmp_gt_i32 s1, s2
; GFX6-NEXT: s_cselect_b32 s2, s3, s2		; GFX6-NEXT: s_cselect_b32 s1, s1, s2
; GFX6-NEXT: s_cmp_lt_i32 s2, s4		; GFX6-NEXT: s_cmp_lt_i32 s1, s4
; GFX6-NEXT: s_cselect_b32 s2, s2, s4		; GFX6-NEXT: s_cselect_b32 s1, s1, s4
; GFX6-NEXT: s_sub_i32 s1, s1, s2
; GFX6-NEXT: s_mov_b32 s2, 0xffff		; GFX6-NEXT: s_mov_b32 s2, 0xffff
; GFX6-NEXT: s_ashr_i32 s1, s1, 16
; GFX6-NEXT: s_and_b32 s1, s1, s2		; GFX6-NEXT: s_and_b32 s1, s1, s2
; GFX6-NEXT: s_and_b32 s0, s0, s2		; GFX6-NEXT: s_and_b32 s0, s0, s2
; GFX6-NEXT: s_lshl_b32 s1, s1, 16		; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_or_b32 s0, s0, s1		; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: ; return to shader part epilog		; GFX6-NEXT: ; return to shader part epilog
;		;
; GFX8-LABEL: s_ssubsat_v2i16:		; GFX8-LABEL: s_ssubsat_v2i16:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines	; GFX10-NEXT: ; return to shader part epilog
%result = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)		%result = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
%cast = bitcast <2 x i16> %result to i32		%cast = bitcast <2 x i16> %result to i32
ret i32 %cast		ret i32 %cast
}		}

define amdgpu_ps float @ssubsat_v2i16_sv(<2 x i16> inreg %lhs, <2 x i16> %rhs) {		define amdgpu_ps float @ssubsat_v2i16_sv(<2 x i16> inreg %lhs, <2 x i16> %rhs) {
; GFX6-LABEL: ssubsat_v2i16_sv:		; GFX6-LABEL: ssubsat_v2i16_sv:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 16		; GFX6-NEXT: s_sext_i32_i16 s0, s0
; GFX6-NEXT: s_cmp_gt_i32 s0, -1		; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX6-NEXT: s_brev_b32 s2, -2		; GFX6-NEXT: s_sext_i32_i16 s1, s1
; GFX6-NEXT: s_cselect_b32 s4, s0, -1		; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16
; GFX6-NEXT: s_sub_i32 s4, s4, s2
; GFX6-NEXT: s_cmp_lt_i32 s0, -1
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX6-NEXT: s_brev_b32 s3, 1
; GFX6-NEXT: s_cselect_b32 s5, s0, -1
; GFX6-NEXT: s_sub_i32 s5, s5, s3
; GFX6-NEXT: v_max_i32_e32 v0, s4, v0
; GFX6-NEXT: v_min_i32_e32 v0, s5, v0
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s0, v0		; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s0, v0
; GFX6-NEXT: s_lshl_b32 s0, s1, 16		; GFX6-NEXT: s_movk_i32 s0, 0x8000
; GFX6-NEXT: s_cmp_gt_i32 s0, -1		; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s1, v1
; GFX6-NEXT: s_cselect_b32 s1, s0, -1		; GFX6-NEXT: s_movk_i32 s2, 0x7fff
; GFX6-NEXT: s_sub_i32 s1, s1, s2		; GFX6-NEXT: v_max_i32_e32 v1, s0, v1
; GFX6-NEXT: s_cmp_lt_i32 s0, -1		; GFX6-NEXT: v_max_i32_e32 v0, s0, v0
; GFX6-NEXT: s_cselect_b32 s2, s0, -1
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: s_sub_i32 s2, s2, s3
; GFX6-NEXT: v_max_i32_e32 v1, s1, v1
; GFX6-NEXT: v_min_i32_e32 v1, s2, v1		; GFX6-NEXT: v_min_i32_e32 v1, s2, v1
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s0, v1
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 16, v1
; GFX6-NEXT: s_mov_b32 s0, 0xffff		; GFX6-NEXT: s_mov_b32 s0, 0xffff
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 16, v0		; GFX6-NEXT: v_min_i32_e32 v0, s2, v0
; GFX6-NEXT: v_and_b32_e32 v1, s0, v1		; GFX6-NEXT: v_and_b32_e32 v1, s0, v1
; GFX6-NEXT: v_and_b32_e32 v0, s0, v0		; GFX6-NEXT: v_and_b32_e32 v0, s0, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1		; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1		; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: ; return to shader part epilog		; GFX6-NEXT: ; return to shader part epilog
;		;
; GFX8-LABEL: ssubsat_v2i16_sv:		; GFX8-LABEL: ssubsat_v2i16_sv:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
Show All 39 Lines	; GFX10-NEXT: ; return to shader part epilog
%result = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)		%result = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
%cast = bitcast <2 x i16> %result to float		%cast = bitcast <2 x i16> %result to float
ret float %cast		ret float %cast
}		}

define amdgpu_ps float @ssubsat_v2i16_vs(<2 x i16> %lhs, <2 x i16> inreg %rhs) {		define amdgpu_ps float @ssubsat_v2i16_vs(<2 x i16> %lhs, <2 x i16> inreg %rhs) {
; GFX6-LABEL: ssubsat_v2i16_vs:		; GFX6-LABEL: ssubsat_v2i16_vs:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0		; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX6-NEXT: s_brev_b32 s2, -2		; GFX6-NEXT: s_sext_i32_i16 s0, s0
; GFX6-NEXT: v_max_i32_e32 v2, -1, v0		; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16
; GFX6-NEXT: s_lshl_b32 s0, s0, 16		; GFX6-NEXT: s_sext_i32_i16 s1, s1
; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s2, v2		; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s0, v0
; GFX6-NEXT: s_brev_b32 s3, 1		; GFX6-NEXT: s_movk_i32 s0, 0x8000
; GFX6-NEXT: v_min_i32_e32 v3, -1, v0		; GFX6-NEXT: v_subrev_i32_e32 v1, vcc, s1, v1
; GFX6-NEXT: v_max_i32_e32 v2, s0, v2		; GFX6-NEXT: s_movk_i32 s2, 0x7fff
; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s3, v3		; GFX6-NEXT: v_max_i32_e32 v1, s0, v1
; GFX6-NEXT: v_min_i32_e32 v2, v2, v3		; GFX6-NEXT: v_max_i32_e32 v0, s0, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1		; GFX6-NEXT: v_min_i32_e32 v1, s2, v1
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
; GFX6-NEXT: v_max_i32_e32 v2, -1, v1
; GFX6-NEXT: v_min_i32_e32 v3, -1, v1
; GFX6-NEXT: s_lshl_b32 s0, s1, 16
; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s2, v2
; GFX6-NEXT: v_max_i32_e32 v2, s0, v2
; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s3, v3
; GFX6-NEXT: v_min_i32_e32 v2, v2, v3
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v2
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 16, v1
; GFX6-NEXT: s_mov_b32 s0, 0xffff		; GFX6-NEXT: s_mov_b32 s0, 0xffff
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 16, v0		; GFX6-NEXT: v_min_i32_e32 v0, s2, v0
; GFX6-NEXT: v_and_b32_e32 v1, s0, v1		; GFX6-NEXT: v_and_b32_e32 v1, s0, v1
; GFX6-NEXT: v_and_b32_e32 v0, s0, v0		; GFX6-NEXT: v_and_b32_e32 v0, s0, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1		; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1		; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: ; return to shader part epilog		; GFX6-NEXT: ; return to shader part epilog
;		;
; GFX8-LABEL: ssubsat_v2i16_vs:		; GFX8-LABEL: ssubsat_v2i16_vs:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; %result = call <3 x i16> @llvm.ssub.sat.v3i16(<3 x i16> %lhs, <3 x i16> %rhs)		; %result = call <3 x i16> @llvm.ssub.sat.v3i16(<3 x i16> %lhs, <3 x i16> %rhs)
; ret <3 x i16> %result		; ret <3 x i16> %result
; }		; }

define <2 x float> @v_ssubsat_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {		define <2 x float> @v_ssubsat_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
; GFX6-LABEL: v_ssubsat_v4i16:		; GFX6-LABEL: v_ssubsat_v4i16:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0		; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX6-NEXT: s_brev_b32 s4, -2		; GFX6-NEXT: v_bfe_i32 v4, v4, 0, 16
; GFX6-NEXT: v_max_i32_e32 v8, -1, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX6-NEXT: v_subrev_i32_e32 v8, vcc, s4, v8
; GFX6-NEXT: s_brev_b32 s5, 1
; GFX6-NEXT: v_min_i32_e32 v10, -1, v0
; GFX6-NEXT: v_subrev_i32_e32 v10, vcc, s5, v10
; GFX6-NEXT: v_max_i32_e32 v4, v8, v4
; GFX6-NEXT: v_min_i32_e32 v4, v4, v10
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v4		; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v5		; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16
; GFX6-NEXT: v_max_i32_e32 v5, -1, v1		; GFX6-NEXT: v_bfe_i32 v4, v5, 0, 16
; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s4, v5
; GFX6-NEXT: v_min_i32_e32 v8, -1, v1
; GFX6-NEXT: v_subrev_i32_e32 v8, vcc, s5, v8
; GFX6-NEXT: v_max_i32_e32 v4, v5, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX6-NEXT: v_min_i32_e32 v4, v4, v8
; GFX6-NEXT: v_bfrev_b32_e32 v9, -2
; GFX6-NEXT: v_max_i32_e32 v5, -1, v2
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v4		; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v6		; GFX6-NEXT: v_bfe_i32 v2, v2, 0, 16
; GFX6-NEXT: v_min_i32_e32 v6, -1, v2		; GFX6-NEXT: v_bfe_i32 v4, v6, 0, 16
; GFX6-NEXT: v_sub_i32_e32 v5, vcc, v5, v9		; GFX6-NEXT: s_movk_i32 s4, 0x8000
; GFX6-NEXT: v_subrev_i32_e32 v6, vcc, s5, v6
; GFX6-NEXT: v_max_i32_e32 v4, v5, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX6-NEXT: v_min_i32_e32 v4, v4, v6
; GFX6-NEXT: v_max_i32_e32 v5, -1, v3
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v4		; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v4
; GFX6-NEXT: v_bfrev_b32_e32 v11, 1		; GFX6-NEXT: v_bfe_i32 v3, v3, 0, 16
; GFX6-NEXT: v_min_i32_e32 v6, -1, v3		; GFX6-NEXT: v_bfe_i32 v4, v7, 0, 16
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v7
; GFX6-NEXT: v_sub_i32_e32 v5, vcc, v5, v9
; GFX6-NEXT: v_sub_i32_e32 v6, vcc, v6, v11
; GFX6-NEXT: v_max_i32_e32 v4, v5, v4
; GFX6-NEXT: v_min_i32_e32 v4, v4, v6
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 16, v1
; GFX6-NEXT: s_mov_b32 s4, 0xffff
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 16, v0
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, v3, v4		; GFX6-NEXT: v_sub_i32_e32 v3, vcc, v3, v4
		; GFX6-NEXT: s_movk_i32 s5, 0x7fff
		; GFX6-NEXT: v_max_i32_e32 v1, s4, v1
		; GFX6-NEXT: v_max_i32_e32 v0, s4, v0
		; GFX6-NEXT: v_max_i32_e32 v2, s4, v2
		; GFX6-NEXT: v_max_i32_e32 v3, s4, v3
		; GFX6-NEXT: v_min_i32_e32 v1, s5, v1
		; GFX6-NEXT: s_mov_b32 s4, 0xffff
		; GFX6-NEXT: v_min_i32_e32 v0, s5, v0
; GFX6-NEXT: v_and_b32_e32 v1, s4, v1		; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
; GFX6-NEXT: v_ashrrev_i32_e32 v2, 16, v2		; GFX6-NEXT: v_min_i32_e32 v2, s5, v2
; GFX6-NEXT: v_ashrrev_i32_e32 v3, 16, v3		; GFX6-NEXT: v_min_i32_e32 v3, s5, v3
; GFX6-NEXT: v_and_b32_e32 v0, s4, v0		; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1		; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1		; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: v_and_b32_e32 v1, s4, v2		; GFX6-NEXT: v_and_b32_e32 v1, s4, v2
; GFX6-NEXT: v_and_b32_e32 v2, s4, v3		; GFX6-NEXT: v_and_b32_e32 v2, s4, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2		; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX6-NEXT: v_or_b32_e32 v1, v1, v2		; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
; GFX6-NEXT: s_setpc_b64 s[30:31]		; GFX6-NEXT: s_setpc_b64 s[30:31]
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines	; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)		%result = call <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
%cast = bitcast <4 x i16> %result to <2 x float>		%cast = bitcast <4 x i16> %result to <2 x float>
ret <2 x float> %cast		ret <2 x float> %cast
}		}

define amdgpu_ps <2 x i32> @s_ssubsat_v4i16(<4 x i16> inreg %lhs, <4 x i16> inreg %rhs) {		define amdgpu_ps <2 x i32> @s_ssubsat_v4i16(<4 x i16> inreg %lhs, <4 x i16> inreg %rhs) {
; GFX6-LABEL: s_ssubsat_v4i16:		; GFX6-LABEL: s_ssubsat_v4i16:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 16		; GFX6-NEXT: s_sext_i32_i16 s0, s0
; GFX6-NEXT: s_lshl_b32 s4, s4, 16		; GFX6-NEXT: s_sext_i32_i16 s4, s4
; GFX6-NEXT: s_cmp_gt_i32 s0, -1
; GFX6-NEXT: s_brev_b32 s8, -2
; GFX6-NEXT: s_cselect_b32 s10, s0, -1
; GFX6-NEXT: s_sub_i32 s10, s10, s8
; GFX6-NEXT: s_cmp_lt_i32 s0, -1
; GFX6-NEXT: s_brev_b32 s9, 1
; GFX6-NEXT: s_cselect_b32 s11, s0, -1
; GFX6-NEXT: s_sub_i32 s11, s11, s9
; GFX6-NEXT: s_cmp_gt_i32 s10, s4
; GFX6-NEXT: s_cselect_b32 s4, s10, s4
; GFX6-NEXT: s_cmp_lt_i32 s4, s11
; GFX6-NEXT: s_cselect_b32 s4, s4, s11
; GFX6-NEXT: s_sub_i32 s0, s0, s4		; GFX6-NEXT: s_sub_i32 s0, s0, s4
; GFX6-NEXT: s_ashr_i32 s0, s0, 16		; GFX6-NEXT: s_movk_i32 s4, 0x8000
; GFX6-NEXT: s_lshl_b32 s1, s1, 16		; GFX6-NEXT: s_cmp_gt_i32 s0, s4
; GFX6-NEXT: s_lshl_b32 s4, s5, 16		; GFX6-NEXT: s_cselect_b32 s0, s0, s4
; GFX6-NEXT: s_cmp_gt_i32 s1, -1		; GFX6-NEXT: s_movk_i32 s8, 0x7fff
; GFX6-NEXT: s_cselect_b32 s5, s1, -1		; GFX6-NEXT: s_cmp_lt_i32 s0, s8
; GFX6-NEXT: s_sub_i32 s5, s5, s8		; GFX6-NEXT: s_sext_i32_i16 s1, s1
; GFX6-NEXT: s_cmp_lt_i32 s1, -1		; GFX6-NEXT: s_sext_i32_i16 s5, s5
; GFX6-NEXT: s_cselect_b32 s10, s1, -1		; GFX6-NEXT: s_cselect_b32 s0, s0, s8
; GFX6-NEXT: s_sub_i32 s10, s10, s9		; GFX6-NEXT: s_sub_i32 s1, s1, s5
; GFX6-NEXT: s_cmp_gt_i32 s5, s4		; GFX6-NEXT: s_cmp_gt_i32 s1, s4
; GFX6-NEXT: s_cselect_b32 s4, s5, s4		; GFX6-NEXT: s_cselect_b32 s1, s1, s4
; GFX6-NEXT: s_cmp_lt_i32 s4, s10		; GFX6-NEXT: s_cmp_lt_i32 s1, s8
; GFX6-NEXT: s_cselect_b32 s4, s4, s10		; GFX6-NEXT: s_sext_i32_i16 s2, s2
; GFX6-NEXT: s_sub_i32 s1, s1, s4		; GFX6-NEXT: s_sext_i32_i16 s5, s6
; GFX6-NEXT: s_ashr_i32 s1, s1, 16		; GFX6-NEXT: s_cselect_b32 s1, s1, s8
; GFX6-NEXT: s_lshl_b32 s2, s2, 16		; GFX6-NEXT: s_sub_i32 s2, s2, s5
; GFX6-NEXT: s_lshl_b32 s4, s6, 16		; GFX6-NEXT: s_cmp_gt_i32 s2, s4
; GFX6-NEXT: s_cmp_gt_i32 s2, -1		; GFX6-NEXT: s_cselect_b32 s2, s2, s4
; GFX6-NEXT: s_cselect_b32 s5, s2, -1		; GFX6-NEXT: s_cmp_lt_i32 s2, s8
; GFX6-NEXT: s_sub_i32 s5, s5, s8		; GFX6-NEXT: s_sext_i32_i16 s3, s3
; GFX6-NEXT: s_cmp_lt_i32 s2, -1		; GFX6-NEXT: s_sext_i32_i16 s5, s7
; GFX6-NEXT: s_cselect_b32 s6, s2, -1		; GFX6-NEXT: s_cselect_b32 s2, s2, s8
; GFX6-NEXT: s_sub_i32 s6, s6, s9		; GFX6-NEXT: s_sub_i32 s3, s3, s5
; GFX6-NEXT: s_cmp_gt_i32 s5, s4		; GFX6-NEXT: s_cmp_gt_i32 s3, s4
; GFX6-NEXT: s_cselect_b32 s4, s5, s4		; GFX6-NEXT: s_cselect_b32 s3, s3, s4
; GFX6-NEXT: s_cmp_lt_i32 s4, s6		; GFX6-NEXT: s_cmp_lt_i32 s3, s8
; GFX6-NEXT: s_cselect_b32 s4, s4, s6
; GFX6-NEXT: s_sub_i32 s2, s2, s4
; GFX6-NEXT: s_ashr_i32 s2, s2, 16
; GFX6-NEXT: s_lshl_b32 s3, s3, 16
; GFX6-NEXT: s_lshl_b32 s4, s7, 16
; GFX6-NEXT: s_cmp_gt_i32 s3, -1
; GFX6-NEXT: s_cselect_b32 s5, s3, -1
; GFX6-NEXT: s_sub_i32 s5, s5, s8
; GFX6-NEXT: s_cmp_lt_i32 s3, -1
; GFX6-NEXT: s_cselect_b32 s6, s3, -1
; GFX6-NEXT: s_sub_i32 s6, s6, s9
; GFX6-NEXT: s_cmp_gt_i32 s5, s4
; GFX6-NEXT: s_cselect_b32 s4, s5, s4
; GFX6-NEXT: s_cmp_lt_i32 s4, s6
; GFX6-NEXT: s_cselect_b32 s4, s4, s6
; GFX6-NEXT: s_sub_i32 s3, s3, s4
; GFX6-NEXT: s_mov_b32 s4, 0xffff		; GFX6-NEXT: s_mov_b32 s4, 0xffff
		; GFX6-NEXT: s_cselect_b32 s3, s3, s8
; GFX6-NEXT: s_and_b32 s1, s1, s4		; GFX6-NEXT: s_and_b32 s1, s1, s4
; GFX6-NEXT: s_ashr_i32 s3, s3, 16
; GFX6-NEXT: s_and_b32 s0, s0, s4		; GFX6-NEXT: s_and_b32 s0, s0, s4
; GFX6-NEXT: s_lshl_b32 s1, s1, 16		; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_or_b32 s0, s0, s1		; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: s_and_b32 s1, s2, s4		; GFX6-NEXT: s_and_b32 s1, s2, s4
; GFX6-NEXT: s_and_b32 s2, s3, s4		; GFX6-NEXT: s_and_b32 s2, s3, s4
; GFX6-NEXT: s_lshl_b32 s2, s2, 16		; GFX6-NEXT: s_lshl_b32 s2, s2, 16
; GFX6-NEXT: s_or_b32 s1, s1, s2		; GFX6-NEXT: s_or_b32 s1, s1, s2
; GFX6-NEXT: ; return to shader part epilog		; GFX6-NEXT: ; return to shader part epilog
▲ Show 20 Lines • Show All 114 Lines • ▼ Show 20 Lines
; %result = call <5 x i16> @llvm.ssub.sat.v5i16(<5 x i16> %lhs, <5 x i16> %rhs)		; %result = call <5 x i16> @llvm.ssub.sat.v5i16(<5 x i16> %lhs, <5 x i16> %rhs)
; ret <5 x i16> %result		; ret <5 x i16> %result
; }		; }

define <3 x float> @v_ssubsat_v6i16(<6 x i16> %lhs, <6 x i16> %rhs) {		define <3 x float> @v_ssubsat_v6i16(<6 x i16> %lhs, <6 x i16> %rhs) {
; GFX6-LABEL: v_ssubsat_v6i16:		; GFX6-LABEL: v_ssubsat_v6i16:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0		; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16
; GFX6-NEXT: s_brev_b32 s4, -2		; GFX6-NEXT: v_bfe_i32 v7, v7, 0, 16
; GFX6-NEXT: v_max_i32_e32 v12, -1, v0		; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v7
; GFX6-NEXT: v_lshlrev_b32_e32 v6, 16, v6		; GFX6-NEXT: v_bfe_i32 v2, v2, 0, 16
; GFX6-NEXT: v_subrev_i32_e32 v12, vcc, s4, v12		; GFX6-NEXT: v_bfe_i32 v7, v8, 0, 16
; GFX6-NEXT: s_brev_b32 s5, 1		; GFX6-NEXT: s_movk_i32 s4, 0x8000
; GFX6-NEXT: v_min_i32_e32 v14, -1, v0		; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v7
; GFX6-NEXT: v_subrev_i32_e32 v14, vcc, s5, v14		; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX6-NEXT: v_max_i32_e32 v6, v12, v6		; GFX6-NEXT: v_bfe_i32 v6, v6, 0, 16
; GFX6-NEXT: v_min_i32_e32 v6, v6, v14		; GFX6-NEXT: v_bfe_i32 v3, v3, 0, 16
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1		; GFX6-NEXT: v_bfe_i32 v7, v9, 0, 16
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v6		; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v6
; GFX6-NEXT: v_lshlrev_b32_e32 v6, 16, v7		; GFX6-NEXT: v_sub_i32_e32 v3, vcc, v3, v7
; GFX6-NEXT: v_max_i32_e32 v7, -1, v1		; GFX6-NEXT: s_movk_i32 s5, 0x7fff
; GFX6-NEXT: v_subrev_i32_e32 v7, vcc, s4, v7		; GFX6-NEXT: v_max_i32_e32 v1, s4, v1
; GFX6-NEXT: v_min_i32_e32 v12, -1, v1		; GFX6-NEXT: v_bfe_i32 v4, v4, 0, 16
; GFX6-NEXT: v_subrev_i32_e32 v12, vcc, s5, v12		; GFX6-NEXT: v_bfe_i32 v7, v10, 0, 16
; GFX6-NEXT: v_max_i32_e32 v6, v7, v6		; GFX6-NEXT: v_max_i32_e32 v0, s4, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2		; GFX6-NEXT: v_max_i32_e32 v2, s4, v2
; GFX6-NEXT: v_min_i32_e32 v6, v6, v12		; GFX6-NEXT: v_max_i32_e32 v3, s4, v3
; GFX6-NEXT: v_bfrev_b32_e32 v13, -2		; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v4, v7
; GFX6-NEXT: v_max_i32_e32 v7, -1, v2		; GFX6-NEXT: v_min_i32_e32 v1, s5, v1
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v6
; GFX6-NEXT: v_lshlrev_b32_e32 v6, 16, v8
; GFX6-NEXT: v_min_i32_e32 v8, -1, v2
; GFX6-NEXT: v_sub_i32_e32 v7, vcc, v7, v13
; GFX6-NEXT: v_subrev_i32_e32 v8, vcc, s5, v8
; GFX6-NEXT: v_max_i32_e32 v6, v7, v6
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX6-NEXT: v_min_i32_e32 v6, v6, v8
; GFX6-NEXT: v_max_i32_e32 v7, -1, v3
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v6
; GFX6-NEXT: v_bfrev_b32_e32 v15, 1
; GFX6-NEXT: v_min_i32_e32 v8, -1, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v6, 16, v9
; GFX6-NEXT: v_sub_i32_e32 v7, vcc, v7, v13
; GFX6-NEXT: v_sub_i32_e32 v8, vcc, v8, v15
; GFX6-NEXT: v_max_i32_e32 v6, v7, v6
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX6-NEXT: v_min_i32_e32 v6, v6, v8
; GFX6-NEXT: v_max_i32_e32 v7, -1, v4
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, v3, v6
; GFX6-NEXT: v_min_i32_e32 v8, -1, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v6, 16, v10
; GFX6-NEXT: v_sub_i32_e32 v7, vcc, v7, v13
; GFX6-NEXT: v_sub_i32_e32 v8, vcc, v8, v15
; GFX6-NEXT: v_max_i32_e32 v6, v7, v6
; GFX6-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX6-NEXT: v_min_i32_e32 v6, v6, v8
; GFX6-NEXT: v_max_i32_e32 v7, -1, v5
; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v4, v6
; GFX6-NEXT: v_min_i32_e32 v8, -1, v5
; GFX6-NEXT: v_lshlrev_b32_e32 v6, 16, v11
; GFX6-NEXT: v_sub_i32_e32 v7, vcc, v7, v13
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 16, v1
; GFX6-NEXT: s_mov_b32 s4, 0xffff		; GFX6-NEXT: s_mov_b32 s4, 0xffff
; GFX6-NEXT: v_sub_i32_e32 v8, vcc, v8, v15		; GFX6-NEXT: v_bfe_i32 v5, v5, 0, 16
; GFX6-NEXT: v_max_i32_e32 v6, v7, v6		; GFX6-NEXT: v_bfe_i32 v7, v11, 0, 16
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 16, v0		; GFX6-NEXT: v_min_i32_e32 v0, s5, v0
; GFX6-NEXT: v_and_b32_e32 v1, s4, v1		; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
; GFX6-NEXT: v_min_i32_e32 v6, v6, v8		; GFX6-NEXT: v_mov_b32_e32 v6, 0xffff8000
; GFX6-NEXT: v_sub_i32_e32 v5, vcc, v5, v6		; GFX6-NEXT: v_sub_i32_e32 v5, vcc, v5, v7
; GFX6-NEXT: v_ashrrev_i32_e32 v2, 16, v2		; GFX6-NEXT: v_max_i32_e32 v5, v5, v6
; GFX6-NEXT: v_ashrrev_i32_e32 v3, 16, v3		; GFX6-NEXT: v_min_i32_e32 v2, s5, v2
		; GFX6-NEXT: v_min_i32_e32 v3, s5, v3
; GFX6-NEXT: v_and_b32_e32 v0, s4, v0		; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1		; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
		; GFX6-NEXT: v_max_i32_e32 v4, v4, v6
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1		; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: v_and_b32_e32 v1, s4, v2		; GFX6-NEXT: v_and_b32_e32 v1, s4, v2
; GFX6-NEXT: v_and_b32_e32 v2, s4, v3		; GFX6-NEXT: v_and_b32_e32 v2, s4, v3
; GFX6-NEXT: v_ashrrev_i32_e32 v5, 16, v5		; GFX6-NEXT: v_min_i32_e32 v5, 0x7fff, v5
; GFX6-NEXT: v_and_b32_e32 v3, s4, v5		; GFX6-NEXT: v_and_b32_e32 v3, s4, v5
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2		; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX6-NEXT: v_ashrrev_i32_e32 v4, 16, v4		; GFX6-NEXT: v_min_i32_e32 v4, s5, v4
; GFX6-NEXT: v_or_b32_e32 v1, v1, v2		; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
; GFX6-NEXT: v_and_b32_e32 v2, s4, v4		; GFX6-NEXT: v_and_b32_e32 v2, s4, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3		; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX6-NEXT: v_or_b32_e32 v2, v2, v3		; GFX6-NEXT: v_or_b32_e32 v2, v2, v3
; GFX6-NEXT: s_setpc_b64 s[30:31]		; GFX6-NEXT: s_setpc_b64 s[30:31]
;		;
; GFX8-LABEL: v_ssubsat_v6i16:		; GFX8-LABEL: v_ssubsat_v6i16:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
▲ Show 20 Lines • Show All 72 Lines • ▼ Show 20 Lines	; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <6 x i16> @llvm.ssub.sat.v6i16(<6 x i16> %lhs, <6 x i16> %rhs)		%result = call <6 x i16> @llvm.ssub.sat.v6i16(<6 x i16> %lhs, <6 x i16> %rhs)
%cast = bitcast <6 x i16> %result to <3 x float>		%cast = bitcast <6 x i16> %result to <3 x float>
ret <3 x float> %cast		ret <3 x float> %cast
}		}

define amdgpu_ps <3 x i32> @s_ssubsat_v6i16(<6 x i16> inreg %lhs, <6 x i16> inreg %rhs) {		define amdgpu_ps <3 x i32> @s_ssubsat_v6i16(<6 x i16> inreg %lhs, <6 x i16> inreg %rhs) {
; GFX6-LABEL: s_ssubsat_v6i16:		; GFX6-LABEL: s_ssubsat_v6i16:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 16		; GFX6-NEXT: s_sext_i32_i16 s0, s0
; GFX6-NEXT: s_lshl_b32 s6, s6, 16		; GFX6-NEXT: s_sext_i32_i16 s6, s6
; GFX6-NEXT: s_cmp_gt_i32 s0, -1
; GFX6-NEXT: s_brev_b32 s12, -2
; GFX6-NEXT: s_cselect_b32 s14, s0, -1
; GFX6-NEXT: s_sub_i32 s14, s14, s12
; GFX6-NEXT: s_cmp_lt_i32 s0, -1
; GFX6-NEXT: s_brev_b32 s13, 1
; GFX6-NEXT: s_cselect_b32 s15, s0, -1
; GFX6-NEXT: s_sub_i32 s15, s15, s13
; GFX6-NEXT: s_cmp_gt_i32 s14, s6
; GFX6-NEXT: s_cselect_b32 s6, s14, s6
; GFX6-NEXT: s_cmp_lt_i32 s6, s15
; GFX6-NEXT: s_cselect_b32 s6, s6, s15
; GFX6-NEXT: s_sub_i32 s0, s0, s6		; GFX6-NEXT: s_sub_i32 s0, s0, s6
; GFX6-NEXT: s_ashr_i32 s0, s0, 16		; GFX6-NEXT: s_movk_i32 s6, 0x8000
; GFX6-NEXT: s_lshl_b32 s1, s1, 16		; GFX6-NEXT: s_cmp_gt_i32 s0, s6
; GFX6-NEXT: s_lshl_b32 s6, s7, 16		; GFX6-NEXT: s_cselect_b32 s0, s0, s6
; GFX6-NEXT: s_cmp_gt_i32 s1, -1		; GFX6-NEXT: s_movk_i32 s12, 0x7fff
; GFX6-NEXT: s_cselect_b32 s7, s1, -1		; GFX6-NEXT: s_cmp_lt_i32 s0, s12
; GFX6-NEXT: s_sub_i32 s7, s7, s12		; GFX6-NEXT: s_sext_i32_i16 s1, s1
; GFX6-NEXT: s_cmp_lt_i32 s1, -1		; GFX6-NEXT: s_sext_i32_i16 s7, s7
; GFX6-NEXT: s_cselect_b32 s14, s1, -1		; GFX6-NEXT: s_cselect_b32 s0, s0, s12
; GFX6-NEXT: s_sub_i32 s14, s14, s13		; GFX6-NEXT: s_sub_i32 s1, s1, s7
; GFX6-NEXT: s_cmp_gt_i32 s7, s6		; GFX6-NEXT: s_cmp_gt_i32 s1, s6
; GFX6-NEXT: s_cselect_b32 s6, s7, s6		; GFX6-NEXT: s_cselect_b32 s1, s1, s6
; GFX6-NEXT: s_cmp_lt_i32 s6, s14		; GFX6-NEXT: s_cmp_lt_i32 s1, s12
; GFX6-NEXT: s_cselect_b32 s6, s6, s14		; GFX6-NEXT: s_sext_i32_i16 s2, s2
; GFX6-NEXT: s_sub_i32 s1, s1, s6		; GFX6-NEXT: s_sext_i32_i16 s7, s8
; GFX6-NEXT: s_ashr_i32 s1, s1, 16		; GFX6-NEXT: s_cselect_b32 s1, s1, s12
; GFX6-NEXT: s_lshl_b32 s2, s2, 16		; GFX6-NEXT: s_sub_i32 s2, s2, s7
; GFX6-NEXT: s_lshl_b32 s6, s8, 16		; GFX6-NEXT: s_cmp_gt_i32 s2, s6
; GFX6-NEXT: s_cmp_gt_i32 s2, -1		; GFX6-NEXT: s_cselect_b32 s2, s2, s6
; GFX6-NEXT: s_cselect_b32 s7, s2, -1		; GFX6-NEXT: s_cmp_lt_i32 s2, s12
; GFX6-NEXT: s_sub_i32 s7, s7, s12		; GFX6-NEXT: s_sext_i32_i16 s3, s3
; GFX6-NEXT: s_cmp_lt_i32 s2, -1		; GFX6-NEXT: s_sext_i32_i16 s7, s9
; GFX6-NEXT: s_cselect_b32 s8, s2, -1		; GFX6-NEXT: s_cselect_b32 s2, s2, s12
; GFX6-NEXT: s_sub_i32 s8, s8, s13		; GFX6-NEXT: s_sub_i32 s3, s3, s7
; GFX6-NEXT: s_cmp_gt_i32 s7, s6		; GFX6-NEXT: s_cmp_gt_i32 s3, s6
; GFX6-NEXT: s_cselect_b32 s6, s7, s6		; GFX6-NEXT: s_cselect_b32 s3, s3, s6
; GFX6-NEXT: s_cmp_lt_i32 s6, s8		; GFX6-NEXT: s_cmp_lt_i32 s3, s12
; GFX6-NEXT: s_cselect_b32 s6, s6, s8		; GFX6-NEXT: s_sext_i32_i16 s4, s4
; GFX6-NEXT: s_sub_i32 s2, s2, s6		; GFX6-NEXT: s_sext_i32_i16 s7, s10
; GFX6-NEXT: s_ashr_i32 s2, s2, 16		; GFX6-NEXT: s_cselect_b32 s3, s3, s12
; GFX6-NEXT: s_lshl_b32 s3, s3, 16		; GFX6-NEXT: s_sub_i32 s4, s4, s7
; GFX6-NEXT: s_lshl_b32 s6, s9, 16		; GFX6-NEXT: s_cmp_gt_i32 s4, s6
; GFX6-NEXT: s_cmp_gt_i32 s3, -1		; GFX6-NEXT: s_cselect_b32 s4, s4, s6
; GFX6-NEXT: s_cselect_b32 s7, s3, -1		; GFX6-NEXT: s_cmp_lt_i32 s4, s12
; GFX6-NEXT: s_sub_i32 s7, s7, s12		; GFX6-NEXT: s_sext_i32_i16 s5, s5
; GFX6-NEXT: s_cmp_lt_i32 s3, -1		; GFX6-NEXT: s_sext_i32_i16 s7, s11
; GFX6-NEXT: s_cselect_b32 s8, s3, -1		; GFX6-NEXT: s_cselect_b32 s4, s4, s12
; GFX6-NEXT: s_sub_i32 s8, s8, s13		; GFX6-NEXT: s_sub_i32 s5, s5, s7
; GFX6-NEXT: s_cmp_gt_i32 s7, s6		; GFX6-NEXT: s_cmp_gt_i32 s5, s6
; GFX6-NEXT: s_cselect_b32 s6, s7, s6		; GFX6-NEXT: s_cselect_b32 s5, s5, s6
; GFX6-NEXT: s_cmp_lt_i32 s6, s8		; GFX6-NEXT: s_cmp_lt_i32 s5, s12
; GFX6-NEXT: s_cselect_b32 s6, s6, s8
; GFX6-NEXT: s_sub_i32 s3, s3, s6
; GFX6-NEXT: s_ashr_i32 s3, s3, 16
; GFX6-NEXT: s_lshl_b32 s4, s4, 16
; GFX6-NEXT: s_lshl_b32 s6, s10, 16
; GFX6-NEXT: s_cmp_gt_i32 s4, -1
; GFX6-NEXT: s_cselect_b32 s7, s4, -1
; GFX6-NEXT: s_sub_i32 s7, s7, s12
; GFX6-NEXT: s_cmp_lt_i32 s4, -1
; GFX6-NEXT: s_cselect_b32 s8, s4, -1
; GFX6-NEXT: s_sub_i32 s8, s8, s13
; GFX6-NEXT: s_cmp_gt_i32 s7, s6
; GFX6-NEXT: s_cselect_b32 s6, s7, s6
; GFX6-NEXT: s_cmp_lt_i32 s6, s8
; GFX6-NEXT: s_cselect_b32 s6, s6, s8
; GFX6-NEXT: s_sub_i32 s4, s4, s6
; GFX6-NEXT: s_ashr_i32 s4, s4, 16
; GFX6-NEXT: s_lshl_b32 s5, s5, 16
; GFX6-NEXT: s_lshl_b32 s6, s11, 16
; GFX6-NEXT: s_cmp_gt_i32 s5, -1
; GFX6-NEXT: s_cselect_b32 s7, s5, -1
; GFX6-NEXT: s_sub_i32 s7, s7, s12
; GFX6-NEXT: s_cmp_lt_i32 s5, -1
; GFX6-NEXT: s_cselect_b32 s8, s5, -1
; GFX6-NEXT: s_sub_i32 s8, s8, s13
; GFX6-NEXT: s_cmp_gt_i32 s7, s6
; GFX6-NEXT: s_cselect_b32 s6, s7, s6
; GFX6-NEXT: s_cmp_lt_i32 s6, s8
; GFX6-NEXT: s_cselect_b32 s6, s6, s8
; GFX6-NEXT: s_sub_i32 s5, s5, s6
; GFX6-NEXT: s_mov_b32 s6, 0xffff		; GFX6-NEXT: s_mov_b32 s6, 0xffff
		; GFX6-NEXT: s_cselect_b32 s5, s5, s12
; GFX6-NEXT: s_and_b32 s1, s1, s6		; GFX6-NEXT: s_and_b32 s1, s1, s6
; GFX6-NEXT: s_and_b32 s0, s0, s6		; GFX6-NEXT: s_and_b32 s0, s0, s6
; GFX6-NEXT: s_lshl_b32 s1, s1, 16		; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_or_b32 s0, s0, s1		; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: s_and_b32 s1, s2, s6		; GFX6-NEXT: s_and_b32 s1, s2, s6
; GFX6-NEXT: s_and_b32 s2, s3, s6		; GFX6-NEXT: s_and_b32 s2, s3, s6
; GFX6-NEXT: s_ashr_i32 s5, s5, 16
; GFX6-NEXT: s_and_b32 s3, s5, s6		; GFX6-NEXT: s_and_b32 s3, s5, s6
; GFX6-NEXT: s_lshl_b32 s2, s2, 16		; GFX6-NEXT: s_lshl_b32 s2, s2, 16
; GFX6-NEXT: s_or_b32 s1, s1, s2		; GFX6-NEXT: s_or_b32 s1, s1, s2
; GFX6-NEXT: s_and_b32 s2, s4, s6		; GFX6-NEXT: s_and_b32 s2, s4, s6
; GFX6-NEXT: s_lshl_b32 s3, s3, 16		; GFX6-NEXT: s_lshl_b32 s3, s3, 16
; GFX6-NEXT: s_or_b32 s2, s2, s3		; GFX6-NEXT: s_or_b32 s2, s2, s3
; GFX6-NEXT: ; return to shader part epilog		; GFX6-NEXT: ; return to shader part epilog
;		;
▲ Show 20 Lines • Show All 145 Lines • ▼ Show 20 Lines	; GFX10-NEXT: ; return to shader part epilog
%cast = bitcast <6 x i16> %result to <3 x i32>		%cast = bitcast <6 x i16> %result to <3 x i32>
ret <3 x i32> %cast		ret <3 x i32> %cast
}		}

define <4 x float> @v_ssubsat_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {		define <4 x float> @v_ssubsat_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
; GFX6-LABEL: v_ssubsat_v8i16:		; GFX6-LABEL: v_ssubsat_v8i16:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0		; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16
; GFX6-NEXT: s_brev_b32 s4, -2		; GFX6-NEXT: v_bfe_i32 v9, v9, 0, 16
; GFX6-NEXT: v_max_i32_e32 v16, -1, v0		; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v9
; GFX6-NEXT: v_lshlrev_b32_e32 v8, 16, v8		; GFX6-NEXT: v_bfe_i32 v2, v2, 0, 16
; GFX6-NEXT: v_subrev_i32_e32 v16, vcc, s4, v16		; GFX6-NEXT: v_bfe_i32 v9, v10, 0, 16
; GFX6-NEXT: s_brev_b32 s5, 1		; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v9
; GFX6-NEXT: v_min_i32_e32 v18, -1, v0		; GFX6-NEXT: v_bfe_i32 v3, v3, 0, 16
; GFX6-NEXT: v_subrev_i32_e32 v18, vcc, s5, v18		; GFX6-NEXT: v_bfe_i32 v9, v11, 0, 16
; GFX6-NEXT: v_max_i32_e32 v8, v16, v8		; GFX6-NEXT: s_movk_i32 s4, 0x8000
; GFX6-NEXT: v_min_i32_e32 v8, v8, v18		; GFX6-NEXT: v_sub_i32_e32 v3, vcc, v3, v9
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1		; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16
		; GFX6-NEXT: v_bfe_i32 v8, v8, 0, 16
		; GFX6-NEXT: v_bfe_i32 v4, v4, 0, 16
		; GFX6-NEXT: v_bfe_i32 v9, v12, 0, 16
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v8		; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v8
; GFX6-NEXT: v_lshlrev_b32_e32 v8, 16, v9		; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v4, v9
; GFX6-NEXT: v_max_i32_e32 v9, -1, v1		; GFX6-NEXT: s_movk_i32 s5, 0x7fff
; GFX6-NEXT: v_subrev_i32_e32 v9, vcc, s4, v9		; GFX6-NEXT: v_max_i32_e32 v1, s4, v1
; GFX6-NEXT: v_min_i32_e32 v16, -1, v1		; GFX6-NEXT: v_bfe_i32 v5, v5, 0, 16
; GFX6-NEXT: v_subrev_i32_e32 v16, vcc, s5, v16		; GFX6-NEXT: v_bfe_i32 v9, v13, 0, 16
; GFX6-NEXT: v_max_i32_e32 v8, v9, v8		; GFX6-NEXT: v_max_i32_e32 v0, s4, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2		; GFX6-NEXT: v_max_i32_e32 v2, s4, v2
; GFX6-NEXT: v_min_i32_e32 v8, v8, v16		; GFX6-NEXT: v_max_i32_e32 v3, s4, v3
; GFX6-NEXT: v_bfrev_b32_e32 v17, -2		; GFX6-NEXT: v_sub_i32_e32 v5, vcc, v5, v9
; GFX6-NEXT: v_max_i32_e32 v9, -1, v2		; GFX6-NEXT: v_min_i32_e32 v1, s5, v1
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v8
; GFX6-NEXT: v_lshlrev_b32_e32 v8, 16, v10
; GFX6-NEXT: v_min_i32_e32 v10, -1, v2
; GFX6-NEXT: v_sub_i32_e32 v9, vcc, v9, v17
; GFX6-NEXT: v_subrev_i32_e32 v10, vcc, s5, v10
; GFX6-NEXT: v_max_i32_e32 v8, v9, v8
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX6-NEXT: v_min_i32_e32 v8, v8, v10
; GFX6-NEXT: v_max_i32_e32 v9, -1, v3
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v8
; GFX6-NEXT: v_bfrev_b32_e32 v19, 1
; GFX6-NEXT: v_min_i32_e32 v10, -1, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v8, 16, v11
; GFX6-NEXT: v_sub_i32_e32 v9, vcc, v9, v17
; GFX6-NEXT: v_sub_i32_e32 v10, vcc, v10, v19
; GFX6-NEXT: v_max_i32_e32 v8, v9, v8
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX6-NEXT: v_min_i32_e32 v8, v8, v10
; GFX6-NEXT: v_max_i32_e32 v9, -1, v4
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, v3, v8
; GFX6-NEXT: v_min_i32_e32 v10, -1, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v8, 16, v12
; GFX6-NEXT: v_sub_i32_e32 v9, vcc, v9, v17
; GFX6-NEXT: v_sub_i32_e32 v10, vcc, v10, v19
; GFX6-NEXT: v_max_i32_e32 v8, v9, v8
; GFX6-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX6-NEXT: v_min_i32_e32 v8, v8, v10
; GFX6-NEXT: v_max_i32_e32 v9, -1, v5
; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v4, v8
; GFX6-NEXT: v_min_i32_e32 v10, -1, v5
; GFX6-NEXT: v_lshlrev_b32_e32 v8, 16, v13
; GFX6-NEXT: v_sub_i32_e32 v9, vcc, v9, v17
; GFX6-NEXT: v_sub_i32_e32 v10, vcc, v10, v19
; GFX6-NEXT: v_max_i32_e32 v8, v9, v8
; GFX6-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX6-NEXT: v_min_i32_e32 v8, v8, v10
; GFX6-NEXT: v_max_i32_e32 v9, -1, v6
; GFX6-NEXT: v_sub_i32_e32 v5, vcc, v5, v8
; GFX6-NEXT: v_min_i32_e32 v10, -1, v6
; GFX6-NEXT: v_lshlrev_b32_e32 v8, 16, v14
; GFX6-NEXT: v_sub_i32_e32 v9, vcc, v9, v17
; GFX6-NEXT: v_sub_i32_e32 v10, vcc, v10, v19
; GFX6-NEXT: v_max_i32_e32 v8, v9, v8
; GFX6-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX6-NEXT: v_min_i32_e32 v8, v8, v10
; GFX6-NEXT: v_max_i32_e32 v9, -1, v7
; GFX6-NEXT: v_sub_i32_e32 v6, vcc, v6, v8
; GFX6-NEXT: v_min_i32_e32 v10, -1, v7
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 16, v1
; GFX6-NEXT: s_mov_b32 s4, 0xffff		; GFX6-NEXT: s_mov_b32 s4, 0xffff
; GFX6-NEXT: v_lshlrev_b32_e32 v8, 16, v15		; GFX6-NEXT: v_bfe_i32 v6, v6, 0, 16
; GFX6-NEXT: v_sub_i32_e32 v9, vcc, v9, v17		; GFX6-NEXT: v_bfe_i32 v9, v14, 0, 16
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 16, v0		; GFX6-NEXT: v_mov_b32_e32 v8, 0xffff8000
		; GFX6-NEXT: v_sub_i32_e32 v6, vcc, v6, v9
		; GFX6-NEXT: v_min_i32_e32 v0, s5, v0
; GFX6-NEXT: v_and_b32_e32 v1, s4, v1		; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
; GFX6-NEXT: v_sub_i32_e32 v10, vcc, v10, v19		; GFX6-NEXT: v_bfe_i32 v7, v7, 0, 16
; GFX6-NEXT: v_max_i32_e32 v8, v9, v8		; GFX6-NEXT: v_bfe_i32 v9, v15, 0, 16
; GFX6-NEXT: v_min_i32_e32 v8, v8, v10		; GFX6-NEXT: v_sub_i32_e32 v7, vcc, v7, v9
; GFX6-NEXT: v_ashrrev_i32_e32 v2, 16, v2		; GFX6-NEXT: v_mov_b32_e32 v16, 0x7fff
; GFX6-NEXT: v_ashrrev_i32_e32 v3, 16, v3		; GFX6-NEXT: v_max_i32_e32 v5, v5, v8
		; GFX6-NEXT: v_min_i32_e32 v2, s5, v2
		; GFX6-NEXT: v_min_i32_e32 v3, s5, v3
; GFX6-NEXT: v_and_b32_e32 v0, s4, v0		; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1		; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_sub_i32_e32 v7, vcc, v7, v8		; GFX6-NEXT: v_max_i32_e32 v4, v4, v8
		; GFX6-NEXT: v_max_i32_e32 v7, v7, v8
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1		; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: v_and_b32_e32 v1, s4, v2		; GFX6-NEXT: v_and_b32_e32 v1, s4, v2
; GFX6-NEXT: v_and_b32_e32 v2, s4, v3		; GFX6-NEXT: v_and_b32_e32 v2, s4, v3
; GFX6-NEXT: v_ashrrev_i32_e32 v5, 16, v5		; GFX6-NEXT: v_min_i32_e32 v5, v5, v16
		; GFX6-NEXT: v_max_i32_e32 v6, v6, v8
; GFX6-NEXT: v_and_b32_e32 v3, s4, v5		; GFX6-NEXT: v_and_b32_e32 v3, s4, v5
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2		; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX6-NEXT: v_ashrrev_i32_e32 v4, 16, v4		; GFX6-NEXT: v_min_i32_e32 v4, s5, v4
; GFX6-NEXT: v_ashrrev_i32_e32 v7, 16, v7		; GFX6-NEXT: v_min_i32_e32 v7, v7, v16
; GFX6-NEXT: v_or_b32_e32 v1, v1, v2		; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
; GFX6-NEXT: v_and_b32_e32 v2, s4, v4		; GFX6-NEXT: v_and_b32_e32 v2, s4, v4
; GFX6-NEXT: v_and_b32_e32 v4, s4, v7		; GFX6-NEXT: v_and_b32_e32 v4, s4, v7
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3		; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX6-NEXT: v_ashrrev_i32_e32 v6, 16, v6		; GFX6-NEXT: v_min_i32_e32 v6, v6, v16
; GFX6-NEXT: v_or_b32_e32 v2, v2, v3		; GFX6-NEXT: v_or_b32_e32 v2, v2, v3
; GFX6-NEXT: v_and_b32_e32 v3, s4, v6		; GFX6-NEXT: v_and_b32_e32 v3, s4, v6
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v4		; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX6-NEXT: v_or_b32_e32 v3, v3, v4		; GFX6-NEXT: v_or_b32_e32 v3, v3, v4
; GFX6-NEXT: s_setpc_b64 s[30:31]		; GFX6-NEXT: s_setpc_b64 s[30:31]
;		;
; GFX8-LABEL: v_ssubsat_v8i16:		; GFX8-LABEL: v_ssubsat_v8i16:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
▲ Show 20 Lines • Show All 90 Lines • ▼ Show 20 Lines	; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)		%result = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
%cast = bitcast <8 x i16> %result to <4 x float>		%cast = bitcast <8 x i16> %result to <4 x float>
ret <4 x float> %cast		ret <4 x float> %cast
}		}

define amdgpu_ps <4 x i32> @s_ssubsat_v8i16(<8 x i16> inreg %lhs, <8 x i16> inreg %rhs) {		define amdgpu_ps <4 x i32> @s_ssubsat_v8i16(<8 x i16> inreg %lhs, <8 x i16> inreg %rhs) {
; GFX6-LABEL: s_ssubsat_v8i16:		; GFX6-LABEL: s_ssubsat_v8i16:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 16		; GFX6-NEXT: s_sext_i32_i16 s0, s0
; GFX6-NEXT: s_lshl_b32 s8, s8, 16		; GFX6-NEXT: s_sext_i32_i16 s8, s8
; GFX6-NEXT: s_cmp_gt_i32 s0, -1
; GFX6-NEXT: s_brev_b32 s16, -2
; GFX6-NEXT: s_cselect_b32 s18, s0, -1
; GFX6-NEXT: s_sub_i32 s18, s18, s16
; GFX6-NEXT: s_cmp_lt_i32 s0, -1
; GFX6-NEXT: s_brev_b32 s17, 1
; GFX6-NEXT: s_cselect_b32 s19, s0, -1
; GFX6-NEXT: s_sub_i32 s19, s19, s17
; GFX6-NEXT: s_cmp_gt_i32 s18, s8
; GFX6-NEXT: s_cselect_b32 s8, s18, s8
; GFX6-NEXT: s_cmp_lt_i32 s8, s19
; GFX6-NEXT: s_cselect_b32 s8, s8, s19
; GFX6-NEXT: s_sub_i32 s0, s0, s8		; GFX6-NEXT: s_sub_i32 s0, s0, s8
; GFX6-NEXT: s_ashr_i32 s0, s0, 16		; GFX6-NEXT: s_movk_i32 s8, 0x8000
; GFX6-NEXT: s_lshl_b32 s1, s1, 16		; GFX6-NEXT: s_cmp_gt_i32 s0, s8
; GFX6-NEXT: s_lshl_b32 s8, s9, 16		; GFX6-NEXT: s_cselect_b32 s0, s0, s8
; GFX6-NEXT: s_cmp_gt_i32 s1, -1		; GFX6-NEXT: s_movk_i32 s16, 0x7fff
; GFX6-NEXT: s_cselect_b32 s9, s1, -1		; GFX6-NEXT: s_cmp_lt_i32 s0, s16
; GFX6-NEXT: s_sub_i32 s9, s9, s16		; GFX6-NEXT: s_sext_i32_i16 s1, s1
; GFX6-NEXT: s_cmp_lt_i32 s1, -1		; GFX6-NEXT: s_sext_i32_i16 s9, s9
; GFX6-NEXT: s_cselect_b32 s18, s1, -1		; GFX6-NEXT: s_cselect_b32 s0, s0, s16
; GFX6-NEXT: s_sub_i32 s18, s18, s17		; GFX6-NEXT: s_sub_i32 s1, s1, s9
; GFX6-NEXT: s_cmp_gt_i32 s9, s8		; GFX6-NEXT: s_cmp_gt_i32 s1, s8
; GFX6-NEXT: s_cselect_b32 s8, s9, s8		; GFX6-NEXT: s_cselect_b32 s1, s1, s8
; GFX6-NEXT: s_cmp_lt_i32 s8, s18		; GFX6-NEXT: s_cmp_lt_i32 s1, s16
; GFX6-NEXT: s_cselect_b32 s8, s8, s18		; GFX6-NEXT: s_sext_i32_i16 s2, s2
; GFX6-NEXT: s_sub_i32 s1, s1, s8		; GFX6-NEXT: s_sext_i32_i16 s9, s10
; GFX6-NEXT: s_ashr_i32 s1, s1, 16		; GFX6-NEXT: s_cselect_b32 s1, s1, s16
; GFX6-NEXT: s_lshl_b32 s2, s2, 16		; GFX6-NEXT: s_sub_i32 s2, s2, s9
; GFX6-NEXT: s_lshl_b32 s8, s10, 16		; GFX6-NEXT: s_cmp_gt_i32 s2, s8
; GFX6-NEXT: s_cmp_gt_i32 s2, -1		; GFX6-NEXT: s_cselect_b32 s2, s2, s8
; GFX6-NEXT: s_cselect_b32 s9, s2, -1		; GFX6-NEXT: s_cmp_lt_i32 s2, s16
; GFX6-NEXT: s_sub_i32 s9, s9, s16		; GFX6-NEXT: s_sext_i32_i16 s3, s3
; GFX6-NEXT: s_cmp_lt_i32 s2, -1		; GFX6-NEXT: s_sext_i32_i16 s9, s11
; GFX6-NEXT: s_cselect_b32 s10, s2, -1		; GFX6-NEXT: s_cselect_b32 s2, s2, s16
; GFX6-NEXT: s_sub_i32 s10, s10, s17		; GFX6-NEXT: s_sub_i32 s3, s3, s9
; GFX6-NEXT: s_cmp_gt_i32 s9, s8		; GFX6-NEXT: s_cmp_gt_i32 s3, s8
; GFX6-NEXT: s_cselect_b32 s8, s9, s8		; GFX6-NEXT: s_cselect_b32 s3, s3, s8
; GFX6-NEXT: s_cmp_lt_i32 s8, s10		; GFX6-NEXT: s_cmp_lt_i32 s3, s16
; GFX6-NEXT: s_cselect_b32 s8, s8, s10		; GFX6-NEXT: s_sext_i32_i16 s4, s4
; GFX6-NEXT: s_sub_i32 s2, s2, s8		; GFX6-NEXT: s_sext_i32_i16 s9, s12
; GFX6-NEXT: s_ashr_i32 s2, s2, 16		; GFX6-NEXT: s_cselect_b32 s3, s3, s16
; GFX6-NEXT: s_lshl_b32 s3, s3, 16		; GFX6-NEXT: s_sub_i32 s4, s4, s9
; GFX6-NEXT: s_lshl_b32 s8, s11, 16		; GFX6-NEXT: s_cmp_gt_i32 s4, s8
; GFX6-NEXT: s_cmp_gt_i32 s3, -1		; GFX6-NEXT: s_cselect_b32 s4, s4, s8
; GFX6-NEXT: s_cselect_b32 s9, s3, -1		; GFX6-NEXT: s_cmp_lt_i32 s4, s16
; GFX6-NEXT: s_sub_i32 s9, s9, s16		; GFX6-NEXT: s_sext_i32_i16 s5, s5
; GFX6-NEXT: s_cmp_lt_i32 s3, -1		; GFX6-NEXT: s_sext_i32_i16 s9, s13
; GFX6-NEXT: s_cselect_b32 s10, s3, -1		; GFX6-NEXT: s_cselect_b32 s4, s4, s16
; GFX6-NEXT: s_sub_i32 s10, s10, s17		; GFX6-NEXT: s_sub_i32 s5, s5, s9
; GFX6-NEXT: s_cmp_gt_i32 s9, s8		; GFX6-NEXT: s_cmp_gt_i32 s5, s8
; GFX6-NEXT: s_cselect_b32 s8, s9, s8		; GFX6-NEXT: s_cselect_b32 s5, s5, s8
; GFX6-NEXT: s_cmp_lt_i32 s8, s10		; GFX6-NEXT: s_cmp_lt_i32 s5, s16
; GFX6-NEXT: s_cselect_b32 s8, s8, s10		; GFX6-NEXT: s_sext_i32_i16 s6, s6
; GFX6-NEXT: s_sub_i32 s3, s3, s8		; GFX6-NEXT: s_sext_i32_i16 s9, s14
; GFX6-NEXT: s_ashr_i32 s3, s3, 16		; GFX6-NEXT: s_cselect_b32 s5, s5, s16
; GFX6-NEXT: s_lshl_b32 s4, s4, 16		; GFX6-NEXT: s_sub_i32 s6, s6, s9
; GFX6-NEXT: s_lshl_b32 s8, s12, 16		; GFX6-NEXT: s_cmp_gt_i32 s6, s8
; GFX6-NEXT: s_cmp_gt_i32 s4, -1		; GFX6-NEXT: s_cselect_b32 s6, s6, s8
; GFX6-NEXT: s_cselect_b32 s9, s4, -1		; GFX6-NEXT: s_cmp_lt_i32 s6, s16
; GFX6-NEXT: s_sub_i32 s9, s9, s16		; GFX6-NEXT: s_sext_i32_i16 s7, s7
; GFX6-NEXT: s_cmp_lt_i32 s4, -1		; GFX6-NEXT: s_sext_i32_i16 s9, s15
; GFX6-NEXT: s_cselect_b32 s10, s4, -1		; GFX6-NEXT: s_cselect_b32 s6, s6, s16
; GFX6-NEXT: s_sub_i32 s10, s10, s17		; GFX6-NEXT: s_sub_i32 s7, s7, s9
; GFX6-NEXT: s_cmp_gt_i32 s9, s8		; GFX6-NEXT: s_cmp_gt_i32 s7, s8
; GFX6-NEXT: s_cselect_b32 s8, s9, s8		; GFX6-NEXT: s_cselect_b32 s7, s7, s8
; GFX6-NEXT: s_cmp_lt_i32 s8, s10		; GFX6-NEXT: s_cmp_lt_i32 s7, s16
; GFX6-NEXT: s_cselect_b32 s8, s8, s10
; GFX6-NEXT: s_sub_i32 s4, s4, s8
; GFX6-NEXT: s_ashr_i32 s4, s4, 16
; GFX6-NEXT: s_lshl_b32 s5, s5, 16
; GFX6-NEXT: s_lshl_b32 s8, s13, 16
; GFX6-NEXT: s_cmp_gt_i32 s5, -1
; GFX6-NEXT: s_cselect_b32 s9, s5, -1
; GFX6-NEXT: s_sub_i32 s9, s9, s16
; GFX6-NEXT: s_cmp_lt_i32 s5, -1
; GFX6-NEXT: s_cselect_b32 s10, s5, -1
; GFX6-NEXT: s_sub_i32 s10, s10, s17
; GFX6-NEXT: s_cmp_gt_i32 s9, s8
; GFX6-NEXT: s_cselect_b32 s8, s9, s8
; GFX6-NEXT: s_cmp_lt_i32 s8, s10
; GFX6-NEXT: s_cselect_b32 s8, s8, s10
; GFX6-NEXT: s_sub_i32 s5, s5, s8
; GFX6-NEXT: s_ashr_i32 s5, s5, 16
; GFX6-NEXT: s_lshl_b32 s6, s6, 16
; GFX6-NEXT: s_lshl_b32 s8, s14, 16
; GFX6-NEXT: s_cmp_gt_i32 s6, -1
; GFX6-NEXT: s_cselect_b32 s9, s6, -1
; GFX6-NEXT: s_sub_i32 s9, s9, s16
; GFX6-NEXT: s_cmp_lt_i32 s6, -1
; GFX6-NEXT: s_cselect_b32 s10, s6, -1
; GFX6-NEXT: s_sub_i32 s10, s10, s17
; GFX6-NEXT: s_cmp_gt_i32 s9, s8
; GFX6-NEXT: s_cselect_b32 s8, s9, s8
; GFX6-NEXT: s_cmp_lt_i32 s8, s10
; GFX6-NEXT: s_cselect_b32 s8, s8, s10
; GFX6-NEXT: s_sub_i32 s6, s6, s8
; GFX6-NEXT: s_ashr_i32 s6, s6, 16
; GFX6-NEXT: s_lshl_b32 s7, s7, 16
; GFX6-NEXT: s_lshl_b32 s8, s15, 16
; GFX6-NEXT: s_cmp_gt_i32 s7, -1
; GFX6-NEXT: s_cselect_b32 s9, s7, -1
; GFX6-NEXT: s_sub_i32 s9, s9, s16
; GFX6-NEXT: s_cmp_lt_i32 s7, -1
; GFX6-NEXT: s_cselect_b32 s10, s7, -1
; GFX6-NEXT: s_sub_i32 s10, s10, s17
; GFX6-NEXT: s_cmp_gt_i32 s9, s8
; GFX6-NEXT: s_cselect_b32 s8, s9, s8
; GFX6-NEXT: s_cmp_lt_i32 s8, s10
; GFX6-NEXT: s_cselect_b32 s8, s8, s10
; GFX6-NEXT: s_sub_i32 s7, s7, s8
; GFX6-NEXT: s_mov_b32 s8, 0xffff		; GFX6-NEXT: s_mov_b32 s8, 0xffff
		; GFX6-NEXT: s_cselect_b32 s7, s7, s16
; GFX6-NEXT: s_and_b32 s1, s1, s8		; GFX6-NEXT: s_and_b32 s1, s1, s8
; GFX6-NEXT: s_and_b32 s0, s0, s8		; GFX6-NEXT: s_and_b32 s0, s0, s8
; GFX6-NEXT: s_lshl_b32 s1, s1, 16		; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_or_b32 s0, s0, s1		; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: s_and_b32 s1, s2, s8		; GFX6-NEXT: s_and_b32 s1, s2, s8
; GFX6-NEXT: s_and_b32 s2, s3, s8		; GFX6-NEXT: s_and_b32 s2, s3, s8
; GFX6-NEXT: s_and_b32 s3, s5, s8		; GFX6-NEXT: s_and_b32 s3, s5, s8
; GFX6-NEXT: s_lshl_b32 s2, s2, 16		; GFX6-NEXT: s_lshl_b32 s2, s2, 16
; GFX6-NEXT: s_ashr_i32 s7, s7, 16
; GFX6-NEXT: s_or_b32 s1, s1, s2		; GFX6-NEXT: s_or_b32 s1, s1, s2
; GFX6-NEXT: s_and_b32 s2, s4, s8		; GFX6-NEXT: s_and_b32 s2, s4, s8
; GFX6-NEXT: s_and_b32 s4, s7, s8		; GFX6-NEXT: s_and_b32 s4, s7, s8
; GFX6-NEXT: s_lshl_b32 s3, s3, 16		; GFX6-NEXT: s_lshl_b32 s3, s3, 16
; GFX6-NEXT: s_or_b32 s2, s2, s3		; GFX6-NEXT: s_or_b32 s2, s2, s3
; GFX6-NEXT: s_and_b32 s3, s6, s8		; GFX6-NEXT: s_and_b32 s3, s6, s8
; GFX6-NEXT: s_lshl_b32 s4, s4, 16		; GFX6-NEXT: s_lshl_b32 s4, s4, 16
; GFX6-NEXT: s_or_b32 s3, s3, s4		; GFX6-NEXT: s_or_b32 s3, s3, s4
▲ Show 20 Lines • Show All 2,906 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py		; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=tahiti -o - %s \| FileCheck -check-prefix=GFX6 %s		; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=tahiti -o - %s \| FileCheck -check-prefix=GFX6 %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=fiji -o - %s \| FileCheck -check-prefix=GFX8 %s		; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=fiji -o - %s \| FileCheck -check-prefix=GFX8 %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -o - %s \| FileCheck -check-prefix=GFX9 %s		; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -o - %s \| FileCheck -check-prefix=GFX9 %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -o - %s \| FileCheck -check-prefix=GFX10 %s		; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -o - %s \| FileCheck -check-prefix=GFX10 %s

define i7 @v_uaddsat_i7(i7 %lhs, i7 %rhs) {		define i7 @v_uaddsat_i7(i7 %lhs, i7 %rhs) {
; GFX6-LABEL: v_uaddsat_i7:		; GFX6-LABEL: v_uaddsat_i7:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 25, v0		; GFX6-NEXT: s_movk_i32 s4, 0x7f
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 25, v1		; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
; GFX6-NEXT: v_xor_b32_e32 v2, -1, v0		; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
; GFX6-NEXT: v_min_u32_e32 v1, v2, v1
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1		; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v0, 25, v0		; GFX6-NEXT: v_min_u32_e32 v0, s4, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]		; GFX6-NEXT: s_setpc_b64 s[30:31]
;		;
; GFX8-LABEL: v_uaddsat_i7:		; GFX8-LABEL: v_uaddsat_i7:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshlrev_b16_e32 v0, 9, v0		; GFX8-NEXT: v_lshlrev_b16_e32 v0, 9, v0
; GFX8-NEXT: v_lshlrev_b16_e32 v1, 9, v1		; GFX8-NEXT: v_lshlrev_b16_e32 v1, 9, v1
; GFX8-NEXT: v_add_u16_e64 v0, v0, v1 clamp		; GFX8-NEXT: v_add_u16_e64 v0, v0, v1 clamp
Show All 21 Lines
; GFX10-NEXT: s_setpc_b64 s[30:31]		; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call i7 @llvm.uadd.sat.i7(i7 %lhs, i7 %rhs)		%result = call i7 @llvm.uadd.sat.i7(i7 %lhs, i7 %rhs)
ret i7 %result		ret i7 %result
}		}

define amdgpu_ps i7 @s_uaddsat_i7(i7 inreg %lhs, i7 inreg %rhs) {		define amdgpu_ps i7 @s_uaddsat_i7(i7 inreg %lhs, i7 inreg %rhs) {
; GFX6-LABEL: s_uaddsat_i7:		; GFX6-LABEL: s_uaddsat_i7:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 25		; GFX6-NEXT: s_movk_i32 s2, 0x7f
; GFX6-NEXT: s_lshl_b32 s1, s1, 25		; GFX6-NEXT: s_and_b32 s0, s0, s2
; GFX6-NEXT: s_not_b32 s2, s0		; GFX6-NEXT: s_and_b32 s1, s1, s2
; GFX6-NEXT: s_cmp_lt_u32 s2, s1
; GFX6-NEXT: s_cselect_b32 s1, s2, s1
; GFX6-NEXT: s_add_i32 s0, s0, s1		; GFX6-NEXT: s_add_i32 s0, s0, s1
; GFX6-NEXT: s_lshr_b32 s0, s0, 25		; GFX6-NEXT: s_cmp_lt_u32 s0, s2
		; GFX6-NEXT: s_cselect_b32 s0, s0, s2
; GFX6-NEXT: ; return to shader part epilog		; GFX6-NEXT: ; return to shader part epilog
;		;
; GFX8-LABEL: s_uaddsat_i7:		; GFX8-LABEL: s_uaddsat_i7:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_bfe_u32 s2, 9, 0x100000		; GFX8-NEXT: s_bfe_u32 s2, 9, 0x100000
; GFX8-NEXT: s_lshl_b32 s1, s1, s2		; GFX8-NEXT: s_lshl_b32 s1, s1, s2
; GFX8-NEXT: s_lshl_b32 s0, s0, s2		; GFX8-NEXT: s_lshl_b32 s0, s0, s2
; GFX8-NEXT: v_mov_b32_e32 v0, s1		; GFX8-NEXT: v_mov_b32_e32 v0, s1
Show All 26 Lines	; GFX10-NEXT: ; return to shader part epilog
%result = call i7 @llvm.uadd.sat.i7(i7 %lhs, i7 %rhs)		%result = call i7 @llvm.uadd.sat.i7(i7 %lhs, i7 %rhs)
ret i7 %result		ret i7 %result
}		}

define i8 @v_uaddsat_i8(i8 %lhs, i8 %rhs) {		define i8 @v_uaddsat_i8(i8 %lhs, i8 %rhs) {
; GFX6-LABEL: v_uaddsat_i8:		; GFX6-LABEL: v_uaddsat_i8:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 24, v0		; GFX6-NEXT: s_movk_i32 s4, 0xff
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v1		; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
; GFX6-NEXT: v_xor_b32_e32 v2, -1, v0		; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
; GFX6-NEXT: v_min_u32_e32 v1, v2, v1
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1		; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v0, 24, v0		; GFX6-NEXT: v_min_u32_e32 v0, s4, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]		; GFX6-NEXT: s_setpc_b64 s[30:31]
;		;
; GFX8-LABEL: v_uaddsat_i8:		; GFX8-LABEL: v_uaddsat_i8:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshlrev_b16_e32 v0, 8, v0		; GFX8-NEXT: v_lshlrev_b16_e32 v0, 8, v0
; GFX8-NEXT: v_lshlrev_b16_e32 v1, 8, v1		; GFX8-NEXT: v_lshlrev_b16_e32 v1, 8, v1
; GFX8-NEXT: v_add_u16_e64 v0, v0, v1 clamp		; GFX8-NEXT: v_add_u16_e64 v0, v0, v1 clamp
Show All 21 Lines
; GFX10-NEXT: s_setpc_b64 s[30:31]		; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call i8 @llvm.uadd.sat.i8(i8 %lhs, i8 %rhs)		%result = call i8 @llvm.uadd.sat.i8(i8 %lhs, i8 %rhs)
ret i8 %result		ret i8 %result
}		}

define amdgpu_ps i8 @s_uaddsat_i8(i8 inreg %lhs, i8 inreg %rhs) {		define amdgpu_ps i8 @s_uaddsat_i8(i8 inreg %lhs, i8 inreg %rhs) {
; GFX6-LABEL: s_uaddsat_i8:		; GFX6-LABEL: s_uaddsat_i8:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 24		; GFX6-NEXT: s_movk_i32 s2, 0xff
; GFX6-NEXT: s_lshl_b32 s1, s1, 24		; GFX6-NEXT: s_and_b32 s0, s0, s2
; GFX6-NEXT: s_not_b32 s2, s0		; GFX6-NEXT: s_and_b32 s1, s1, s2
; GFX6-NEXT: s_cmp_lt_u32 s2, s1
; GFX6-NEXT: s_cselect_b32 s1, s2, s1
; GFX6-NEXT: s_add_i32 s0, s0, s1		; GFX6-NEXT: s_add_i32 s0, s0, s1
; GFX6-NEXT: s_lshr_b32 s0, s0, 24		; GFX6-NEXT: s_cmp_lt_u32 s0, s2
		; GFX6-NEXT: s_cselect_b32 s0, s0, s2
; GFX6-NEXT: ; return to shader part epilog		; GFX6-NEXT: ; return to shader part epilog
;		;
; GFX8-LABEL: s_uaddsat_i8:		; GFX8-LABEL: s_uaddsat_i8:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_bfe_u32 s2, 8, 0x100000		; GFX8-NEXT: s_bfe_u32 s2, 8, 0x100000
; GFX8-NEXT: s_lshl_b32 s1, s1, s2		; GFX8-NEXT: s_lshl_b32 s1, s1, s2
; GFX8-NEXT: s_lshl_b32 s0, s0, s2		; GFX8-NEXT: s_lshl_b32 s0, s0, s2
; GFX8-NEXT: v_mov_b32_e32 v0, s1		; GFX8-NEXT: v_mov_b32_e32 v0, s1
Show All 26 Lines	; GFX10-NEXT: ; return to shader part epilog
%result = call i8 @llvm.uadd.sat.i8(i8 %lhs, i8 %rhs)		%result = call i8 @llvm.uadd.sat.i8(i8 %lhs, i8 %rhs)
ret i8 %result		ret i8 %result
}		}

define i16 @v_uaddsat_v2i8(i16 %lhs.arg, i16 %rhs.arg) {		define i16 @v_uaddsat_v2i8(i16 %lhs.arg, i16 %rhs.arg) {
; GFX6-LABEL: v_uaddsat_v2i8:		; GFX6-LABEL: v_uaddsat_v2i8:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
		; GFX6-NEXT: s_movk_i32 s4, 0xff
; GFX6-NEXT: v_lshrrev_b32_e32 v2, 8, v0		; GFX6-NEXT: v_lshrrev_b32_e32 v2, 8, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 24, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 8, v1		; GFX6-NEXT: v_lshrrev_b32_e32 v3, 8, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v1		; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
; GFX6-NEXT: v_xor_b32_e32 v4, -1, v0		; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
; GFX6-NEXT: v_min_u32_e32 v1, v4, v1
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1		; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v2		; GFX6-NEXT: v_and_b32_e32 v1, s4, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 24, v3		; GFX6-NEXT: v_and_b32_e32 v2, s4, v3
; GFX6-NEXT: v_xor_b32_e32 v3, -1, v1
; GFX6-NEXT: v_min_u32_e32 v2, v3, v2
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v2		; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v2
; GFX6-NEXT: v_lshrrev_b32_e32 v1, 24, v1		; GFX6-NEXT: v_min_u32_e32 v1, s4, v1
; GFX6-NEXT: v_mov_b32_e32 v2, 0xff		; GFX6-NEXT: v_min_u32_e32 v0, s4, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v0, 24, v0		; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
; GFX6-NEXT: v_and_b32_e32 v1, v1, v2		; GFX6-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX6-NEXT: v_and_b32_e32 v0, v0, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 8, v1		; GFX6-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1		; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]		; GFX6-NEXT: s_setpc_b64 s[30:31]
;		;
; GFX8-LABEL: v_uaddsat_v2i8:		; GFX8-LABEL: v_uaddsat_v2i8:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v2, 8		; GFX8-NEXT: v_mov_b32_e32 v2, 8
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines	; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8> %lhs, <2 x i8> %rhs)		%result = call <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8> %lhs, <2 x i8> %rhs)
%cast.result = bitcast <2 x i8> %result to i16		%cast.result = bitcast <2 x i8> %result to i16
ret i16 %cast.result		ret i16 %cast.result
}		}

define amdgpu_ps i16 @s_uaddsat_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg) {		define amdgpu_ps i16 @s_uaddsat_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg) {
; GFX6-LABEL: s_uaddsat_v2i8:		; GFX6-LABEL: s_uaddsat_v2i8:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
		; GFX6-NEXT: s_movk_i32 s4, 0xff
; GFX6-NEXT: s_lshr_b32 s2, s0, 8		; GFX6-NEXT: s_lshr_b32 s2, s0, 8
; GFX6-NEXT: s_lshl_b32 s0, s0, 24
; GFX6-NEXT: s_lshr_b32 s3, s1, 8		; GFX6-NEXT: s_lshr_b32 s3, s1, 8
; GFX6-NEXT: s_lshl_b32 s1, s1, 24		; GFX6-NEXT: s_and_b32 s0, s0, s4
; GFX6-NEXT: s_not_b32 s4, s0		; GFX6-NEXT: s_and_b32 s1, s1, s4
; GFX6-NEXT: s_cmp_lt_u32 s4, s1
; GFX6-NEXT: s_cselect_b32 s1, s4, s1
; GFX6-NEXT: s_add_i32 s0, s0, s1		; GFX6-NEXT: s_add_i32 s0, s0, s1
; GFX6-NEXT: s_lshl_b32 s1, s2, 24		; GFX6-NEXT: s_cmp_lt_u32 s0, s4
; GFX6-NEXT: s_lshl_b32 s2, s3, 24		; GFX6-NEXT: s_cselect_b32 s0, s0, s4
; GFX6-NEXT: s_lshr_b32 s0, s0, 24		; GFX6-NEXT: s_and_b32 s1, s2, s4
; GFX6-NEXT: s_not_b32 s3, s1		; GFX6-NEXT: s_and_b32 s2, s3, s4
; GFX6-NEXT: s_cmp_lt_u32 s3, s2
; GFX6-NEXT: s_cselect_b32 s2, s3, s2
; GFX6-NEXT: s_add_i32 s1, s1, s2		; GFX6-NEXT: s_add_i32 s1, s1, s2
; GFX6-NEXT: s_movk_i32 s2, 0xff		; GFX6-NEXT: s_cmp_lt_u32 s1, s4
; GFX6-NEXT: s_lshr_b32 s1, s1, 24		; GFX6-NEXT: s_cselect_b32 s1, s1, s4
; GFX6-NEXT: s_and_b32 s1, s1, s2		; GFX6-NEXT: s_and_b32 s1, s1, s4
; GFX6-NEXT: s_and_b32 s0, s0, s2		; GFX6-NEXT: s_and_b32 s0, s0, s4
; GFX6-NEXT: s_lshl_b32 s1, s1, 8		; GFX6-NEXT: s_lshl_b32 s1, s1, 8
; GFX6-NEXT: s_or_b32 s0, s0, s1		; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: ; return to shader part epilog		; GFX6-NEXT: ; return to shader part epilog
;		;
; GFX8-LABEL: s_uaddsat_v2i8:		; GFX8-LABEL: s_uaddsat_v2i8:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_bfe_u32 s4, 8, 0x100000		; GFX8-NEXT: s_bfe_u32 s4, 8, 0x100000
; GFX8-NEXT: s_lshr_b32 s3, s1, 8		; GFX8-NEXT: s_lshr_b32 s3, s1, 8
▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 Lines	; GFX10-NEXT: ; return to shader part epilog
%cast.result = bitcast <2 x i8> %result to i16		%cast.result = bitcast <2 x i8> %result to i16
ret i16 %cast.result		ret i16 %cast.result
}		}

define i32 @v_uaddsat_v4i8(i32 %lhs.arg, i32 %rhs.arg) {		define i32 @v_uaddsat_v4i8(i32 %lhs.arg, i32 %rhs.arg) {
; GFX6-LABEL: v_uaddsat_v4i8:		; GFX6-LABEL: v_uaddsat_v4i8:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
		; GFX6-NEXT: s_movk_i32 s4, 0xff
; GFX6-NEXT: v_lshrrev_b32_e32 v2, 8, v0		; GFX6-NEXT: v_lshrrev_b32_e32 v2, 8, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v0		; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v4, 24, v0		; GFX6-NEXT: v_lshrrev_b32_e32 v4, 24, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 24, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v5, 8, v1		; GFX6-NEXT: v_lshrrev_b32_e32 v5, 8, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v6, 16, v1		; GFX6-NEXT: v_lshrrev_b32_e32 v6, 16, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v7, 24, v1		; GFX6-NEXT: v_lshrrev_b32_e32 v7, 24, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v1		; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
; GFX6-NEXT: v_xor_b32_e32 v8, -1, v0		; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
; GFX6-NEXT: v_min_u32_e32 v1, v8, v1
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1		; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v2		; GFX6-NEXT: v_and_b32_e32 v1, s4, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 24, v5		; GFX6-NEXT: v_and_b32_e32 v2, s4, v5
; GFX6-NEXT: v_xor_b32_e32 v5, -1, v1
; GFX6-NEXT: v_min_u32_e32 v2, v5, v2
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v2		; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 24, v3		; GFX6-NEXT: v_min_u32_e32 v1, s4, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 24, v6		; GFX6-NEXT: v_and_b32_e32 v2, s4, v3
; GFX6-NEXT: v_xor_b32_e32 v5, -1, v2		; GFX6-NEXT: v_and_b32_e32 v3, s4, v6
; GFX6-NEXT: v_min_u32_e32 v3, v5, v3
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3		; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 24, v4		; GFX6-NEXT: v_min_u32_e32 v0, s4, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v1, 24, v1
; GFX6-NEXT: s_movk_i32 s4, 0xff
; GFX6-NEXT: v_lshrrev_b32_e32 v0, 24, v0
; GFX6-NEXT: v_and_b32_e32 v1, s4, v1		; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 24, v7		; GFX6-NEXT: v_and_b32_e32 v3, s4, v4
; GFX6-NEXT: v_xor_b32_e32 v5, -1, v3		; GFX6-NEXT: v_and_b32_e32 v4, s4, v7
; GFX6-NEXT: v_min_u32_e32 v4, v5, v4		; GFX6-NEXT: v_min_u32_e32 v2, s4, v2
; GFX6-NEXT: v_lshrrev_b32_e32 v2, 24, v2
; GFX6-NEXT: v_and_b32_e32 v0, s4, v0		; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 8, v1		; GFX6-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v4		; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v4
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1		; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: v_and_b32_e32 v1, s4, v2		; GFX6-NEXT: v_and_b32_e32 v1, s4, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1		; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 24, v3		; GFX6-NEXT: v_min_u32_e32 v3, s4, v3
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1		; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: v_and_b32_e32 v1, s4, v3		; GFX6-NEXT: v_and_b32_e32 v1, 0xff, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v1		; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1		; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]		; GFX6-NEXT: s_setpc_b64 s[30:31]
;		;
; GFX8-LABEL: v_uaddsat_v4i8:		; GFX8-LABEL: v_uaddsat_v4i8:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v2, 8		; GFX8-NEXT: v_mov_b32_e32 v2, 8
▲ Show 20 Lines • Show All 100 Lines • ▼ Show 20 Lines	; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <4 x i8> @llvm.uadd.sat.v4i8(<4 x i8> %lhs, <4 x i8> %rhs)		%result = call <4 x i8> @llvm.uadd.sat.v4i8(<4 x i8> %lhs, <4 x i8> %rhs)
%cast.result = bitcast <4 x i8> %result to i32		%cast.result = bitcast <4 x i8> %result to i32
ret i32 %cast.result		ret i32 %cast.result
}		}

define amdgpu_ps i32 @s_uaddsat_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg) {		define amdgpu_ps i32 @s_uaddsat_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg) {
; GFX6-LABEL: s_uaddsat_v4i8:		; GFX6-LABEL: s_uaddsat_v4i8:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
		; GFX6-NEXT: s_movk_i32 s8, 0xff
; GFX6-NEXT: s_lshr_b32 s2, s0, 8		; GFX6-NEXT: s_lshr_b32 s2, s0, 8
; GFX6-NEXT: s_lshr_b32 s3, s0, 16		; GFX6-NEXT: s_lshr_b32 s3, s0, 16
; GFX6-NEXT: s_lshr_b32 s4, s0, 24		; GFX6-NEXT: s_lshr_b32 s4, s0, 24
; GFX6-NEXT: s_lshl_b32 s0, s0, 24
; GFX6-NEXT: s_lshr_b32 s5, s1, 8		; GFX6-NEXT: s_lshr_b32 s5, s1, 8
; GFX6-NEXT: s_lshr_b32 s6, s1, 16		; GFX6-NEXT: s_lshr_b32 s6, s1, 16
; GFX6-NEXT: s_lshr_b32 s7, s1, 24		; GFX6-NEXT: s_lshr_b32 s7, s1, 24
; GFX6-NEXT: s_lshl_b32 s1, s1, 24		; GFX6-NEXT: s_and_b32 s0, s0, s8
; GFX6-NEXT: s_not_b32 s8, s0		; GFX6-NEXT: s_and_b32 s1, s1, s8
; GFX6-NEXT: s_cmp_lt_u32 s8, s1
; GFX6-NEXT: s_cselect_b32 s1, s8, s1
; GFX6-NEXT: s_add_i32 s0, s0, s1		; GFX6-NEXT: s_add_i32 s0, s0, s1
; GFX6-NEXT: s_lshl_b32 s1, s2, 24		; GFX6-NEXT: s_cmp_lt_u32 s0, s8
; GFX6-NEXT: s_lshl_b32 s2, s5, 24		; GFX6-NEXT: s_cselect_b32 s0, s0, s8
; GFX6-NEXT: s_lshr_b32 s0, s0, 24		; GFX6-NEXT: s_and_b32 s1, s2, s8
; GFX6-NEXT: s_not_b32 s5, s1		; GFX6-NEXT: s_and_b32 s2, s5, s8
; GFX6-NEXT: s_cmp_lt_u32 s5, s2
; GFX6-NEXT: s_cselect_b32 s2, s5, s2
; GFX6-NEXT: s_add_i32 s1, s1, s2		; GFX6-NEXT: s_add_i32 s1, s1, s2
; GFX6-NEXT: s_lshl_b32 s2, s3, 24		; GFX6-NEXT: s_cmp_lt_u32 s1, s8
; GFX6-NEXT: s_lshr_b32 s1, s1, 24		; GFX6-NEXT: s_cselect_b32 s1, s1, s8
; GFX6-NEXT: s_lshl_b32 s3, s6, 24		; GFX6-NEXT: s_and_b32 s2, s3, s8
; GFX6-NEXT: s_not_b32 s5, s2		; GFX6-NEXT: s_and_b32 s3, s6, s8
; GFX6-NEXT: s_cmp_lt_u32 s5, s3
; GFX6-NEXT: s_cselect_b32 s3, s5, s3
; GFX6-NEXT: s_add_i32 s2, s2, s3		; GFX6-NEXT: s_add_i32 s2, s2, s3
; GFX6-NEXT: s_lshl_b32 s3, s4, 24		; GFX6-NEXT: s_cmp_lt_u32 s2, s8
; GFX6-NEXT: s_lshr_b32 s2, s2, 24		; GFX6-NEXT: s_cselect_b32 s2, s2, s8
; GFX6-NEXT: s_lshl_b32 s4, s7, 24		; GFX6-NEXT: s_and_b32 s3, s4, s8
; GFX6-NEXT: s_not_b32 s5, s3		; GFX6-NEXT: s_and_b32 s4, s7, s8
; GFX6-NEXT: s_cmp_lt_u32 s5, s4
; GFX6-NEXT: s_cselect_b32 s4, s5, s4
; GFX6-NEXT: s_add_i32 s3, s3, s4		; GFX6-NEXT: s_add_i32 s3, s3, s4
; GFX6-NEXT: s_movk_i32 s4, 0xff		; GFX6-NEXT: s_cmp_lt_u32 s3, s8
; GFX6-NEXT: s_and_b32 s1, s1, s4		; GFX6-NEXT: s_cselect_b32 s3, s3, s8
; GFX6-NEXT: s_and_b32 s0, s0, s4		; GFX6-NEXT: s_and_b32 s1, s1, s8
		; GFX6-NEXT: s_and_b32 s0, s0, s8
; GFX6-NEXT: s_lshl_b32 s1, s1, 8		; GFX6-NEXT: s_lshl_b32 s1, s1, 8
; GFX6-NEXT: s_or_b32 s0, s0, s1		; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: s_and_b32 s1, s2, s4		; GFX6-NEXT: s_and_b32 s1, s2, s8
; GFX6-NEXT: s_lshl_b32 s1, s1, 16		; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_lshr_b32 s3, s3, 24
; GFX6-NEXT: s_or_b32 s0, s0, s1		; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: s_and_b32 s1, s3, s4		; GFX6-NEXT: s_and_b32 s1, s3, s8
; GFX6-NEXT: s_lshl_b32 s1, s1, 24		; GFX6-NEXT: s_lshl_b32 s1, s1, 24
; GFX6-NEXT: s_or_b32 s0, s0, s1		; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: ; return to shader part epilog		; GFX6-NEXT: ; return to shader part epilog
;		;
; GFX8-LABEL: s_uaddsat_v4i8:		; GFX8-LABEL: s_uaddsat_v4i8:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_bfe_u32 s8, 8, 0x100000		; GFX8-NEXT: s_bfe_u32 s8, 8, 0x100000
; GFX8-NEXT: s_lshr_b32 s5, s1, 8		; GFX8-NEXT: s_lshr_b32 s5, s1, 8
▲ Show 20 Lines • Show All 126 Lines • ▼ Show 20 Lines	; GFX10-NEXT: ; return to shader part epilog
%cast.result = bitcast <4 x i8> %result to i32		%cast.result = bitcast <4 x i8> %result to i32
ret i32 %cast.result		ret i32 %cast.result
}		}

define i24 @v_uaddsat_i24(i24 %lhs, i24 %rhs) {		define i24 @v_uaddsat_i24(i24 %lhs, i24 %rhs) {
; GFX6-LABEL: v_uaddsat_i24:		; GFX6-LABEL: v_uaddsat_i24:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 8, v0		; GFX6-NEXT: s_mov_b32 s4, 0xffffff
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 8, v1		; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
; GFX6-NEXT: v_xor_b32_e32 v2, -1, v0		; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
; GFX6-NEXT: v_min_u32_e32 v1, v2, v1
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1		; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v0, 8, v0		; GFX6-NEXT: v_min_u32_e32 v0, s4, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]		; GFX6-NEXT: s_setpc_b64 s[30:31]
;		;
; GFX8-LABEL: v_uaddsat_i24:		; GFX8-LABEL: v_uaddsat_i24:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshlrev_b32_e32 v0, 8, v0		; GFX8-NEXT: v_lshlrev_b32_e32 v0, 8, v0
; GFX8-NEXT: v_lshlrev_b32_e32 v1, 8, v1		; GFX8-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX8-NEXT: v_add_u32_e64 v0, s[4:5], v0, v1 clamp		; GFX8-NEXT: v_add_u32_e64 v0, s[4:5], v0, v1 clamp
Show All 21 Lines
; GFX10-NEXT: s_setpc_b64 s[30:31]		; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call i24 @llvm.uadd.sat.i24(i24 %lhs, i24 %rhs)		%result = call i24 @llvm.uadd.sat.i24(i24 %lhs, i24 %rhs)
ret i24 %result		ret i24 %result
}		}

define amdgpu_ps i24 @s_uaddsat_i24(i24 inreg %lhs, i24 inreg %rhs) {		define amdgpu_ps i24 @s_uaddsat_i24(i24 inreg %lhs, i24 inreg %rhs) {
; GFX6-LABEL: s_uaddsat_i24:		; GFX6-LABEL: s_uaddsat_i24:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 8		; GFX6-NEXT: s_mov_b32 s2, 0xffffff
; GFX6-NEXT: s_lshl_b32 s1, s1, 8		; GFX6-NEXT: s_and_b32 s0, s0, s2
; GFX6-NEXT: s_not_b32 s2, s0		; GFX6-NEXT: s_and_b32 s1, s1, s2
; GFX6-NEXT: s_cmp_lt_u32 s2, s1
; GFX6-NEXT: s_cselect_b32 s1, s2, s1
; GFX6-NEXT: s_add_i32 s0, s0, s1		; GFX6-NEXT: s_add_i32 s0, s0, s1
; GFX6-NEXT: s_lshr_b32 s0, s0, 8		; GFX6-NEXT: s_cmp_lt_u32 s0, s2
		; GFX6-NEXT: s_cselect_b32 s0, s0, s2
; GFX6-NEXT: ; return to shader part epilog		; GFX6-NEXT: ; return to shader part epilog
;		;
; GFX8-LABEL: s_uaddsat_i24:		; GFX8-LABEL: s_uaddsat_i24:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_lshl_b32 s1, s1, 8		; GFX8-NEXT: s_lshl_b32 s1, s1, 8
; GFX8-NEXT: s_lshl_b32 s0, s0, 8		; GFX8-NEXT: s_lshl_b32 s0, s0, 8
; GFX8-NEXT: v_mov_b32_e32 v0, s1		; GFX8-NEXT: v_mov_b32_e32 v0, s1
; GFX8-NEXT: v_add_u32_e64 v0, s[0:1], s0, v0 clamp		; GFX8-NEXT: v_add_u32_e64 v0, s[0:1], s0, v0 clamp
▲ Show 20 Lines • Show All 919 Lines • ▼ Show 20 Lines	; GFX10-NEXT: ; return to shader part epilog
%result = call <16 x i32> @llvm.uadd.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)		%result = call <16 x i32> @llvm.uadd.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)
ret <16 x i32> %result		ret <16 x i32> %result
}		}

define i16 @v_uaddsat_i16(i16 %lhs, i16 %rhs) {		define i16 @v_uaddsat_i16(i16 %lhs, i16 %rhs) {
; GFX6-LABEL: v_uaddsat_i16:		; GFX6-LABEL: v_uaddsat_i16:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0		; GFX6-NEXT: s_mov_b32 s4, 0xffff
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1		; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
; GFX6-NEXT: v_xor_b32_e32 v2, -1, v0		; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
; GFX6-NEXT: v_min_u32_e32 v1, v2, v1
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1		; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0		; GFX6-NEXT: v_min_u32_e32 v0, s4, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]		; GFX6-NEXT: s_setpc_b64 s[30:31]
;		;
; GFX8-LABEL: v_uaddsat_i16:		; GFX8-LABEL: v_uaddsat_i16:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_add_u16_e64 v0, v0, v1 clamp		; GFX8-NEXT: v_add_u16_e64 v0, v0, v1 clamp
; GFX8-NEXT: s_setpc_b64 s[30:31]		; GFX8-NEXT: s_setpc_b64 s[30:31]
;		;
Show All 12 Lines
; GFX10-NEXT: s_setpc_b64 s[30:31]		; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call i16 @llvm.uadd.sat.i16(i16 %lhs, i16 %rhs)		%result = call i16 @llvm.uadd.sat.i16(i16 %lhs, i16 %rhs)
ret i16 %result		ret i16 %result
}		}

define amdgpu_ps i16 @s_uaddsat_i16(i16 inreg %lhs, i16 inreg %rhs) {		define amdgpu_ps i16 @s_uaddsat_i16(i16 inreg %lhs, i16 inreg %rhs) {
; GFX6-LABEL: s_uaddsat_i16:		; GFX6-LABEL: s_uaddsat_i16:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 16		; GFX6-NEXT: s_mov_b32 s2, 0xffff
; GFX6-NEXT: s_lshl_b32 s1, s1, 16		; GFX6-NEXT: s_and_b32 s0, s0, s2
; GFX6-NEXT: s_not_b32 s2, s0		; GFX6-NEXT: s_and_b32 s1, s1, s2
; GFX6-NEXT: s_cmp_lt_u32 s2, s1
; GFX6-NEXT: s_cselect_b32 s1, s2, s1
; GFX6-NEXT: s_add_i32 s0, s0, s1		; GFX6-NEXT: s_add_i32 s0, s0, s1
; GFX6-NEXT: s_lshr_b32 s0, s0, 16		; GFX6-NEXT: s_cmp_lt_u32 s0, s2
		; GFX6-NEXT: s_cselect_b32 s0, s0, s2
; GFX6-NEXT: ; return to shader part epilog		; GFX6-NEXT: ; return to shader part epilog
;		;
; GFX8-LABEL: s_uaddsat_i16:		; GFX8-LABEL: s_uaddsat_i16:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: v_mov_b32_e32 v0, s1		; GFX8-NEXT: v_mov_b32_e32 v0, s1
; GFX8-NEXT: v_add_u16_e64 v0, s0, v0 clamp		; GFX8-NEXT: v_add_u16_e64 v0, s0, v0 clamp
; GFX8-NEXT: v_readfirstlane_b32 s0, v0		; GFX8-NEXT: v_readfirstlane_b32 s0, v0
; GFX8-NEXT: ; return to shader part epilog		; GFX8-NEXT: ; return to shader part epilog
Show All 13 Lines
; GFX10-NEXT: ; return to shader part epilog		; GFX10-NEXT: ; return to shader part epilog
%result = call i16 @llvm.uadd.sat.i16(i16 %lhs, i16 %rhs)		%result = call i16 @llvm.uadd.sat.i16(i16 %lhs, i16 %rhs)
ret i16 %result		ret i16 %result
}		}

define amdgpu_ps half @uaddsat_i16_sv(i16 inreg %lhs, i16 %rhs) {		define amdgpu_ps half @uaddsat_i16_sv(i16 inreg %lhs, i16 %rhs) {
; GFX6-LABEL: uaddsat_i16_sv:		; GFX6-LABEL: uaddsat_i16_sv:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 16		; GFX6-NEXT: s_mov_b32 s1, 0xffff
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0		; GFX6-NEXT: s_and_b32 s0, s0, s1
; GFX6-NEXT: s_not_b32 s1, s0		; GFX6-NEXT: v_and_b32_e32 v0, s1, v0
; GFX6-NEXT: v_min_u32_e32 v0, s1, v0
; GFX6-NEXT: v_add_i32_e32 v0, vcc, s0, v0		; GFX6-NEXT: v_add_i32_e32 v0, vcc, s0, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0		; GFX6-NEXT: v_min_u32_e32 v0, s1, v0
; GFX6-NEXT: ; return to shader part epilog		; GFX6-NEXT: ; return to shader part epilog
;		;
; GFX8-LABEL: uaddsat_i16_sv:		; GFX8-LABEL: uaddsat_i16_sv:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: v_add_u16_e64 v0, s0, v0 clamp		; GFX8-NEXT: v_add_u16_e64 v0, s0, v0 clamp
; GFX8-NEXT: ; return to shader part epilog		; GFX8-NEXT: ; return to shader part epilog
;		;
; GFX9-LABEL: uaddsat_i16_sv:		; GFX9-LABEL: uaddsat_i16_sv:
Show All 9 Lines	; GFX10-NEXT: ; return to shader part epilog
%result = call i16 @llvm.uadd.sat.i16(i16 %lhs, i16 %rhs)		%result = call i16 @llvm.uadd.sat.i16(i16 %lhs, i16 %rhs)
%cast = bitcast i16 %result to half		%cast = bitcast i16 %result to half
ret half %cast		ret half %cast
}		}

define amdgpu_ps half @uaddsat_i16_vs(i16 %lhs, i16 inreg %rhs) {		define amdgpu_ps half @uaddsat_i16_vs(i16 %lhs, i16 inreg %rhs) {
; GFX6-LABEL: uaddsat_i16_vs:		; GFX6-LABEL: uaddsat_i16_vs:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0		; GFX6-NEXT: s_mov_b32 s1, 0xffff
; GFX6-NEXT: s_lshl_b32 s0, s0, 16		; GFX6-NEXT: v_and_b32_e32 v0, s1, v0
; GFX6-NEXT: v_xor_b32_e32 v1, -1, v0		; GFX6-NEXT: s_and_b32 s0, s0, s1
; GFX6-NEXT: v_min_u32_e32 v1, s0, v1		; GFX6-NEXT: v_add_i32_e32 v0, vcc, s0, v0
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1		; GFX6-NEXT: v_min_u32_e32 v0, s1, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX6-NEXT: ; return to shader part epilog		; GFX6-NEXT: ; return to shader part epilog
;		;
; GFX8-LABEL: uaddsat_i16_vs:		; GFX8-LABEL: uaddsat_i16_vs:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: v_add_u16_e64 v0, v0, s0 clamp		; GFX8-NEXT: v_add_u16_e64 v0, v0, s0 clamp
; GFX8-NEXT: ; return to shader part epilog		; GFX8-NEXT: ; return to shader part epilog
;		;
; GFX9-LABEL: uaddsat_i16_vs:		; GFX9-LABEL: uaddsat_i16_vs:
Show All 10 Lines	; GFX10-NEXT: ; return to shader part epilog
%cast = bitcast i16 %result to half		%cast = bitcast i16 %result to half
ret half %cast		ret half %cast
}		}

define <2 x i16> @v_uaddsat_v2i16(<2 x i16> %lhs, <2 x i16> %rhs) {		define <2 x i16> @v_uaddsat_v2i16(<2 x i16> %lhs, <2 x i16> %rhs) {
; GFX6-LABEL: v_uaddsat_v2i16:		; GFX6-LABEL: v_uaddsat_v2i16:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0		; GFX6-NEXT: s_mov_b32 s4, 0xffff
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2		; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
; GFX6-NEXT: v_xor_b32_e32 v4, -1, v0		; GFX6-NEXT: v_and_b32_e32 v2, s4, v2
; GFX6-NEXT: v_min_u32_e32 v2, v4, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2		; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v3		; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
; GFX6-NEXT: v_xor_b32_e32 v3, -1, v1		; GFX6-NEXT: v_and_b32_e32 v2, s4, v3
; GFX6-NEXT: v_min_u32_e32 v2, v3, v2
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v2		; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v2
; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0		; GFX6-NEXT: v_min_u32_e32 v0, s4, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v1		; GFX6-NEXT: v_min_u32_e32 v1, s4, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]		; GFX6-NEXT: s_setpc_b64 s[30:31]
;		;
; GFX8-LABEL: v_uaddsat_v2i16:		; GFX8-LABEL: v_uaddsat_v2i16:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_add_u16_e64 v2, v0, v1 clamp		; GFX8-NEXT: v_add_u16_e64 v2, v0, v1 clamp
; GFX8-NEXT: v_add_u16_sdwa v0, v0, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1		; GFX8-NEXT: v_add_u16_sdwa v0, v0, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX8-NEXT: v_mov_b32_e32 v1, 16		; GFX8-NEXT: v_mov_b32_e32 v1, 16
Show All 16 Lines
; GFX10-NEXT: s_setpc_b64 s[30:31]		; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)		%result = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
ret <2 x i16> %result		ret <2 x i16> %result
}		}

define amdgpu_ps i32 @s_uaddsat_v2i16(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs) {		define amdgpu_ps i32 @s_uaddsat_v2i16(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs) {
; GFX6-LABEL: s_uaddsat_v2i16:		; GFX6-LABEL: s_uaddsat_v2i16:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 16		; GFX6-NEXT: s_mov_b32 s4, 0xffff
; GFX6-NEXT: s_lshl_b32 s2, s2, 16		; GFX6-NEXT: s_and_b32 s0, s0, s4
; GFX6-NEXT: s_not_b32 s4, s0		; GFX6-NEXT: s_and_b32 s2, s2, s4
; GFX6-NEXT: s_cmp_lt_u32 s4, s2
; GFX6-NEXT: s_cselect_b32 s2, s4, s2
; GFX6-NEXT: s_add_i32 s0, s0, s2		; GFX6-NEXT: s_add_i32 s0, s0, s2
; GFX6-NEXT: s_lshl_b32 s1, s1, 16		; GFX6-NEXT: s_cmp_lt_u32 s0, s4
; GFX6-NEXT: s_lshl_b32 s2, s3, 16		; GFX6-NEXT: s_cselect_b32 s0, s0, s4
; GFX6-NEXT: s_lshr_b32 s0, s0, 16		; GFX6-NEXT: s_and_b32 s1, s1, s4
; GFX6-NEXT: s_not_b32 s3, s1		; GFX6-NEXT: s_and_b32 s2, s3, s4
; GFX6-NEXT: s_cmp_lt_u32 s3, s2
; GFX6-NEXT: s_cselect_b32 s2, s3, s2
; GFX6-NEXT: s_add_i32 s1, s1, s2		; GFX6-NEXT: s_add_i32 s1, s1, s2
; GFX6-NEXT: s_mov_b32 s2, 0xffff		; GFX6-NEXT: s_cmp_lt_u32 s1, s4
; GFX6-NEXT: s_lshr_b32 s1, s1, 16		; GFX6-NEXT: s_cselect_b32 s1, s1, s4
; GFX6-NEXT: s_and_b32 s1, s1, s2		; GFX6-NEXT: s_and_b32 s1, s1, s4
; GFX6-NEXT: s_and_b32 s0, s0, s2		; GFX6-NEXT: s_and_b32 s0, s0, s4
; GFX6-NEXT: s_lshl_b32 s1, s1, 16		; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_or_b32 s0, s0, s1		; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: ; return to shader part epilog		; GFX6-NEXT: ; return to shader part epilog
;		;
; GFX8-LABEL: s_uaddsat_v2i16:		; GFX8-LABEL: s_uaddsat_v2i16:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_lshr_b32 s3, s1, 16		; GFX8-NEXT: s_lshr_b32 s3, s1, 16
; GFX8-NEXT: s_lshr_b32 s2, s0, 16		; GFX8-NEXT: s_lshr_b32 s2, s0, 16
Show All 23 Lines	; GFX10-NEXT: ; return to shader part epilog
%result = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)		%result = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
%cast = bitcast <2 x i16> %result to i32		%cast = bitcast <2 x i16> %result to i32
ret i32 %cast		ret i32 %cast
}		}

define amdgpu_ps float @uaddsat_v2i16_sv(<2 x i16> inreg %lhs, <2 x i16> %rhs) {		define amdgpu_ps float @uaddsat_v2i16_sv(<2 x i16> inreg %lhs, <2 x i16> %rhs) {
; GFX6-LABEL: uaddsat_v2i16_sv:		; GFX6-LABEL: uaddsat_v2i16_sv:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 16		; GFX6-NEXT: s_mov_b32 s2, 0xffff
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0		; GFX6-NEXT: s_and_b32 s0, s0, s2
; GFX6-NEXT: s_not_b32 s2, s0		; GFX6-NEXT: v_and_b32_e32 v0, s2, v0
; GFX6-NEXT: v_min_u32_e32 v0, s2, v0
; GFX6-NEXT: v_add_i32_e32 v0, vcc, s0, v0		; GFX6-NEXT: v_add_i32_e32 v0, vcc, s0, v0
; GFX6-NEXT: s_lshl_b32 s0, s1, 16		; GFX6-NEXT: s_and_b32 s0, s1, s2
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1		; GFX6-NEXT: v_and_b32_e32 v1, s2, v1
; GFX6-NEXT: s_not_b32 s1, s0
; GFX6-NEXT: v_min_u32_e32 v1, s1, v1
; GFX6-NEXT: v_add_i32_e32 v1, vcc, s0, v1		; GFX6-NEXT: v_add_i32_e32 v1, vcc, s0, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v1		; GFX6-NEXT: v_min_u32_e32 v1, s2, v1
; GFX6-NEXT: s_mov_b32 s0, 0xffff		; GFX6-NEXT: v_min_u32_e32 v0, s2, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0		; GFX6-NEXT: v_and_b32_e32 v1, s2, v1
; GFX6-NEXT: v_and_b32_e32 v1, s0, v1		; GFX6-NEXT: v_and_b32_e32 v0, s2, v0
; GFX6-NEXT: v_and_b32_e32 v0, s0, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1		; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1		; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: ; return to shader part epilog		; GFX6-NEXT: ; return to shader part epilog
;		;
; GFX8-LABEL: uaddsat_v2i16_sv:		; GFX8-LABEL: uaddsat_v2i16_sv:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_lshr_b32 s1, s0, 16		; GFX8-NEXT: s_lshr_b32 s1, s0, 16
; GFX8-NEXT: v_mov_b32_e32 v2, s1		; GFX8-NEXT: v_mov_b32_e32 v2, s1
Show All 17 Lines	; GFX10-NEXT: ; return to shader part epilog
%result = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)		%result = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
%cast = bitcast <2 x i16> %result to float		%cast = bitcast <2 x i16> %result to float
ret float %cast		ret float %cast
}		}

define amdgpu_ps float @uaddsat_v2i16_vs(<2 x i16> %lhs, <2 x i16> inreg %rhs) {		define amdgpu_ps float @uaddsat_v2i16_vs(<2 x i16> %lhs, <2 x i16> inreg %rhs) {
; GFX6-LABEL: uaddsat_v2i16_vs:		; GFX6-LABEL: uaddsat_v2i16_vs:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0		; GFX6-NEXT: s_mov_b32 s2, 0xffff
; GFX6-NEXT: s_lshl_b32 s0, s0, 16		; GFX6-NEXT: v_and_b32_e32 v0, s2, v0
; GFX6-NEXT: v_xor_b32_e32 v2, -1, v0		; GFX6-NEXT: s_and_b32 s0, s0, s2
; GFX6-NEXT: v_min_u32_e32 v2, s0, v2		; GFX6-NEXT: v_add_i32_e32 v0, vcc, s0, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1		; GFX6-NEXT: v_and_b32_e32 v1, s2, v1
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2		; GFX6-NEXT: s_and_b32 s0, s1, s2
; GFX6-NEXT: s_lshl_b32 s0, s1, 16		; GFX6-NEXT: v_add_i32_e32 v1, vcc, s0, v1
; GFX6-NEXT: v_xor_b32_e32 v2, -1, v1		; GFX6-NEXT: v_min_u32_e32 v1, s2, v1
; GFX6-NEXT: v_min_u32_e32 v2, s0, v2		; GFX6-NEXT: v_min_u32_e32 v0, s2, v0
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v2		; GFX6-NEXT: v_and_b32_e32 v1, s2, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v1		; GFX6-NEXT: v_and_b32_e32 v0, s2, v0
; GFX6-NEXT: s_mov_b32 s0, 0xffff
; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX6-NEXT: v_and_b32_e32 v1, s0, v1
; GFX6-NEXT: v_and_b32_e32 v0, s0, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1		; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1		; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: ; return to shader part epilog		; GFX6-NEXT: ; return to shader part epilog
;		;
; GFX8-LABEL: uaddsat_v2i16_vs:		; GFX8-LABEL: uaddsat_v2i16_vs:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_lshr_b32 s1, s0, 16		; GFX8-NEXT: s_lshr_b32 s1, s0, 16
; GFX8-NEXT: v_mov_b32_e32 v2, s1		; GFX8-NEXT: v_mov_b32_e32 v2, s1
Show All 29 Lines
; %result = call <3 x i16> @llvm.uadd.sat.v3i16(<3 x i16> %lhs, <3 x i16> %rhs)		; %result = call <3 x i16> @llvm.uadd.sat.v3i16(<3 x i16> %lhs, <3 x i16> %rhs)
; ret <3 x i16> %result		; ret <3 x i16> %result
; }		; }

define <2 x float> @v_uaddsat_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {		define <2 x float> @v_uaddsat_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
; GFX6-LABEL: v_uaddsat_v4i16:		; GFX6-LABEL: v_uaddsat_v4i16:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0		; GFX6-NEXT: s_mov_b32 s4, 0xffff
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v4		; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
; GFX6-NEXT: v_xor_b32_e32 v8, -1, v0		; GFX6-NEXT: v_and_b32_e32 v4, s4, v4
; GFX6-NEXT: v_min_u32_e32 v4, v8, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v4		; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v5		; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
; GFX6-NEXT: v_xor_b32_e32 v5, -1, v1		; GFX6-NEXT: v_and_b32_e32 v4, s4, v5
; GFX6-NEXT: v_min_u32_e32 v4, v5, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v4		; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v6		; GFX6-NEXT: v_and_b32_e32 v2, s4, v2
; GFX6-NEXT: v_xor_b32_e32 v5, -1, v2		; GFX6-NEXT: v_and_b32_e32 v4, s4, v6
; GFX6-NEXT: v_min_u32_e32 v4, v5, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4		; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v7		; GFX6-NEXT: v_min_u32_e32 v1, s4, v1
; GFX6-NEXT: v_xor_b32_e32 v5, -1, v3		; GFX6-NEXT: v_and_b32_e32 v3, s4, v3
; GFX6-NEXT: v_min_u32_e32 v4, v5, v4		; GFX6-NEXT: v_and_b32_e32 v4, s4, v7
; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v1		; GFX6-NEXT: v_min_u32_e32 v0, s4, v0
; GFX6-NEXT: s_mov_b32 s4, 0xffff
; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v4		; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v4
; GFX6-NEXT: v_and_b32_e32 v1, s4, v1		; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v2		; GFX6-NEXT: v_mov_b32_e32 v8, 0xffff
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v3		; GFX6-NEXT: v_min_u32_e32 v2, s4, v2
		; GFX6-NEXT: v_min_u32_e32 v3, s4, v3
; GFX6-NEXT: v_and_b32_e32 v0, s4, v0		; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1		; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1		; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: v_and_b32_e32 v1, s4, v2		; GFX6-NEXT: v_and_b32_e32 v1, v2, v8
; GFX6-NEXT: v_and_b32_e32 v2, s4, v3		; GFX6-NEXT: v_and_b32_e32 v2, v3, v8
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2		; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX6-NEXT: v_or_b32_e32 v1, v1, v2		; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
; GFX6-NEXT: s_setpc_b64 s[30:31]		; GFX6-NEXT: s_setpc_b64 s[30:31]
;		;
; GFX8-LABEL: v_uaddsat_v4i16:		; GFX8-LABEL: v_uaddsat_v4i16:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_add_u16_e64 v4, v0, v2 clamp		; GFX8-NEXT: v_add_u16_e64 v4, v0, v2 clamp
Show All 25 Lines	; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <4 x i16> @llvm.uadd.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)		%result = call <4 x i16> @llvm.uadd.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
%cast = bitcast <4 x i16> %result to <2 x float>		%cast = bitcast <4 x i16> %result to <2 x float>
ret <2 x float> %cast		ret <2 x float> %cast
}		}

define amdgpu_ps <2 x i32> @s_uaddsat_v4i16(<4 x i16> inreg %lhs, <4 x i16> inreg %rhs) {		define amdgpu_ps <2 x i32> @s_uaddsat_v4i16(<4 x i16> inreg %lhs, <4 x i16> inreg %rhs) {
; GFX6-LABEL: s_uaddsat_v4i16:		; GFX6-LABEL: s_uaddsat_v4i16:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 16		; GFX6-NEXT: s_mov_b32 s8, 0xffff
; GFX6-NEXT: s_lshl_b32 s4, s4, 16		; GFX6-NEXT: s_and_b32 s0, s0, s8
; GFX6-NEXT: s_not_b32 s8, s0		; GFX6-NEXT: s_and_b32 s4, s4, s8
; GFX6-NEXT: s_cmp_lt_u32 s8, s4
; GFX6-NEXT: s_cselect_b32 s4, s8, s4
; GFX6-NEXT: s_add_i32 s0, s0, s4		; GFX6-NEXT: s_add_i32 s0, s0, s4
; GFX6-NEXT: s_lshl_b32 s1, s1, 16		; GFX6-NEXT: s_cmp_lt_u32 s0, s8
; GFX6-NEXT: s_lshl_b32 s4, s5, 16		; GFX6-NEXT: s_cselect_b32 s0, s0, s8
; GFX6-NEXT: s_lshr_b32 s0, s0, 16		; GFX6-NEXT: s_and_b32 s1, s1, s8
; GFX6-NEXT: s_not_b32 s5, s1		; GFX6-NEXT: s_and_b32 s4, s5, s8
; GFX6-NEXT: s_cmp_lt_u32 s5, s4
; GFX6-NEXT: s_cselect_b32 s4, s5, s4
; GFX6-NEXT: s_add_i32 s1, s1, s4		; GFX6-NEXT: s_add_i32 s1, s1, s4
; GFX6-NEXT: s_lshl_b32 s2, s2, 16		; GFX6-NEXT: s_cmp_lt_u32 s1, s8
; GFX6-NEXT: s_lshr_b32 s1, s1, 16		; GFX6-NEXT: s_cselect_b32 s1, s1, s8
; GFX6-NEXT: s_lshl_b32 s4, s6, 16		; GFX6-NEXT: s_and_b32 s2, s2, s8
; GFX6-NEXT: s_not_b32 s5, s2		; GFX6-NEXT: s_and_b32 s4, s6, s8
; GFX6-NEXT: s_cmp_lt_u32 s5, s4
; GFX6-NEXT: s_cselect_b32 s4, s5, s4
; GFX6-NEXT: s_add_i32 s2, s2, s4		; GFX6-NEXT: s_add_i32 s2, s2, s4
; GFX6-NEXT: s_lshl_b32 s3, s3, 16		; GFX6-NEXT: s_cmp_lt_u32 s2, s8
; GFX6-NEXT: s_lshr_b32 s2, s2, 16		; GFX6-NEXT: s_cselect_b32 s2, s2, s8
; GFX6-NEXT: s_lshl_b32 s4, s7, 16		; GFX6-NEXT: s_and_b32 s3, s3, s8
; GFX6-NEXT: s_not_b32 s5, s3		; GFX6-NEXT: s_and_b32 s4, s7, s8
; GFX6-NEXT: s_cmp_lt_u32 s5, s4
; GFX6-NEXT: s_cselect_b32 s4, s5, s4
; GFX6-NEXT: s_add_i32 s3, s3, s4		; GFX6-NEXT: s_add_i32 s3, s3, s4
; GFX6-NEXT: s_mov_b32 s4, 0xffff		; GFX6-NEXT: s_cmp_lt_u32 s3, s8
; GFX6-NEXT: s_and_b32 s1, s1, s4		; GFX6-NEXT: s_cselect_b32 s3, s3, s8
; GFX6-NEXT: s_lshr_b32 s3, s3, 16		; GFX6-NEXT: s_and_b32 s1, s1, s8
; GFX6-NEXT: s_and_b32 s0, s0, s4		; GFX6-NEXT: s_and_b32 s0, s0, s8
; GFX6-NEXT: s_lshl_b32 s1, s1, 16		; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_or_b32 s0, s0, s1		; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: s_and_b32 s1, s2, s4		; GFX6-NEXT: s_and_b32 s1, s2, s8
; GFX6-NEXT: s_and_b32 s2, s3, s4		; GFX6-NEXT: s_and_b32 s2, s3, s8
; GFX6-NEXT: s_lshl_b32 s2, s2, 16		; GFX6-NEXT: s_lshl_b32 s2, s2, 16
; GFX6-NEXT: s_or_b32 s1, s1, s2		; GFX6-NEXT: s_or_b32 s1, s1, s2
; GFX6-NEXT: ; return to shader part epilog		; GFX6-NEXT: ; return to shader part epilog
;		;
; GFX8-LABEL: s_uaddsat_v4i16:		; GFX8-LABEL: s_uaddsat_v4i16:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_lshr_b32 s6, s2, 16		; GFX8-NEXT: s_lshr_b32 s6, s2, 16
; GFX8-NEXT: s_lshr_b32 s7, s3, 16		; GFX8-NEXT: s_lshr_b32 s7, s3, 16
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Lines
; %result = call <5 x i16> @llvm.uadd.sat.v5i16(<5 x i16> %lhs, <5 x i16> %rhs)		; %result = call <5 x i16> @llvm.uadd.sat.v5i16(<5 x i16> %lhs, <5 x i16> %rhs)
; ret <5 x i16> %result		; ret <5 x i16> %result
; }		; }

define <3 x float> @v_uaddsat_v6i16(<6 x i16> %lhs, <6 x i16> %rhs) {		define <3 x float> @v_uaddsat_v6i16(<6 x i16> %lhs, <6 x i16> %rhs) {
; GFX6-LABEL: v_uaddsat_v6i16:		; GFX6-LABEL: v_uaddsat_v6i16:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0		; GFX6-NEXT: s_mov_b32 s4, 0xffff
; GFX6-NEXT: v_lshlrev_b32_e32 v6, 16, v6		; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
; GFX6-NEXT: v_xor_b32_e32 v12, -1, v0		; GFX6-NEXT: v_and_b32_e32 v6, s4, v6
; GFX6-NEXT: v_min_u32_e32 v6, v12, v6
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v6		; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v6
; GFX6-NEXT: v_lshlrev_b32_e32 v6, 16, v7		; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
; GFX6-NEXT: v_xor_b32_e32 v7, -1, v1		; GFX6-NEXT: v_and_b32_e32 v6, s4, v7
; GFX6-NEXT: v_min_u32_e32 v6, v7, v6
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v6		; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v6
; GFX6-NEXT: v_lshlrev_b32_e32 v6, 16, v8		; GFX6-NEXT: v_and_b32_e32 v2, s4, v2
; GFX6-NEXT: v_xor_b32_e32 v7, -1, v2		; GFX6-NEXT: v_and_b32_e32 v6, s4, v8
; GFX6-NEXT: v_min_u32_e32 v6, v7, v6
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v6		; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v6
; GFX6-NEXT: v_lshlrev_b32_e32 v6, 16, v9		; GFX6-NEXT: v_and_b32_e32 v3, s4, v3
; GFX6-NEXT: v_xor_b32_e32 v7, -1, v3		; GFX6-NEXT: v_and_b32_e32 v6, s4, v9
; GFX6-NEXT: v_min_u32_e32 v6, v7, v6
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v6		; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v6
; GFX6-NEXT: v_lshlrev_b32_e32 v6, 16, v10		; GFX6-NEXT: v_mov_b32_e32 v12, 0xffff
; GFX6-NEXT: v_xor_b32_e32 v7, -1, v4		; GFX6-NEXT: v_min_u32_e32 v1, s4, v1
; GFX6-NEXT: v_min_u32_e32 v6, v7, v6		; GFX6-NEXT: v_and_b32_e32 v4, s4, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v5, 16, v5		; GFX6-NEXT: v_and_b32_e32 v6, s4, v10
; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v6		; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v6
; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v1		; GFX6-NEXT: v_min_u32_e32 v0, s4, v0
; GFX6-NEXT: s_mov_b32 s4, 0xffff		; GFX6-NEXT: v_and_b32_e32 v1, v1, v12
; GFX6-NEXT: v_lshlrev_b32_e32 v6, 16, v11		; GFX6-NEXT: v_and_b32_e32 v5, s4, v5
; GFX6-NEXT: v_xor_b32_e32 v7, -1, v5		; GFX6-NEXT: v_and_b32_e32 v6, v11, v12
; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
; GFX6-NEXT: v_min_u32_e32 v6, v7, v6
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v6		; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v2		; GFX6-NEXT: v_min_u32_e32 v2, s4, v2
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v3		; GFX6-NEXT: v_min_u32_e32 v3, s4, v3
; GFX6-NEXT: v_and_b32_e32 v0, s4, v0		; GFX6-NEXT: v_and_b32_e32 v0, v0, v12
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1		; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1		; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: v_and_b32_e32 v1, s4, v2		; GFX6-NEXT: v_and_b32_e32 v1, v2, v12
; GFX6-NEXT: v_and_b32_e32 v2, s4, v3		; GFX6-NEXT: v_and_b32_e32 v2, v3, v12
; GFX6-NEXT: v_lshrrev_b32_e32 v5, 16, v5		; GFX6-NEXT: v_min_u32_e32 v5, v5, v12
; GFX6-NEXT: v_and_b32_e32 v3, s4, v5		; GFX6-NEXT: v_and_b32_e32 v3, v5, v12
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2		; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX6-NEXT: v_lshrrev_b32_e32 v4, 16, v4		; GFX6-NEXT: v_min_u32_e32 v4, s4, v4
; GFX6-NEXT: v_or_b32_e32 v1, v1, v2		; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
; GFX6-NEXT: v_and_b32_e32 v2, s4, v4		; GFX6-NEXT: v_and_b32_e32 v2, v4, v12
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3		; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX6-NEXT: v_or_b32_e32 v2, v2, v3		; GFX6-NEXT: v_or_b32_e32 v2, v2, v3
; GFX6-NEXT: s_setpc_b64 s[30:31]		; GFX6-NEXT: s_setpc_b64 s[30:31]
;		;
; GFX8-LABEL: v_uaddsat_v6i16:		; GFX8-LABEL: v_uaddsat_v6i16:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_add_u16_e64 v6, v0, v3 clamp		; GFX8-NEXT: v_add_u16_e64 v6, v0, v3 clamp
Show All 32 Lines	; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <6 x i16> @llvm.uadd.sat.v6i16(<6 x i16> %lhs, <6 x i16> %rhs)		%result = call <6 x i16> @llvm.uadd.sat.v6i16(<6 x i16> %lhs, <6 x i16> %rhs)
%cast = bitcast <6 x i16> %result to <3 x float>		%cast = bitcast <6 x i16> %result to <3 x float>
ret <3 x float> %cast		ret <3 x float> %cast
}		}

define amdgpu_ps <3 x i32> @s_uaddsat_v6i16(<6 x i16> inreg %lhs, <6 x i16> inreg %rhs) {		define amdgpu_ps <3 x i32> @s_uaddsat_v6i16(<6 x i16> inreg %lhs, <6 x i16> inreg %rhs) {
; GFX6-LABEL: s_uaddsat_v6i16:		; GFX6-LABEL: s_uaddsat_v6i16:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 16		; GFX6-NEXT: s_mov_b32 s12, 0xffff
; GFX6-NEXT: s_lshl_b32 s6, s6, 16		; GFX6-NEXT: s_and_b32 s0, s0, s12
; GFX6-NEXT: s_not_b32 s12, s0		; GFX6-NEXT: s_and_b32 s6, s6, s12
; GFX6-NEXT: s_cmp_lt_u32 s12, s6
; GFX6-NEXT: s_cselect_b32 s6, s12, s6
; GFX6-NEXT: s_add_i32 s0, s0, s6		; GFX6-NEXT: s_add_i32 s0, s0, s6
; GFX6-NEXT: s_lshl_b32 s1, s1, 16		; GFX6-NEXT: s_cmp_lt_u32 s0, s12
; GFX6-NEXT: s_lshl_b32 s6, s7, 16		; GFX6-NEXT: s_cselect_b32 s0, s0, s12
; GFX6-NEXT: s_lshr_b32 s0, s0, 16		; GFX6-NEXT: s_and_b32 s1, s1, s12
; GFX6-NEXT: s_not_b32 s7, s1		; GFX6-NEXT: s_and_b32 s6, s7, s12
; GFX6-NEXT: s_cmp_lt_u32 s7, s6
; GFX6-NEXT: s_cselect_b32 s6, s7, s6
; GFX6-NEXT: s_add_i32 s1, s1, s6		; GFX6-NEXT: s_add_i32 s1, s1, s6
; GFX6-NEXT: s_lshl_b32 s2, s2, 16		; GFX6-NEXT: s_cmp_lt_u32 s1, s12
; GFX6-NEXT: s_lshr_b32 s1, s1, 16		; GFX6-NEXT: s_cselect_b32 s1, s1, s12
; GFX6-NEXT: s_lshl_b32 s6, s8, 16		; GFX6-NEXT: s_and_b32 s2, s2, s12
; GFX6-NEXT: s_not_b32 s7, s2		; GFX6-NEXT: s_and_b32 s6, s8, s12
; GFX6-NEXT: s_cmp_lt_u32 s7, s6
; GFX6-NEXT: s_cselect_b32 s6, s7, s6
; GFX6-NEXT: s_add_i32 s2, s2, s6		; GFX6-NEXT: s_add_i32 s2, s2, s6
; GFX6-NEXT: s_lshl_b32 s3, s3, 16		; GFX6-NEXT: s_cmp_lt_u32 s2, s12
; GFX6-NEXT: s_lshr_b32 s2, s2, 16		; GFX6-NEXT: s_cselect_b32 s2, s2, s12
; GFX6-NEXT: s_lshl_b32 s6, s9, 16		; GFX6-NEXT: s_and_b32 s3, s3, s12
; GFX6-NEXT: s_not_b32 s7, s3		; GFX6-NEXT: s_and_b32 s6, s9, s12
; GFX6-NEXT: s_cmp_lt_u32 s7, s6
; GFX6-NEXT: s_cselect_b32 s6, s7, s6
; GFX6-NEXT: s_add_i32 s3, s3, s6		; GFX6-NEXT: s_add_i32 s3, s3, s6
; GFX6-NEXT: s_lshl_b32 s4, s4, 16		; GFX6-NEXT: s_cmp_lt_u32 s3, s12
; GFX6-NEXT: s_lshr_b32 s3, s3, 16		; GFX6-NEXT: s_cselect_b32 s3, s3, s12
; GFX6-NEXT: s_lshl_b32 s6, s10, 16		; GFX6-NEXT: s_and_b32 s4, s4, s12
; GFX6-NEXT: s_not_b32 s7, s4		; GFX6-NEXT: s_and_b32 s6, s10, s12
; GFX6-NEXT: s_cmp_lt_u32 s7, s6
; GFX6-NEXT: s_cselect_b32 s6, s7, s6
; GFX6-NEXT: s_add_i32 s4, s4, s6		; GFX6-NEXT: s_add_i32 s4, s4, s6
; GFX6-NEXT: s_lshl_b32 s5, s5, 16		; GFX6-NEXT: s_cmp_lt_u32 s4, s12
; GFX6-NEXT: s_lshr_b32 s4, s4, 16		; GFX6-NEXT: s_cselect_b32 s4, s4, s12
; GFX6-NEXT: s_lshl_b32 s6, s11, 16		; GFX6-NEXT: s_and_b32 s5, s5, s12
; GFX6-NEXT: s_not_b32 s7, s5		; GFX6-NEXT: s_and_b32 s6, s11, s12
; GFX6-NEXT: s_cmp_lt_u32 s7, s6
; GFX6-NEXT: s_cselect_b32 s6, s7, s6
; GFX6-NEXT: s_add_i32 s5, s5, s6		; GFX6-NEXT: s_add_i32 s5, s5, s6
; GFX6-NEXT: s_mov_b32 s6, 0xffff		; GFX6-NEXT: s_cmp_lt_u32 s5, s12
; GFX6-NEXT: s_and_b32 s1, s1, s6		; GFX6-NEXT: s_cselect_b32 s5, s5, s12
; GFX6-NEXT: s_and_b32 s0, s0, s6		; GFX6-NEXT: s_and_b32 s1, s1, s12
		; GFX6-NEXT: s_and_b32 s0, s0, s12
; GFX6-NEXT: s_lshl_b32 s1, s1, 16		; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_or_b32 s0, s0, s1		; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: s_and_b32 s1, s2, s6		; GFX6-NEXT: s_and_b32 s1, s2, s12
; GFX6-NEXT: s_and_b32 s2, s3, s6		; GFX6-NEXT: s_and_b32 s2, s3, s12
; GFX6-NEXT: s_lshr_b32 s5, s5, 16		; GFX6-NEXT: s_and_b32 s3, s5, s12
; GFX6-NEXT: s_and_b32 s3, s5, s6
; GFX6-NEXT: s_lshl_b32 s2, s2, 16		; GFX6-NEXT: s_lshl_b32 s2, s2, 16
; GFX6-NEXT: s_or_b32 s1, s1, s2		; GFX6-NEXT: s_or_b32 s1, s1, s2
; GFX6-NEXT: s_and_b32 s2, s4, s6		; GFX6-NEXT: s_and_b32 s2, s4, s12
; GFX6-NEXT: s_lshl_b32 s3, s3, 16		; GFX6-NEXT: s_lshl_b32 s3, s3, 16
; GFX6-NEXT: s_or_b32 s2, s2, s3		; GFX6-NEXT: s_or_b32 s2, s2, s3
; GFX6-NEXT: ; return to shader part epilog		; GFX6-NEXT: ; return to shader part epilog
;		;
; GFX8-LABEL: s_uaddsat_v6i16:		; GFX8-LABEL: s_uaddsat_v6i16:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_lshr_b32 s9, s3, 16		; GFX8-NEXT: s_lshr_b32 s9, s3, 16
; GFX8-NEXT: s_lshr_b32 s10, s4, 16		; GFX8-NEXT: s_lshr_b32 s10, s4, 16
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines	; GFX10-NEXT: ; return to shader part epilog
%cast = bitcast <6 x i16> %result to <3 x i32>		%cast = bitcast <6 x i16> %result to <3 x i32>
ret <3 x i32> %cast		ret <3 x i32> %cast
}		}

define <4 x float> @v_uaddsat_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {		define <4 x float> @v_uaddsat_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
; GFX6-LABEL: v_uaddsat_v8i16:		; GFX6-LABEL: v_uaddsat_v8i16:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0		; GFX6-NEXT: s_mov_b32 s4, 0xffff
; GFX6-NEXT: v_lshlrev_b32_e32 v8, 16, v8		; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
; GFX6-NEXT: v_xor_b32_e32 v16, -1, v0		; GFX6-NEXT: v_and_b32_e32 v8, s4, v8
; GFX6-NEXT: v_min_u32_e32 v8, v16, v8
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v8		; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v8
; GFX6-NEXT: v_lshlrev_b32_e32 v8, 16, v9		; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
; GFX6-NEXT: v_xor_b32_e32 v9, -1, v1		; GFX6-NEXT: v_and_b32_e32 v8, s4, v9
; GFX6-NEXT: v_min_u32_e32 v8, v9, v8
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v8		; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v8
; GFX6-NEXT: v_lshlrev_b32_e32 v8, 16, v10		; GFX6-NEXT: v_and_b32_e32 v2, s4, v2
; GFX6-NEXT: v_xor_b32_e32 v9, -1, v2		; GFX6-NEXT: v_and_b32_e32 v8, s4, v10
; GFX6-NEXT: v_min_u32_e32 v8, v9, v8
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v8		; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v8
; GFX6-NEXT: v_lshlrev_b32_e32 v8, 16, v11		; GFX6-NEXT: v_and_b32_e32 v3, s4, v3
; GFX6-NEXT: v_xor_b32_e32 v9, -1, v3		; GFX6-NEXT: v_and_b32_e32 v8, s4, v11
; GFX6-NEXT: v_min_u32_e32 v8, v9, v8
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v8		; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v8
; GFX6-NEXT: v_lshlrev_b32_e32 v8, 16, v12		; GFX6-NEXT: v_mov_b32_e32 v16, 0xffff
; GFX6-NEXT: v_xor_b32_e32 v9, -1, v4		; GFX6-NEXT: v_and_b32_e32 v4, s4, v4
; GFX6-NEXT: v_min_u32_e32 v8, v9, v8		; GFX6-NEXT: v_and_b32_e32 v8, s4, v12
; GFX6-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v8		; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v8
; GFX6-NEXT: v_lshlrev_b32_e32 v8, 16, v13		; GFX6-NEXT: v_min_u32_e32 v1, s4, v1
; GFX6-NEXT: v_xor_b32_e32 v9, -1, v5		; GFX6-NEXT: v_and_b32_e32 v5, s4, v5
; GFX6-NEXT: v_min_u32_e32 v8, v9, v8		; GFX6-NEXT: v_and_b32_e32 v8, v13, v16
; GFX6-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v8		; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; GFX6-NEXT: v_lshlrev_b32_e32 v8, 16, v14		; GFX6-NEXT: v_min_u32_e32 v0, s4, v0
; GFX6-NEXT: v_xor_b32_e32 v9, -1, v6		; GFX6-NEXT: v_and_b32_e32 v1, v1, v16
; GFX6-NEXT: v_min_u32_e32 v8, v9, v8		; GFX6-NEXT: v_and_b32_e32 v6, v6, v16
; GFX6-NEXT: v_lshlrev_b32_e32 v7, 16, v7		; GFX6-NEXT: v_and_b32_e32 v8, v14, v16
; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX6-NEXT: s_mov_b32 s4, 0xffff
; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v8		; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v8
; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0		; GFX6-NEXT: v_min_u32_e32 v2, s4, v2
; GFX6-NEXT: v_and_b32_e32 v1, s4, v1		; GFX6-NEXT: v_min_u32_e32 v3, s4, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v8, 16, v15		; GFX6-NEXT: v_and_b32_e32 v7, v7, v16
; GFX6-NEXT: v_xor_b32_e32 v9, -1, v7		; GFX6-NEXT: v_and_b32_e32 v8, v15, v16
; GFX6-NEXT: v_min_u32_e32 v8, v9, v8		; GFX6-NEXT: v_and_b32_e32 v0, v0, v16
; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1		; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_add_i32_e32 v7, vcc, v7, v8		; GFX6-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1		; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: v_and_b32_e32 v1, s4, v2		; GFX6-NEXT: v_and_b32_e32 v1, v2, v16
; GFX6-NEXT: v_and_b32_e32 v2, s4, v3		; GFX6-NEXT: v_and_b32_e32 v2, v3, v16
; GFX6-NEXT: v_lshrrev_b32_e32 v5, 16, v5		; GFX6-NEXT: v_min_u32_e32 v5, v5, v16
; GFX6-NEXT: v_and_b32_e32 v3, s4, v5		; GFX6-NEXT: v_and_b32_e32 v3, v5, v16
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2		; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX6-NEXT: v_lshrrev_b32_e32 v4, 16, v4		; GFX6-NEXT: v_min_u32_e32 v4, s4, v4
; GFX6-NEXT: v_lshrrev_b32_e32 v7, 16, v7		; GFX6-NEXT: v_min_u32_e32 v7, v7, v16
; GFX6-NEXT: v_or_b32_e32 v1, v1, v2		; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
; GFX6-NEXT: v_and_b32_e32 v2, s4, v4		; GFX6-NEXT: v_and_b32_e32 v2, v4, v16
; GFX6-NEXT: v_and_b32_e32 v4, s4, v7		; GFX6-NEXT: v_and_b32_e32 v4, v7, v16
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3		; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX6-NEXT: v_lshrrev_b32_e32 v6, 16, v6		; GFX6-NEXT: v_min_u32_e32 v6, v6, v16
; GFX6-NEXT: v_or_b32_e32 v2, v2, v3		; GFX6-NEXT: v_or_b32_e32 v2, v2, v3
; GFX6-NEXT: v_and_b32_e32 v3, s4, v6		; GFX6-NEXT: v_and_b32_e32 v3, v6, v16
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v4		; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX6-NEXT: v_or_b32_e32 v3, v3, v4		; GFX6-NEXT: v_or_b32_e32 v3, v3, v4
; GFX6-NEXT: s_setpc_b64 s[30:31]		; GFX6-NEXT: s_setpc_b64 s[30:31]
;		;
; GFX8-LABEL: v_uaddsat_v8i16:		; GFX8-LABEL: v_uaddsat_v8i16:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_add_u16_e64 v8, v0, v4 clamp		; GFX8-NEXT: v_add_u16_e64 v8, v0, v4 clamp
Show All 38 Lines	; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)		%result = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
%cast = bitcast <8 x i16> %result to <4 x float>		%cast = bitcast <8 x i16> %result to <4 x float>
ret <4 x float> %cast		ret <4 x float> %cast
}		}

define amdgpu_ps <4 x i32> @s_uaddsat_v8i16(<8 x i16> inreg %lhs, <8 x i16> inreg %rhs) {		define amdgpu_ps <4 x i32> @s_uaddsat_v8i16(<8 x i16> inreg %lhs, <8 x i16> inreg %rhs) {
; GFX6-LABEL: s_uaddsat_v8i16:		; GFX6-LABEL: s_uaddsat_v8i16:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 16		; GFX6-NEXT: s_mov_b32 s16, 0xffff
; GFX6-NEXT: s_lshl_b32 s8, s8, 16		; GFX6-NEXT: s_and_b32 s0, s0, s16
; GFX6-NEXT: s_not_b32 s16, s0		; GFX6-NEXT: s_and_b32 s8, s8, s16
; GFX6-NEXT: s_cmp_lt_u32 s16, s8
; GFX6-NEXT: s_cselect_b32 s8, s16, s8
; GFX6-NEXT: s_add_i32 s0, s0, s8		; GFX6-NEXT: s_add_i32 s0, s0, s8
; GFX6-NEXT: s_lshl_b32 s1, s1, 16		; GFX6-NEXT: s_cmp_lt_u32 s0, s16
; GFX6-NEXT: s_lshl_b32 s8, s9, 16		; GFX6-NEXT: s_cselect_b32 s0, s0, s16
; GFX6-NEXT: s_lshr_b32 s0, s0, 16		; GFX6-NEXT: s_and_b32 s1, s1, s16
; GFX6-NEXT: s_not_b32 s9, s1		; GFX6-NEXT: s_and_b32 s8, s9, s16
; GFX6-NEXT: s_cmp_lt_u32 s9, s8
; GFX6-NEXT: s_cselect_b32 s8, s9, s8
; GFX6-NEXT: s_add_i32 s1, s1, s8		; GFX6-NEXT: s_add_i32 s1, s1, s8
; GFX6-NEXT: s_lshl_b32 s2, s2, 16		; GFX6-NEXT: s_cmp_lt_u32 s1, s16
; GFX6-NEXT: s_lshr_b32 s1, s1, 16		; GFX6-NEXT: s_cselect_b32 s1, s1, s16
; GFX6-NEXT: s_lshl_b32 s8, s10, 16		; GFX6-NEXT: s_and_b32 s2, s2, s16
; GFX6-NEXT: s_not_b32 s9, s2		; GFX6-NEXT: s_and_b32 s8, s10, s16
; GFX6-NEXT: s_cmp_lt_u32 s9, s8
; GFX6-NEXT: s_cselect_b32 s8, s9, s8
; GFX6-NEXT: s_add_i32 s2, s2, s8		; GFX6-NEXT: s_add_i32 s2, s2, s8
; GFX6-NEXT: s_lshl_b32 s3, s3, 16		; GFX6-NEXT: s_cmp_lt_u32 s2, s16
; GFX6-NEXT: s_lshr_b32 s2, s2, 16		; GFX6-NEXT: s_cselect_b32 s2, s2, s16
; GFX6-NEXT: s_lshl_b32 s8, s11, 16		; GFX6-NEXT: s_and_b32 s3, s3, s16
; GFX6-NEXT: s_not_b32 s9, s3		; GFX6-NEXT: s_and_b32 s8, s11, s16
; GFX6-NEXT: s_cmp_lt_u32 s9, s8
; GFX6-NEXT: s_cselect_b32 s8, s9, s8
; GFX6-NEXT: s_add_i32 s3, s3, s8		; GFX6-NEXT: s_add_i32 s3, s3, s8
; GFX6-NEXT: s_lshl_b32 s4, s4, 16		; GFX6-NEXT: s_cmp_lt_u32 s3, s16
; GFX6-NEXT: s_lshr_b32 s3, s3, 16		; GFX6-NEXT: s_cselect_b32 s3, s3, s16
; GFX6-NEXT: s_lshl_b32 s8, s12, 16		; GFX6-NEXT: s_and_b32 s4, s4, s16
; GFX6-NEXT: s_not_b32 s9, s4		; GFX6-NEXT: s_and_b32 s8, s12, s16
; GFX6-NEXT: s_cmp_lt_u32 s9, s8
; GFX6-NEXT: s_cselect_b32 s8, s9, s8
; GFX6-NEXT: s_add_i32 s4, s4, s8		; GFX6-NEXT: s_add_i32 s4, s4, s8
; GFX6-NEXT: s_lshl_b32 s5, s5, 16		; GFX6-NEXT: s_cmp_lt_u32 s4, s16
; GFX6-NEXT: s_lshr_b32 s4, s4, 16		; GFX6-NEXT: s_cselect_b32 s4, s4, s16
; GFX6-NEXT: s_lshl_b32 s8, s13, 16		; GFX6-NEXT: s_and_b32 s5, s5, s16
; GFX6-NEXT: s_not_b32 s9, s5		; GFX6-NEXT: s_and_b32 s8, s13, s16
; GFX6-NEXT: s_cmp_lt_u32 s9, s8
; GFX6-NEXT: s_cselect_b32 s8, s9, s8
; GFX6-NEXT: s_add_i32 s5, s5, s8		; GFX6-NEXT: s_add_i32 s5, s5, s8
; GFX6-NEXT: s_lshl_b32 s6, s6, 16		; GFX6-NEXT: s_cmp_lt_u32 s5, s16
; GFX6-NEXT: s_lshr_b32 s5, s5, 16		; GFX6-NEXT: s_cselect_b32 s5, s5, s16
; GFX6-NEXT: s_lshl_b32 s8, s14, 16		; GFX6-NEXT: s_and_b32 s6, s6, s16
; GFX6-NEXT: s_not_b32 s9, s6		; GFX6-NEXT: s_and_b32 s8, s14, s16
; GFX6-NEXT: s_cmp_lt_u32 s9, s8
; GFX6-NEXT: s_cselect_b32 s8, s9, s8
; GFX6-NEXT: s_add_i32 s6, s6, s8		; GFX6-NEXT: s_add_i32 s6, s6, s8
; GFX6-NEXT: s_lshl_b32 s7, s7, 16		; GFX6-NEXT: s_cmp_lt_u32 s6, s16
; GFX6-NEXT: s_lshr_b32 s6, s6, 16		; GFX6-NEXT: s_cselect_b32 s6, s6, s16
; GFX6-NEXT: s_lshl_b32 s8, s15, 16		; GFX6-NEXT: s_and_b32 s7, s7, s16
; GFX6-NEXT: s_not_b32 s9, s7		; GFX6-NEXT: s_and_b32 s8, s15, s16
; GFX6-NEXT: s_cmp_lt_u32 s9, s8
; GFX6-NEXT: s_cselect_b32 s8, s9, s8
; GFX6-NEXT: s_add_i32 s7, s7, s8		; GFX6-NEXT: s_add_i32 s7, s7, s8
; GFX6-NEXT: s_mov_b32 s8, 0xffff		; GFX6-NEXT: s_cmp_lt_u32 s7, s16
; GFX6-NEXT: s_and_b32 s1, s1, s8		; GFX6-NEXT: s_cselect_b32 s7, s7, s16
; GFX6-NEXT: s_and_b32 s0, s0, s8		; GFX6-NEXT: s_and_b32 s1, s1, s16
		; GFX6-NEXT: s_and_b32 s0, s0, s16
; GFX6-NEXT: s_lshl_b32 s1, s1, 16		; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_or_b32 s0, s0, s1		; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: s_and_b32 s1, s2, s8		; GFX6-NEXT: s_and_b32 s1, s2, s16
; GFX6-NEXT: s_and_b32 s2, s3, s8		; GFX6-NEXT: s_and_b32 s2, s3, s16
; GFX6-NEXT: s_and_b32 s3, s5, s8		; GFX6-NEXT: s_and_b32 s3, s5, s16
; GFX6-NEXT: s_lshl_b32 s2, s2, 16		; GFX6-NEXT: s_lshl_b32 s2, s2, 16
; GFX6-NEXT: s_lshr_b32 s7, s7, 16
; GFX6-NEXT: s_or_b32 s1, s1, s2		; GFX6-NEXT: s_or_b32 s1, s1, s2
; GFX6-NEXT: s_and_b32 s2, s4, s8		; GFX6-NEXT: s_and_b32 s2, s4, s16
; GFX6-NEXT: s_and_b32 s4, s7, s8		; GFX6-NEXT: s_and_b32 s4, s7, s16
; GFX6-NEXT: s_lshl_b32 s3, s3, 16		; GFX6-NEXT: s_lshl_b32 s3, s3, 16
; GFX6-NEXT: s_or_b32 s2, s2, s3		; GFX6-NEXT: s_or_b32 s2, s2, s3
; GFX6-NEXT: s_and_b32 s3, s6, s8		; GFX6-NEXT: s_and_b32 s3, s6, s16
; GFX6-NEXT: s_lshl_b32 s4, s4, 16		; GFX6-NEXT: s_lshl_b32 s4, s4, 16
; GFX6-NEXT: s_or_b32 s3, s3, s4		; GFX6-NEXT: s_or_b32 s3, s3, s4
; GFX6-NEXT: ; return to shader part epilog		; GFX6-NEXT: ; return to shader part epilog
;		;
; GFX8-LABEL: s_uaddsat_v8i16:		; GFX8-LABEL: s_uaddsat_v8i16:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_lshr_b32 s12, s4, 16		; GFX8-NEXT: s_lshr_b32 s12, s4, 16
; GFX8-NEXT: s_lshr_b32 s13, s5, 16		; GFX8-NEXT: s_lshr_b32 s13, s5, 16
▲ Show 20 Lines • Show All 1,371 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py		; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=tahiti -o - %s \| FileCheck -check-prefix=GFX6 %s		; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=tahiti -o - %s \| FileCheck -check-prefix=GFX6 %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=fiji -o - %s \| FileCheck -check-prefix=GFX8 %s		; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=fiji -o - %s \| FileCheck -check-prefix=GFX8 %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -o - %s \| FileCheck -check-prefix=GFX9 %s		; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -o - %s \| FileCheck -check-prefix=GFX9 %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -o - %s \| FileCheck -check-prefix=GFX10 %s		; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -o - %s \| FileCheck -check-prefix=GFX10 %s

define i7 @v_usubsat_i7(i7 %lhs, i7 %rhs) {		define i7 @v_usubsat_i7(i7 %lhs, i7 %rhs) {
; GFX6-LABEL: v_usubsat_i7:		; GFX6-LABEL: v_usubsat_i7:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 25, v0		; GFX6-NEXT: s_movk_i32 s4, 0x7f
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 25, v1		; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
; GFX6-NEXT: v_min_u32_e32 v1, v0, v1		; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
		; GFX6-NEXT: v_max_u32_e32 v0, v0, v1
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1		; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v0, 25, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]		; GFX6-NEXT: s_setpc_b64 s[30:31]
;		;
; GFX8-LABEL: v_usubsat_i7:		; GFX8-LABEL: v_usubsat_i7:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshlrev_b16_e32 v0, 9, v0		; GFX8-NEXT: v_lshlrev_b16_e32 v0, 9, v0
; GFX8-NEXT: v_lshlrev_b16_e32 v1, 9, v1		; GFX8-NEXT: v_lshlrev_b16_e32 v1, 9, v1
; GFX8-NEXT: v_sub_u16_e64 v0, v0, v1 clamp		; GFX8-NEXT: v_sub_u16_e64 v0, v0, v1 clamp
Show All 21 Lines
; GFX10-NEXT: s_setpc_b64 s[30:31]		; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call i7 @llvm.usub.sat.i7(i7 %lhs, i7 %rhs)		%result = call i7 @llvm.usub.sat.i7(i7 %lhs, i7 %rhs)
ret i7 %result		ret i7 %result
}		}

define amdgpu_ps i7 @s_usubsat_i7(i7 inreg %lhs, i7 inreg %rhs) {		define amdgpu_ps i7 @s_usubsat_i7(i7 inreg %lhs, i7 inreg %rhs) {
; GFX6-LABEL: s_usubsat_i7:		; GFX6-LABEL: s_usubsat_i7:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 25		; GFX6-NEXT: s_movk_i32 s2, 0x7f
; GFX6-NEXT: s_lshl_b32 s1, s1, 25		; GFX6-NEXT: s_and_b32 s0, s0, s2
; GFX6-NEXT: s_cmp_lt_u32 s0, s1		; GFX6-NEXT: s_and_b32 s1, s1, s2
; GFX6-NEXT: s_cselect_b32 s1, s0, s1		; GFX6-NEXT: s_cmp_gt_u32 s0, s1
		; GFX6-NEXT: s_cselect_b32 s0, s0, s1
; GFX6-NEXT: s_sub_i32 s0, s0, s1		; GFX6-NEXT: s_sub_i32 s0, s0, s1
; GFX6-NEXT: s_lshr_b32 s0, s0, 25
; GFX6-NEXT: ; return to shader part epilog		; GFX6-NEXT: ; return to shader part epilog
;		;
; GFX8-LABEL: s_usubsat_i7:		; GFX8-LABEL: s_usubsat_i7:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_bfe_u32 s2, 9, 0x100000		; GFX8-NEXT: s_bfe_u32 s2, 9, 0x100000
; GFX8-NEXT: s_lshl_b32 s1, s1, s2		; GFX8-NEXT: s_lshl_b32 s1, s1, s2
; GFX8-NEXT: s_lshl_b32 s0, s0, s2		; GFX8-NEXT: s_lshl_b32 s0, s0, s2
; GFX8-NEXT: v_mov_b32_e32 v0, s1		; GFX8-NEXT: v_mov_b32_e32 v0, s1
Show All 26 Lines	; GFX10-NEXT: ; return to shader part epilog
%result = call i7 @llvm.usub.sat.i7(i7 %lhs, i7 %rhs)		%result = call i7 @llvm.usub.sat.i7(i7 %lhs, i7 %rhs)
ret i7 %result		ret i7 %result
}		}

define i8 @v_usubsat_i8(i8 %lhs, i8 %rhs) {		define i8 @v_usubsat_i8(i8 %lhs, i8 %rhs) {
; GFX6-LABEL: v_usubsat_i8:		; GFX6-LABEL: v_usubsat_i8:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 24, v0		; GFX6-NEXT: s_movk_i32 s4, 0xff
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v1		; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
; GFX6-NEXT: v_min_u32_e32 v1, v0, v1		; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
		; GFX6-NEXT: v_max_u32_e32 v0, v0, v1
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1		; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v0, 24, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]		; GFX6-NEXT: s_setpc_b64 s[30:31]
;		;
; GFX8-LABEL: v_usubsat_i8:		; GFX8-LABEL: v_usubsat_i8:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshlrev_b16_e32 v0, 8, v0		; GFX8-NEXT: v_lshlrev_b16_e32 v0, 8, v0
; GFX8-NEXT: v_lshlrev_b16_e32 v1, 8, v1		; GFX8-NEXT: v_lshlrev_b16_e32 v1, 8, v1
; GFX8-NEXT: v_sub_u16_e64 v0, v0, v1 clamp		; GFX8-NEXT: v_sub_u16_e64 v0, v0, v1 clamp
Show All 21 Lines
; GFX10-NEXT: s_setpc_b64 s[30:31]		; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call i8 @llvm.usub.sat.i8(i8 %lhs, i8 %rhs)		%result = call i8 @llvm.usub.sat.i8(i8 %lhs, i8 %rhs)
ret i8 %result		ret i8 %result
}		}

define amdgpu_ps i8 @s_usubsat_i8(i8 inreg %lhs, i8 inreg %rhs) {		define amdgpu_ps i8 @s_usubsat_i8(i8 inreg %lhs, i8 inreg %rhs) {
; GFX6-LABEL: s_usubsat_i8:		; GFX6-LABEL: s_usubsat_i8:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 24		; GFX6-NEXT: s_movk_i32 s2, 0xff
; GFX6-NEXT: s_lshl_b32 s1, s1, 24		; GFX6-NEXT: s_and_b32 s0, s0, s2
; GFX6-NEXT: s_cmp_lt_u32 s0, s1		; GFX6-NEXT: s_and_b32 s1, s1, s2
; GFX6-NEXT: s_cselect_b32 s1, s0, s1		; GFX6-NEXT: s_cmp_gt_u32 s0, s1
		; GFX6-NEXT: s_cselect_b32 s0, s0, s1
; GFX6-NEXT: s_sub_i32 s0, s0, s1		; GFX6-NEXT: s_sub_i32 s0, s0, s1
; GFX6-NEXT: s_lshr_b32 s0, s0, 24
; GFX6-NEXT: ; return to shader part epilog		; GFX6-NEXT: ; return to shader part epilog
;		;
; GFX8-LABEL: s_usubsat_i8:		; GFX8-LABEL: s_usubsat_i8:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_bfe_u32 s2, 8, 0x100000		; GFX8-NEXT: s_bfe_u32 s2, 8, 0x100000
; GFX8-NEXT: s_lshl_b32 s1, s1, s2		; GFX8-NEXT: s_lshl_b32 s1, s1, s2
; GFX8-NEXT: s_lshl_b32 s0, s0, s2		; GFX8-NEXT: s_lshl_b32 s0, s0, s2
; GFX8-NEXT: v_mov_b32_e32 v0, s1		; GFX8-NEXT: v_mov_b32_e32 v0, s1
Show All 26 Lines	; GFX10-NEXT: ; return to shader part epilog
%result = call i8 @llvm.usub.sat.i8(i8 %lhs, i8 %rhs)		%result = call i8 @llvm.usub.sat.i8(i8 %lhs, i8 %rhs)
ret i8 %result		ret i8 %result
}		}

define i16 @v_usubsat_v2i8(i16 %lhs.arg, i16 %rhs.arg) {		define i16 @v_usubsat_v2i8(i16 %lhs.arg, i16 %rhs.arg) {
; GFX6-LABEL: v_usubsat_v2i8:		; GFX6-LABEL: v_usubsat_v2i8:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
		; GFX6-NEXT: s_movk_i32 s4, 0xff
; GFX6-NEXT: v_lshrrev_b32_e32 v2, 8, v0		; GFX6-NEXT: v_lshrrev_b32_e32 v2, 8, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 8, v1		; GFX6-NEXT: v_lshrrev_b32_e32 v3, 8, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 24, v0		; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v1		; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
; GFX6-NEXT: v_min_u32_e32 v1, v0, v1		; GFX6-NEXT: v_max_u32_e32 v0, v0, v1
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1		; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v2		; GFX6-NEXT: v_and_b32_e32 v1, s4, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 24, v3		; GFX6-NEXT: v_and_b32_e32 v2, s4, v3
; GFX6-NEXT: v_min_u32_e32 v2, v1, v2		; GFX6-NEXT: v_max_u32_e32 v1, v1, v2
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v2		; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v2
; GFX6-NEXT: v_lshrrev_b32_e32 v1, 24, v1		; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
; GFX6-NEXT: v_mov_b32_e32 v2, 0xff		; GFX6-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v0, 24, v0
; GFX6-NEXT: v_and_b32_e32 v1, v1, v2
; GFX6-NEXT: v_and_b32_e32 v0, v0, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 8, v1		; GFX6-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1		; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]		; GFX6-NEXT: s_setpc_b64 s[30:31]
;		;
; GFX8-LABEL: v_usubsat_v2i8:		; GFX8-LABEL: v_usubsat_v2i8:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v2, 8		; GFX8-NEXT: v_mov_b32_e32 v2, 8
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines	; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i8> @llvm.usub.sat.v2i8(<2 x i8> %lhs, <2 x i8> %rhs)		%result = call <2 x i8> @llvm.usub.sat.v2i8(<2 x i8> %lhs, <2 x i8> %rhs)
%cast.result = bitcast <2 x i8> %result to i16		%cast.result = bitcast <2 x i8> %result to i16
ret i16 %cast.result		ret i16 %cast.result
}		}

define amdgpu_ps i16 @s_usubsat_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg) {		define amdgpu_ps i16 @s_usubsat_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg) {
; GFX6-LABEL: s_usubsat_v2i8:		; GFX6-LABEL: s_usubsat_v2i8:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
		; GFX6-NEXT: s_movk_i32 s4, 0xff
; GFX6-NEXT: s_lshr_b32 s2, s0, 8		; GFX6-NEXT: s_lshr_b32 s2, s0, 8
; GFX6-NEXT: s_lshr_b32 s3, s1, 8		; GFX6-NEXT: s_lshr_b32 s3, s1, 8
; GFX6-NEXT: s_lshl_b32 s0, s0, 24		; GFX6-NEXT: s_and_b32 s0, s0, s4
; GFX6-NEXT: s_lshl_b32 s1, s1, 24		; GFX6-NEXT: s_and_b32 s1, s1, s4
; GFX6-NEXT: s_cmp_lt_u32 s0, s1		; GFX6-NEXT: s_cmp_gt_u32 s0, s1
; GFX6-NEXT: s_cselect_b32 s1, s0, s1		; GFX6-NEXT: s_cselect_b32 s0, s0, s1
; GFX6-NEXT: s_sub_i32 s0, s0, s1		; GFX6-NEXT: s_sub_i32 s0, s0, s1
; GFX6-NEXT: s_lshl_b32 s1, s2, 24		; GFX6-NEXT: s_and_b32 s1, s2, s4
; GFX6-NEXT: s_lshr_b32 s0, s0, 24		; GFX6-NEXT: s_and_b32 s2, s3, s4
; GFX6-NEXT: s_lshl_b32 s2, s3, 24		; GFX6-NEXT: s_cmp_gt_u32 s1, s2
; GFX6-NEXT: s_cmp_lt_u32 s1, s2		; GFX6-NEXT: s_cselect_b32 s1, s1, s2
; GFX6-NEXT: s_cselect_b32 s2, s1, s2
; GFX6-NEXT: s_sub_i32 s1, s1, s2		; GFX6-NEXT: s_sub_i32 s1, s1, s2
; GFX6-NEXT: s_movk_i32 s2, 0xff		; GFX6-NEXT: s_and_b32 s1, s1, s4
; GFX6-NEXT: s_lshr_b32 s1, s1, 24		; GFX6-NEXT: s_and_b32 s0, s0, s4
; GFX6-NEXT: s_and_b32 s1, s1, s2
; GFX6-NEXT: s_and_b32 s0, s0, s2
; GFX6-NEXT: s_lshl_b32 s1, s1, 8		; GFX6-NEXT: s_lshl_b32 s1, s1, 8
; GFX6-NEXT: s_or_b32 s0, s0, s1		; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: ; return to shader part epilog		; GFX6-NEXT: ; return to shader part epilog
;		;
; GFX8-LABEL: s_usubsat_v2i8:		; GFX8-LABEL: s_usubsat_v2i8:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_bfe_u32 s4, 8, 0x100000		; GFX8-NEXT: s_bfe_u32 s4, 8, 0x100000
; GFX8-NEXT: s_lshr_b32 s3, s1, 8		; GFX8-NEXT: s_lshr_b32 s3, s1, 8
▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 Lines	; GFX10-NEXT: ; return to shader part epilog
%cast.result = bitcast <2 x i8> %result to i16		%cast.result = bitcast <2 x i8> %result to i16
ret i16 %cast.result		ret i16 %cast.result
}		}

define i32 @v_usubsat_v4i8(i32 %lhs.arg, i32 %rhs.arg) {		define i32 @v_usubsat_v4i8(i32 %lhs.arg, i32 %rhs.arg) {
; GFX6-LABEL: v_usubsat_v4i8:		; GFX6-LABEL: v_usubsat_v4i8:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
		; GFX6-NEXT: s_movk_i32 s4, 0xff
; GFX6-NEXT: v_lshrrev_b32_e32 v2, 8, v0		; GFX6-NEXT: v_lshrrev_b32_e32 v2, 8, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v0		; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v4, 24, v0		; GFX6-NEXT: v_lshrrev_b32_e32 v4, 24, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v5, 8, v1		; GFX6-NEXT: v_lshrrev_b32_e32 v5, 8, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v6, 16, v1		; GFX6-NEXT: v_lshrrev_b32_e32 v6, 16, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v7, 24, v1		; GFX6-NEXT: v_lshrrev_b32_e32 v7, 24, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 24, v0		; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v1		; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
; GFX6-NEXT: v_min_u32_e32 v1, v0, v1		; GFX6-NEXT: v_max_u32_e32 v0, v0, v1
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1		; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v2		; GFX6-NEXT: v_and_b32_e32 v1, s4, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 24, v5		; GFX6-NEXT: v_and_b32_e32 v2, s4, v5
; GFX6-NEXT: v_min_u32_e32 v2, v1, v2		; GFX6-NEXT: v_max_u32_e32 v1, v1, v2
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v2		; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 24, v3		; GFX6-NEXT: v_and_b32_e32 v2, s4, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 24, v6		; GFX6-NEXT: v_and_b32_e32 v3, s4, v6
; GFX6-NEXT: v_min_u32_e32 v3, v2, v3		; GFX6-NEXT: v_max_u32_e32 v2, v2, v3
; GFX6-NEXT: v_lshrrev_b32_e32 v1, 24, v1
; GFX6-NEXT: s_movk_i32 s4, 0xff
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v3
; GFX6-NEXT: v_lshrrev_b32_e32 v0, 24, v0
; GFX6-NEXT: v_and_b32_e32 v1, s4, v1		; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 24, v4		; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 24, v7		; GFX6-NEXT: v_and_b32_e32 v3, s4, v4
; GFX6-NEXT: v_min_u32_e32 v4, v3, v4		; GFX6-NEXT: v_and_b32_e32 v4, s4, v7
; GFX6-NEXT: v_lshrrev_b32_e32 v2, 24, v2
; GFX6-NEXT: v_and_b32_e32 v0, s4, v0		; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 8, v1		; GFX6-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, v3, v4		; GFX6-NEXT: v_max_u32_e32 v3, v3, v4
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1		; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: v_and_b32_e32 v1, s4, v2		; GFX6-NEXT: v_and_b32_e32 v1, s4, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1		; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 24, v3		; GFX6-NEXT: v_sub_i32_e32 v3, vcc, v3, v4
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1		; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: v_and_b32_e32 v1, s4, v3		; GFX6-NEXT: v_and_b32_e32 v1, 0xff, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v1		; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1		; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]		; GFX6-NEXT: s_setpc_b64 s[30:31]
;		;
; GFX8-LABEL: v_usubsat_v4i8:		; GFX8-LABEL: v_usubsat_v4i8:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v2, 8		; GFX8-NEXT: v_mov_b32_e32 v2, 8
▲ Show 20 Lines • Show All 100 Lines • ▼ Show 20 Lines	; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <4 x i8> @llvm.usub.sat.v4i8(<4 x i8> %lhs, <4 x i8> %rhs)		%result = call <4 x i8> @llvm.usub.sat.v4i8(<4 x i8> %lhs, <4 x i8> %rhs)
%cast.result = bitcast <4 x i8> %result to i32		%cast.result = bitcast <4 x i8> %result to i32
ret i32 %cast.result		ret i32 %cast.result
}		}

define amdgpu_ps i32 @s_usubsat_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg) {		define amdgpu_ps i32 @s_usubsat_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg) {
; GFX6-LABEL: s_usubsat_v4i8:		; GFX6-LABEL: s_usubsat_v4i8:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
		; GFX6-NEXT: s_movk_i32 s8, 0xff
; GFX6-NEXT: s_lshr_b32 s2, s0, 8		; GFX6-NEXT: s_lshr_b32 s2, s0, 8
; GFX6-NEXT: s_lshr_b32 s3, s0, 16		; GFX6-NEXT: s_lshr_b32 s3, s0, 16
; GFX6-NEXT: s_lshr_b32 s4, s0, 24		; GFX6-NEXT: s_lshr_b32 s4, s0, 24
; GFX6-NEXT: s_lshr_b32 s5, s1, 8		; GFX6-NEXT: s_lshr_b32 s5, s1, 8
; GFX6-NEXT: s_lshr_b32 s6, s1, 16		; GFX6-NEXT: s_lshr_b32 s6, s1, 16
; GFX6-NEXT: s_lshr_b32 s7, s1, 24		; GFX6-NEXT: s_lshr_b32 s7, s1, 24
; GFX6-NEXT: s_lshl_b32 s0, s0, 24		; GFX6-NEXT: s_and_b32 s0, s0, s8
; GFX6-NEXT: s_lshl_b32 s1, s1, 24		; GFX6-NEXT: s_and_b32 s1, s1, s8
; GFX6-NEXT: s_cmp_lt_u32 s0, s1		; GFX6-NEXT: s_cmp_gt_u32 s0, s1
; GFX6-NEXT: s_cselect_b32 s1, s0, s1		; GFX6-NEXT: s_cselect_b32 s0, s0, s1
; GFX6-NEXT: s_sub_i32 s0, s0, s1		; GFX6-NEXT: s_sub_i32 s0, s0, s1
; GFX6-NEXT: s_lshl_b32 s1, s2, 24		; GFX6-NEXT: s_and_b32 s1, s2, s8
; GFX6-NEXT: s_lshr_b32 s0, s0, 24		; GFX6-NEXT: s_and_b32 s2, s5, s8
; GFX6-NEXT: s_lshl_b32 s2, s5, 24		; GFX6-NEXT: s_cmp_gt_u32 s1, s2
; GFX6-NEXT: s_cmp_lt_u32 s1, s2		; GFX6-NEXT: s_cselect_b32 s1, s1, s2
; GFX6-NEXT: s_cselect_b32 s2, s1, s2
; GFX6-NEXT: s_sub_i32 s1, s1, s2		; GFX6-NEXT: s_sub_i32 s1, s1, s2
; GFX6-NEXT: s_lshl_b32 s2, s3, 24		; GFX6-NEXT: s_and_b32 s2, s3, s8
; GFX6-NEXT: s_lshr_b32 s1, s1, 24		; GFX6-NEXT: s_and_b32 s3, s6, s8
; GFX6-NEXT: s_lshl_b32 s3, s6, 24		; GFX6-NEXT: s_cmp_gt_u32 s2, s3
; GFX6-NEXT: s_cmp_lt_u32 s2, s3		; GFX6-NEXT: s_cselect_b32 s2, s2, s3
; GFX6-NEXT: s_cselect_b32 s3, s2, s3
; GFX6-NEXT: s_sub_i32 s2, s2, s3		; GFX6-NEXT: s_sub_i32 s2, s2, s3
; GFX6-NEXT: s_lshl_b32 s3, s4, 24		; GFX6-NEXT: s_and_b32 s3, s4, s8
; GFX6-NEXT: s_lshr_b32 s2, s2, 24		; GFX6-NEXT: s_and_b32 s4, s7, s8
; GFX6-NEXT: s_lshl_b32 s4, s7, 24		; GFX6-NEXT: s_cmp_gt_u32 s3, s4
; GFX6-NEXT: s_cmp_lt_u32 s3, s4		; GFX6-NEXT: s_cselect_b32 s3, s3, s4
; GFX6-NEXT: s_cselect_b32 s4, s3, s4		; GFX6-NEXT: s_and_b32 s1, s1, s8
; GFX6-NEXT: s_sub_i32 s3, s3, s4		; GFX6-NEXT: s_and_b32 s0, s0, s8
; GFX6-NEXT: s_movk_i32 s4, 0xff
; GFX6-NEXT: s_and_b32 s1, s1, s4
; GFX6-NEXT: s_and_b32 s0, s0, s4
; GFX6-NEXT: s_lshl_b32 s1, s1, 8		; GFX6-NEXT: s_lshl_b32 s1, s1, 8
; GFX6-NEXT: s_or_b32 s0, s0, s1		; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: s_and_b32 s1, s2, s4		; GFX6-NEXT: s_and_b32 s1, s2, s8
; GFX6-NEXT: s_lshl_b32 s1, s1, 16		; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_lshr_b32 s3, s3, 24		; GFX6-NEXT: s_sub_i32 s3, s3, s4
; GFX6-NEXT: s_or_b32 s0, s0, s1		; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: s_and_b32 s1, s3, s4		; GFX6-NEXT: s_and_b32 s1, s3, s8
; GFX6-NEXT: s_lshl_b32 s1, s1, 24		; GFX6-NEXT: s_lshl_b32 s1, s1, 24
; GFX6-NEXT: s_or_b32 s0, s0, s1		; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: ; return to shader part epilog		; GFX6-NEXT: ; return to shader part epilog
;		;
; GFX8-LABEL: s_usubsat_v4i8:		; GFX8-LABEL: s_usubsat_v4i8:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_bfe_u32 s8, 8, 0x100000		; GFX8-NEXT: s_bfe_u32 s8, 8, 0x100000
; GFX8-NEXT: s_lshr_b32 s5, s1, 8		; GFX8-NEXT: s_lshr_b32 s5, s1, 8
▲ Show 20 Lines • Show All 126 Lines • ▼ Show 20 Lines	; GFX10-NEXT: ; return to shader part epilog
%cast.result = bitcast <4 x i8> %result to i32		%cast.result = bitcast <4 x i8> %result to i32
ret i32 %cast.result		ret i32 %cast.result
}		}

define i24 @v_usubsat_i24(i24 %lhs, i24 %rhs) {		define i24 @v_usubsat_i24(i24 %lhs, i24 %rhs) {
; GFX6-LABEL: v_usubsat_i24:		; GFX6-LABEL: v_usubsat_i24:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 8, v0		; GFX6-NEXT: s_mov_b32 s4, 0xffffff
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 8, v1		; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
; GFX6-NEXT: v_min_u32_e32 v1, v0, v1		; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
		; GFX6-NEXT: v_max_u32_e32 v0, v0, v1
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1		; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v0, 8, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]		; GFX6-NEXT: s_setpc_b64 s[30:31]
;		;
; GFX8-LABEL: v_usubsat_i24:		; GFX8-LABEL: v_usubsat_i24:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshlrev_b32_e32 v0, 8, v0		; GFX8-NEXT: v_lshlrev_b32_e32 v0, 8, v0
; GFX8-NEXT: v_lshlrev_b32_e32 v1, 8, v1		; GFX8-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX8-NEXT: v_sub_u32_e64 v0, s[4:5], v0, v1 clamp		; GFX8-NEXT: v_sub_u32_e64 v0, s[4:5], v0, v1 clamp
Show All 21 Lines
; GFX10-NEXT: s_setpc_b64 s[30:31]		; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call i24 @llvm.usub.sat.i24(i24 %lhs, i24 %rhs)		%result = call i24 @llvm.usub.sat.i24(i24 %lhs, i24 %rhs)
ret i24 %result		ret i24 %result
}		}

define amdgpu_ps i24 @s_usubsat_i24(i24 inreg %lhs, i24 inreg %rhs) {		define amdgpu_ps i24 @s_usubsat_i24(i24 inreg %lhs, i24 inreg %rhs) {
; GFX6-LABEL: s_usubsat_i24:		; GFX6-LABEL: s_usubsat_i24:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 8		; GFX6-NEXT: s_mov_b32 s2, 0xffffff
; GFX6-NEXT: s_lshl_b32 s1, s1, 8		; GFX6-NEXT: s_and_b32 s0, s0, s2
; GFX6-NEXT: s_cmp_lt_u32 s0, s1		; GFX6-NEXT: s_and_b32 s1, s1, s2
; GFX6-NEXT: s_cselect_b32 s1, s0, s1		; GFX6-NEXT: s_cmp_gt_u32 s0, s1
		; GFX6-NEXT: s_cselect_b32 s0, s0, s1
; GFX6-NEXT: s_sub_i32 s0, s0, s1		; GFX6-NEXT: s_sub_i32 s0, s0, s1
; GFX6-NEXT: s_lshr_b32 s0, s0, 8
; GFX6-NEXT: ; return to shader part epilog		; GFX6-NEXT: ; return to shader part epilog
;		;
; GFX8-LABEL: s_usubsat_i24:		; GFX8-LABEL: s_usubsat_i24:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_lshl_b32 s1, s1, 8		; GFX8-NEXT: s_lshl_b32 s1, s1, 8
; GFX8-NEXT: s_lshl_b32 s0, s0, 8		; GFX8-NEXT: s_lshl_b32 s0, s0, 8
; GFX8-NEXT: v_mov_b32_e32 v0, s1		; GFX8-NEXT: v_mov_b32_e32 v0, s1
; GFX8-NEXT: v_sub_u32_e64 v0, s[0:1], s0, v0 clamp		; GFX8-NEXT: v_sub_u32_e64 v0, s[0:1], s0, v0 clamp
Show All 23 Lines	; GFX10-NEXT: ; return to shader part epilog
%result = call i24 @llvm.usub.sat.i24(i24 %lhs, i24 %rhs)		%result = call i24 @llvm.usub.sat.i24(i24 %lhs, i24 %rhs)
ret i24 %result		ret i24 %result
}		}

define i32 @v_usubsat_i32(i32 %lhs, i32 %rhs) {		define i32 @v_usubsat_i32(i32 %lhs, i32 %rhs) {
; GFX6-LABEL: v_usubsat_i32:		; GFX6-LABEL: v_usubsat_i32:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_min_u32_e32 v1, v0, v1		; GFX6-NEXT: v_max_u32_e32 v0, v0, v1
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1		; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]		; GFX6-NEXT: s_setpc_b64 s[30:31]
;		;
; GFX8-LABEL: v_usubsat_i32:		; GFX8-LABEL: v_usubsat_i32:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_sub_u32_e64 v0, s[4:5], v0, v1 clamp		; GFX8-NEXT: v_sub_u32_e64 v0, s[4:5], v0, v1 clamp
; GFX8-NEXT: s_setpc_b64 s[30:31]		; GFX8-NEXT: s_setpc_b64 s[30:31]
Show All 13 Lines
; GFX10-NEXT: s_setpc_b64 s[30:31]		; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call i32 @llvm.usub.sat.i32(i32 %lhs, i32 %rhs)		%result = call i32 @llvm.usub.sat.i32(i32 %lhs, i32 %rhs)
ret i32 %result		ret i32 %result
}		}

define amdgpu_ps i32 @s_usubsat_i32(i32 inreg %lhs, i32 inreg %rhs) {		define amdgpu_ps i32 @s_usubsat_i32(i32 inreg %lhs, i32 inreg %rhs) {
; GFX6-LABEL: s_usubsat_i32:		; GFX6-LABEL: s_usubsat_i32:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_cmp_lt_u32 s0, s1		; GFX6-NEXT: s_cmp_gt_u32 s0, s1
; GFX6-NEXT: s_cselect_b32 s1, s0, s1		; GFX6-NEXT: s_cselect_b32 s0, s0, s1
; GFX6-NEXT: s_sub_i32 s0, s0, s1		; GFX6-NEXT: s_sub_i32 s0, s0, s1
; GFX6-NEXT: ; return to shader part epilog		; GFX6-NEXT: ; return to shader part epilog
;		;
; GFX8-LABEL: s_usubsat_i32:		; GFX8-LABEL: s_usubsat_i32:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: v_mov_b32_e32 v0, s1		; GFX8-NEXT: v_mov_b32_e32 v0, s1
; GFX8-NEXT: v_sub_u32_e64 v0, s[0:1], s0, v0 clamp		; GFX8-NEXT: v_sub_u32_e64 v0, s[0:1], s0, v0 clamp
; GFX8-NEXT: v_readfirstlane_b32 s0, v0		; GFX8-NEXT: v_readfirstlane_b32 s0, v0
Show All 14 Lines
; GFX10-NEXT: ; return to shader part epilog		; GFX10-NEXT: ; return to shader part epilog
%result = call i32 @llvm.usub.sat.i32(i32 %lhs, i32 %rhs)		%result = call i32 @llvm.usub.sat.i32(i32 %lhs, i32 %rhs)
ret i32 %result		ret i32 %result
}		}

define amdgpu_ps float @usubsat_i32_sv(i32 inreg %lhs, i32 %rhs) {		define amdgpu_ps float @usubsat_i32_sv(i32 inreg %lhs, i32 %rhs) {
; GFX6-LABEL: usubsat_i32_sv:		; GFX6-LABEL: usubsat_i32_sv:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: v_min_u32_e32 v0, s0, v0		; GFX6-NEXT: v_max_u32_e32 v1, s0, v0
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s0, v0		; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v1, v0
; GFX6-NEXT: ; return to shader part epilog		; GFX6-NEXT: ; return to shader part epilog
;		;
; GFX8-LABEL: usubsat_i32_sv:		; GFX8-LABEL: usubsat_i32_sv:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: v_sub_u32_e64 v0, s[0:1], s0, v0 clamp		; GFX8-NEXT: v_sub_u32_e64 v0, s[0:1], s0, v0 clamp
; GFX8-NEXT: ; return to shader part epilog		; GFX8-NEXT: ; return to shader part epilog
;		;
; GFX9-LABEL: usubsat_i32_sv:		; GFX9-LABEL: usubsat_i32_sv:
Show All 9 Lines	; GFX10-NEXT: ; return to shader part epilog
%result = call i32 @llvm.usub.sat.i32(i32 %lhs, i32 %rhs)		%result = call i32 @llvm.usub.sat.i32(i32 %lhs, i32 %rhs)
%cast = bitcast i32 %result to float		%cast = bitcast i32 %result to float
ret float %cast		ret float %cast
}		}

define amdgpu_ps float @usubsat_i32_vs(i32 %lhs, i32 inreg %rhs) {		define amdgpu_ps float @usubsat_i32_vs(i32 %lhs, i32 inreg %rhs) {
; GFX6-LABEL: usubsat_i32_vs:		; GFX6-LABEL: usubsat_i32_vs:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: v_min_u32_e32 v1, s0, v0		; GFX6-NEXT: v_max_u32_e32 v0, s0, v0
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1		; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s0, v0
; GFX6-NEXT: ; return to shader part epilog		; GFX6-NEXT: ; return to shader part epilog
;		;
; GFX8-LABEL: usubsat_i32_vs:		; GFX8-LABEL: usubsat_i32_vs:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: v_sub_u32_e64 v0, s[0:1], v0, s0 clamp		; GFX8-NEXT: v_sub_u32_e64 v0, s[0:1], v0, s0 clamp
; GFX8-NEXT: ; return to shader part epilog		; GFX8-NEXT: ; return to shader part epilog
;		;
; GFX9-LABEL: usubsat_i32_vs:		; GFX9-LABEL: usubsat_i32_vs:
Show All 10 Lines	; GFX10-NEXT: ; return to shader part epilog
%cast = bitcast i32 %result to float		%cast = bitcast i32 %result to float
ret float %cast		ret float %cast
}		}

define <2 x i32> @v_usubsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {		define <2 x i32> @v_usubsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
; GFX6-LABEL: v_usubsat_v2i32:		; GFX6-LABEL: v_usubsat_v2i32:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_min_u32_e32 v2, v0, v2		; GFX6-NEXT: v_max_u32_e32 v0, v0, v2
		; GFX6-NEXT: v_max_u32_e32 v1, v1, v3
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v2		; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
; GFX6-NEXT: v_min_u32_e32 v2, v1, v3		; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v3
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v2
; GFX6-NEXT: s_setpc_b64 s[30:31]		; GFX6-NEXT: s_setpc_b64 s[30:31]
;		;
; GFX8-LABEL: v_usubsat_v2i32:		; GFX8-LABEL: v_usubsat_v2i32:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_sub_u32_e64 v0, s[4:5], v0, v2 clamp		; GFX8-NEXT: v_sub_u32_e64 v0, s[4:5], v0, v2 clamp
; GFX8-NEXT: v_sub_u32_e64 v1, s[4:5], v1, v3 clamp		; GFX8-NEXT: v_sub_u32_e64 v1, s[4:5], v1, v3 clamp
; GFX8-NEXT: s_setpc_b64 s[30:31]		; GFX8-NEXT: s_setpc_b64 s[30:31]
Show All 15 Lines
; GFX10-NEXT: s_setpc_b64 s[30:31]		; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i32> @llvm.usub.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)		%result = call <2 x i32> @llvm.usub.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
ret <2 x i32> %result		ret <2 x i32> %result
}		}

define amdgpu_ps <2 x i32> @s_usubsat_v2i32(<2 x i32> inreg %lhs, <2 x i32> inreg %rhs) {		define amdgpu_ps <2 x i32> @s_usubsat_v2i32(<2 x i32> inreg %lhs, <2 x i32> inreg %rhs) {
; GFX6-LABEL: s_usubsat_v2i32:		; GFX6-LABEL: s_usubsat_v2i32:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_cmp_lt_u32 s0, s2		; GFX6-NEXT: s_cmp_gt_u32 s0, s2
; GFX6-NEXT: s_cselect_b32 s2, s0, s2		; GFX6-NEXT: s_cselect_b32 s0, s0, s2
; GFX6-NEXT: s_sub_i32 s0, s0, s2		; GFX6-NEXT: s_sub_i32 s0, s0, s2
; GFX6-NEXT: s_cmp_lt_u32 s1, s3		; GFX6-NEXT: s_cmp_gt_u32 s1, s3
; GFX6-NEXT: s_cselect_b32 s2, s1, s3		; GFX6-NEXT: s_cselect_b32 s1, s1, s3
; GFX6-NEXT: s_sub_i32 s1, s1, s2		; GFX6-NEXT: s_sub_i32 s1, s1, s3
; GFX6-NEXT: ; return to shader part epilog		; GFX6-NEXT: ; return to shader part epilog
;		;
; GFX8-LABEL: s_usubsat_v2i32:		; GFX8-LABEL: s_usubsat_v2i32:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: v_mov_b32_e32 v0, s2		; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v1, s3		; GFX8-NEXT: v_mov_b32_e32 v1, s3
; GFX8-NEXT: v_sub_u32_e64 v0, s[4:5], s0, v0 clamp		; GFX8-NEXT: v_sub_u32_e64 v0, s[4:5], s0, v0 clamp
; GFX8-NEXT: v_sub_u32_e64 v1, s[0:1], s1, v1 clamp		; GFX8-NEXT: v_sub_u32_e64 v1, s[0:1], s1, v1 clamp
Show All 22 Lines	; GFX10-NEXT: ; return to shader part epilog
%result = call <2 x i32> @llvm.usub.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)		%result = call <2 x i32> @llvm.usub.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
ret <2 x i32> %result		ret <2 x i32> %result
}		}

define <3 x i32> @v_usubsat_v3i32(<3 x i32> %lhs, <3 x i32> %rhs) {		define <3 x i32> @v_usubsat_v3i32(<3 x i32> %lhs, <3 x i32> %rhs) {
; GFX6-LABEL: v_usubsat_v3i32:		; GFX6-LABEL: v_usubsat_v3i32:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_min_u32_e32 v3, v0, v3		; GFX6-NEXT: v_max_u32_e32 v0, v0, v3
		; GFX6-NEXT: v_max_u32_e32 v1, v1, v4
		; GFX6-NEXT: v_max_u32_e32 v2, v2, v5
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v3		; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v3
; GFX6-NEXT: v_min_u32_e32 v3, v1, v4		; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v4
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v3		; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v5
; GFX6-NEXT: v_min_u32_e32 v3, v2, v5
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v3
; GFX6-NEXT: s_setpc_b64 s[30:31]		; GFX6-NEXT: s_setpc_b64 s[30:31]
;		;
; GFX8-LABEL: v_usubsat_v3i32:		; GFX8-LABEL: v_usubsat_v3i32:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_sub_u32_e64 v0, s[4:5], v0, v3 clamp		; GFX8-NEXT: v_sub_u32_e64 v0, s[4:5], v0, v3 clamp
; GFX8-NEXT: v_sub_u32_e64 v1, s[4:5], v1, v4 clamp		; GFX8-NEXT: v_sub_u32_e64 v1, s[4:5], v1, v4 clamp
; GFX8-NEXT: v_sub_u32_e64 v2, s[4:5], v2, v5 clamp		; GFX8-NEXT: v_sub_u32_e64 v2, s[4:5], v2, v5 clamp
Show All 18 Lines
; GFX10-NEXT: s_setpc_b64 s[30:31]		; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <3 x i32> @llvm.usub.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs)		%result = call <3 x i32> @llvm.usub.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs)
ret <3 x i32> %result		ret <3 x i32> %result
}		}

define amdgpu_ps <3 x i32> @s_usubsat_v3i32(<3 x i32> inreg %lhs, <3 x i32> inreg %rhs) {		define amdgpu_ps <3 x i32> @s_usubsat_v3i32(<3 x i32> inreg %lhs, <3 x i32> inreg %rhs) {
; GFX6-LABEL: s_usubsat_v3i32:		; GFX6-LABEL: s_usubsat_v3i32:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_cmp_lt_u32 s0, s3		; GFX6-NEXT: s_cmp_gt_u32 s0, s3
; GFX6-NEXT: s_cselect_b32 s3, s0, s3		; GFX6-NEXT: s_cselect_b32 s0, s0, s3
; GFX6-NEXT: s_sub_i32 s0, s0, s3		; GFX6-NEXT: s_sub_i32 s0, s0, s3
; GFX6-NEXT: s_cmp_lt_u32 s1, s4		; GFX6-NEXT: s_cmp_gt_u32 s1, s4
; GFX6-NEXT: s_cselect_b32 s3, s1, s4		; GFX6-NEXT: s_cselect_b32 s1, s1, s4
; GFX6-NEXT: s_sub_i32 s1, s1, s3		; GFX6-NEXT: s_sub_i32 s1, s1, s4
; GFX6-NEXT: s_cmp_lt_u32 s2, s5		; GFX6-NEXT: s_cmp_gt_u32 s2, s5
; GFX6-NEXT: s_cselect_b32 s3, s2, s5		; GFX6-NEXT: s_cselect_b32 s2, s2, s5
; GFX6-NEXT: s_sub_i32 s2, s2, s3		; GFX6-NEXT: s_sub_i32 s2, s2, s5
; GFX6-NEXT: ; return to shader part epilog		; GFX6-NEXT: ; return to shader part epilog
;		;
; GFX8-LABEL: s_usubsat_v3i32:		; GFX8-LABEL: s_usubsat_v3i32:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: v_mov_b32_e32 v0, s3		; GFX8-NEXT: v_mov_b32_e32 v0, s3
; GFX8-NEXT: v_mov_b32_e32 v1, s4		; GFX8-NEXT: v_mov_b32_e32 v1, s4
; GFX8-NEXT: v_mov_b32_e32 v2, s5		; GFX8-NEXT: v_mov_b32_e32 v2, s5
; GFX8-NEXT: v_sub_u32_e64 v0, s[6:7], s0, v0 clamp		; GFX8-NEXT: v_sub_u32_e64 v0, s[6:7], s0, v0 clamp
Show All 30 Lines	; GFX10-NEXT: ; return to shader part epilog
%result = call <3 x i32> @llvm.usub.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs)		%result = call <3 x i32> @llvm.usub.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs)
ret <3 x i32> %result		ret <3 x i32> %result
}		}

define <4 x i32> @v_usubsat_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {		define <4 x i32> @v_usubsat_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
; GFX6-LABEL: v_usubsat_v4i32:		; GFX6-LABEL: v_usubsat_v4i32:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_min_u32_e32 v4, v0, v4		; GFX6-NEXT: v_max_u32_e32 v0, v0, v4
		; GFX6-NEXT: v_max_u32_e32 v1, v1, v5
		; GFX6-NEXT: v_max_u32_e32 v2, v2, v6
		; GFX6-NEXT: v_max_u32_e32 v3, v3, v7
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v4		; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v4
; GFX6-NEXT: v_min_u32_e32 v4, v1, v5		; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v5
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v4		; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v6
; GFX6-NEXT: v_min_u32_e32 v4, v2, v6		; GFX6-NEXT: v_sub_i32_e32 v3, vcc, v3, v7
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v4
; GFX6-NEXT: v_min_u32_e32 v4, v3, v7
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, v3, v4
; GFX6-NEXT: s_setpc_b64 s[30:31]		; GFX6-NEXT: s_setpc_b64 s[30:31]
;		;
; GFX8-LABEL: v_usubsat_v4i32:		; GFX8-LABEL: v_usubsat_v4i32:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_sub_u32_e64 v0, s[4:5], v0, v4 clamp		; GFX8-NEXT: v_sub_u32_e64 v0, s[4:5], v0, v4 clamp
; GFX8-NEXT: v_sub_u32_e64 v1, s[4:5], v1, v5 clamp		; GFX8-NEXT: v_sub_u32_e64 v1, s[4:5], v1, v5 clamp
; GFX8-NEXT: v_sub_u32_e64 v2, s[4:5], v2, v6 clamp		; GFX8-NEXT: v_sub_u32_e64 v2, s[4:5], v2, v6 clamp
Show All 21 Lines
; GFX10-NEXT: s_setpc_b64 s[30:31]		; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)		%result = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
ret <4 x i32> %result		ret <4 x i32> %result
}		}

define amdgpu_ps <4 x i32> @s_usubsat_v4i32(<4 x i32> inreg %lhs, <4 x i32> inreg %rhs) {		define amdgpu_ps <4 x i32> @s_usubsat_v4i32(<4 x i32> inreg %lhs, <4 x i32> inreg %rhs) {
; GFX6-LABEL: s_usubsat_v4i32:		; GFX6-LABEL: s_usubsat_v4i32:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_cmp_lt_u32 s0, s4		; GFX6-NEXT: s_cmp_gt_u32 s0, s4
; GFX6-NEXT: s_cselect_b32 s4, s0, s4		; GFX6-NEXT: s_cselect_b32 s0, s0, s4
; GFX6-NEXT: s_sub_i32 s0, s0, s4		; GFX6-NEXT: s_sub_i32 s0, s0, s4
; GFX6-NEXT: s_cmp_lt_u32 s1, s5		; GFX6-NEXT: s_cmp_gt_u32 s1, s5
; GFX6-NEXT: s_cselect_b32 s4, s1, s5		; GFX6-NEXT: s_cselect_b32 s1, s1, s5
; GFX6-NEXT: s_sub_i32 s1, s1, s4		; GFX6-NEXT: s_sub_i32 s1, s1, s5
; GFX6-NEXT: s_cmp_lt_u32 s2, s6		; GFX6-NEXT: s_cmp_gt_u32 s2, s6
; GFX6-NEXT: s_cselect_b32 s4, s2, s6		; GFX6-NEXT: s_cselect_b32 s2, s2, s6
; GFX6-NEXT: s_sub_i32 s2, s2, s4		; GFX6-NEXT: s_sub_i32 s2, s2, s6
; GFX6-NEXT: s_cmp_lt_u32 s3, s7		; GFX6-NEXT: s_cmp_gt_u32 s3, s7
; GFX6-NEXT: s_cselect_b32 s4, s3, s7		; GFX6-NEXT: s_cselect_b32 s3, s3, s7
; GFX6-NEXT: s_sub_i32 s3, s3, s4		; GFX6-NEXT: s_sub_i32 s3, s3, s7
; GFX6-NEXT: ; return to shader part epilog		; GFX6-NEXT: ; return to shader part epilog
;		;
; GFX8-LABEL: s_usubsat_v4i32:		; GFX8-LABEL: s_usubsat_v4i32:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: v_mov_b32_e32 v0, s4		; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_mov_b32_e32 v1, s5		; GFX8-NEXT: v_mov_b32_e32 v1, s5
; GFX8-NEXT: v_mov_b32_e32 v2, s6		; GFX8-NEXT: v_mov_b32_e32 v2, s6
; GFX8-NEXT: v_mov_b32_e32 v3, s7		; GFX8-NEXT: v_mov_b32_e32 v3, s7
Show All 38 Lines	; GFX10-NEXT: ; return to shader part epilog
%result = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)		%result = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
ret <4 x i32> %result		ret <4 x i32> %result
}		}

define <5 x i32> @v_usubsat_v5i32(<5 x i32> %lhs, <5 x i32> %rhs) {		define <5 x i32> @v_usubsat_v5i32(<5 x i32> %lhs, <5 x i32> %rhs) {
; GFX6-LABEL: v_usubsat_v5i32:		; GFX6-LABEL: v_usubsat_v5i32:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_min_u32_e32 v5, v0, v5		; GFX6-NEXT: v_max_u32_e32 v0, v0, v5
		; GFX6-NEXT: v_max_u32_e32 v1, v1, v6
		; GFX6-NEXT: v_max_u32_e32 v2, v2, v7
		; GFX6-NEXT: v_max_u32_e32 v3, v3, v8
		; GFX6-NEXT: v_max_u32_e32 v4, v4, v9
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v5		; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v5
; GFX6-NEXT: v_min_u32_e32 v5, v1, v6		; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v6
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v5		; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v7
; GFX6-NEXT: v_min_u32_e32 v5, v2, v7		; GFX6-NEXT: v_sub_i32_e32 v3, vcc, v3, v8
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v5		; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v4, v9
; GFX6-NEXT: v_min_u32_e32 v5, v3, v8
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, v3, v5
; GFX6-NEXT: v_min_u32_e32 v5, v4, v9
; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v4, v5
; GFX6-NEXT: s_setpc_b64 s[30:31]		; GFX6-NEXT: s_setpc_b64 s[30:31]
;		;
; GFX8-LABEL: v_usubsat_v5i32:		; GFX8-LABEL: v_usubsat_v5i32:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_sub_u32_e64 v0, s[4:5], v0, v5 clamp		; GFX8-NEXT: v_sub_u32_e64 v0, s[4:5], v0, v5 clamp
; GFX8-NEXT: v_sub_u32_e64 v1, s[4:5], v1, v6 clamp		; GFX8-NEXT: v_sub_u32_e64 v1, s[4:5], v1, v6 clamp
; GFX8-NEXT: v_sub_u32_e64 v2, s[4:5], v2, v7 clamp		; GFX8-NEXT: v_sub_u32_e64 v2, s[4:5], v2, v7 clamp
Show All 24 Lines
; GFX10-NEXT: s_setpc_b64 s[30:31]		; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <5 x i32> @llvm.usub.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs)		%result = call <5 x i32> @llvm.usub.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs)
ret <5 x i32> %result		ret <5 x i32> %result
}		}

define amdgpu_ps <5 x i32> @s_usubsat_v5i32(<5 x i32> inreg %lhs, <5 x i32> inreg %rhs) {		define amdgpu_ps <5 x i32> @s_usubsat_v5i32(<5 x i32> inreg %lhs, <5 x i32> inreg %rhs) {
; GFX6-LABEL: s_usubsat_v5i32:		; GFX6-LABEL: s_usubsat_v5i32:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_cmp_lt_u32 s0, s5		; GFX6-NEXT: s_cmp_gt_u32 s0, s5
; GFX6-NEXT: s_cselect_b32 s5, s0, s5		; GFX6-NEXT: s_cselect_b32 s0, s0, s5
; GFX6-NEXT: s_sub_i32 s0, s0, s5		; GFX6-NEXT: s_sub_i32 s0, s0, s5
; GFX6-NEXT: s_cmp_lt_u32 s1, s6		; GFX6-NEXT: s_cmp_gt_u32 s1, s6
; GFX6-NEXT: s_cselect_b32 s5, s1, s6		; GFX6-NEXT: s_cselect_b32 s1, s1, s6
; GFX6-NEXT: s_sub_i32 s1, s1, s5		; GFX6-NEXT: s_sub_i32 s1, s1, s6
; GFX6-NEXT: s_cmp_lt_u32 s2, s7		; GFX6-NEXT: s_cmp_gt_u32 s2, s7
; GFX6-NEXT: s_cselect_b32 s5, s2, s7		; GFX6-NEXT: s_cselect_b32 s2, s2, s7
; GFX6-NEXT: s_sub_i32 s2, s2, s5		; GFX6-NEXT: s_sub_i32 s2, s2, s7
; GFX6-NEXT: s_cmp_lt_u32 s3, s8		; GFX6-NEXT: s_cmp_gt_u32 s3, s8
; GFX6-NEXT: s_cselect_b32 s5, s3, s8		; GFX6-NEXT: s_cselect_b32 s3, s3, s8
; GFX6-NEXT: s_sub_i32 s3, s3, s5		; GFX6-NEXT: s_sub_i32 s3, s3, s8
; GFX6-NEXT: s_cmp_lt_u32 s4, s9		; GFX6-NEXT: s_cmp_gt_u32 s4, s9
; GFX6-NEXT: s_cselect_b32 s5, s4, s9		; GFX6-NEXT: s_cselect_b32 s4, s4, s9
; GFX6-NEXT: s_sub_i32 s4, s4, s5		; GFX6-NEXT: s_sub_i32 s4, s4, s9
; GFX6-NEXT: ; return to shader part epilog		; GFX6-NEXT: ; return to shader part epilog
;		;
; GFX8-LABEL: s_usubsat_v5i32:		; GFX8-LABEL: s_usubsat_v5i32:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: v_mov_b32_e32 v0, s5		; GFX8-NEXT: v_mov_b32_e32 v0, s5
; GFX8-NEXT: v_mov_b32_e32 v1, s6		; GFX8-NEXT: v_mov_b32_e32 v1, s6
; GFX8-NEXT: v_mov_b32_e32 v2, s7		; GFX8-NEXT: v_mov_b32_e32 v2, s7
; GFX8-NEXT: v_mov_b32_e32 v3, s8		; GFX8-NEXT: v_mov_b32_e32 v3, s8
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines	; GFX10-NEXT: ; return to shader part epilog
%result = call <5 x i32> @llvm.usub.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs)		%result = call <5 x i32> @llvm.usub.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs)
ret <5 x i32> %result		ret <5 x i32> %result
}		}

define <16 x i32> @v_usubsat_v16i32(<16 x i32> %lhs, <16 x i32> %rhs) {		define <16 x i32> @v_usubsat_v16i32(<16 x i32> %lhs, <16 x i32> %rhs) {
; GFX6-LABEL: v_usubsat_v16i32:		; GFX6-LABEL: v_usubsat_v16i32:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_min_u32_e32 v16, v0, v16		; GFX6-NEXT: v_max_u32_e32 v0, v0, v16
		; GFX6-NEXT: v_max_u32_e32 v1, v1, v17
		; GFX6-NEXT: v_max_u32_e32 v2, v2, v18
		; GFX6-NEXT: v_max_u32_e32 v3, v3, v19
		; GFX6-NEXT: v_max_u32_e32 v4, v4, v20
		; GFX6-NEXT: v_max_u32_e32 v5, v5, v21
		; GFX6-NEXT: v_max_u32_e32 v6, v6, v22
		; GFX6-NEXT: v_max_u32_e32 v7, v7, v23
		; GFX6-NEXT: v_max_u32_e32 v8, v8, v24
		; GFX6-NEXT: v_max_u32_e32 v9, v9, v25
		; GFX6-NEXT: v_max_u32_e32 v10, v10, v26
		; GFX6-NEXT: v_max_u32_e32 v11, v11, v27
		; GFX6-NEXT: v_max_u32_e32 v12, v12, v28
		; GFX6-NEXT: v_max_u32_e32 v13, v13, v29
		; GFX6-NEXT: v_max_u32_e32 v14, v14, v30
		; GFX6-NEXT: v_max_u32_e32 v15, v15, v31
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v16		; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v16
; GFX6-NEXT: v_min_u32_e32 v16, v1, v17		; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v17
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v16		; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v18
; GFX6-NEXT: v_min_u32_e32 v16, v2, v18		; GFX6-NEXT: v_sub_i32_e32 v3, vcc, v3, v19
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v16		; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v4, v20
; GFX6-NEXT: v_min_u32_e32 v16, v3, v19		; GFX6-NEXT: v_sub_i32_e32 v5, vcc, v5, v21
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, v3, v16		; GFX6-NEXT: v_sub_i32_e32 v6, vcc, v6, v22
; GFX6-NEXT: v_min_u32_e32 v16, v4, v20		; GFX6-NEXT: v_sub_i32_e32 v7, vcc, v7, v23
; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v4, v16		; GFX6-NEXT: v_sub_i32_e32 v8, vcc, v8, v24
; GFX6-NEXT: v_min_u32_e32 v16, v5, v21		; GFX6-NEXT: v_sub_i32_e32 v9, vcc, v9, v25
; GFX6-NEXT: v_sub_i32_e32 v5, vcc, v5, v16		; GFX6-NEXT: v_sub_i32_e32 v10, vcc, v10, v26
; GFX6-NEXT: v_min_u32_e32 v16, v6, v22		; GFX6-NEXT: v_sub_i32_e32 v11, vcc, v11, v27
; GFX6-NEXT: v_sub_i32_e32 v6, vcc, v6, v16		; GFX6-NEXT: v_sub_i32_e32 v12, vcc, v12, v28
; GFX6-NEXT: v_min_u32_e32 v16, v7, v23		; GFX6-NEXT: v_sub_i32_e32 v13, vcc, v13, v29
; GFX6-NEXT: v_sub_i32_e32 v7, vcc, v7, v16		; GFX6-NEXT: v_sub_i32_e32 v14, vcc, v14, v30
; GFX6-NEXT: v_min_u32_e32 v16, v8, v24		; GFX6-NEXT: v_sub_i32_e32 v15, vcc, v15, v31
; GFX6-NEXT: v_sub_i32_e32 v8, vcc, v8, v16
; GFX6-NEXT: v_min_u32_e32 v16, v9, v25
; GFX6-NEXT: v_sub_i32_e32 v9, vcc, v9, v16
; GFX6-NEXT: v_min_u32_e32 v16, v10, v26
; GFX6-NEXT: v_sub_i32_e32 v10, vcc, v10, v16
; GFX6-NEXT: v_min_u32_e32 v16, v11, v27
; GFX6-NEXT: v_sub_i32_e32 v11, vcc, v11, v16
; GFX6-NEXT: v_min_u32_e32 v16, v12, v28
; GFX6-NEXT: v_sub_i32_e32 v12, vcc, v12, v16
; GFX6-NEXT: v_min_u32_e32 v16, v13, v29
; GFX6-NEXT: v_sub_i32_e32 v13, vcc, v13, v16
; GFX6-NEXT: v_min_u32_e32 v16, v14, v30
; GFX6-NEXT: v_sub_i32_e32 v14, vcc, v14, v16
; GFX6-NEXT: v_min_u32_e32 v16, v15, v31
; GFX6-NEXT: v_sub_i32_e32 v15, vcc, v15, v16
; GFX6-NEXT: s_setpc_b64 s[30:31]		; GFX6-NEXT: s_setpc_b64 s[30:31]
;		;
; GFX8-LABEL: v_usubsat_v16i32:		; GFX8-LABEL: v_usubsat_v16i32:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_sub_u32_e64 v0, s[4:5], v0, v16 clamp		; GFX8-NEXT: v_sub_u32_e64 v0, s[4:5], v0, v16 clamp
; GFX8-NEXT: v_sub_u32_e64 v1, s[4:5], v1, v17 clamp		; GFX8-NEXT: v_sub_u32_e64 v1, s[4:5], v1, v17 clamp
; GFX8-NEXT: v_sub_u32_e64 v2, s[4:5], v2, v18 clamp		; GFX8-NEXT: v_sub_u32_e64 v2, s[4:5], v2, v18 clamp
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
; GFX10-NEXT: s_setpc_b64 s[30:31]		; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)		%result = call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)
ret <16 x i32> %result		ret <16 x i32> %result
}		}

define amdgpu_ps <16 x i32> @s_usubsat_v16i32(<16 x i32> inreg %lhs, <16 x i32> inreg %rhs) {		define amdgpu_ps <16 x i32> @s_usubsat_v16i32(<16 x i32> inreg %lhs, <16 x i32> inreg %rhs) {
; GFX6-LABEL: s_usubsat_v16i32:		; GFX6-LABEL: s_usubsat_v16i32:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_cmp_lt_u32 s0, s16		; GFX6-NEXT: s_cmp_gt_u32 s0, s16
; GFX6-NEXT: s_cselect_b32 s16, s0, s16		; GFX6-NEXT: s_cselect_b32 s32, s0, s16
; GFX6-NEXT: s_sub_i32 s0, s0, s16		; GFX6-NEXT: s_sub_i32 s0, s32, s16
; GFX6-NEXT: s_cmp_lt_u32 s1, s17		; GFX6-NEXT: s_cmp_gt_u32 s1, s17
; GFX6-NEXT: s_cselect_b32 s16, s1, s17		; GFX6-NEXT: s_cselect_b32 s1, s1, s17
; GFX6-NEXT: s_sub_i32 s1, s1, s16		; GFX6-NEXT: s_sub_i32 s1, s1, s17
; GFX6-NEXT: s_cmp_lt_u32 s2, s18		; GFX6-NEXT: s_cmp_gt_u32 s2, s18
; GFX6-NEXT: s_cselect_b32 s16, s2, s18		; GFX6-NEXT: s_cselect_b32 s2, s2, s18
; GFX6-NEXT: s_sub_i32 s2, s2, s16		; GFX6-NEXT: s_sub_i32 s2, s2, s18
; GFX6-NEXT: s_cmp_lt_u32 s3, s19		; GFX6-NEXT: s_cmp_gt_u32 s3, s19
; GFX6-NEXT: s_cselect_b32 s16, s3, s19		; GFX6-NEXT: s_cselect_b32 s3, s3, s19
; GFX6-NEXT: s_sub_i32 s3, s3, s16		; GFX6-NEXT: s_sub_i32 s3, s3, s19
; GFX6-NEXT: s_cmp_lt_u32 s4, s20		; GFX6-NEXT: s_cmp_gt_u32 s4, s20
; GFX6-NEXT: s_cselect_b32 s16, s4, s20		; GFX6-NEXT: s_cselect_b32 s4, s4, s20
; GFX6-NEXT: s_sub_i32 s4, s4, s16		; GFX6-NEXT: s_sub_i32 s4, s4, s20
; GFX6-NEXT: s_cmp_lt_u32 s5, s21		; GFX6-NEXT: s_cmp_gt_u32 s5, s21
; GFX6-NEXT: s_cselect_b32 s16, s5, s21		; GFX6-NEXT: s_cselect_b32 s5, s5, s21
; GFX6-NEXT: s_sub_i32 s5, s5, s16		; GFX6-NEXT: s_sub_i32 s5, s5, s21
; GFX6-NEXT: s_cmp_lt_u32 s6, s22		; GFX6-NEXT: s_cmp_gt_u32 s6, s22
; GFX6-NEXT: s_cselect_b32 s16, s6, s22		; GFX6-NEXT: s_cselect_b32 s6, s6, s22
; GFX6-NEXT: s_sub_i32 s6, s6, s16		; GFX6-NEXT: s_sub_i32 s6, s6, s22
; GFX6-NEXT: s_cmp_lt_u32 s7, s23		; GFX6-NEXT: s_cmp_gt_u32 s7, s23
; GFX6-NEXT: s_cselect_b32 s16, s7, s23		; GFX6-NEXT: s_cselect_b32 s7, s7, s23
; GFX6-NEXT: s_sub_i32 s7, s7, s16		; GFX6-NEXT: s_sub_i32 s7, s7, s23
; GFX6-NEXT: s_cmp_lt_u32 s8, s24		; GFX6-NEXT: s_cmp_gt_u32 s8, s24
; GFX6-NEXT: s_cselect_b32 s16, s8, s24		; GFX6-NEXT: s_cselect_b32 s8, s8, s24
; GFX6-NEXT: s_sub_i32 s8, s8, s16		; GFX6-NEXT: s_sub_i32 s8, s8, s24
; GFX6-NEXT: s_cmp_lt_u32 s9, s25		; GFX6-NEXT: s_cmp_gt_u32 s9, s25
; GFX6-NEXT: s_cselect_b32 s16, s9, s25		; GFX6-NEXT: s_cselect_b32 s9, s9, s25
; GFX6-NEXT: s_sub_i32 s9, s9, s16		; GFX6-NEXT: s_sub_i32 s9, s9, s25
; GFX6-NEXT: s_cmp_lt_u32 s10, s26		; GFX6-NEXT: s_cmp_gt_u32 s10, s26
; GFX6-NEXT: s_cselect_b32 s16, s10, s26		; GFX6-NEXT: s_cselect_b32 s10, s10, s26
; GFX6-NEXT: s_sub_i32 s10, s10, s16		; GFX6-NEXT: s_sub_i32 s10, s10, s26
; GFX6-NEXT: s_cmp_lt_u32 s11, s27		; GFX6-NEXT: s_cmp_gt_u32 s11, s27
; GFX6-NEXT: s_cselect_b32 s16, s11, s27		; GFX6-NEXT: s_cselect_b32 s11, s11, s27
; GFX6-NEXT: s_sub_i32 s11, s11, s16		; GFX6-NEXT: s_sub_i32 s11, s11, s27
; GFX6-NEXT: s_cmp_lt_u32 s12, s28		; GFX6-NEXT: s_cmp_gt_u32 s12, s28
; GFX6-NEXT: s_cselect_b32 s16, s12, s28		; GFX6-NEXT: s_cselect_b32 s12, s12, s28
; GFX6-NEXT: s_sub_i32 s12, s12, s16		; GFX6-NEXT: s_sub_i32 s12, s12, s28
; GFX6-NEXT: s_cmp_lt_u32 s13, s29		; GFX6-NEXT: s_cmp_gt_u32 s13, s29
; GFX6-NEXT: s_cselect_b32 s16, s13, s29		; GFX6-NEXT: s_cselect_b32 s13, s13, s29
; GFX6-NEXT: s_sub_i32 s13, s13, s16		; GFX6-NEXT: s_sub_i32 s13, s13, s29
; GFX6-NEXT: s_cmp_lt_u32 s14, s30		; GFX6-NEXT: s_cmp_gt_u32 s14, s30
; GFX6-NEXT: s_cselect_b32 s16, s14, s30		; GFX6-NEXT: s_cselect_b32 s14, s14, s30
; GFX6-NEXT: s_sub_i32 s14, s14, s16		; GFX6-NEXT: s_sub_i32 s14, s14, s30
; GFX6-NEXT: s_cmp_lt_u32 s15, s31		; GFX6-NEXT: s_cmp_gt_u32 s15, s31
; GFX6-NEXT: s_cselect_b32 s16, s15, s31		; GFX6-NEXT: s_cselect_b32 s15, s15, s31
; GFX6-NEXT: s_sub_i32 s15, s15, s16		; GFX6-NEXT: s_sub_i32 s15, s15, s31
; GFX6-NEXT: ; return to shader part epilog		; GFX6-NEXT: ; return to shader part epilog
;		;
; GFX8-LABEL: s_usubsat_v16i32:		; GFX8-LABEL: s_usubsat_v16i32:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: v_mov_b32_e32 v0, s16		; GFX8-NEXT: v_mov_b32_e32 v0, s16
; GFX8-NEXT: v_mov_b32_e32 v1, s17		; GFX8-NEXT: v_mov_b32_e32 v1, s17
; GFX8-NEXT: v_mov_b32_e32 v2, s18		; GFX8-NEXT: v_mov_b32_e32 v2, s18
; GFX8-NEXT: v_mov_b32_e32 v3, s19		; GFX8-NEXT: v_mov_b32_e32 v3, s19
▲ Show 20 Lines • Show All 134 Lines • ▼ Show 20 Lines	; GFX10-NEXT: ; return to shader part epilog
%result = call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)		%result = call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)
ret <16 x i32> %result		ret <16 x i32> %result
}		}

define i16 @v_usubsat_i16(i16 %lhs, i16 %rhs) {		define i16 @v_usubsat_i16(i16 %lhs, i16 %rhs) {
; GFX6-LABEL: v_usubsat_i16:		; GFX6-LABEL: v_usubsat_i16:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0		; GFX6-NEXT: s_mov_b32 s4, 0xffff
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1		; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
; GFX6-NEXT: v_min_u32_e32 v1, v0, v1		; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
		; GFX6-NEXT: v_max_u32_e32 v0, v0, v1
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1		; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]		; GFX6-NEXT: s_setpc_b64 s[30:31]
;		;
; GFX8-LABEL: v_usubsat_i16:		; GFX8-LABEL: v_usubsat_i16:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_sub_u16_e64 v0, v0, v1 clamp		; GFX8-NEXT: v_sub_u16_e64 v0, v0, v1 clamp
; GFX8-NEXT: s_setpc_b64 s[30:31]		; GFX8-NEXT: s_setpc_b64 s[30:31]
;		;
Show All 12 Lines
; GFX10-NEXT: s_setpc_b64 s[30:31]		; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call i16 @llvm.usub.sat.i16(i16 %lhs, i16 %rhs)		%result = call i16 @llvm.usub.sat.i16(i16 %lhs, i16 %rhs)
ret i16 %result		ret i16 %result
}		}

define amdgpu_ps i16 @s_usubsat_i16(i16 inreg %lhs, i16 inreg %rhs) {		define amdgpu_ps i16 @s_usubsat_i16(i16 inreg %lhs, i16 inreg %rhs) {
; GFX6-LABEL: s_usubsat_i16:		; GFX6-LABEL: s_usubsat_i16:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 16		; GFX6-NEXT: s_mov_b32 s2, 0xffff
; GFX6-NEXT: s_lshl_b32 s1, s1, 16		; GFX6-NEXT: s_and_b32 s0, s0, s2
; GFX6-NEXT: s_cmp_lt_u32 s0, s1		; GFX6-NEXT: s_and_b32 s1, s1, s2
; GFX6-NEXT: s_cselect_b32 s1, s0, s1		; GFX6-NEXT: s_cmp_gt_u32 s0, s1
		; GFX6-NEXT: s_cselect_b32 s0, s0, s1
; GFX6-NEXT: s_sub_i32 s0, s0, s1		; GFX6-NEXT: s_sub_i32 s0, s0, s1
; GFX6-NEXT: s_lshr_b32 s0, s0, 16
; GFX6-NEXT: ; return to shader part epilog		; GFX6-NEXT: ; return to shader part epilog
;		;
; GFX8-LABEL: s_usubsat_i16:		; GFX8-LABEL: s_usubsat_i16:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: v_mov_b32_e32 v0, s1		; GFX8-NEXT: v_mov_b32_e32 v0, s1
; GFX8-NEXT: v_sub_u16_e64 v0, s0, v0 clamp		; GFX8-NEXT: v_sub_u16_e64 v0, s0, v0 clamp
; GFX8-NEXT: v_readfirstlane_b32 s0, v0		; GFX8-NEXT: v_readfirstlane_b32 s0, v0
; GFX8-NEXT: ; return to shader part epilog		; GFX8-NEXT: ; return to shader part epilog
Show All 13 Lines
; GFX10-NEXT: ; return to shader part epilog		; GFX10-NEXT: ; return to shader part epilog
%result = call i16 @llvm.usub.sat.i16(i16 %lhs, i16 %rhs)		%result = call i16 @llvm.usub.sat.i16(i16 %lhs, i16 %rhs)
ret i16 %result		ret i16 %result
}		}

define amdgpu_ps half @usubsat_i16_sv(i16 inreg %lhs, i16 %rhs) {		define amdgpu_ps half @usubsat_i16_sv(i16 inreg %lhs, i16 %rhs) {
; GFX6-LABEL: usubsat_i16_sv:		; GFX6-LABEL: usubsat_i16_sv:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 16		; GFX6-NEXT: s_mov_b32 s1, 0xffff
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0		; GFX6-NEXT: s_and_b32 s0, s0, s1
; GFX6-NEXT: v_min_u32_e32 v0, s0, v0		; GFX6-NEXT: v_and_b32_e32 v0, s1, v0
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s0, v0		; GFX6-NEXT: v_max_u32_e32 v1, s0, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0		; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v1, v0
; GFX6-NEXT: ; return to shader part epilog		; GFX6-NEXT: ; return to shader part epilog
;		;
; GFX8-LABEL: usubsat_i16_sv:		; GFX8-LABEL: usubsat_i16_sv:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: v_sub_u16_e64 v0, s0, v0 clamp		; GFX8-NEXT: v_sub_u16_e64 v0, s0, v0 clamp
; GFX8-NEXT: ; return to shader part epilog		; GFX8-NEXT: ; return to shader part epilog
;		;
; GFX9-LABEL: usubsat_i16_sv:		; GFX9-LABEL: usubsat_i16_sv:
Show All 9 Lines	; GFX10-NEXT: ; return to shader part epilog
%result = call i16 @llvm.usub.sat.i16(i16 %lhs, i16 %rhs)		%result = call i16 @llvm.usub.sat.i16(i16 %lhs, i16 %rhs)
%cast = bitcast i16 %result to half		%cast = bitcast i16 %result to half
ret half %cast		ret half %cast
}		}

define amdgpu_ps half @usubsat_i16_vs(i16 %lhs, i16 inreg %rhs) {		define amdgpu_ps half @usubsat_i16_vs(i16 %lhs, i16 inreg %rhs) {
; GFX6-LABEL: usubsat_i16_vs:		; GFX6-LABEL: usubsat_i16_vs:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0		; GFX6-NEXT: s_mov_b32 s1, 0xffff
; GFX6-NEXT: s_lshl_b32 s0, s0, 16		; GFX6-NEXT: v_and_b32_e32 v0, s1, v0
; GFX6-NEXT: v_min_u32_e32 v1, s0, v0		; GFX6-NEXT: s_and_b32 s0, s0, s1
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1		; GFX6-NEXT: v_max_u32_e32 v0, s0, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0		; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s0, v0
; GFX6-NEXT: ; return to shader part epilog		; GFX6-NEXT: ; return to shader part epilog
;		;
; GFX8-LABEL: usubsat_i16_vs:		; GFX8-LABEL: usubsat_i16_vs:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: v_sub_u16_e64 v0, v0, s0 clamp		; GFX8-NEXT: v_sub_u16_e64 v0, v0, s0 clamp
; GFX8-NEXT: ; return to shader part epilog		; GFX8-NEXT: ; return to shader part epilog
;		;
; GFX9-LABEL: usubsat_i16_vs:		; GFX9-LABEL: usubsat_i16_vs:
Show All 10 Lines	; GFX10-NEXT: ; return to shader part epilog
%cast = bitcast i16 %result to half		%cast = bitcast i16 %result to half
ret half %cast		ret half %cast
}		}

define <2 x i16> @v_usubsat_v2i16(<2 x i16> %lhs, <2 x i16> %rhs) {		define <2 x i16> @v_usubsat_v2i16(<2 x i16> %lhs, <2 x i16> %rhs) {
; GFX6-LABEL: v_usubsat_v2i16:		; GFX6-LABEL: v_usubsat_v2i16:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0		; GFX6-NEXT: s_mov_b32 s4, 0xffff
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2		; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
; GFX6-NEXT: v_min_u32_e32 v2, v0, v2		; GFX6-NEXT: v_and_b32_e32 v2, s4, v2
		; GFX6-NEXT: v_max_u32_e32 v0, v0, v2
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v2		; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1		; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v3		; GFX6-NEXT: v_and_b32_e32 v2, s4, v3
; GFX6-NEXT: v_min_u32_e32 v2, v1, v2		; GFX6-NEXT: v_max_u32_e32 v1, v1, v2
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v2		; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v2
; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]		; GFX6-NEXT: s_setpc_b64 s[30:31]
;		;
; GFX8-LABEL: v_usubsat_v2i16:		; GFX8-LABEL: v_usubsat_v2i16:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_sub_u16_e64 v2, v0, v1 clamp		; GFX8-NEXT: v_sub_u16_e64 v2, v0, v1 clamp
; GFX8-NEXT: v_sub_u16_sdwa v0, v0, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1		; GFX8-NEXT: v_sub_u16_sdwa v0, v0, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; GFX8-NEXT: v_mov_b32_e32 v1, 16		; GFX8-NEXT: v_mov_b32_e32 v1, 16
Show All 16 Lines
; GFX10-NEXT: s_setpc_b64 s[30:31]		; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i16> @llvm.usub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)		%result = call <2 x i16> @llvm.usub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
ret <2 x i16> %result		ret <2 x i16> %result
}		}

define amdgpu_ps i32 @s_usubsat_v2i16(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs) {		define amdgpu_ps i32 @s_usubsat_v2i16(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs) {
; GFX6-LABEL: s_usubsat_v2i16:		; GFX6-LABEL: s_usubsat_v2i16:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 16		; GFX6-NEXT: s_mov_b32 s4, 0xffff
; GFX6-NEXT: s_lshl_b32 s2, s2, 16		; GFX6-NEXT: s_and_b32 s0, s0, s4
; GFX6-NEXT: s_cmp_lt_u32 s0, s2		; GFX6-NEXT: s_and_b32 s2, s2, s4
; GFX6-NEXT: s_cselect_b32 s2, s0, s2		; GFX6-NEXT: s_cmp_gt_u32 s0, s2
		; GFX6-NEXT: s_cselect_b32 s0, s0, s2
; GFX6-NEXT: s_sub_i32 s0, s0, s2		; GFX6-NEXT: s_sub_i32 s0, s0, s2
; GFX6-NEXT: s_lshr_b32 s0, s0, 16		; GFX6-NEXT: s_and_b32 s1, s1, s4
; GFX6-NEXT: s_lshl_b32 s1, s1, 16		; GFX6-NEXT: s_and_b32 s2, s3, s4
; GFX6-NEXT: s_lshl_b32 s2, s3, 16		; GFX6-NEXT: s_cmp_gt_u32 s1, s2
; GFX6-NEXT: s_cmp_lt_u32 s1, s2		; GFX6-NEXT: s_cselect_b32 s1, s1, s2
; GFX6-NEXT: s_cselect_b32 s2, s1, s2
; GFX6-NEXT: s_sub_i32 s1, s1, s2		; GFX6-NEXT: s_sub_i32 s1, s1, s2
; GFX6-NEXT: s_mov_b32 s2, 0xffff		; GFX6-NEXT: s_and_b32 s1, s1, s4
; GFX6-NEXT: s_lshr_b32 s1, s1, 16		; GFX6-NEXT: s_and_b32 s0, s0, s4
; GFX6-NEXT: s_and_b32 s1, s1, s2
; GFX6-NEXT: s_and_b32 s0, s0, s2
; GFX6-NEXT: s_lshl_b32 s1, s1, 16		; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_or_b32 s0, s0, s1		; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: ; return to shader part epilog		; GFX6-NEXT: ; return to shader part epilog
;		;
; GFX8-LABEL: s_usubsat_v2i16:		; GFX8-LABEL: s_usubsat_v2i16:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_lshr_b32 s3, s1, 16		; GFX8-NEXT: s_lshr_b32 s3, s1, 16
; GFX8-NEXT: s_lshr_b32 s2, s0, 16		; GFX8-NEXT: s_lshr_b32 s2, s0, 16
Show All 23 Lines	; GFX10-NEXT: ; return to shader part epilog
%result = call <2 x i16> @llvm.usub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)		%result = call <2 x i16> @llvm.usub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
%cast = bitcast <2 x i16> %result to i32		%cast = bitcast <2 x i16> %result to i32
ret i32 %cast		ret i32 %cast
}		}

define amdgpu_ps float @usubsat_v2i16_sv(<2 x i16> inreg %lhs, <2 x i16> %rhs) {		define amdgpu_ps float @usubsat_v2i16_sv(<2 x i16> inreg %lhs, <2 x i16> %rhs) {
; GFX6-LABEL: usubsat_v2i16_sv:		; GFX6-LABEL: usubsat_v2i16_sv:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 16		; GFX6-NEXT: s_mov_b32 s2, 0xffff
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0		; GFX6-NEXT: s_and_b32 s0, s0, s2
; GFX6-NEXT: v_min_u32_e32 v0, s0, v0		; GFX6-NEXT: v_and_b32_e32 v0, s2, v0
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s0, v0		; GFX6-NEXT: v_max_u32_e32 v2, s0, v0
; GFX6-NEXT: s_lshl_b32 s0, s1, 16		; GFX6-NEXT: s_and_b32 s0, s1, s2
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1		; GFX6-NEXT: v_and_b32_e32 v1, s2, v1
; GFX6-NEXT: v_min_u32_e32 v1, s0, v1		; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v2, v0
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s0, v1		; GFX6-NEXT: v_max_u32_e32 v2, s0, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v1		; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v2, v1
; GFX6-NEXT: s_mov_b32 s0, 0xffff		; GFX6-NEXT: v_and_b32_e32 v1, s2, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0		; GFX6-NEXT: v_and_b32_e32 v0, s2, v0
; GFX6-NEXT: v_and_b32_e32 v1, s0, v1
; GFX6-NEXT: v_and_b32_e32 v0, s0, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1		; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1		; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: ; return to shader part epilog		; GFX6-NEXT: ; return to shader part epilog
;		;
; GFX8-LABEL: usubsat_v2i16_sv:		; GFX8-LABEL: usubsat_v2i16_sv:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_lshr_b32 s1, s0, 16		; GFX8-NEXT: s_lshr_b32 s1, s0, 16
; GFX8-NEXT: v_mov_b32_e32 v2, s1		; GFX8-NEXT: v_mov_b32_e32 v2, s1
Show All 17 Lines	; GFX10-NEXT: ; return to shader part epilog
%result = call <2 x i16> @llvm.usub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)		%result = call <2 x i16> @llvm.usub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
%cast = bitcast <2 x i16> %result to float		%cast = bitcast <2 x i16> %result to float
ret float %cast		ret float %cast
}		}

define amdgpu_ps float @usubsat_v2i16_vs(<2 x i16> %lhs, <2 x i16> inreg %rhs) {		define amdgpu_ps float @usubsat_v2i16_vs(<2 x i16> %lhs, <2 x i16> inreg %rhs) {
; GFX6-LABEL: usubsat_v2i16_vs:		; GFX6-LABEL: usubsat_v2i16_vs:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0		; GFX6-NEXT: s_mov_b32 s2, 0xffff
; GFX6-NEXT: s_lshl_b32 s0, s0, 16		; GFX6-NEXT: v_and_b32_e32 v0, s2, v0
; GFX6-NEXT: v_min_u32_e32 v2, s0, v0		; GFX6-NEXT: s_and_b32 s0, s0, s2
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1		; GFX6-NEXT: v_max_u32_e32 v0, s0, v0
; GFX6-NEXT: s_lshl_b32 s0, s1, 16		; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s0, v0
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v2		; GFX6-NEXT: v_and_b32_e32 v1, s2, v1
; GFX6-NEXT: v_min_u32_e32 v2, s0, v1		; GFX6-NEXT: s_and_b32 s0, s1, s2
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v2		; GFX6-NEXT: v_max_u32_e32 v1, s0, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v1		; GFX6-NEXT: v_subrev_i32_e32 v1, vcc, s0, v1
; GFX6-NEXT: s_mov_b32 s0, 0xffff		; GFX6-NEXT: v_and_b32_e32 v1, s2, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0		; GFX6-NEXT: v_and_b32_e32 v0, s2, v0
; GFX6-NEXT: v_and_b32_e32 v1, s0, v1
; GFX6-NEXT: v_and_b32_e32 v0, s0, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1		; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1		; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: ; return to shader part epilog		; GFX6-NEXT: ; return to shader part epilog
;		;
; GFX8-LABEL: usubsat_v2i16_vs:		; GFX8-LABEL: usubsat_v2i16_vs:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_lshr_b32 s1, s0, 16		; GFX8-NEXT: s_lshr_b32 s1, s0, 16
; GFX8-NEXT: v_mov_b32_e32 v2, s1		; GFX8-NEXT: v_mov_b32_e32 v2, s1
Show All 29 Lines
; %result = call <3 x i16> @llvm.usub.sat.v3i16(<3 x i16> %lhs, <3 x i16> %rhs)		; %result = call <3 x i16> @llvm.usub.sat.v3i16(<3 x i16> %lhs, <3 x i16> %rhs)
; ret <3 x i16> %result		; ret <3 x i16> %result
; }		; }

define <2 x float> @v_usubsat_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {		define <2 x float> @v_usubsat_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
; GFX6-LABEL: v_usubsat_v4i16:		; GFX6-LABEL: v_usubsat_v4i16:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0		; GFX6-NEXT: s_mov_b32 s4, 0xffff
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v4		; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
; GFX6-NEXT: v_min_u32_e32 v4, v0, v4		; GFX6-NEXT: v_and_b32_e32 v4, s4, v4
		; GFX6-NEXT: v_max_u32_e32 v0, v0, v4
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v4		; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1		; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v5		; GFX6-NEXT: v_and_b32_e32 v4, s4, v5
; GFX6-NEXT: v_min_u32_e32 v4, v1, v4		; GFX6-NEXT: v_max_u32_e32 v1, v1, v4
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v4		; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2		; GFX6-NEXT: v_and_b32_e32 v2, s4, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v6		; GFX6-NEXT: v_and_b32_e32 v4, s4, v6
; GFX6-NEXT: v_min_u32_e32 v4, v2, v4		; GFX6-NEXT: v_max_u32_e32 v2, v2, v4
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v4		; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3		; GFX6-NEXT: v_and_b32_e32 v3, s4, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v7		; GFX6-NEXT: v_and_b32_e32 v4, s4, v7
; GFX6-NEXT: v_min_u32_e32 v4, v3, v4		; GFX6-NEXT: v_max_u32_e32 v3, v3, v4
; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX6-NEXT: s_mov_b32 s4, 0xffff
; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, v3, v4
; GFX6-NEXT: v_and_b32_e32 v1, s4, v1		; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v2		; GFX6-NEXT: v_mov_b32_e32 v8, 0xffff
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v3		; GFX6-NEXT: v_sub_i32_e32 v3, vcc, v3, v4
; GFX6-NEXT: v_and_b32_e32 v0, s4, v0		; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1		; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1		; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: v_and_b32_e32 v1, s4, v2		; GFX6-NEXT: v_and_b32_e32 v1, v2, v8
; GFX6-NEXT: v_and_b32_e32 v2, s4, v3		; GFX6-NEXT: v_and_b32_e32 v2, v3, v8
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2		; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX6-NEXT: v_or_b32_e32 v1, v1, v2		; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
; GFX6-NEXT: s_setpc_b64 s[30:31]		; GFX6-NEXT: s_setpc_b64 s[30:31]
;		;
; GFX8-LABEL: v_usubsat_v4i16:		; GFX8-LABEL: v_usubsat_v4i16:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_sub_u16_e64 v4, v0, v2 clamp		; GFX8-NEXT: v_sub_u16_e64 v4, v0, v2 clamp
Show All 25 Lines	; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <4 x i16> @llvm.usub.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)		%result = call <4 x i16> @llvm.usub.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
%cast = bitcast <4 x i16> %result to <2 x float>		%cast = bitcast <4 x i16> %result to <2 x float>
ret <2 x float> %cast		ret <2 x float> %cast
}		}

define amdgpu_ps <2 x i32> @s_usubsat_v4i16(<4 x i16> inreg %lhs, <4 x i16> inreg %rhs) {		define amdgpu_ps <2 x i32> @s_usubsat_v4i16(<4 x i16> inreg %lhs, <4 x i16> inreg %rhs) {
; GFX6-LABEL: s_usubsat_v4i16:		; GFX6-LABEL: s_usubsat_v4i16:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 16		; GFX6-NEXT: s_mov_b32 s8, 0xffff
; GFX6-NEXT: s_lshl_b32 s4, s4, 16		; GFX6-NEXT: s_and_b32 s0, s0, s8
; GFX6-NEXT: s_cmp_lt_u32 s0, s4		; GFX6-NEXT: s_and_b32 s4, s4, s8
; GFX6-NEXT: s_cselect_b32 s4, s0, s4		; GFX6-NEXT: s_cmp_gt_u32 s0, s4
		; GFX6-NEXT: s_cselect_b32 s0, s0, s4
; GFX6-NEXT: s_sub_i32 s0, s0, s4		; GFX6-NEXT: s_sub_i32 s0, s0, s4
; GFX6-NEXT: s_lshr_b32 s0, s0, 16		; GFX6-NEXT: s_and_b32 s1, s1, s8
; GFX6-NEXT: s_lshl_b32 s1, s1, 16		; GFX6-NEXT: s_and_b32 s4, s5, s8
; GFX6-NEXT: s_lshl_b32 s4, s5, 16		; GFX6-NEXT: s_cmp_gt_u32 s1, s4
; GFX6-NEXT: s_cmp_lt_u32 s1, s4		; GFX6-NEXT: s_cselect_b32 s1, s1, s4
; GFX6-NEXT: s_cselect_b32 s4, s1, s4
; GFX6-NEXT: s_sub_i32 s1, s1, s4		; GFX6-NEXT: s_sub_i32 s1, s1, s4
; GFX6-NEXT: s_lshr_b32 s1, s1, 16		; GFX6-NEXT: s_and_b32 s2, s2, s8
; GFX6-NEXT: s_lshl_b32 s2, s2, 16		; GFX6-NEXT: s_and_b32 s4, s6, s8
; GFX6-NEXT: s_lshl_b32 s4, s6, 16		; GFX6-NEXT: s_cmp_gt_u32 s2, s4
; GFX6-NEXT: s_cmp_lt_u32 s2, s4		; GFX6-NEXT: s_cselect_b32 s2, s2, s4
; GFX6-NEXT: s_cselect_b32 s4, s2, s4
; GFX6-NEXT: s_sub_i32 s2, s2, s4		; GFX6-NEXT: s_sub_i32 s2, s2, s4
; GFX6-NEXT: s_lshr_b32 s2, s2, 16		; GFX6-NEXT: s_and_b32 s3, s3, s8
; GFX6-NEXT: s_lshl_b32 s3, s3, 16		; GFX6-NEXT: s_and_b32 s4, s7, s8
; GFX6-NEXT: s_lshl_b32 s4, s7, 16		; GFX6-NEXT: s_cmp_gt_u32 s3, s4
; GFX6-NEXT: s_cmp_lt_u32 s3, s4		; GFX6-NEXT: s_cselect_b32 s3, s3, s4
; GFX6-NEXT: s_cselect_b32 s4, s3, s4		; GFX6-NEXT: s_and_b32 s1, s1, s8
; GFX6-NEXT: s_sub_i32 s3, s3, s4		; GFX6-NEXT: s_sub_i32 s3, s3, s4
; GFX6-NEXT: s_mov_b32 s4, 0xffff		; GFX6-NEXT: s_and_b32 s0, s0, s8
; GFX6-NEXT: s_and_b32 s1, s1, s4
; GFX6-NEXT: s_lshr_b32 s3, s3, 16
; GFX6-NEXT: s_and_b32 s0, s0, s4
; GFX6-NEXT: s_lshl_b32 s1, s1, 16		; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_or_b32 s0, s0, s1		; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: s_and_b32 s1, s2, s4		; GFX6-NEXT: s_and_b32 s1, s2, s8
; GFX6-NEXT: s_and_b32 s2, s3, s4		; GFX6-NEXT: s_and_b32 s2, s3, s8
; GFX6-NEXT: s_lshl_b32 s2, s2, 16		; GFX6-NEXT: s_lshl_b32 s2, s2, 16
; GFX6-NEXT: s_or_b32 s1, s1, s2		; GFX6-NEXT: s_or_b32 s1, s1, s2
; GFX6-NEXT: ; return to shader part epilog		; GFX6-NEXT: ; return to shader part epilog
;		;
; GFX8-LABEL: s_usubsat_v4i16:		; GFX8-LABEL: s_usubsat_v4i16:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_lshr_b32 s6, s2, 16		; GFX8-NEXT: s_lshr_b32 s6, s2, 16
; GFX8-NEXT: s_lshr_b32 s7, s3, 16		; GFX8-NEXT: s_lshr_b32 s7, s3, 16
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Lines
; %result = call <5 x i16> @llvm.usub.sat.v5i16(<5 x i16> %lhs, <5 x i16> %rhs)		; %result = call <5 x i16> @llvm.usub.sat.v5i16(<5 x i16> %lhs, <5 x i16> %rhs)
; ret <5 x i16> %result		; ret <5 x i16> %result
; }		; }

define <3 x float> @v_usubsat_v6i16(<6 x i16> %lhs, <6 x i16> %rhs) {		define <3 x float> @v_usubsat_v6i16(<6 x i16> %lhs, <6 x i16> %rhs) {
; GFX6-LABEL: v_usubsat_v6i16:		; GFX6-LABEL: v_usubsat_v6i16:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0		; GFX6-NEXT: s_mov_b32 s4, 0xffff
; GFX6-NEXT: v_lshlrev_b32_e32 v6, 16, v6		; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
; GFX6-NEXT: v_min_u32_e32 v6, v0, v6		; GFX6-NEXT: v_and_b32_e32 v6, s4, v6
		; GFX6-NEXT: v_max_u32_e32 v0, v0, v6
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v6		; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v6
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1		; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v6, 16, v7		; GFX6-NEXT: v_and_b32_e32 v6, s4, v7
; GFX6-NEXT: v_min_u32_e32 v6, v1, v6		; GFX6-NEXT: v_max_u32_e32 v1, v1, v6
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v6		; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v6
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2		; GFX6-NEXT: v_and_b32_e32 v2, s4, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v6, 16, v8		; GFX6-NEXT: v_and_b32_e32 v6, s4, v8
; GFX6-NEXT: v_min_u32_e32 v6, v2, v6		; GFX6-NEXT: v_max_u32_e32 v2, v2, v6
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v6		; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v6
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3		; GFX6-NEXT: v_and_b32_e32 v3, s4, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v6, 16, v9		; GFX6-NEXT: v_and_b32_e32 v6, s4, v9
; GFX6-NEXT: v_min_u32_e32 v6, v3, v6		; GFX6-NEXT: v_max_u32_e32 v3, v3, v6
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, v3, v6		; GFX6-NEXT: v_sub_i32_e32 v3, vcc, v3, v6
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v4		; GFX6-NEXT: v_and_b32_e32 v4, s4, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v6, 16, v10		; GFX6-NEXT: v_and_b32_e32 v6, s4, v10
; GFX6-NEXT: v_min_u32_e32 v6, v4, v6		; GFX6-NEXT: v_mov_b32_e32 v12, 0xffff
		; GFX6-NEXT: v_max_u32_e32 v4, v4, v6
		; GFX6-NEXT: v_and_b32_e32 v1, v1, v12
; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v4, v6		; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v4, v6
; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v1		; GFX6-NEXT: v_and_b32_e32 v5, s4, v5
; GFX6-NEXT: s_mov_b32 s4, 0xffff		; GFX6-NEXT: v_and_b32_e32 v6, v11, v12
; GFX6-NEXT: v_lshlrev_b32_e32 v5, 16, v5		; GFX6-NEXT: v_max_u32_e32 v5, v5, v6
; GFX6-NEXT: v_lshlrev_b32_e32 v6, 16, v11		; GFX6-NEXT: v_and_b32_e32 v0, v0, v12
; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX6-NEXT: v_min_u32_e32 v6, v5, v6
; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
; GFX6-NEXT: v_sub_i32_e32 v5, vcc, v5, v6
; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1		; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1		; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: v_and_b32_e32 v1, s4, v2		; GFX6-NEXT: v_and_b32_e32 v1, v2, v12
; GFX6-NEXT: v_and_b32_e32 v2, s4, v3		; GFX6-NEXT: v_and_b32_e32 v2, v3, v12
; GFX6-NEXT: v_lshrrev_b32_e32 v5, 16, v5		; GFX6-NEXT: v_sub_i32_e32 v5, vcc, v5, v6
; GFX6-NEXT: v_and_b32_e32 v3, s4, v5		; GFX6-NEXT: v_and_b32_e32 v3, v5, v12
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2		; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX6-NEXT: v_lshrrev_b32_e32 v4, 16, v4
; GFX6-NEXT: v_or_b32_e32 v1, v1, v2		; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
; GFX6-NEXT: v_and_b32_e32 v2, s4, v4		; GFX6-NEXT: v_and_b32_e32 v2, v4, v12
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3		; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX6-NEXT: v_or_b32_e32 v2, v2, v3		; GFX6-NEXT: v_or_b32_e32 v2, v2, v3
; GFX6-NEXT: s_setpc_b64 s[30:31]		; GFX6-NEXT: s_setpc_b64 s[30:31]
;		;
; GFX8-LABEL: v_usubsat_v6i16:		; GFX8-LABEL: v_usubsat_v6i16:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_sub_u16_e64 v6, v0, v3 clamp		; GFX8-NEXT: v_sub_u16_e64 v6, v0, v3 clamp
Show All 32 Lines	; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <6 x i16> @llvm.usub.sat.v6i16(<6 x i16> %lhs, <6 x i16> %rhs)		%result = call <6 x i16> @llvm.usub.sat.v6i16(<6 x i16> %lhs, <6 x i16> %rhs)
%cast = bitcast <6 x i16> %result to <3 x float>		%cast = bitcast <6 x i16> %result to <3 x float>
ret <3 x float> %cast		ret <3 x float> %cast
}		}

define amdgpu_ps <3 x i32> @s_usubsat_v6i16(<6 x i16> inreg %lhs, <6 x i16> inreg %rhs) {		define amdgpu_ps <3 x i32> @s_usubsat_v6i16(<6 x i16> inreg %lhs, <6 x i16> inreg %rhs) {
; GFX6-LABEL: s_usubsat_v6i16:		; GFX6-LABEL: s_usubsat_v6i16:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 16		; GFX6-NEXT: s_mov_b32 s12, 0xffff
; GFX6-NEXT: s_lshl_b32 s6, s6, 16		; GFX6-NEXT: s_and_b32 s0, s0, s12
; GFX6-NEXT: s_cmp_lt_u32 s0, s6		; GFX6-NEXT: s_and_b32 s6, s6, s12
; GFX6-NEXT: s_cselect_b32 s6, s0, s6		; GFX6-NEXT: s_cmp_gt_u32 s0, s6
		; GFX6-NEXT: s_cselect_b32 s0, s0, s6
; GFX6-NEXT: s_sub_i32 s0, s0, s6		; GFX6-NEXT: s_sub_i32 s0, s0, s6
; GFX6-NEXT: s_lshr_b32 s0, s0, 16		; GFX6-NEXT: s_and_b32 s1, s1, s12
; GFX6-NEXT: s_lshl_b32 s1, s1, 16		; GFX6-NEXT: s_and_b32 s6, s7, s12
; GFX6-NEXT: s_lshl_b32 s6, s7, 16		; GFX6-NEXT: s_cmp_gt_u32 s1, s6
; GFX6-NEXT: s_cmp_lt_u32 s1, s6		; GFX6-NEXT: s_cselect_b32 s1, s1, s6
; GFX6-NEXT: s_cselect_b32 s6, s1, s6
; GFX6-NEXT: s_sub_i32 s1, s1, s6		; GFX6-NEXT: s_sub_i32 s1, s1, s6
; GFX6-NEXT: s_lshr_b32 s1, s1, 16		; GFX6-NEXT: s_and_b32 s2, s2, s12
; GFX6-NEXT: s_lshl_b32 s2, s2, 16		; GFX6-NEXT: s_and_b32 s6, s8, s12
; GFX6-NEXT: s_lshl_b32 s6, s8, 16		; GFX6-NEXT: s_cmp_gt_u32 s2, s6
; GFX6-NEXT: s_cmp_lt_u32 s2, s6		; GFX6-NEXT: s_cselect_b32 s2, s2, s6
; GFX6-NEXT: s_cselect_b32 s6, s2, s6
; GFX6-NEXT: s_sub_i32 s2, s2, s6		; GFX6-NEXT: s_sub_i32 s2, s2, s6
; GFX6-NEXT: s_lshr_b32 s2, s2, 16		; GFX6-NEXT: s_and_b32 s3, s3, s12
; GFX6-NEXT: s_lshl_b32 s3, s3, 16		; GFX6-NEXT: s_and_b32 s6, s9, s12
; GFX6-NEXT: s_lshl_b32 s6, s9, 16		; GFX6-NEXT: s_cmp_gt_u32 s3, s6
; GFX6-NEXT: s_cmp_lt_u32 s3, s6		; GFX6-NEXT: s_cselect_b32 s3, s3, s6
; GFX6-NEXT: s_cselect_b32 s6, s3, s6
; GFX6-NEXT: s_sub_i32 s3, s3, s6		; GFX6-NEXT: s_sub_i32 s3, s3, s6
; GFX6-NEXT: s_lshr_b32 s3, s3, 16		; GFX6-NEXT: s_and_b32 s4, s4, s12
; GFX6-NEXT: s_lshl_b32 s4, s4, 16		; GFX6-NEXT: s_and_b32 s6, s10, s12
; GFX6-NEXT: s_lshl_b32 s6, s10, 16		; GFX6-NEXT: s_cmp_gt_u32 s4, s6
; GFX6-NEXT: s_cmp_lt_u32 s4, s6		; GFX6-NEXT: s_cselect_b32 s4, s4, s6
; GFX6-NEXT: s_cselect_b32 s6, s4, s6
; GFX6-NEXT: s_sub_i32 s4, s4, s6		; GFX6-NEXT: s_sub_i32 s4, s4, s6
; GFX6-NEXT: s_lshr_b32 s4, s4, 16		; GFX6-NEXT: s_and_b32 s5, s5, s12
; GFX6-NEXT: s_lshl_b32 s5, s5, 16		; GFX6-NEXT: s_and_b32 s6, s11, s12
; GFX6-NEXT: s_lshl_b32 s6, s11, 16		; GFX6-NEXT: s_cmp_gt_u32 s5, s6
; GFX6-NEXT: s_cmp_lt_u32 s5, s6		; GFX6-NEXT: s_cselect_b32 s5, s5, s6
; GFX6-NEXT: s_cselect_b32 s6, s5, s6		; GFX6-NEXT: s_and_b32 s1, s1, s12
; GFX6-NEXT: s_sub_i32 s5, s5, s6		; GFX6-NEXT: s_and_b32 s0, s0, s12
; GFX6-NEXT: s_mov_b32 s6, 0xffff
; GFX6-NEXT: s_and_b32 s1, s1, s6
; GFX6-NEXT: s_and_b32 s0, s0, s6
; GFX6-NEXT: s_lshl_b32 s1, s1, 16		; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_or_b32 s0, s0, s1		; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: s_and_b32 s1, s2, s6		; GFX6-NEXT: s_and_b32 s1, s2, s12
; GFX6-NEXT: s_and_b32 s2, s3, s6		; GFX6-NEXT: s_and_b32 s2, s3, s12
; GFX6-NEXT: s_lshr_b32 s5, s5, 16		; GFX6-NEXT: s_sub_i32 s5, s5, s6
; GFX6-NEXT: s_and_b32 s3, s5, s6		; GFX6-NEXT: s_and_b32 s3, s5, s12
; GFX6-NEXT: s_lshl_b32 s2, s2, 16		; GFX6-NEXT: s_lshl_b32 s2, s2, 16
; GFX6-NEXT: s_or_b32 s1, s1, s2		; GFX6-NEXT: s_or_b32 s1, s1, s2
; GFX6-NEXT: s_and_b32 s2, s4, s6		; GFX6-NEXT: s_and_b32 s2, s4, s12
; GFX6-NEXT: s_lshl_b32 s3, s3, 16		; GFX6-NEXT: s_lshl_b32 s3, s3, 16
; GFX6-NEXT: s_or_b32 s2, s2, s3		; GFX6-NEXT: s_or_b32 s2, s2, s3
; GFX6-NEXT: ; return to shader part epilog		; GFX6-NEXT: ; return to shader part epilog
;		;
; GFX8-LABEL: s_usubsat_v6i16:		; GFX8-LABEL: s_usubsat_v6i16:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_lshr_b32 s9, s3, 16		; GFX8-NEXT: s_lshr_b32 s9, s3, 16
; GFX8-NEXT: s_lshr_b32 s10, s4, 16		; GFX8-NEXT: s_lshr_b32 s10, s4, 16
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines	; GFX10-NEXT: ; return to shader part epilog
%cast = bitcast <6 x i16> %result to <3 x i32>		%cast = bitcast <6 x i16> %result to <3 x i32>
ret <3 x i32> %cast		ret <3 x i32> %cast
}		}

define <4 x float> @v_usubsat_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {		define <4 x float> @v_usubsat_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
; GFX6-LABEL: v_usubsat_v8i16:		; GFX6-LABEL: v_usubsat_v8i16:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0		; GFX6-NEXT: s_mov_b32 s4, 0xffff
; GFX6-NEXT: v_lshlrev_b32_e32 v8, 16, v8		; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
; GFX6-NEXT: v_min_u32_e32 v8, v0, v8		; GFX6-NEXT: v_and_b32_e32 v8, s4, v8
		; GFX6-NEXT: v_max_u32_e32 v0, v0, v8
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v8		; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v8
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1		; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v8, 16, v9		; GFX6-NEXT: v_and_b32_e32 v8, s4, v9
; GFX6-NEXT: v_min_u32_e32 v8, v1, v8		; GFX6-NEXT: v_max_u32_e32 v1, v1, v8
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v8		; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v8
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2		; GFX6-NEXT: v_and_b32_e32 v2, s4, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v8, 16, v10		; GFX6-NEXT: v_and_b32_e32 v8, s4, v10
; GFX6-NEXT: v_min_u32_e32 v8, v2, v8		; GFX6-NEXT: v_max_u32_e32 v2, v2, v8
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v8		; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v8
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3		; GFX6-NEXT: v_and_b32_e32 v3, s4, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v8, 16, v11		; GFX6-NEXT: v_and_b32_e32 v8, s4, v11
; GFX6-NEXT: v_min_u32_e32 v8, v3, v8		; GFX6-NEXT: v_max_u32_e32 v3, v3, v8
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, v3, v8		; GFX6-NEXT: v_sub_i32_e32 v3, vcc, v3, v8
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v4		; GFX6-NEXT: v_and_b32_e32 v4, s4, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v8, 16, v12		; GFX6-NEXT: v_and_b32_e32 v8, s4, v12
; GFX6-NEXT: v_min_u32_e32 v8, v4, v8		; GFX6-NEXT: v_mov_b32_e32 v16, 0xffff
		; GFX6-NEXT: v_max_u32_e32 v4, v4, v8
; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v4, v8		; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v4, v8
; GFX6-NEXT: v_lshlrev_b32_e32 v5, 16, v5		; GFX6-NEXT: v_and_b32_e32 v5, s4, v5
; GFX6-NEXT: v_lshlrev_b32_e32 v8, 16, v13		; GFX6-NEXT: v_and_b32_e32 v8, v13, v16
; GFX6-NEXT: v_min_u32_e32 v8, v5, v8		; GFX6-NEXT: v_max_u32_e32 v5, v5, v8
; GFX6-NEXT: v_sub_i32_e32 v5, vcc, v5, v8		; GFX6-NEXT: v_sub_i32_e32 v5, vcc, v5, v8
; GFX6-NEXT: v_lshlrev_b32_e32 v6, 16, v6		; GFX6-NEXT: v_and_b32_e32 v6, v6, v16
; GFX6-NEXT: v_lshlrev_b32_e32 v8, 16, v14		; GFX6-NEXT: v_and_b32_e32 v8, v14, v16
; GFX6-NEXT: v_min_u32_e32 v8, v6, v8		; GFX6-NEXT: v_max_u32_e32 v6, v6, v8
; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v1		; GFX6-NEXT: v_and_b32_e32 v1, v1, v16
; GFX6-NEXT: s_mov_b32 s4, 0xffff
; GFX6-NEXT: v_sub_i32_e32 v6, vcc, v6, v8		; GFX6-NEXT: v_sub_i32_e32 v6, vcc, v6, v8
; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0		; GFX6-NEXT: v_and_b32_e32 v7, v7, v16
; GFX6-NEXT: v_and_b32_e32 v1, s4, v1		; GFX6-NEXT: v_and_b32_e32 v8, v15, v16
; GFX6-NEXT: v_lshlrev_b32_e32 v7, 16, v7		; GFX6-NEXT: v_and_b32_e32 v0, v0, v16
; GFX6-NEXT: v_lshlrev_b32_e32 v8, 16, v15
; GFX6-NEXT: v_min_u32_e32 v8, v7, v8
; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1		; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_sub_i32_e32 v7, vcc, v7, v8		; GFX6-NEXT: v_max_u32_e32 v7, v7, v8
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1		; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: v_and_b32_e32 v1, s4, v2		; GFX6-NEXT: v_and_b32_e32 v1, v2, v16
; GFX6-NEXT: v_and_b32_e32 v2, s4, v3		; GFX6-NEXT: v_and_b32_e32 v2, v3, v16
; GFX6-NEXT: v_lshrrev_b32_e32 v5, 16, v5		; GFX6-NEXT: v_and_b32_e32 v3, v5, v16
; GFX6-NEXT: v_and_b32_e32 v3, s4, v5
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2		; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX6-NEXT: v_lshrrev_b32_e32 v4, 16, v4		; GFX6-NEXT: v_sub_i32_e32 v7, vcc, v7, v8
; GFX6-NEXT: v_lshrrev_b32_e32 v7, 16, v7
; GFX6-NEXT: v_or_b32_e32 v1, v1, v2		; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
; GFX6-NEXT: v_and_b32_e32 v2, s4, v4		; GFX6-NEXT: v_and_b32_e32 v2, v4, v16
; GFX6-NEXT: v_and_b32_e32 v4, s4, v7		; GFX6-NEXT: v_and_b32_e32 v4, v7, v16
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3		; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX6-NEXT: v_lshrrev_b32_e32 v6, 16, v6
; GFX6-NEXT: v_or_b32_e32 v2, v2, v3		; GFX6-NEXT: v_or_b32_e32 v2, v2, v3
; GFX6-NEXT: v_and_b32_e32 v3, s4, v6		; GFX6-NEXT: v_and_b32_e32 v3, v6, v16
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v4		; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX6-NEXT: v_or_b32_e32 v3, v3, v4		; GFX6-NEXT: v_or_b32_e32 v3, v3, v4
; GFX6-NEXT: s_setpc_b64 s[30:31]		; GFX6-NEXT: s_setpc_b64 s[30:31]
;		;
; GFX8-LABEL: v_usubsat_v8i16:		; GFX8-LABEL: v_usubsat_v8i16:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)		; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_sub_u16_e64 v8, v0, v4 clamp		; GFX8-NEXT: v_sub_u16_e64 v8, v0, v4 clamp
Show All 38 Lines	; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)		%result = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
%cast = bitcast <8 x i16> %result to <4 x float>		%cast = bitcast <8 x i16> %result to <4 x float>
ret <4 x float> %cast		ret <4 x float> %cast
}		}

define amdgpu_ps <4 x i32> @s_usubsat_v8i16(<8 x i16> inreg %lhs, <8 x i16> inreg %rhs) {		define amdgpu_ps <4 x i32> @s_usubsat_v8i16(<8 x i16> inreg %lhs, <8 x i16> inreg %rhs) {
; GFX6-LABEL: s_usubsat_v8i16:		; GFX6-LABEL: s_usubsat_v8i16:
; GFX6: ; %bb.0:		; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 16		; GFX6-NEXT: s_mov_b32 s16, 0xffff
; GFX6-NEXT: s_lshl_b32 s8, s8, 16		; GFX6-NEXT: s_and_b32 s0, s0, s16
; GFX6-NEXT: s_cmp_lt_u32 s0, s8		; GFX6-NEXT: s_and_b32 s8, s8, s16
; GFX6-NEXT: s_cselect_b32 s8, s0, s8		; GFX6-NEXT: s_cmp_gt_u32 s0, s8
		; GFX6-NEXT: s_cselect_b32 s0, s0, s8
; GFX6-NEXT: s_sub_i32 s0, s0, s8		; GFX6-NEXT: s_sub_i32 s0, s0, s8
; GFX6-NEXT: s_lshr_b32 s0, s0, 16		; GFX6-NEXT: s_and_b32 s1, s1, s16
; GFX6-NEXT: s_lshl_b32 s1, s1, 16		; GFX6-NEXT: s_and_b32 s8, s9, s16
; GFX6-NEXT: s_lshl_b32 s8, s9, 16		; GFX6-NEXT: s_cmp_gt_u32 s1, s8
; GFX6-NEXT: s_cmp_lt_u32 s1, s8		; GFX6-NEXT: s_cselect_b32 s1, s1, s8
; GFX6-NEXT: s_cselect_b32 s8, s1, s8
; GFX6-NEXT: s_sub_i32 s1, s1, s8		; GFX6-NEXT: s_sub_i32 s1, s1, s8
; GFX6-NEXT: s_lshr_b32 s1, s1, 16		; GFX6-NEXT: s_and_b32 s2, s2, s16
; GFX6-NEXT: s_lshl_b32 s2, s2, 16		; GFX6-NEXT: s_and_b32 s8, s10, s16
; GFX6-NEXT: s_lshl_b32 s8, s10, 16		; GFX6-NEXT: s_cmp_gt_u32 s2, s8
; GFX6-NEXT: s_cmp_lt_u32 s2, s8		; GFX6-NEXT: s_cselect_b32 s2, s2, s8
; GFX6-NEXT: s_cselect_b32 s8, s2, s8
; GFX6-NEXT: s_sub_i32 s2, s2, s8		; GFX6-NEXT: s_sub_i32 s2, s2, s8
; GFX6-NEXT: s_lshr_b32 s2, s2, 16		; GFX6-NEXT: s_and_b32 s3, s3, s16
; GFX6-NEXT: s_lshl_b32 s3, s3, 16		; GFX6-NEXT: s_and_b32 s8, s11, s16
; GFX6-NEXT: s_lshl_b32 s8, s11, 16		; GFX6-NEXT: s_cmp_gt_u32 s3, s8
; GFX6-NEXT: s_cmp_lt_u32 s3, s8		; GFX6-NEXT: s_cselect_b32 s3, s3, s8
; GFX6-NEXT: s_cselect_b32 s8, s3, s8
; GFX6-NEXT: s_sub_i32 s3, s3, s8		; GFX6-NEXT: s_sub_i32 s3, s3, s8
; GFX6-NEXT: s_lshr_b32 s3, s3, 16		; GFX6-NEXT: s_and_b32 s4, s4, s16
; GFX6-NEXT: s_lshl_b32 s4, s4, 16		; GFX6-NEXT: s_and_b32 s8, s12, s16
; GFX6-NEXT: s_lshl_b32 s8, s12, 16		; GFX6-NEXT: s_cmp_gt_u32 s4, s8
; GFX6-NEXT: s_cmp_lt_u32 s4, s8		; GFX6-NEXT: s_cselect_b32 s4, s4, s8
; GFX6-NEXT: s_cselect_b32 s8, s4, s8
; GFX6-NEXT: s_sub_i32 s4, s4, s8		; GFX6-NEXT: s_sub_i32 s4, s4, s8
; GFX6-NEXT: s_lshr_b32 s4, s4, 16		; GFX6-NEXT: s_and_b32 s5, s5, s16
; GFX6-NEXT: s_lshl_b32 s5, s5, 16		; GFX6-NEXT: s_and_b32 s8, s13, s16
; GFX6-NEXT: s_lshl_b32 s8, s13, 16		; GFX6-NEXT: s_cmp_gt_u32 s5, s8
; GFX6-NEXT: s_cmp_lt_u32 s5, s8		; GFX6-NEXT: s_cselect_b32 s5, s5, s8
; GFX6-NEXT: s_cselect_b32 s8, s5, s8
; GFX6-NEXT: s_sub_i32 s5, s5, s8		; GFX6-NEXT: s_sub_i32 s5, s5, s8
; GFX6-NEXT: s_lshr_b32 s5, s5, 16		; GFX6-NEXT: s_and_b32 s6, s6, s16
; GFX6-NEXT: s_lshl_b32 s6, s6, 16		; GFX6-NEXT: s_and_b32 s8, s14, s16
; GFX6-NEXT: s_lshl_b32 s8, s14, 16		; GFX6-NEXT: s_cmp_gt_u32 s6, s8
; GFX6-NEXT: s_cmp_lt_u32 s6, s8		; GFX6-NEXT: s_cselect_b32 s6, s6, s8
; GFX6-NEXT: s_cselect_b32 s8, s6, s8
; GFX6-NEXT: s_sub_i32 s6, s6, s8		; GFX6-NEXT: s_sub_i32 s6, s6, s8
; GFX6-NEXT: s_lshr_b32 s6, s6, 16		; GFX6-NEXT: s_and_b32 s7, s7, s16
; GFX6-NEXT: s_lshl_b32 s7, s7, 16		; GFX6-NEXT: s_and_b32 s8, s15, s16
; GFX6-NEXT: s_lshl_b32 s8, s15, 16		; GFX6-NEXT: s_cmp_gt_u32 s7, s8
; GFX6-NEXT: s_cmp_lt_u32 s7, s8		; GFX6-NEXT: s_cselect_b32 s7, s7, s8
; GFX6-NEXT: s_cselect_b32 s8, s7, s8		; GFX6-NEXT: s_and_b32 s1, s1, s16
; GFX6-NEXT: s_sub_i32 s7, s7, s8		; GFX6-NEXT: s_and_b32 s0, s0, s16
; GFX6-NEXT: s_mov_b32 s8, 0xffff
; GFX6-NEXT: s_and_b32 s1, s1, s8
; GFX6-NEXT: s_and_b32 s0, s0, s8
; GFX6-NEXT: s_lshl_b32 s1, s1, 16		; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_or_b32 s0, s0, s1		; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: s_and_b32 s1, s2, s8		; GFX6-NEXT: s_and_b32 s1, s2, s16
; GFX6-NEXT: s_and_b32 s2, s3, s8		; GFX6-NEXT: s_and_b32 s2, s3, s16
; GFX6-NEXT: s_and_b32 s3, s5, s8		; GFX6-NEXT: s_and_b32 s3, s5, s16
; GFX6-NEXT: s_lshl_b32 s2, s2, 16		; GFX6-NEXT: s_lshl_b32 s2, s2, 16
; GFX6-NEXT: s_lshr_b32 s7, s7, 16		; GFX6-NEXT: s_sub_i32 s7, s7, s8
; GFX6-NEXT: s_or_b32 s1, s1, s2		; GFX6-NEXT: s_or_b32 s1, s1, s2
; GFX6-NEXT: s_and_b32 s2, s4, s8		; GFX6-NEXT: s_and_b32 s2, s4, s16
; GFX6-NEXT: s_and_b32 s4, s7, s8		; GFX6-NEXT: s_and_b32 s4, s7, s16
; GFX6-NEXT: s_lshl_b32 s3, s3, 16		; GFX6-NEXT: s_lshl_b32 s3, s3, 16
; GFX6-NEXT: s_or_b32 s2, s2, s3		; GFX6-NEXT: s_or_b32 s2, s2, s3
; GFX6-NEXT: s_and_b32 s3, s6, s8		; GFX6-NEXT: s_and_b32 s3, s6, s16
; GFX6-NEXT: s_lshl_b32 s4, s4, 16		; GFX6-NEXT: s_lshl_b32 s4, s4, 16
; GFX6-NEXT: s_or_b32 s3, s3, s4		; GFX6-NEXT: s_or_b32 s3, s3, s4
; GFX6-NEXT: ; return to shader part epilog		; GFX6-NEXT: ; return to shader part epilog
;		;
; GFX8-LABEL: s_usubsat_v8i16:		; GFX8-LABEL: s_usubsat_v8i16:
; GFX8: ; %bb.0:		; GFX8: ; %bb.0:
; GFX8-NEXT: s_lshr_b32 s12, s4, 16		; GFX8-NEXT: s_lshr_b32 s12, s4, 16
; GFX8-NEXT: s_lshr_b32 s13, s5, 16		; GFX8-NEXT: s_lshr_b32 s13, s5, 16
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GlobalISel: Augment addsat/subsat lowering with an optional typeNeeds ReviewPublic

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Diff 287500

llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h

llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddsat.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubsat.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddsat.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubsat.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll

GlobalISel: Augment addsat/subsat lowering with an optional type
Needs ReviewPublic