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[X86] Turn X86DAGToDAGISel::tryVPTERNLOG into a fully custom instruction selector that can handle bitcasts between logic ops
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Authored by craig.topper on Sat, Jul 11, 1:03 PM.

Details

Summary

Previously we just matched the logic ops and replaced with an
X86ISD::VPTERNLOG node that we would send through the normal
pattern match. But that approach couldn't handle a bitcast
between the logic ops. Extending that approach would require us
to peek through the bitcasts and emit new bitcasts to match
the types. Those new bitcasts would then have to be properly
topologically sorted.

This patch instead switches to directly emitting the
MachineSDNode and skips the normal tablegen pattern matching.
We do have to handle load folding and broadcast load folding
ourselves now. Which also means commuting the immediate control.

Diff Detail

Event Timeline

craig.topper created this revision.Sat, Jul 11, 1:03 PM
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Do we need additional mask/maskz predicate test coverage?

Do we still need all the ternlog isel patterns in X86InstrAVX512.td?

Do we need additional mask/maskz predicate test coverage?

We currently fail to match those cases before and after this patch. I might look into that as a follow up.

Do we still need all the ternlog isel patterns in X86InstrAVX512.td?

We definitely need a lot of them. The user facing intrinsics use them.

Ping. Does this patch look ok as is? I can add more tests for mask/maskz but this patch won't affect them. I can raise a bug to support them once this lands?

RKSimon accepted this revision.Sun, Jul 26, 5:41 AM

LGTM - sorry for the delay

This revision is now accepted and ready to land.Sun, Jul 26, 5:41 AM
This revision was automatically updated to reflect the committed changes.