[llvm][ELF][AArch64] Handle R_AARCH64_PLT32 relocation

[leonardchan]

Summary

This patch allows for usage of the @PLT modifier in AArch64 assembly which lowers to an R_AARCH64_PLT32 relocation. See D81184 for handling this relocation in lld.

[MaskRay]

llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp

402

Reusing PREL32 seems wrong.

llvm/test/MC/AArch64/elf-reloc-plt32.s

2

Just use -triple=aarch64. You are testing a generic ELF behavior. Don't append Linux or Fuchsia.

9

This line is redundant

10

Replace 4 with {{.*}}

11

Better adding a CHECK-NEXT: }

[leonardchan]

llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp

402

Split into another case. From what I could tell, it should be nearly the same except the upper bound is 2^31.

[MaskRay]

Looks great! But you'll need thumb-ups from Peter(s)

llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp

406

(& 0xffffffffU) seems to be redundant.

llvm/test/MC/AArch64/elf-reloc-plt32.s

10

Indent by 2 spaces

[psmith]

That looks good to me too. Thanks for the updates.

llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp

case ELF::R_AARCH64_ABS32: {
     uint64_t Result = Value + Addend;
     assert(static_cast<int64_t>(Result) >= INT32_MIN && Result < UINT32_MAX);
     write(isBE, TargetPtr, static_cast<uint32_t>(Result & 0xffffffffU));
     break;
   }
   case ELF::R_AARCH64_ABS64:
     write(isBE, TargetPtr, Value + Addend);
     break;
+  case ELF::R_AARCH64_PLT32: {
+    uint64_t Result = Value + Addend - FinalAddress;
+    assert(static_cast<int64_t>(Result) >= INT32_MIN &&
+           static_cast<int64_t>(Result) <= INT32_MAX);
+    write(isBE, TargetPtr, static_cast<uint32_t>(Result));
+    break;
+  }
   case ELF::R_AARCH64_PREL32: {
     uint64_t Result = Value + Addend - FinalAddress;
     assert(static_cast<int64_t>(Result) >= INT32_MIN &&
            static_cast<int64_t>(Result) <= UINT32_MAX);
     write(isBE, TargetPtr, static_cast<uint32_t>(Result & 0xffffffffU));
     break;
   }
   case ELF::R_AARCH64_PREL64:

llvm/lib/Target/AArch64/AArch64TargetObjectFile.h

 #include "llvm/Target/TargetLoweringObjectFile.h"
 
 namespace llvm {
 class AArch64TargetMachine;
 
 /// This implementation is used for AArch64 ELF targets (Linux in particular).
 class AArch64_ELFTargetObjectFile : public TargetLoweringObjectFileELF {
   void Initialize(MCContext &Ctx, const TargetMachine &TM) override;
+
+public:
+  AArch64_ELFTargetObjectFile() {
+    PLTRelativeVariantKind = MCSymbolRefExpr::VK_PLT;
+  }
 };
 
 /// AArch64_MachoTargetObjectFile - This TLOF implementation is used for Darwin.
 class AArch64_MachoTargetObjectFile : public TargetLoweringObjectFileMachO {
 public:
   AArch64_MachoTargetObjectFile();
 
   const MCExpr *getTTypeGlobalReference(const GlobalValue *GV,

llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp

unsigned AArch64ELFObjectWriter::getRelocType(MCContext &Ctx,
   if (Kind >= FirstLiteralRelocationKind)
     return Kind - FirstLiteralRelocationKind;
   AArch64MCExpr::VariantKind RefKind =
       static_cast<AArch64MCExpr::VariantKind>(Target.getRefKind());
   AArch64MCExpr::VariantKind SymLoc = AArch64MCExpr::getSymbolLoc(RefKind);
   bool IsNC = AArch64MCExpr::isNotChecked(RefKind);
 
   assert((!Target.getSymA() ||
-          Target.getSymA()->getKind() == MCSymbolRefExpr::VK_None) &&
+          Target.getSymA()->getKind() == MCSymbolRefExpr::VK_None ||
+          Target.getSymA()->getKind() == MCSymbolRefExpr::VK_PLT) &&
          "Should only be expression-level modifiers here");
 
   assert((!Target.getSymB() ||
           Target.getSymB()->getKind() == MCSymbolRefExpr::VK_None) &&
          "Should only be expression-level modifiers here");
 
   if (IsPCRel) {
     switch (Kind) {
     case FK_Data_1:
       Ctx.reportError(Fixup.getLoc(), "1-byte data relocations not supported");
       return ELF::R_AARCH64_NONE;
     case FK_Data_2:
       return R_CLS(PREL16);
-    case FK_Data_4:
-      return R_CLS(PREL32);
+    case FK_Data_4: {
+      return Target.getAccessVariant() == MCSymbolRefExpr::VK_PLT
+                 ? R_CLS(PLT32)
+                 : R_CLS(PREL32);
+    }
     case FK_Data_8:
       if (IsILP32) {
         Ctx.reportError(Fixup.getLoc(),
                         "ILP32 8 byte PC relative data "
                         "relocation not supported (LP64 eqv: PREL64)");
         return ELF::R_AARCH64_NONE;
       } else
         return ELF::R_AARCH64_PREL64;

llvm/test/MC/AArch64/elf-reloc-plt32.s

+// RUN: llvm-mc -triple=aarch64 -filetype=obj %s -o - | \
+// RUN:   llvm-readobj -r | FileCheck %s
+
+        .section .data
+this:
+        .word extern_func@PLT - this + 4
+
+// CHECK:      Section ({{.*}}) .rela.data
+// CHECK-NEXT:   0x0 R_AARCH64_PLT32 extern_func 0x4
+// CHECK-NEXT: }