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[AMDGPU] Fix failure in VCC spilling
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Authored by critson on Jun 5 2020, 12:02 AM.

Details

Summary

Spills of VCC (SGPR64) will fail with new SGPR spill code,
because super register is not correctly resolved.

Diff Detail

Event Timeline

critson created this revision.Jun 5 2020, 12:02 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 5 2020, 12:02 AM
arsenm added inline comments.Jun 5 2020, 6:10 AM
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
946

Don't you just need to change SGPR_64RegClass to SReg_64RegClass (or maybe the XEXEC variant?)

llvm/test/CodeGen/AMDGPU/spill-special-sgpr.mir
3

-mattr=-wavefrontsize32,+wavefrontsize64 is unnecessary since wave32 is the default

critson updated this revision to Diff 268990.Jun 5 2020, 8:07 PM

Change to SReg_64_XEXECRegClass.

critson marked 3 inline comments as done.Jun 5 2020, 8:09 PM
critson added inline comments.
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
946

Thanks, that is a better solution.

llvm/test/CodeGen/AMDGPU/spill-special-sgpr.mir
3

This is setting wave64 as the test is not intended for wave32.

arsenm accepted this revision.Jun 16 2020, 8:04 AM

LGTM with test nit

llvm/test/CodeGen/AMDGPU/spill-special-sgpr.mir
17

I think I'd go for generated mir checks in this case rather than the manual checks

This revision is now accepted and ready to land.Jun 16 2020, 8:04 AM
This revision was automatically updated to reflect the committed changes.
critson marked an inline comment as done.